Random question number generator and method suitable for question and answer mode watchdog

Abstract

The invention discloses a random question number generator and method suitable for a question and answer mode watchdog, and belongs to the technical field of integrated circuit safety. Comprising an on-chip high-frequency oscillation source, an enabling controller, a low-power-consumption controller, a pseudo-random number generator and a random code hopping device. According to the method, an external dog feeding signal is used for triggering, a non-reproducible hopping code value is generated by using different sources of clock sources and physical deviation of signal transmission, a pseudo-random number generator is controlled to operate within a random duration, and a low-power-consumption state is entered after a final random problem number is output and latched. Through hardware-level entropy source enhancement and dynamic power consumption management, the predictable potential safety hazard of the traditional pseudo-random number sequence is fundamentally solved, and the balance of high randomness, high attack resistance and low power consumption is realized at low cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit security technology, and in particular to a random question number generator and method suitable for a question-and-answer watchdog. BACKGROUND

[0002] With the increasing complexity and integration of automotive electronics and industrial control systems, the requirements for system functional safety have reached an unprecedented level. In such safety-critical systems, watchdogs, as an effective monitoring mechanism, are widely used to detect whether the system has failed or the program has run away.

[0003] Traditional watchdogs usually use a "timed feeding" mechanism, i.e., the microprocessor being monitored needs to send a "feeding" signal to the watchdog circuit within a specified time window. This mechanism can only verify whether the microprocessor core is still executing instructions, but cannot verify the logical correctness of the program flow, nor can it diagnose potential faults in core peripherals or data buses. This limitation makes it difficult for traditional watchdogs to meet the requirements of ASIL-C / D high safety integrity levels defined in ISO 26262 and other standards.

[0004] To compensate for the above shortcomings, question-and-answer watchdogs have emerged. The core principle is that the watchdog circuit actively sends a random "question" to the monitored system, which must correctly calculate the answer according to the pre-set algorithm (such as a specific arithmetic operation or table lookup operation) and return the "answer" within a strictly limited time window. By verifying the correctness of the answer, the question-and-answer watchdog not only confirms that the processor is running, but also confirms the correctness of its program logic and execution path, thereby significantly improving the system's diagnostic coverage. The question-and-answer watchdog can limit the question-and-answer process to complete within a configurable maximum time, and immediately start a new question process after completion. It can also be divided into an open window with a configurable time limit and a closed window watchdog, where the question-and-answer process can only be performed in the open window, and after completion, it enters the closed window, rather than immediately entering the next open window. For example, as shown in the flowchart Figure 1 When feeding is successful, it enters the closed window; the system must complete all responses within the open window, otherwise it is considered invalid.

[0005] Currently, the generation of random question numbers in mainstream question-and-answer watchdogs generally relies on linear feedback shift registers (LFSR) to generate pseudo-random number sequences. LFSR is widely used due to its simple hardware implementation and low resource consumption.

[0006] However, this LFSR-based pseudo-random question number generation method has the following inherent defects and security risks:

[0007] (1) Periodicity and predictability of the sequence: LFSR generates a "pseudo-random" sequence, whose sequence state is uniquely determined by the current register value and the feedback polynomial. Although the sequence period can be extended by increasing the number of register bits, any LFSR based on deterministic algorithm will eventually enter a cyclic state. Attackers or failure modes can analyze the feedback polynomial by long-term observation or reverse engineering, and predict the subsequent problem number sequence.

[0008] (2) Lack of deterministic entropy source: The randomness of LFSR is completely derived from its initial seed value, and its internal state transition is purely digital logic operation, lacking unpredictable physical entropy source. Once the initial seed is cracked or the sequence enters a stable state, its output is completely determined and does not have true randomness.

[0009] (3) Weak resistance to attacks: When facing malicious attacks, attackers can use the predictability of the sequence to precompute the correct answer, so that even in the case of system failure or malicious control, they can still fake valid responses and bypass the watchdog security monitoring mechanism. This makes the entire system's security defense line useless. SUMMARY

[0010] To overcome the shortcomings of the prior art, the present application provides a random question number generator and method suitable for question and answer watchdog, which overcomes the shortcomings of the prior art, enhances the hardware-level entropy source and dynamic power management, and fundamentally solves the security risks of predictable traditional pseudo-random number sequences, achieving a balance between high randomness, high attack resistance and low power consumption at low cost.

[0011] To achieve the above purpose, the present application is realized by the following technical solutions:

[0012] A random question number generator suitable for question and answer watchdog, comprising an on-chip high-frequency oscillator, an enable controller, a low-power controller, a pseudo-random number generator and a random skipper;

[0013] The on-chip high-frequency oscillator is used to generate a reference clock signal;

[0014] The enable controller is connected with the on-chip high-frequency oscillator and the external processor communication interface, and is used to output an enable signal in response to the watchdog feeding command of the external processor;

[0015] The low-power controller is connected with the on-chip high-frequency oscillator and the enable controller, and is used to output a clock enable signal according to the enable signal;

[0016] The clock input of the random hopping code generator is connected to an on-chip high-frequency oscillator, and the enable input of the random hopping code generator is connected to a low-power controller. In the active state, the random hopping code generator generates a hopping code value based on the current value of the internal counter and the non-steady-state physical deviation of the external communication time, and performs a decrementing count.

[0017] The clock input of the pseudo-random number generator is connected to an on-chip high-frequency oscillator, the enable input of the pseudo-random number generator is connected to a low-power controller, and the seed input of the pseudo-random number generator is associated with the output of a random hopping code generator, used to generate random numbers during the counting period of the random hopping code generator, and output random numbers as random question numbers when the random hopping code generator counts to zero.

[0018] Preferably, the initial hopping code value of the random hopping code generator is determined by the real-time count value of the internal counter synchronized by the on-chip high-frequency oscillation source and the non-steady-state deviation at the communication moment when the external processor sends the dog-feeding command.

[0019] Preferably, the count value of the internal counter and the non-steady-state deviation at the communication time are combined through logical operations to form the initial hopping code value of the random hopping code generator.

[0020] Preferably, the pseudo-random number generator is a linear feedback shift register.

[0021] Preferably, the initial seed value of the linear feedback shift register in each generation process is the final random question number output from the previous process.

[0022] Preferably, the low-power controller is further configured to:

[0023] When the random number generator counts to zero, a data latching mechanism is triggered to latch the random number output by the pseudo-random number generator as a valid random question number; then a shutdown command is sent to the enable controller to put the random number generator and the pseudo-random number generator into a low-power sleep state.

[0024] Preferably, the enable controller receives the dog-feed command from the external processor via the SPI communication interface.

[0025] This invention also discloses a working method based on the above-mentioned random question number generator, characterized by including the following steps:

[0026] Step S1: System initialization and reference clock establishment; the on-chip high-frequency oscillator is started, so that it outputs a stable reference clock signal; at the same time, an internal counter starts to perform cyclic counting based on the reference clock signal;

[0027] Step S2: Dog feeding signal monitoring and enable triggering; The enable controller continuously monitors the signals sent by the external processor through the communication interface; The enable controller is triggered when and only when a valid dog feeding signal conforming to the preset protocol format is detected, switching from the waiting state to the active state and outputting an enable signal;

[0028] Step S3: Low-power state switching and module activation; The low-power controller receives the enable signal from the enable controller, and then outputs a clock enable signal to the pseudo-random number generator and the random hopping code generator to wake them up from the low-power sleep state and enter the normal working mode.

[0029] Step S4: Unpredictable skip code value generation and loading; The random skip code generator obtains an initial skip code value, which is obtained by logical XOR operation between the real-time instantaneous value of the internal counter and the non-steady-state deviation; The random skip code generator loads the initial skip code value and starts the decrementing count operation with the reference clock signal as the timing reference;

[0030] Step S5: Random sequence generation based on the hopping code period; synchronously with the random hopping code generator, the pseudo-random number generator is started; it runs continuously based on the reference clock signal throughout the entire decrementing counting period of the random hopping code generator, executes its internal state transition and operation logic, and dynamically generates an original random number sequence.

[0031] Step S6: Latching the final random question number; When the countdown of the random skipping code reaches zero, a count termination signal is generated; In response to this signal, the low-power controller triggers a data latching action, latches the random value output by the pseudo-random number generator at this time, and determines it as the valid random question number for this cycle;

[0032] Step S7: System reset and low-power loop establishment; After the random question number is latched, the low-power controller controls the pseudo-random number generator and random code skipper to exit the normal working mode and re-enter the low-power sleep state; the enable controller is reset to the waiting state; the system returns to step S2 and waits for the next valid dog feed signal to be triggered, thereby forming a periodic, event-driven random question number generation loop.

[0033] Preferably, in step S7, after the low-power controller sends a shutdown command to the enable controller, the loop counting of the internal counter is not reset and continues.

[0034] This invention provides a random question number generator and method suitable for question-answering watchdog timers, offering the following advantages: By introducing a physical entropy source based on the physical deviation of time intervals, the initial value of the random hopping code generator is jointly determined by the instantaneous value of the internal counter and the non-steady-state characteristics of communication time caused by voltage jitter and temperature drift. This randomness based on chip physical characteristics is microscopic and uncontrollable, making each generated hopping code value physically unreproducible, fundamentally eliminating the possibility of predicting the question number sequence through mathematical analysis. Furthermore, by employing a dual randomization mechanism of "random initial value" and "random generation length," attackers cannot predict either the starting point or the ending point, thus making it impossible to determine the final latched question number. This effectively resists various malicious attacks, including time-series analysis attacks, exhaustive attacks, and model prediction attacks, greatly enhancing the security barrier of question-answering watchdog timers. Precise clock enable control of the pseudo-random number generator and random hopping code generator is implemented through a low-power controller, ensuring that these two core computing modules are activated and run at full speed only for a very short time after receiving a valid watchdog signal. Once the random question number is generated, the module immediately enters a low-power sleep state. This event-driven dynamic power management mechanism enables the system to maintain ultra-low static power consumption for the vast majority of the time. Furthermore, because the entropy source driving the entire process is a continuously changing physical phenomenon, and the initial value of the random number generator is completely different each time it is triggered, the starting point and length of the pseudo-random number generator's computation continuously change. Therefore, its output random question number sequence has no fixed period; it is infinite and non-repeating, completely solving the fundamental defect of the predictable period of traditional LFSR sequences and providing long-term, sustainable security for the system. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this invention or the prior art, the accompanying drawings used in the description of this invention or the prior art will be briefly introduced below.

[0036] Figure 1 A flowchart illustrating the steps involved in starting a window-based question-and-answer watchdog timer in the prior art, where the watchdog first enters an open window.

[0037] Figure 2 This is a schematic diagram of the structure of the present invention;

[0038] Figure 3 This is a flowchart illustrating the steps of the random question number generator of the present invention.

[0039] Figure 4 This is a schematic diagram of the initial value generation mechanism of the random hopping code generator in this invention;

[0040] Figure 5 This is a flowchart of the low-power state transition process in this invention;

[0041] Figure 6 This is a schematic diagram of the entropy source mixing and security enhancement mechanism in this invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0043] Example 1, as Figures 2-6 As shown, the present invention discloses a random question number generator suitable for question-and-answer watchdog timers, including an on-chip high-frequency oscillation source 1, an enable controller 2, a low-power controller 3, a pseudo-random number generator 4, and a random code jumper 5.

[0044] Among them, the on-chip high-frequency oscillator 1 serves as the main clock source for the entire system, independent of the clock of the external main control processor (MCU). This independent source is one of the foundations for generating physical randomness. After power-on, the on-chip high-frequency oscillator 1 generates a reference clock signal with stable frequency and phase, providing a synchronous clock for all sequential logic circuits in the system.

[0045] Enable controller 2 is a state machine. It connects to an external processor via an off-chip communication interface such as SPI, continuously monitors and decodes commands from the processor, and identifies valid "feed the dog" excitation signals. Only when it receives a signal that conforms to a preset protocol will enable controller 2 switch from the sleep waiting state to the active state, output an enable pulse, and start the subsequent random number generation process.

[0046] The low-power controller 3 is connected to the on-chip high-frequency oscillator 1 and the enable controller 2. It receives the start command from the enable controller 2 and outputs clock enable signals to the pseudo-random number generator 4 and the random code skipping unit 5 according to a preset power consumption strategy. This design employs dynamic gating clock technology, which provides a clock to these two core computing modules only when random problems need to be generated, and immediately cuts off the clock after the task is completed, thereby significantly reducing the average power consumption of the system.

[0047] In this embodiment, the low-power controller 3 is further configured to: trigger a data latching mechanism when the random number hopping code 5 counts to zero, latching the random number output by the pseudo-random number generator 4 as a valid random question number; and then send a shutdown command to the enable controller 2 to cause the random number hopping code 5 and the pseudo-random number generator 4 to enter a low-power sleep state.

[0048] The clock input of the random hopping code generator 5 is connected to the on-chip high-frequency oscillator 1, and the enable input of the random hopping code generator 5 is connected to the low-power controller 3. It is used to generate hopping code values ​​based on the current value of the internal counter and the non-steady-state physical deviation at the time of external communication in the active state, and to count down.

[0049] The random skipper 5 is a decremental counter with an initial value that can be loaded. Its key lies in its initial value loading mechanism:

[0050] Entropy Source 1: Internal Counter Value: The system contains a free-running counter that continuously cycles with the clock of high-frequency oscillation source 1. The instantaneous value of this counter is captured at the precise moment the enable controller 2 is triggered. Because the arrival time of the dog-feed signal is asynchronous, this count value itself is a difficult-to-predict variable.

[0051] Entropy Source Two: Unsteady Physical Deviation During Communication: When signals are transmitted within the chip, path delays caused by micro-fluctuations in the power supply voltage and chip temperature drift result in random deviations on the order of nanoseconds. This physical uncertainty makes the precise timing of the enable signal output by enable controller 2 truly random.

[0052] Entropy source mixing: The two values ​​mentioned above (the instantaneous value of the internal counter and the physical time deviation information) are mixed through a logic operation unit (such as an XOR gate) to generate an initial skip code value that combines digital uncertainty and physical irreproducibility, and then loaded into the random skip code generator 5. Subsequently, the random skip code generator 5 starts counting down from this value.

[0053] The clock input of pseudo-random number generator 4 is connected to the on-chip high-frequency oscillator 1, the enable input of pseudo-random number generator 4 is connected to the low-power controller 3, and the seed input of pseudo-random number generator 4 is associated with the output of random hopping code generator 5. In this embodiment, pseudo-random number generator 4 is implemented using a linear feedback shift register (LFSR). During the entire decrementing count of random hopping code generator 5, the LFSR continuously performs shift and feedback operations under clock drive, generating a long-period pseudo-random sequence. When random hopping code generator 5 counts to zero, it outputs a random number as the random question number. The initial seed of the LFSR can be set to the final output of the previous process, thereby achieving iterative accumulation of entropy and further enhancing randomness.

[0054] Working principle:

[0055] The workflow of this invention is an event-driven, periodic loop. After the system powers on, the high-frequency oscillator 1 and the internal counter begin operating. The enable controller 2 is in a listening state, while other modules are in a low-power sleep state. The overall system static power consumption is extremely low. When the external processor sends a valid watchdog timer signal, the enable controller 2 is triggered, which then wakes up the random number generator 5 and the pseudo-random number generator 4 via the low-power controller 3. The random number generator 5 captures and calculates an unreproducible initial value for the jump code. The jump code generator begins to decrement its count, and its counting period itself is a random variable. At the same time, the pseudo-random number generator 4 is started and operates rapidly within this random-length clock cycle, outputting a constantly changing sequence of random numbers. The instant the count of the random number generator 5 reaches zero is a definite time endpoint. The low-power controller 3 immediately triggers the latch, latching the output value of the pseudo-random number generator 4 at the current moment as the valid random number for this operation. After the task is completed, the low-power controller 3 immediately cuts off the clock of subsequent modules, and the system quickly returns to a low-power standby state, waiting for the next watchdog timer trigger.

[0056] Unlike existing pseudo-random number generators that rely purely on deterministic numerical algorithms (such as LFSR), this invention introduces a physical entropy source based on the physical deviation of time intervals. The initial value of the random hopping code generator 5 is jointly determined by the instantaneous value of the internal counter and the non-steady-state characteristics of communication time caused by voltage jitter and temperature drift. This randomness based on the chip's physical characteristics is microscopic and uncontrollable, making each generated hopping code value physically unreproducible, fundamentally eliminating the possibility of predicting the question number sequence through mathematical analysis. Furthermore, a dual randomization mechanism of "random initial value" and "random generation length" is employed. Not only is the hopping code initial value random, but the operation cycle of the pseudo-random number generator 4 (i.e., the decrementing count time of the random hopping code generator) determined by this value is also random. Attackers cannot predict the starting point or the ending point, thus making it impossible to determine the final latched question number. This effectively resists various malicious attacks, including time-series analysis attacks, exhaustive attacks, and model prediction attacks, greatly enhancing the security barrier of the question-answering watchdog. Precise clock enable control is implemented for the pseudo-random number generator 4 and the random number jumper 5 by the low-power controller 3, ensuring that these two core computing modules are activated and run at full speed only for a very short time after receiving a valid dog-feed signal. Once the random question number is generated, the module immediately enters a low-power sleep state. This event-driven dynamic power management mechanism enables the system to maintain ultra-low static power consumption for most of the time, perfectly meeting the needs of power-sensitive applications such as automotive electronics and industrial control. In addition, since the entropy source driving the entire process is a continuously changing physical phenomenon, and the initial value of the random number jumper is completely different each time it is triggered, the starting point and length of the pseudo-random number generator 4's operation continuously change. From a macroscopic and long-term perspective, its output random question number sequence has no fixed period and is infinite and non-repeating, completely solving the fundamental defect of the predictable period of traditional LFSR sequences and providing long-term and sustainable security for the system.

[0057] Furthermore, this invention cleverly utilizes the clock source (on-chip high-frequency oscillation source 1) inherent within the functional safety chip and its different origin from the main control chip's clock, as well as the inherent physical deviation in signal transmission, as the core entropy source. Without introducing expensive hardware such as a separate true random number generator (TRNG) chip or complex analog noise acquisition circuits, it achieves safety performance comparable to a dedicated TRNG without significantly increasing chip area or manufacturing costs.

[0058] Example 2, as Figure 3 As shown, this embodiment takes a typical safety-critical scenario in automotive electronics as an example, illustrating a question-and-answer watchdog timer random question number generation process applied to the engine control unit (ECU). The main system parameters are assumed to be as follows:

[0059] On-chip high-frequency oscillator 1: frequency is 40 MHz.

[0060] Internal counter: A 32-bit free-running counter with the aforementioned 40MHz clock signal as its source.

[0061] Communication interface: SPI interface.

[0062] Pseudo-random number generator 4: A 32-bit linear feedback shift register (LFSR).

[0063] Random jumper (5): A 16-bit decrementing counter.

[0064] The specific implementation steps are as follows:

[0065] Step S1: System initialization and reference clock establishment; The system is powered on and reset, and the on-chip high-frequency oscillator 1 is started. After a microsecond-level stabilization time, it outputs a stable 40 MHz clock signal; At the same time, the 32-bit internal counter is released after reset and starts counting cyclically at a frequency of 40 MHz.

[0066] Step S2: Dog feed signal monitoring and enable triggering; Enable controller 2 continuously monitors the SPI bus. Its internally preset valid dog feed signal format is a 16-bit specific command code. When the external processor (ECU) sends this specific command code via SPI, enable controller 2 accurately identifies the command under SPI clock synchronization. Due to the micro-jitter of the chip power supply network voltage and the instantaneous change of junction temperature, the delay of the SPI data bits on the internal transmission path of the chip has a random deviation of approximately ±100ps. This results in the unpredictable physical randomness of the precise rising edge time of the enable signal output by enable controller 2.

[0067] Upon recognizing a command, enable controller 2 immediately switches from a low level to a high level and outputs an enable signal.

[0068] Step S3: Low-power state switching and module activation; The low-power controller 3 detects the rising edge of the enable signal from the enable controller 2 and then sends an "on" command to the clock gating unit of the pseudo-random number generator 4 (LFSR) and the random code skipper 5. The pseudo-random number generator 4 and the random code skipper 5, which were previously in the clock off state, are activated and begin to receive the 40MHz clock signal, ready to run.

[0069] Step S4: Unpredictable hopping code value generation and loading; In the first clock cycle when the enable signal is valid, the random hopping code 5 performs the following operations:

[0070] 1. Capture internal counter value: Locks the instantaneous value of the current 32-bit internal counter.

[0071] 2. Incorporating Physical Randomness: The lower 16 bits of the aforementioned counter value are XORed with a hardware state determined by physical timing deviation (e.g., the output of a metastable latch). The result is used as the initial skip code value and loaded into the 16-bit random skip code 5.

[0072] The random hopping code 5 starts from the initial hopping code value and counts down based on a 40MHz clock.

[0073] Step S5: Random sequence generation based on the skipping code period; Synchronized with the random skipping code 5 in step S4, the pseudo-random number generator 4 is activated. The initial seed of the pseudo-random number generator 4 is set to the random question number that was successfully generated and latched last time (if it is the first run, a factory-preset default seed is loaded). During the entire decrementing counting period of the random skipping code 5, the pseudo-random number generator 4, driven by a 40MHz clock, continuously performs shift and feedback operations, executes its internal state transition and operation logic, and dynamically generates an original random number sequence;

[0074] Step S6: Latching the final random question number; When the countdown of the random number generator 5 reaches zero, the random number generator 5 immediately sends a counting termination pulse signal to the low-power controller 3. On the next rising edge of the clock after receiving this pulse, the low-power controller 3 triggers the data latch connected to the output of the LFSR. At this time, the current 32-bit state of the pseudo-random number generator 4 is instantly latched and output as the valid random question number to the comparison logic unit of the question-and-answer watchdog timer for verification with the answer returned by the ECU.

[0075] Step S7: System Reset and Low-Power Loop Establishment; After completing the latching action, the low-power controller 3 immediately removes the clock enable signal for the pseudo-random number generator 4 and the random hopping code generator 5. The pseudo-random number generator 4 and the random hopping code generator 5 immediately stop working and enter a near-zero dynamic power consumption sleep state. The enable controller 2 also resets its internal state and restarts listening to the SPI bus, waiting for the next valid dog feed command. This forms a periodic, event-driven random number generation loop. During this process, the 32-bit internal counter remains unaffected and continues to run freely, preparing new, unpredictable instantaneous values ​​for the next entropy acquisition.

[0076] At this point, a complete random question number generation cycle is finished. The system quickly returns to ultra-low power monitoring mode, and the ECU must complete the preset calculation for the random question number and return the correct answer within the response time window specified by the watchdog timer.

[0077] This invention employs a dual uncertainty of "random initial value" and "random generation length" through the aforementioned method. Attackers cannot predict not only the initial value of the random number generator but also when the pseudo-random number generator will be latched (i.e., when the random number generator's count will reach zero). This method fundamentally eliminates all possibilities of predicting the output through timing analysis or model reconstruction, providing security far exceeding traditional fixed-period LFSR methods. Furthermore, this method does not rely on pure software algorithms but actively collects and utilizes the chip's inherent physical entropy sources (communication timing deviation, instantaneous counter value). This method injects true, uncontrollable randomness from the very source of random number generation, making the "seed" and "length" of each generation process physically unreproducible. In addition, the core of this invention is a "wait-trigger-work-sleep" cycle. For the vast majority of the time, the core computing units (pseudo-random number generator, random number generator) are in a clock-off sleep state, and the system only maintains the most basic listening function, achieving extremely low average static power consumption. Power consumption is precisely time-managed through a low-power controller. The high-power module is activated only within the absolutely necessary time window after receiving a valid external event (dog feed signal). Its clock is immediately cut off upon task completion, minimizing power consumption while providing robust security features, making it particularly suitable for battery-powered or power-constrained embedded scenarios. Furthermore, this method defines a complete, self-managed process loop from triggering and computation to reset. This process does not rely on external software intervention and is entirely controlled autonomously by the hardware logic, avoiding the risk of the random number generation process being tampered with or bypassed due to software errors or malicious code, thus providing higher reliability and interference resistance.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A random question number generator suitable for use in a question and answer watchdog, characterized by: The chip includes an on-chip high-frequency oscillator (1), an enable controller (2), a low-power controller (3), a pseudo-random number generator (4), and a random skipper (5). The on-chip high-frequency oscillator (1) is used to generate a reference clock signal. The enable controller (2) is connected to the on-chip high-frequency oscillator (1) and an external processor through a communication interface, and is used to output an enable signal in response to a feed command from the external processor. The low-power controller (3) is connected to the on-chip high-frequency oscillator (1) and the enable controller (2), and is used to output a clock enable signal according to the enable signal. The clock input of the random skipper (5) is connected to the on-chip high-frequency oscillator (1), and the enable input of the random skipper (5) is connected to the low-power controller (3), which is used to generate a skip value based on the current value of an internal counter and the non-steady physical deviation of the external communication time in the active state, and to count down. The clock input of the pseudo-random number generator (4) is connected to the on-chip high-frequency oscillator (1), the enable input of the pseudo-random number generator (4) is connected to the low-power controller (3), and the seed input of the pseudo-random number generator (4) is associated with the output of the random skipper (5), which is used to generate a random number during the counting of the random skipper (5), and output the random number as a random question number when the random skipper (5) counts to zero.

2. A random question number generator for a question and answer watchdog according to claim 1, characterized in that: The initial skip value of the random skipper (5) is determined by the real-time counting value of the internal counter synchronized by the on-chip high-frequency oscillator (1) and the non-steady deviation of the communication time when the external processor sends the feed command.

3. A random question number generator for a question and answer watchdog according to claim 2, characterized in that: The counting value of the internal counter and the non-steady deviation of the communication time are combined through logical operation to form the initial skip value of the random skipper (5).

4. A random question number generator for a question and answer watchdog according to claim 1, characterized in that: The pseudo-random number generator (4) is a linear feedback shift register.

5. A random question number generator for a question and answer watchdog according to claim 4, characterized in that: The initial seed value of the linear feedback shift register in each generation process is the final random question number output in the last process.

6. A random question number generator for a question and answer watchdog according to claim 1, characterized in that: The low-power controller (3) is further configured to: trigger a data latch mechanism to latch the random number output by the pseudo-random number generator (4) as a valid random question number when the random skipper (5) counts to zero; and then send a shutdown instruction to the enable controller (2) to make the random skipper (5) and the pseudo-random number generator (4) enter a low-power sleep state.

7. A random question number generator for a question and answer watchdog according to claim 1, characterized in that: The enable controller (2) receives the feed command from the external processor through an SPI communication interface.

8. A method of operating a random question number generator according to any one of claims 1 to 7, characterised in that: The method comprises the following steps: Step S1: system initialization and reference clock establishment; the on-chip high-frequency oscillator (1) is started to output a stable reference clock signal; at the same time, an internal counter starts to count based on the reference clock signal; Step S2: feed signal monitoring and enable triggering; the enable controller (2) continuously monitors the signal sent by the external processor through the communication interface; when and only when a valid feed signal conforming to the preset protocol format is detected, the enable controller (2) is triggered to switch from the waiting state to the active state and output an enable signal; Step S3: low power state switching and module activation; the low power controller (3) receives the enable signal from the enable controller (2), and then outputs a clock enable signal to the pseudo-random number generator (4) and the random skipper (5), so as to wake up the two from the low power sleep state and enter the normal working mode; Step S4: unpredictable skip value generation and loading; the random skipper (5) obtains an initial skip value, and the initial skip value is obtained through logical exclusive or operation of a real-time instantaneous value of an internal counter and a non-steady-state deviation; the random skipper (5) loads the initial skip value, and starts the decrement counting operation with the reference clock signal as the timing reference; Step S5: random sequence generation based on skip period; the pseudo-random number generator (4) is started synchronously with the random skipper (5); During the entire decrement counting period of the random skipper (5), the pseudo-random number generator (4) continuously runs based on the reference clock signal, executes the internal state transition and operation logic, and dynamically generates an original random number sequence; Step S6: final random question number latching; when the decrement counting of the random skipper (5) reaches zero, a counting termination signal is generated; the low power controller (3) triggers the data latching action in response to the signal, latches the random number value output by the pseudo-random number generator (4) at this time, and determines the random number value as the valid random question number of this cycle; Step S7: system reset and low power cycle establishment; after the latching of the random question number is completed, the low power controller (3) controls the pseudo-random number generator (4) and the random skipper (5) to exit the normal working mode and re-enter the low power sleep state; the enable controller (2) is reset to the waiting state; the system returns to step S2, waits for the trigger of the next valid dog feeding signal, and thus forms a periodic and event-driven random question number generation cycle.

9. A random question number generator for a question and answer watchdog according to claim 1, characterized in that: In step S7, after the low power controller (3) sends the closing instruction to the enable controller (2), the cycle counting of the internal counter is not reset and continues.

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