Communication method based on low-noise high-dynamic full-wave radio frequency channel amplification circuit

Abstract

The invention discloses a communication method based on a low-noise high-dynamic full-wave radio frequency channel amplification circuit, and relates to the field of wireless communication and radio frequency integrated circuits. The method comprises the following steps: firstly, sampling a baseband signal and constructing a multi-dimensional time sequence feature vector containing a historical state and a change rate; predicting a signal envelope peak value in a future time window by using a lightweight long short-term memory network (LSTM); a dynamic bias control signal is then generated based on reverse mapping and parasitic parameter compensation. Digital delay is introduced into a radio frequency main path, so that bias voltage is pre-loaded to a grid electrode of an amplifier before a radio frequency signal arrives, and negative delay control is realized; and finally driving the amplifier through asymmetric filtering. According to the invention, the problem of signal truncation distortion caused by response lag in the traditional dynamic bias technology is solved, the amplifier is in a deep AB-class or B-class state of low quiescent current for a long time while ensuring no distortion in a high dynamic range, the power consumption and the thermal noise are greatly reduced, and the signal-to-noise ratio of the system is improved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, specifically to a communication method based on a low-noise, high-dynamic full-wave radio frequency channel amplifier circuit. Background Technology

[0002] Modern wireless communication systems (such as 5G and WiFi 6) commonly employ high-order modulation techniques like Orthogonal Frequency Division Multiplexing (OFDM), resulting in signals with extremely high peak-to-average power ratios (PAPR). Traditional RF power amplifiers, to prevent nonlinear distortion when processing sudden large signals, typically require a high static bias current, operating in Class A or shallow Class AB mode. However, communication signals operate at low power for most of the time, and maintaining a high static bias for extended periods leads to significant power consumption and severe heat generation. Increased chip junction temperature not only reduces device lifespan but, more importantly, significantly increases electron thermal motion, introducing additional thermal noise, raising the receiver's noise floor, and severely degrading the system's signal-to-noise ratio.

[0003] To reduce power consumption, existing technologies typically employ envelope tracking or dynamic biasing techniques, attempting to adjust the bias voltage in real time based on the amplitude of the input signal. However, analog biasing circuits and power modulators inherently have physical bandwidth limitations and response delays. When the input RF signal undergoes rapid changes, the bias voltage adjustment often lags behind the signal change, causing the amplifier to fail to obtain sufficient gain at the rising edge of the signal, resulting in "truncation distortion" or peak clipping. This timing mismatch limits the application of dynamic biasing technology in high-frequency broadband systems, making it difficult to effectively reduce thermal noise and power consumption while maintaining high dynamic range (linearity). Summary of the Invention

[0004] The purpose of this invention is to provide a communication method based on a low-noise, high-dynamic full-wave radio frequency channel amplifier circuit. By introducing a long short-term memory network (LSTM) for timing prediction, intelligent control of amplifier bias is achieved.

[0005] To achieve the above objectives, the present invention proposes the following technical solution: a communication method based on a low-noise, high-dynamic-range full-wave radio frequency channel amplifier circuit, the method comprising the following steps: Step S1: In the digital baseband domain, the in-phase and quadrature components of the radio frequency signal are sampled in real time, and a multi-dimensional time-series feature vector containing historical states and rates of change is constructed. Step S2: Input the multidimensional temporal feature vector into the pre-trained Long Short-Term Memory (LSTM) network model, and use the gating mechanism of the LSTM network to perform temporal reasoning to predict the signal envelope peak value within the future preset time window. Step S3: Establish the inverse mapping relationship between transistor bias voltage and signal envelope, generate the corresponding dynamic bias control signal based on the predicted signal envelope peak value, and superimpose the compensation component for transistor parasitic parameters. Step S4: Introduce digital delay in the main path of the radio frequency signal so that the generated dynamic bias control signal is preloaded onto the transistor gate before the radio frequency signal reaches the amplifier, thereby achieving negative delay bias control. Step S5: Perform asymmetric smoothing filtering on the dynamic bias control signal, and then drive the RF amplifier through digital-to-analog conversion to maintain a high dynamic range while operating in a low-noise state.

[0006] Furthermore, in this invention, the specific process of constructing the multidimensional temporal feature vector in step S1 includes: Calculate the arithmetic square root of the sum of the squares of the in-phase components and the quadrature components to obtain the instantaneous envelope magnitude. By using a sliding time window to statistically analyze the signal peak value in real time, the instantaneous envelope magnitude is dynamically normalized to eliminate the impact of input power fluctuations on the network model. The difference between the normalized envelope value at the current time and the normalized envelope value at the previous time is calculated to obtain the first-order difference feature. The normalized envelope value at the current time, the normalized envelope sequence at historical time, and the first-order difference feature are combined to form the multidimensional temporal feature vector.

[0007] Furthermore, in this invention, in step S2, predicting the signal envelope peak value within a future preset time window refers to: The output layer of the Long Short-Term Memory network model does not directly predict the value at a single moment. Instead, it uses a fully connected layer to regress and predict the maximum envelope amplitude over the entire time period corresponding to the future physical lead, ensuring that the generated bias voltage can fully cover the highest point of signal fluctuations that may occur within that time period.

[0008] Furthermore, in this invention, in step S2, the long short-term memory network model adopts a lightweight structure: The forget gate is used to determine how much historical memory information to retain from the cell state at the previous time step, the input gate is used to determine how much new information from the current time step feature vector is updated to the cell state, and the output gate is used to calculate the current hidden layer output by combining the updated cell state, thereby capturing the long-term dependence and burst characteristics of radio frequency signals.

[0009] Furthermore, in this invention, in step S3, establishing the inverse mapping relationship between the transistor bias voltage and the signal envelope includes: Based on the transfer characteristic curve of the RF amplifier transistor, a static mapping function is constructed using a polynomial fitting method; The constant term of the mapping function is set to correspond to the deep AB or B operating point of the transistor, so that the transistor is in a state of extremely low quiescent current when the prediction envelope is zero or small signal, in order to suppress thermal noise.

[0010] Furthermore, in this invention, in step S3, superimposing compensation components for transistor parasitic parameters means: Calculate the rate of change of the peak value of the predicted signal envelope over time; Multiplying the rate of change by the time constant coefficient related to the bias circuit setup time and the transistor gate input capacitance, we obtain the feedforward differential compensation voltage. The feedforward differential compensation voltage is superimposed on the voltage generated by the static mapping function to generate an overshoot voltage to accelerate the charging and discharging process of the gate capacitor.

[0011] Furthermore, in this invention, the specific method for implementing negative delay bias control in step S4 is as follows: The total signal processing delay of the control path is calculated, which includes the long short-term memory network inference time, the digital-to-analog conversion time, and the analog bias circuit setup time. Configure the depth of the digital delay buffer for the main path of the radio frequency signal so that the delay of the main path is greater than or equal to the sum of the total signal processing delay and the safety setup time margin of the control path, thereby ensuring that the setup of the bias voltage precedes the arrival of the radio frequency signal on the time axis.

[0012] Furthermore, in this invention, in step S5, the asymmetric smoothing filtering of the dynamic bias control signal employs a fast-attack, slow-fading strategy: When the bias control voltage generated at the current moment is higher than the output voltage at the previous moment, the filter is in a shoot-through state, and the output voltage immediately rises following the current bias control voltage. When the bias control voltage generated at the current moment is lower than or equal to the output voltage at the previous moment, the filter is in attenuation state, and the output voltage decreases slowly relative to the output voltage at the previous moment according to the preset attenuation coefficient.

[0013] Furthermore, in this invention, the asymmetric smoothing filter process is used for: To avoid frequent bias voltage jumps caused by minute jitters in the predicted envelope, suppress the resulting switching noise and modulation sideband, and mitigate drastic fluctuations in the junction temperature of the power amplifier transistor, thereby reducing the thermal memory effect.

[0014] A communication system implementing the above method includes: The digital baseband processing module is used to perform signal sampling, feature extraction, and long short-term memory network inference. A digital delay buffer module, connected in series in the main RF signal path, is used to provide programmable digital delay; The bias control module, which includes a digital-to-analog converter and a bias drive circuit, is used to convert the inference results into an analog bias voltage and apply it to the amplifier. The radio frequency power amplifier has its gate bias voltage dynamically adjusted by the bias control module, and its signal input terminal is connected to the output terminal of the digital delay buffer module.

[0015] Beneficial effects: The technical solution of this application has the following technical effects: First, by leveraging the precise predictive capabilities of LSTM for future signal waveforms and combining it with the digital delay of the RF main path, a "negative delay" control mechanism is constructed at the physical level. This means that the bias voltage can be established before the RF signal reaches the transistor gate, completely eliminating the tracking lag problem in traditional dynamic biasing techniques. This allows the amplifier to avoid truncation distortion and AM-PM distortion caused by untimely response when processing high-speed broadband signals, ensuring the system's high dynamic range and linearity.

[0016] Secondly, this method significantly reduces the system's static power consumption and thermal noise. Due to its precise "predictive" capability, the amplifier can safely operate in a deep Class AB or even Class B extremely low bias state for most small-signal or no-signal periods, without requiring a large static current margin to handle sudden signals, as is the case in traditional designs. This operating mode drastically reduces average current and chip heat generation, effectively suppressing broadband thermal noise caused by temperature based on the principles of thermal noise physics, thereby improving the signal-to-noise ratio of the communication channel without increasing additional hardware costs.

[0017] Furthermore, this invention comprehensively considers the parasitic parameters and thermal memory effects of transistors. By superimposing feedforward differential compensation for parasitic capacitance into the control algorithm and employing an asymmetric filtering strategy of "fast attack and slow decay," the overshoot voltage overcomes the charging and discharging inertia of the gate capacitance, thereby improving the driving speed. On the other hand, it smooths the bias drop process, avoiding switching noise and spectral regeneration caused by frequent switching, thus ensuring the stability and spectral purity of the system in complex electromagnetic environments.

[0018] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below can be considered part of the inventive subject matter of this disclosure, provided that such concepts do not contradict each other.

[0019] The foregoing and other aspects, embodiments, and features of the teachings of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description

[0020] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the invention will now be described by way of example and with reference to the accompanying drawings, wherein: Figure 1 The time-domain waveform comparison chart demonstrates the effect of "negative delay / zero truncation"; Figure 2 AM-AM dynamic distortion characteristic curves demonstrate "high dynamics / high linearity"; Figure 3 The output spectrum characteristic comparison chart proves "low interference / pure spectrum"; Figure 4 The transient power consumption and thermal noise statistics prove "low power consumption / low thermal noise"; Figure 5 This is a schematic diagram of the process of the present invention. Detailed Implementation

[0021] The embodiments of the invention are described in detail below with reference to the accompanying drawings to clearly illustrate the structure, purpose, advantages, positional relationships, and connection methods of each component. It should be noted that the directional indications (such as "front," "back," "up," and "down") involved in this embodiment are based on the posture shown in the drawings and are only used to describe the relative positional relationships and movement of the components. If the posture changes, the directional indications will be adjusted accordingly. The term "connection" includes mechanical connections and electrical connections, and can be fixed connections, detachable connections, or indirect connections through an intermediate medium. The specific meaning is understood by those skilled in the art based on the context.

[0022] The core design intent of this invention is to break the zero-sum game between "high dynamic range" and "low static power consumption" in RF power amplifier design. Traditional technologies, in order to ensure no distortion, must keep the amplifier in a high-current "standby" state for a long time, resulting in huge thermal noise and energy waste. While conventional dynamic biasing techniques, such as envelope tracking, can reduce power consumption, due to the physical inertia of analog circuits, they cannot keep up with the rapid changes of broadband signals such as 5G, resulting in "tracking lag" and signal truncation.

[0023] This invention constructs a parallel "predictive-control" path in the digital baseband domain, utilizing the timing inference capability of a Long Short-Term Memory (LSTM) network, combined with the digital delay of the RF main path, to physically build a "negative delay" control mechanism. In short, the system trades digital storage for time, allowing the bias voltage to "predict the future" and be "in place" before the RF signal reaches the transistor gate. This enables the amplifier to safely "sleep" in deep Class AB or Class B, extremely low-noise states during most periods of no signal or small signal time, precisely waking up only at the moment a large signal arrives, thus achieving both extreme linearity and extremely low thermal noise.

[0024] Based on the above ideas, this embodiment proposes a communication system based on a low-noise, high-dynamic full-wave RF channel amplifier circuit. This system, through co-design of hardware and software, solves the trade-off between time delay hysteresis and linearity in traditional RF amplifiers under dynamic bias. The core hardware components of the system include: Digital baseband processing module: The hardware selection utilizes high-performance field-programmable gate arrays (FPGAs), such as the Xilinx UltraScale series, or multi-core heterogeneous DSPs. Its principle is that, as the "brain" of the system, it integrates parallel pipelined logic. It is responsible for real-time acquisition of in-phase (I) and quadrature (Q) baseband signals and running a pruned and quantized optimized lightweight long short-term memory (LSTM) inference engine. The parallel computing capability of the FPGA ensures microsecond-level inference speeds, meeting the real-time processing requirements of broadband signals such as 5G NR.

[0025] Digital delay buffer module: The hardware selection adopts a first-in-first-out (FIFO) memory built based on the FPGA's internal Block RAM. Its principle is to be connected in series in the main path of the RF signal to store and delay I / Q data sent to the RF upconversion link. Its delay depth is programmable and adjustable. Its advantage is that it provides the physical basis for achieving "negative delay" control. By artificially delaying the main signal, time is gained for LSTM operations and analog circuit response, allowing the bias voltage to be "in place" before the signal arrives.

[0026] Bias-controlled digital-to-analog converter and driver circuit: The hardware selection uses a high sampling rate (>200MSps), low-glitch DAC chip, paired with a high-voltage slew rate operational amplifier. Its principle is to receive digital control codes from the baseband processor, convert them into analog voltage signals, and drive the gate of the power amplifier. The advantage is that the high-voltage slew rate op-amp can rapidly charge and discharge the gate input capacitance of the transistor, ensuring a fast transient response of the bias voltage.

[0027] RF power amplifier: The hardware selection utilizes gallium nitride high electron mobility transistors or laterally diffused metal-oxide semiconductors. Its principle is to amplify the power of RF signals. In this embodiment, the amplifier's quiescent operating point is set at deep Class AB or even Class B. The advantage is extremely low quiescent current when there is no large signal, significantly reducing average power consumption and chip junction temperature, thus reducing the thermal noise problem according to the thermal noise formula. Physically, it reduces thermal noise.

[0028] The specific implementation steps of the communication method are as follows: The system's workflow consists of five key steps, integrating deep learning algorithms with RF circuit physical characteristic compensation: Step S1: Constructing multidimensional temporal feature vectors and adaptive normalization preprocessing To enable LSTM models to accurately capture the burst characteristics of radio frequency signals, especially high PAPR signals such as OFDM, it is necessary to construct time-series features that include historical trends and rates of change, rather than simply inputting the current value. Furthermore, preprocessing is required to prevent the neural network from saturating due to excessively large differences in the amplitude of the input data.

[0029] To calculate the instantaneous envelope modulus, firstly, the current sampling time is calculated in real time. n instantaneous envelope magnitude of baseband signal A [ n ]: ; A [ n ]: Indicates the first n The instantaneous amplitude of the digital baseband signal, i.e., the modulus, is calculated at each sampling time.

[0030] I [ n ]: indicates the first n The in-phase component signal value at each sampling time.

[0031] Q [ n ]: indicates the first n The quadrature component signal values ​​at each sampling time.

[0032] Then, dynamic normalization is performed by introducing a dynamic peak tracker to normalize the signal and obtain dimensionless values ​​suitable for neural network input. x [ n ]: ; x [ n ]: Represents the input signal value after normalization, with its range limited to [range missing]. β: represents the scaling safety factor, which is set to 1.1 in this embodiment to reserve dynamic margin and prevent overflow.

[0033] ϵ: Represents a very small positive constant to prevent the denominator from being zero.

[0034] The innovation of this embodiment in constructing multidimensional feature tensors lies in the introduction of "first-order difference features" to construct the feature tensor. U n .

[0035] ; U n : Represents the feature matrix input into the LSTM neural network.

[0036] L : Indicates the length of the selected time series, that is, the historical length of the network "lookback".

[0037] Δ x [ n ]: Represents the first-order difference characteristic of the signal. The physical meaning of is the rate of change of the signal.

[0038] Introducing differential features makes the network extremely sensitive to the "rising edge" of the signal, enabling it to predict burst pulses earlier.

[0039] The principle of phase space reconstruction is as follows: the nonlinear distortion of RF amplifiers, such as AM-AM and AM-PM distortion, depends not only on the current signal amplitude but also on the signal's "memory effect," i.e., its state at past moments. Constructing a phase space reconstruction includes historical sequences... The eigenvectors are actually reconstructed in a high-dimensional space to reconstruct the dynamic trajectory of the signal, enabling LSTM to "see" the full waveform of the signal.

[0040] Introducing a differential term is equivalent to introducing the concept of "velocity" from physics. For power amplifiers, the rapid rise time of a large signal is the region most prone to nonlinear distortion. Explicitly informing the neural network of the current signal's "rise time" can greatly improve the network's sensitivity to sudden pulses.

[0041] This step is the cornerstone of the entire intelligent control process. Without the "adaptive normalization" of the data, the LSTM network in the subsequent step S2 will fall into the gradient saturation region or an unstable state due to the excessively large dynamic range of the input data, such as from the mV level of a small signal to the V level of a large signal. Only by transforming the physical signal into statistical features through this step can the neural network work effectively.

[0042] This step significantly enhances the model's ability to capture "rare large signals," enabling accurate prediction of high-frequency envelopes even at low sampling rates. This is because traditional methods only input amplitude, requiring the network to "learn" the rate of change, which necessitates deep networks and extensive computation. This step, through manual feature engineering, directly injects "difference (velocity)" features, essentially giving the network a "hint," allowing a lightweight model to achieve the predictive accuracy of deep, large models, thus resolving the contradiction between limited hardware resources and high-precision prediction.

[0043] Step S2: Peak-holding prediction for the "future time window" based on lightweight LSTM This step utilizes the gating mechanism of LSTM to memorize long-term dependencies and predict future signal strength. Unlike traditional single-point prediction, this embodiment employs "interval maximum prediction" to provide a safety margin for the bias voltage and eliminate peak clipping.

[0044] First, the internal state of the LSTM is updated. The LSTM unit operations inside the FPGA follow the following mathematical model: ; ; ; ; : Represents the hidden state, reflecting the current dynamic characteristics.

[0045] : These represent the Sigmoid activation function and the hyperbolic tangent activation function, respectively.

[0046] ⊙: Represents the Hadamard product (multiplication of corresponding elements).

[0047] : These represent the trained weight matrix, recursive weight matrix, and bias vector, respectively.

[0048] In future peak prediction, the network's output layer predicts the future physical lead time. Maximum envelope value within : ; : Represents the maximum envelope value of the signal predicted by the network within a future time window.

[0049] max: indicates the operation of retrieving the maximum value.

[0050] This "envelope of envelopes" strategy ensures that even if there are tiny time jitters in the prediction, the generated bias voltage can completely cover the signal peak, achieving "zero truncation distortion".

[0051] LSTM solves the gradient vanishing problem of traditional RNNs through a "gating" structure. In radio frequency scenarios, the "forget gate" is responsible for filtering out noise and irrelevant historical fluctuations, while the "input gate" is responsible for capturing the burst features of the current frame.

[0052] Traditional regression prediction is point-to-point. This scheme changes to prediction... The maximum value within an interval is mathematically a "container of envelopes" strategy.

[0053] This step takes over the characteristic input from S1 and provides the "control target" for S3. It is the decision center for the conversion from the digital domain (information) to the analog domain (energy). The accuracy of the prediction directly determines whether the subsequent bias voltage is sufficient, that is, whether the amplifier will experience peak clipping.

[0054] This step achieves absolute safety control with "zero truncation distortion," ensuring that the amplifier will not produce intermodulation distortion even with minor timing jitter in network inference. This is because conventional dynamic biasing techniques aim for a "close" fit to the envelope; any slight prediction deviation, such as phase lag or lead, will cause the signal peak to exceed the bias voltage range, resulting in severe "hard truncation." This solution, by predicting the "maximum value within the time window," effectively constructs a "voltage protection umbrella" wider than the signal waveform. Although it sacrifices negligible efficiency—meaning the umbrella is slightly larger—it gains extremely high linearity and reliability, something traditional analog envelope tracking cannot achieve.

[0055] Step S3: Inverse bias mapping based on transistor parasitic parameter compensation This step transforms the neural network's predictions into actual voltage control signals. It requires considering not only the static nonlinearity of the transistor but also compensating for the dynamic charging and discharging hysteresis caused by the gate capacitance.

[0056] First, the static bias mapping is based on a polynomial fit of the transistor I-V curve: ; Character explanation: : Indicates the static base bias voltage.

[0057] c 0: Represents a constant term, set as the operating point of the transistor in deep Class AB or Class B. This ensures that the amplifier operates at extremely low power consumption and low thermal noise during small-signal conditions.

[0058] c 1, c 2: Represents the linear and nonlinear fitting coefficients.

[0059] Then, dynamic feedforward differential compensation is introduced, which includes a compensation term proportional to the rate of change of the signal: ; : Represents the final digital control word, corresponding to the actual gate voltage.

[0060] : Represents the first derivative of the predicted envelope over time, i.e., the rate of change.

[0061] λ: represents the compensation gain coefficient.

[0062] When the signal rises rapidly, this formula generates an additional voltage overshoot. This overshoot voltage forcibly accelerates the charging process of the gate capacitor, physically offsetting the inertia of the analog circuit and greatly increasing the bandwidth.

[0063] Transconductance of transistors It is gate voltage The nonlinear function. To ensure constant gain, i.e., linear amplification, the bias voltage must be based on... I−V The curve undergoes nonlinear pre-distortion.

[0064] Physical model of capacitor charging and discharging: RF power transistors (especially GaN HEMTs) have non-negligible gate-source parasitic capacitances. According to the formula I= To make the gate voltage Rapid changes necessitate the provision of enormous instantaneous drive current.

[0065] This step is crucial in converting the "mathematical prediction value" output by S2 into a "physical control quantity". S2 solves the problem of "how much voltage is needed", while S3 solves the problem of "how to quickly get the voltage in place".

[0066] This step overcomes the physical bandwidth limitation of the bias circuit, enabling narrowband bias circuits to drive broadband RF signals, such as 100MHz. This is because traditional techniques are limited by the slew rate of the operational amplifier and cannot follow fast signals. The feedforward differential compensation term in this step... In reality, it's a "pre-emphasis" signal. When a large signal is predicted, the system intentionally outputs an "overshoot voltage" much higher than the target value, using this overshoot to forcibly "fill" the gate capacitance, thus offsetting physical inertia. This approach of "compensating for hardware defects with software algorithms" produces an unexpected bandwidth expansion effect.

[0067] Step S4: Precise timing alignment of the RF main path and the bias control path By introducing digital delay into the main path, a "negative delay" system is constructed to solve the response lag problem of traditional dynamic bias.

[0068] The timing constraint formula is as follows: ; : Indicates the delay duration set for the digital delay buffer.

[0069] : Indicates the inherent transmission delay of the radio frequency signal path.

[0070] : Represents the total signal processing delay of the control path, including LSTM operation + DAC conversion + op-amp setup.

[0071] : Indicates the time margin for establishment.

[0072] Advantages: It allows the bias voltage to be established stably before the RF signal reaches the transistor gate. For RF signals, the bias circuit seems to have the ability to "predict the future," completely eliminating dynamic distortion.

[0073] In the physical world, the effect cannot precede the cause. However, in digital signal processing, by introducing a delay... We have turned the "present" into "history". For the delayed radio frequency signal, the undelayed bias control signal comes from the "future".

[0074] Analog circuits (DACs, op-amps) need time to reach a steady state. This time must be allowed. This ensures that the bias voltage is completely stable and free from any transient fluctuations the instant the radio frequency signal reaches the transistor gate.

[0075] This is the "spatiotemporal hub" of the entire system. It coordinates the speed differences between S2 (LSTM computation flow, slow) and S3 (analog drive flow, slow) and the main RF path (light speed propagation, fast). Without this step, even the most accurate predictions will suffer from severe AM-PM distortion due to phase misalignment.

[0076] This step completely eliminates AM-PM (amplitude-phase) distortion caused by dynamic bias, achieving excellent EVM (error vector amplitude) without the need for complex digital predistortion (DPD). This is because in traditional envelope tracking techniques, the bias voltage changes "simultaneously" with the signal, and these voltage changes cause variations in the transistor junction capacitance. Changes in voltage cause phase rotation. This solution uses a "negative delay" to ensure the bias voltage is stable before the signal arrives. This means that at the moment the signal passes through the transistor, the transistor's state is static, not dynamically changing, thus physically eliminating the path to AM-PM distortion.

[0077] Step S5: Asymmetric hysteresis filtering To smooth the control voltage and avoid spectral regeneration and thermal memory effects caused by frequent switching, a nonlinear digital filter was designed.

[0078] Employing a fast-attack, slow-decay logic: ; : This represents the smooth control signal that is ultimately output to the DAC.

[0079] : Indicates the output at the previous time step.

[0080] α : Represents the attenuation coefficient, which takes a small value, such as 0.01.

[0081] First line (fast attack): Respond immediately when a large signal arrives to ensure linearity.

[0082] The second line (slow decay): The signal decreases slowly as it falls back.

[0083] This hysteresis characteristic avoids "video bandwidth" noise while smoothing out transistor junction temperature changes and reducing low-frequency distortion caused by thermal memory effects.

[0084] Rapid fluctuations in bias voltage are essentially amplitude modulation (AM) of the radio frequency (RF) signal. If the bias voltage drops too quickly, its high-frequency components will mix into the RF band, creating "video bandwidth noise".

[0085] Chip temperature The changes in current are much slower than those in electrical signals. Frequent and drastic current fluctuations can cause oscillations in the temperature gradient on the chip surface, resulting in a thermal memory effect and increased low-frequency noise.

[0086] This is the final "security check" before output. S2 and S3 prioritize "speed" and "accuracy," while S5 prioritizes "stability" and "cleanliness." It is responsible for correcting any oversensitivity that may have occurred in the preceding steps, ensuring the system's cleanliness in the frequency domain.

[0087] This step, while maintaining high efficiency, lowers the amplifier's output noise floor by more than 10dB and eliminates the "shark fin" spectral regeneration commonly found in dynamic biasing techniques. This is because "fast attack" ensures large signals are not distorted; "slow decay" not only smooths the control voltage but, more importantly, creates a thermal buffer. By artificially slowing down the rate of current decay, the junction temperature change of the transistor is smoothed out (equivalent to increasing heat capacity). This temperature stability directly leads to gain stability and a reduction in thermal noise (4kTRB), a thermal-electrical synergistic optimization effect that is difficult to achieve through simple circuit design.

[0088] In summary, the working principle of this system can be summarized as "parallel splitting, delay-forward prediction, and physical feedforward".

[0089] When the baseband I / Q signal enters the FPGA, it is copied into two paths: Signal path: Entering the FIFO and waiting in a queue, with a delay of tens of nanoseconds artificially introduced.

[0090] Control Path: Immediately enter the preprocessing and LSTM inference modules. Utilizing LSTM to learn the timing characteristics of the signal, the system predicts subsequent large signal peaks within microseconds and calculates the overshoot voltage that can overcome capacitive inertia by combining derivative compensation.

[0091] Because the signal path is delayed, the control voltage has ample time to be converted into an analog high voltage by the DAC and driver circuitry. When the RF signal in the FIFO is finally released and reaches the power amplifier gate, the optimal bias voltage is already "waiting" there. After the signal ends, the bias voltage slowly drops back to a low-power state, waiting for the next pulse.

[0092] Leveraging the precise prediction capabilities of LSTM, the amplifier operates in deep Class AB or Class B mode for over 90% of its off-peak time, significantly reducing static power consumption. The lower junction temperature directly reduces electron thermal motion, thereby physically lowering the thermal noise floor and improving receiver sensitivity.

[0093] The "negative delay" mechanism completely solves the bandwidth limitation and time delay problems of analog envelope tracking technology. Even when faced with broadband burst signals above 100MHz, it can guarantee zero-delay response of bias voltage, eliminating truncation distortion and AM-PM distortion.

[0094] The introduced "fast attack and slow decay" filtering and feedforward differential compensation effectively suppress adjacent channel interference (ACPR) and switching noise caused by bias modulation, ensuring a clean transmission spectrum.

[0095] This embodiment provides an experimental scheme designed to rigorously verify the effectiveness of the present invention in solving the two core problems of "time delay distortion" and "high power consumption thermal noise".

[0096] I. Experimental Environment Setup and Preparation Hardware platform setup: Build a test board that includes an FPGA as a digital baseband processor, running LSTM inference, a high-speed broadband DAC, an RF upconversion link, and an RF power amplifier based on gallium nitride (GaN) transistors.

[0097] Configure a programmable digital delay line FIFO in the RF main path, initially set to 20ns.

[0098] Connects to a four-channel high-precision oscilloscope, spectrum analyzer, vector network analyzer (VNA), and high-sensitivity thermal imager.

[0099] The model deployment collects typical 5G NR (New Radio) OFDM signal data as the training set and trains the LSTM model offline.

[0100] The trained LSTM weights and nonlinear bias mapping table are burned into the FPGA.

[0101] II. Specific Experimental Procedures and Result Analysis Experiment 1: Verification of Time-Domain Response and Negative Delay Mechanism (Results) Figure 1 ) Experimental steps: Signal input: The signal source generates a burst pulse radio frequency signal with an extremely fast rise time of <10ns.

[0102] Control group settings: Setting A: Traditional dynamic bias: The LSTM prediction function and digital delay in the FPGA are turned off, and the bias voltage is directly controlled by the traditional envelope detection method.

[0103] Setting B in this invention: Enable the LSTM prediction engine and enable the digital delay function of the RF main path.

[0104] Data acquisition: Using an oscilloscope, probes simultaneously detect two test points: ① the gate bias voltage of the power amplifier; ② the envelope of the radio frequency signal reaching the input of the power amplifier.

[0105] Figure 1 Results Analysis: Observations show that in setting A, the red dashed bias voltage waveform occurs significantly later than the RF signal peak, resulting in the RF signal head being "flattened." In setting B, the oscilloscope shows that the bias voltage (green solid line) begins to rise approximately 2.5 microseconds before the RF signal (blue solid line) arrives, and remains at a high potential when the signal peak arrives.

[0106] Experiments have demonstrated the effectiveness of the "negative delay" control mechanism of this invention. By trading digital delay for prediction time, the bias voltage achieves a physical "lead time," completely solving the tracking lag problem caused by bandwidth limitations in traditional technologies and eliminating truncation distortion.

[0107] Experiment 2: AM-AM Dynamic Linearity Test (Results) Figure 2 ) Experimental steps: Signal input: Input a continuous wave signal with power linearly scanned from -20dBm to +30dBm.

[0108] Mode switching: Mode A: Traditional fixed bias (shallow AB class). Mode B: Traditional analog envelope tracking. Mode C: The method of this invention (predictive bias + parasitic parameter compensation).

[0109] Data logging: The amplifier gain under different input powers was measured using a vector network analyzer, and the AM-AM characteristic curves were plotted.

[0110] Figure 2 Results Analysis: Observations show that Mode B (red curve) exhibits a significant gain drop in the high-power region, indicating compression. This suggests that hysteresis leads to nonlinearity under large signals. In contrast, Mode C (blue curve) shows a gain curve that almost coincides with the ideal reference (gray line) across the entire power range, without significant compression.

[0111] This demonstrates that the present invention exhibits excellent linearity over a high dynamic range. The precise prediction of the LSTM, combined with feedforward differential compensation (to counteract capacitance effects), allows the amplifier to maintain a constant gain even under large signal conditions.

[0112] Experiment 3: Broadband Spectrum Purity Test (Results) Figure 3 ) Experimental steps: Signal input: Input a 5G NR modulated signal with a bandwidth of 100MHz.

[0113] Comparative test: The "Fast-Attack Slow-Decay" filtering algorithm of this invention is enabled.

[0114] Disable the filtering algorithm and drive the system directly using only the raw predicted values.

[0115] Measurement: The adjacent channel power leakage ratio (ACPR) within a 20MHz range to the left and right of the center frequency was observed using a spectrum analyzer.

[0116] Figure 3 Results Analysis: Observations show that when filtering is disabled, there is high spectral regeneration on both sides of the main peak (similar to a shark fin). After enabling the method of this invention (green line), the side lobes on both sides of the main peak decrease sharply, and the adjacent channel interference is reduced by about 15 dB compared to the traditional method.

[0117] This demonstrates that the "fast attack, slow decay" filtering strategy of this invention effectively suppresses video bandwidth noise introduced by rapid switching of bias voltage, ensures the purity of the output spectrum, and reduces interference to adjacent channels.

[0118] Experiment 4: Comprehensive Test of Transient Power Consumption and Thermal Noise (Results) Figure 4 ) Experimental steps: Scenario simulation: Simulates real communication traffic, which is sparse, meaning that data transmission and idle waiting alternate.

[0119] Parameter monitoring: A series current probe is used to record the instantaneous waveform of the drain current. A noise analyzer is used to measure the noise figure of the amplifier when there is no large signal input. A thermocouple or thermal imager is used to record the stable temperature of the chip surface.

[0120] Observation results (top half): The current of a conventional Class A bias is a continuous high straight line (red). In contrast, the current waveform of this invention (blue) stays close to the bottom for most of the time (deep Class AB state), only rising as needed when a signal pulse occurs. The shaded area shows a saving of approximately 60%-70% in energy consumption.

[0121] Observation results (bottom half): Due to the reduction in average power consumption, the chip junction temperature decreased by approximately 25°C. The noise histogram shows that the thermal noise floor of this invention (blue bar on the right) is significantly lower than that of the conventional method at high temperatures (red bar on the left).

[0122] The conclusion proves that the formula has been verified. The physical effect is that by keeping the amplifier in an extremely low quiescent current state during idle periods, the invention significantly reduces heat generation, thereby physically reducing thermal noise and improving the signal-to-noise ratio of the receiver.

[0123] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A method of communication based on a low-noise high-dynamic full-wave radio frequency channel amplification circuit, characterized in that, The method comprises the following steps: Step S1, real-time sampling of in-phase components and quadrature components of a radio frequency signal in a digital baseband domain, and constructing a multi-dimensional time sequence feature vector containing historical states and change rates; Step S2, inputting the multi-dimensional time sequence feature vector into a pre-trained long short-term memory (LSTM) model, using the gating mechanism of the long short-term memory network for time sequence reasoning, and predicting signal envelope peaks in a future preset time window; Step S3, establishing an inverse mapping relationship between transistor bias voltage and signal envelope, generating a corresponding dynamic bias control signal based on the predicted signal envelope peak, and superimposing a compensation component for transistor parasitic parameters; Step S4, introducing a digital delay in the main path of the radio frequency signal, so that the generated dynamic bias control signal is preloaded to the transistor gate before the radio frequency signal reaches the amplifier, realizing negative delay bias control; Step S5, performing asymmetric smoothing filtering processing on the dynamic bias control signal, and then driving the radio frequency amplifier through digital-to-analog conversion, so that it is in a low-noise working state while maintaining a high dynamic range.

2. The communication method according to claim 1, characterized by, In step S1, the specific process of constructing a multi-dimensional time sequence feature vector includes: Calculate the arithmetic square root of the sum of squares of the in-phase component and the quadrature component to obtain the instantaneous envelope modulus; Use a sliding time window to real-time statistics signal peak, and dynamically normalize the instantaneous envelope modulus to eliminate the influence of input power fluctuations on the network model; Calculate the difference between the current normalized envelope value and the previous normalized envelope value to obtain a first-order difference feature, and combine the current normalized envelope value, the normalized envelope sequence at the historical time, and the first-order difference feature to form the multi-dimensional time sequence feature vector.

3. The communication method according to claim 1, wherein, In step S2, predicting the signal envelope peak in the future preset time window means: The output layer of the long short-term memory network model does not directly predict the value at a single time, but predicts the maximum envelope amplitude in the entire time period corresponding to the physical advance amount in the future through a fully connected layer regression, ensuring that the generated bias voltage can completely cover the highest point of signal fluctuations in that time period.

4. The communication method according to claim 1, characterized by, In step S2, the long short-term memory network model adopts a lightweight structure: Use the forget gate to determine how much historical memory information to retain from the cell state at the previous time, use the input gate to determine how much new information in the current time feature vector to update to the cell state, and calculate the current hidden layer output by combining the updated cell state through the output gate, to capture the long-time dependence and burst characteristics of the radio frequency signal.

5. The communication method according to claim 1, wherein, In step S3, establishing an inverse mapping relationship between transistor bias voltage and signal envelope includes: According to the transfer characteristic curve of the radio frequency amplification transistor, a polynomial fitting method is used to construct a static mapping function; Set the constant term of the mapping function to correspond to the deep AB or B class working point of the transistor, so that when the predicted envelope is zero or small signal, the transistor is in an extremely low static current state to suppress thermal noise.

6. The communication method of claim 1, wherein, In step S3, superimposing a compensation component for transistor parasitic parameters means: Calculate the rate of change of the predicted signal envelope peak over time; The rate of change is multiplied by a time constant coefficient related to the bias circuit establishment time and the transistor gate input capacitance to obtain a feedforward differential compensation voltage; The feedforward differential compensation voltage is superimposed on the voltage generated by the static mapping function to generate an overshoot voltage to accelerate the charging and discharging process of the gate capacitance.

7. The communication method of claim 1, wherein, In step S4, the specific method of negative delay bias control is: Calculate the total signal processing delay of the control channel, which includes the long short-term memory network inference time, the digital-to-analog conversion time and the analog bias circuit establishment time; The depth of the digital delay buffer of the radio frequency signal main channel is configured so that the delay amount of the main channel is greater than or equal to the sum of the signal processing total delay of the control channel and the safe establishment time margin, thereby ensuring that the establishment of the bias voltage is ahead of the arrival of the radio frequency signal on the time axis.

8. The communication method of claim 1, wherein, In step S5, the asymmetric smoothing filter processing of the dynamic bias control signal adopts the fast attack and slow decay strategy: When the bias control voltage generated at the current time is higher than the output voltage at the last time, the filter is in a straight-through state, and the output voltage immediately follows the current bias control voltage and rises; When the bias control voltage generated at the current time is lower than or equal to the output voltage at the last time, the filter is in a decay state, and the output voltage slowly decreases relative to the output voltage at the last time according to a preset decay coefficient.

9. The communication method according to claim 8, wherein, The asymmetric smoothing filter processing is used to: Avoid frequent jumps of the bias voltage caused by small jitter of the predicted envelope, suppress the switching noise and modulation sideband generated thereby, and slow down the drastic fluctuations of the power amplifier transistor junction temperature, thereby reducing the thermal memory effect.

10. A communication system implementing the method of any one of claims 1 to 9, characterized in that, It includes: A digital baseband processing module for performing signal sampling, feature extraction and long short-term memory network inference; A digital delay buffer module connected in series in the radio frequency signal main channel for providing programmable digital delay; A bias control module including a digital-to-analog converter and a bias drive circuit for converting the inference result into an analog bias voltage and applying it to the amplifier; A radio frequency power amplifier whose gate bias voltage is dynamically adjusted by the bias control module, and whose signal input end is connected to the output end of the digital delay buffer module.

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