A low-latency chip-level optoelectronic hybrid integrated network and a communication method thereof

Abstract

The application discloses a low-latency chip-level optoelectronic hybrid integrated network and a communication method thereof, and belongs to the technical field of communication, comprising: a plurality of dies, the upper surface of each die comprising a plurality of cluster structures; each cluster structure comprising a plurality of communication cores and one routing node; the lower surface of each die comprising a signal processing unit, a plurality of optical transmitters and a plurality of optical detectors; the signal processing unit being electrically connected with the plurality of optical transmitters and the plurality of optical detectors; further comprising: a substrate, the substrate comprising an inner ring optical waveguide bus, an outer ring optical waveguide bus and a plurality of optical interfaces; the inner ring optical waveguide bus and the outer ring optical waveguide bus being provided with optical signals of a plurality of wavelengths; the substrate being located below the plurality of dies, and two optical interfaces being arranged below each die. The application realizes non-blocking optical signal transmission through the combination of optical interfaces and optical waveguide buses, and reduces the transmission latency of optical communication.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, specifically relating to a low-latency chip-level optoelectronic hybrid integrated network and its communication method. Background Technology

[0002] With the continuous evolution of high-performance computing technology and the exponential growth of data capacity, traditional on-chip buses are gradually revealing their shortcomings in multi-core systems. Their bandwidth expansion is limited, making it difficult to meet the demands of large-scale concurrent transmission. Furthermore, as the number of cores increases, signal latency accumulates, severely restricting system response speed. Network-on-Chip (NoC) introduces a communication network architecture into chip design, achieving efficient data interaction through topology routing mechanisms, supporting large-scale concurrent data communication, and offering greater flexibility and fault tolerance. However, when the number of communication cores is further increased, the total bandwidth will reach its physical limit. Simultaneously, the extended communication distance and upgraded transmission requirements will cause significant electromagnetic crosstalk, which, combined with the thermal accumulation effect of centralized interconnects, will directly affect the stability and reliability of the chip.

[0003] The emergence of chip-level optoelectronic hybrid integrated networks provides a key path to solving the above problems. It fully leverages the core advantages of optical signals—high transmission speed, strong anti-interference capability, and low energy density—while maintaining compatibility with electrical signals in short-distance transmission, supporting complex routing layouts and dynamic configurations. Compared to traditional electrical interconnect NoCs, this architecture offers a comprehensive advantage of greater bandwidth, higher data throughput, lower latency, and lower power consumption, making it suitable for complex scenarios such as ultra-large-scale computing.

[0004] Optical communication circuits typically employ a network model consisting of optical links and optical routers, or an optical waveguide bus combining optical routers and optical interfaces. Regarding core components, optical routers and interfaces are mostly built upon tunable microring resonators, and their operation requires precise control via electrical signals. Furthermore, the physical characteristics of optical signals mean they cannot be temporarily stored when routing nodes are congested, unlike electrical signals. Therefore, communication algorithms designed based on existing on-chip optoelectronic hybrid network architectures all involve the process of configuring optical links using electrical signals. The latency generated by this electrical configuration step accounts for a significant portion of the overall transmission latency, becoming a key bottleneck restricting system performance improvement. Therefore, optimizing the electrical configuration of optical paths is crucial for reducing end-to-end transmission latency in chip-level optoelectronic hybrid integrated networks. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a low-latency chip-level optoelectronic hybrid integrated network machine communication method.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention provides a low-latency chip-level optoelectronic hybrid integrated network, comprising: multiple dies, each die having multiple cluster structures on its upper surface; each cluster structure having multiple communication cores and one routing node; each die having a signal processing unit, multiple optical transmitters and multiple photodetectors on its lower surface; the signal processing unit being electrically connected to the multiple optical transmitters and multiple photodetectors.

[0008] It also includes: a substrate, which includes an inner ring optical waveguide bus, an outer ring optical waveguide bus and multiple optical interfaces; the substrate is located below multiple dies, and each die has two optical interfaces below it.

[0009] Optionally, the multiple clustered routing nodes are interconnected via metal interconnects.

[0010] Optionally, the multiple clustered routing nodes are connected to the signal processing unit on the lower surface of the die via TSV.

[0011] Optionally, each die has two optical interfaces, one of which is connected to the inner ring optical waveguide bus, and the other is connected to the outer ring optical waveguide bus.

[0012] In a second aspect, the present invention provides a low-latency chip-level optoelectronic hybrid integrated network communication method, applied to the low-latency chip-level optoelectronic hybrid integrated network described in the first aspect, the method comprising:

[0013] The source communication core on the source die sends the first data to the source routing node; wherein, the source communication core and the source routing node belong to the same cluster structure;

[0014] The source routing node transmits the first data to the signal processing unit of the source die via TSV;

[0015] After the signal processing unit of the source die transmits the first data to the optical transmitter of the source die, it converts the first data into a first optical signal through the optical transmitter and sends it to the inner ring optical waveguide bus or the outer ring optical waveguide bus.

[0016] The inner or outer ring optical waveguide bus transmits the first optical signal to the optical interface of the target die, where the first optical signal is filtered and transmitted to the photodetector of the target die.

[0017] The photodetector of the target die converts the filtered first optical signal into a second electrical signal and sends it to the signal processing unit of the target die.

[0018] The signal processing unit of the target die sends the second electrical signal to the target routing node of the target die via TSV;

[0019] The destination routing node transmits the second electrical signal to the destination communication core; wherein, the destination communication core and the destination routing node belong to the same cluster structure;

[0020] The destination communication core generates a response signal based on the second electrical signal and returns the response signal to the source communication core via the outer ring optical waveguide bus or the inner ring optical waveguide bus in the same communication mode.

[0021] Optionally, the electrical communication process on the source die includes:

[0022] When the source communication core generates a communication request, it creates a routing request signal and sends it to the source routing node;

[0023] The source routing node calculates the output port for the output signal based on the routing request signal and the XY-YX adaptive routing algorithm;

[0024] When the output port is not blocked, an ACK signal is returned to the source communication core, and a new routing request signal is sent to the target routing node corresponding to the output port; wherein, the source routing node and the target routing node are located on the same die; the target routing node is the routing node on the source die;

[0025] After receiving the ACK signal, the source communication core sends the second data to the source routing node and creates a release signal for the source communication core.

[0026] Optionally, the operation process of the XY-YX adaptive routing algorithm includes:

[0027] When the source routing node receives the routing request signal, it compares the X coordinates of the target routing node and the source routing node using the XY routing algorithm, and then compares the Y coordinates of the target routing node and the source routing node to obtain the first output port for outputting the signal.

[0028] When the first output port is blocked, the Y coordinates of the target routing node and the source routing node are compared by the YX routing algorithm, and then the X coordinates of the target routing node and the source routing node are compared to obtain the second output port for outputting the signal.

[0029] When both the first output port and the second output port are blocked, the number of blocking times of the first output port and the second output port are compared. The blocking information of the output port with fewer blocking times is loaded onto the NAK signal and returned to the source communication core.

[0030] Optionally, when both the first output port and the second output port are blocked, after comparing the blocking counts of the first output port and the second output port respectively, selecting the output port with fewer blocking counts, loading the blocking information onto the NAK (Negative Acknowledgment) signal, and returning it to the source communication core, the method further includes:

[0031] When the source communication core receives the NAK signal, it buffers the second data into the source communication core.

[0032] Based on the blocking information in the NAK signal, a corresponding re-request delay is generated;

[0033] After re-requesting the delay, the routing request signal is sent again to the source routing node.

[0034] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0035] In the above technical solution, the present invention configures an optical interface and uses multiple wavelengths of optical signals to achieve unobstructed optical signal transmission between dies by combining inner / outer ring optical waveguide buses, thereby reducing the transmission delay of inter-die optical communication.

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of a low-latency chip-level optoelectronic hybrid integrated network provided in an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of an inner / outer ring optical waveguide bus using six wavelength optical signals to achieve optical signal transmission, provided by an embodiment of the present invention.

[0039] Figure 3 This is a flowchart of a low-latency chip-level optoelectronic hybrid integrated network communication method provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of an inter-die communication process provided in an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of an XY-YX adaptive routing algorithm for addressing provided in an embodiment of the present invention.

[0042] Explanation of reference numerals in the attached figures

[0043] 1. Bare die; 2. Cluster structure; 3. Substrate; 4. Communication core; 5. Routing node; 6. Optical transmitter; 7. Photodetector; 8. Signal processing unit; 9. Optical interface. Detailed Implementation

[0044] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0045] Figure 1 This is a schematic diagram of the structure of a low-latency chip-level optoelectronic hybrid integrated network provided in an embodiment of the present invention, as shown below. Figure 1 As shown, it may include: multiple bare dies 1, the upper surface of each bare die 1 includes multiple cluster structures 2; each cluster structure 2 includes multiple communication cores 4 and one routing node 5; the lower surface of each bare die 1 includes a signal processing unit 8, multiple optical transmitters 6 and multiple photodetectors 7; the signal processing unit 8 is electrically connected to the multiple optical transmitters 6 and the multiple photodetectors 7.

[0046] The aforementioned chip-level optoelectronic hybrid integrated network also includes: a substrate 3, which includes an inner ring optical waveguide bus, an outer ring optical waveguide bus, and multiple optical interfaces 9; the inner ring optical waveguide bus and the outer ring optical waveguide bus are equipped with optical signals of multiple wavelengths; the substrate 3 is located below multiple dies 1, and each die 1 is provided with two optical interfaces 9.

[0047] Optionally, the routing nodes 5 of the multiple cluster structures 2 are interconnected with each other via metal interconnects; the routing nodes 5 of the multiple cluster structures 2 are connected to the signal processing unit 8 on the lower surface of the bare die 1 via TSV.

[0048] Optionally, each die 1 has two optical interfaces 9 below it, one of which is connected to the inner ring optical waveguide bus, and the other is connected to the outer ring optical waveguide bus.

[0049] For example, such as Figure 1As shown, the upper layer of the low-latency chip-level optoelectronic hybrid integrated network includes four dies 1. Each die 1 has nine cluster structures 2 on its front side, and each cluster structure contains four communication cores 4 and one routing node 5. The routing nodes 5 in the nine cluster structures 2 are interconnected via metal interconnects. Each die 1 has a signal processing unit 8, three specific-wavelength optical transmitters 6, and three specific-wavelength photodetectors 7 on its back side. The routing nodes 5 are connected to the signal processing unit 8 on the back side of the die 1 via TSVs (Through-Silicon Vias). The signal processing unit 8 is connected to the three optical transmitters 6 and the three photodetectors 7. The lower substrate 3 of this integrated network includes an inner-ring optical waveguide bus, an outer-ring optical waveguide bus, and eight optical interfaces 9. Two optical interfaces 9 are located below each die 1, connected to the inner-ring and outer-ring optical waveguide buses respectively, and can transmit or receive optical signals of specific wavelengths from other dies 1.

[0050] It is worth mentioning that, Figure 2 This is a schematic diagram illustrating the optical signal transmission process using six wavelength optical signals in an inner / outer ring optical waveguide bus, as provided in an embodiment of the present invention. Figure 2 As shown, each line represents an optical signal of a certain wavelength. By configuring optical interface 9 (for example, this optical interface can be connected to the on-chip multi-dimensional (de)multiplexer of the microring resonator using an adiabatic structure), it is combined with the inner / outer ring optical waveguide bus to achieve unobstructed optical signal transmission between the four bare dies I, II, III and IV using six different wavelength optical signals.

[0051] Figure 3 This is a flowchart of a low-latency chip-level optoelectronic hybrid integrated network communication method provided by an embodiment of the present invention, such as... Figure 3 As shown, the method may include the following steps:

[0052] S301, The source communication core on the source die sends the first data to the source routing node; wherein, the source communication core and the source routing node belong to the same cluster structure;

[0053] S302, The source routing node transmits the first data to the signal processing unit of the source die via TSV;

[0054] S303, after the signal processing unit of the source die transmits the first data to the optical transmitter of the source die, the first data is converted into a first optical signal by the optical transmitter and then sent to the inner ring optical waveguide bus or the outer ring optical waveguide bus.

[0055] S304, the inner ring optical waveguide bus or the outer ring optical waveguide bus transmits the first optical signal to the optical interface of the target die, filters the first optical signal in the optical interface and transmits it to the photodetector of the target die;

[0056] S305, the photodetector of the target die converts the filtered first optical signal into a second electrical signal and sends it to the signal processing unit of the target die;

[0057] S306, The signal processing unit of the destination die sends the second electrical signal to the destination routing node of the destination die via TSV;

[0058] S307. The destination routing node transmits the second electrical signal to the destination communication core; wherein, the destination communication core and the destination routing node belong to the same cluster structure;

[0059] S308. The destination communication core generates a response signal based on the second electrical signal and returns the response signal to the source communication core through the outer ring optical waveguide bus or the inner ring optical waveguide bus in the same communication mode.

[0060] It is understandable that S301 to S308 represent the optical signal transmission process between the bare dies. Specifically, Figure 4 This is a schematic diagram of an inter-die communication process provided by an embodiment of the present invention, such as... Figure 4 As shown, the source communication core on the source die first sends the first data to the source routing node in the same cluster structure. The source routing node transmits the first data to the signal processing unit of the source die via TSV. This module loads the first data at a specific wavelength and sends it to the inner / outer ring optical waveguide bus via an optical transmitter. The data is transmitted along a specific direction in the inner / outer ring optical waveguide bus. At the optical interface below the destination die, a frequency-selective filtered photodetector receives the specific wavelength signal, and the signal processing unit then receives the first data. This first data can be transmitted via TSV to the destination routing node in the destination cluster structure, and then to the destination communication core. When the destination communication core receives the first data sent by the source die, it transmits an acknowledgment signal to the source communication core via the outer / inner ring optical waveguide bus using the same communication process, completing one inter-die optical signal transmission. It is worth mentioning that when the transmission path of the first optical signal uses the inner ring optical waveguide bus, the return of the response signal uses the outer ring optical waveguide bus; similarly, when the transmission path of the first optical signal uses the outer ring optical waveguide bus, the return of the response signal uses the inner ring optical waveguide bus.

[0061] Optionally, the electrical communication process on the source die includes:

[0062] When the source communication core generates a communication request, it creates a route request signal and sends it to the source routing node;

[0063] The source routing node calculates the output port for the output signal based on the routing request signal and the XY-YX adaptive routing algorithm;

[0064] When the output port is not blocked, an ACK signal is returned to the source communication core, and a new route request signal is sent to the target routing node corresponding to the output port; wherein, the source routing node and the target routing node are located on the same die; the target routing node is the routing node on the source die;

[0065] After receiving the ACK signal, the source communication core sends the second data to the source routing node and creates a release signal for the source communication core.

[0066] It is understood that the above steps constitute the electrical communication process between different routing nodes on the source die. In the integrated network architecture of this invention, the electrical communication process on the die is as follows: Figure 4 As shown, when the source communication core generates an on-chip communication request, it creates a routing request signal and sends this signal from the source node (i.e., the source communication core) to routing node A in the source cluster structure. Upon receiving the routing request signal from the source communication core, routing node A calculates the output port using the XY-YX adaptive routing algorithm. If the output port is not blocked, it returns an ACK signal to the source communication core and initiates a new routing request signal to the routing node B corresponding to that output port. Simultaneously, the source node receives the ACK signal from routing node A, sends the second data to the source routing node A, and creates a release signal for the source communication core to send other data.

[0067] Optionally, the operation process of the XY-YX adaptive routing algorithm includes:

[0068] When the source routing node receives a routing request signal, it compares the X coordinates of the target routing node and the source routing node using the XY routing algorithm, and then compares the Y coordinates of the target routing node and the source routing node to obtain the first output port for outputting the signal.

[0069] When the first output port is blocked, the Y coordinates of the target routing node and the source routing node are compared by the YX routing algorithm, and then the X coordinates of the target routing node and the source routing node are compared to obtain the second output port for output signal;

[0070] When both the first output port and the second output port are blocked, the number of blocking times of the first output port and the second output port are compared. The blocking information of the output port with fewer blocking times is selected, loaded onto the NAK signal, and returned to the source communication core.

[0071] When both the first output port and the second output port are blocked, the method of the present invention further includes: comparing the number of blocking times of the first output port and the second output port, selecting the output port with fewer blocking times to load the blocking information onto the NAK signal, and returning it to the source communication core;

[0072] When the source communication core receives the NAK signal, it buffers the second data into the source communication core;

[0073] Based on the blocking information in the NAK signal, a corresponding re-request delay is generated;

[0074] After re-requesting the delay, send the routing request signal to the source routing node again.

[0075] Specifically, the operation process of the XY-YX adaptive algorithm proposed in this invention includes: when the source routing node generates an on-chip routing request, it first caches the data in the current source routing node and sends a routing request signal to the target routing node. The target routing node selects its output port number by first comparing the X coordinates of the source routing node and the target routing node, and then comparing the Y coordinates. If the corresponding first output port is not blocked, it returns an ACK signal to the source routing node and sends a routing request signal to the target routing node connected to that output port. If the port is blocked, the YX algorithm is used to first compare the Y coordinates of the source routing node and the target routing node, and then compare the X coordinates. If the corresponding second output port is not blocked, it returns an ACK signal to the source routing node and sends a routing request signal to the target routing node connected to that second output port. If the output ports calculated by the above two algorithms are both blocked, the blocking counts of the first and second output ports are compared, and the blocking information of the port with fewer blocking counts is loaded onto the NAK signal and returned to the source communication core. If the source communication core receives an ACK signal, it sends the data to the source routing node and occupies the port. If the source communication core receives a NAK signal, it buffers the data and generates a corresponding re-request delay t based on the number of blocking events in the NAK signal. After delay t, it repeats the above route request operation. The source communication core will not release the port until it receives an ACK signal from the routing node and completes data transmission. This routing process is repeated until the XY-YX adaptive routing algorithm completes the final ACK signal transmission, successfully receives data, and releases the port, thus completing one on-chip electrical communication cycle.

[0076] It is worth mentioning that when the sum of the x and y coordinates of any routing node is odd, and the routing request signal has occupied any output port of the routing node, when the number of times the output port is blocked reaches the set blocking number threshold, the routing information and data information of the output port are cached, and the output port is released. After the preset delay time is reached, the output port is re-requested to be occupied.

[0077] Figure 5 This is a schematic diagram of an XY-YX adaptive routing algorithm for addressing provided in an embodiment of the present invention, as shown below. Figure 5As shown, the low-latency chip-level optoelectronic hybrid integrated network of the present invention includes nine routing nodes, namely a, b, c, d, e, f, g, h, and i. Each routing node has four communication cores. For example, a1, a2, a3, and a4 are the four communication cores of routing node a, and e1, e2, e3, and e4 are the four communication cores of routing node e. The routing process for routing node a to transmit data to other clustered routing nodes e on the same die refers to the electrical communication process on the die. It is worth mentioning that routing node a can act as a source routing node in the electrical communication process.

[0078] For example, when routing node b transmits data to routing node c, routing node b first generates a route request signal. Upon receiving the route request signal, routing node c calculates the output port using the XY-YX adaptive routing algorithm. If all output ports are blocked, it returns a NAK signal to routing node b. Upon receiving the NAK signal, routing node b buffers the returned data and generates a corresponding retransmission route request time t based on the number of blocking attempts contained in the NAK signal. Simultaneously, routing node c's transmission port is released, while routing node b's transmission port is occupied. After time t, if the retransmission route request is successful, data transmission from routing node b to routing node c can be completed using the same routing mechanism; if the retransmission fails, the above process is repeated until transmission is complete.

[0079] This invention improves data transmission efficiency by dividing the on-chip electrical communication process into on-chip electrical communication and inter-chip optical communication processes for parallel data transmission. In the on-chip electrical communication process, by dividing the communication grid into a cluster structure and using an XY-YX adaptive algorithm, the routing path or route request retransmission time can be dynamically adjusted based on the real-time congestion status of a port of a routing node. This improves the utilization rate of on-chip paths, increases the probability of successful route requests when data is congested, provides high flexibility, and reduces on-chip data communication latency. In the inter-chip optical communication process, by configuring optical interfaces and using six wavelengths to achieve non-blocking optical signal transmission between four bare dies, the transmission latency of inter-chip communication is reduced.

[0080] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0081] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0082] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0083] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0084] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A low-latency chip-level optoelectronic hybrid integrated network communication method, applied to a low-latency chip-level optoelectronic hybrid integrated network, characterized in that, The method includes: The source communication core on the source die sends the first data to the source routing node; wherein, the source communication core and the source routing node belong to the same cluster structure; The source routing node transmits the first data to the signal processing unit of the source die via TSV; After the signal processing unit of the source die transmits the first data to the optical transmitter of the source die, it converts the first data into a first optical signal through the optical transmitter and sends it to the inner ring optical waveguide bus or the outer ring optical waveguide bus. The inner or outer ring optical waveguide bus transmits the first optical signal to the optical interface of the target die, where the first optical signal is filtered and transmitted to the photodetector of the target die. The photodetector of the target die converts the filtered first optical signal into a second electrical signal and sends it to the signal processing unit of the target die. The signal processing unit of the target die sends the second electrical signal to the target routing node of the target die via TSV; The destination routing node transmits the second electrical signal to the destination communication core; wherein, the destination communication core and the destination routing node belong to the same cluster structure; The destination communication core generates a response signal based on the second electrical signal and returns the response signal to the source communication core via the outer ring optical waveguide bus or the inner ring optical waveguide bus in the same communication mode.

2. The low-latency chip-level optoelectronic hybrid integrated network communication method according to claim 1, characterized in that, The electrical communication process on the source die includes: When the source communication core generates a communication request, it creates a routing request signal and sends it to the source routing node; The source routing node calculates the output port for the output signal based on the routing request signal and the XY-YX adaptive routing algorithm; When the output port is not blocked, an ACK signal is returned to the source communication core, and a new routing request signal is sent to the target routing node corresponding to the output port; wherein, the source routing node and the target routing node are located on the same die; the target routing node is the routing node on the source die; After receiving the ACK signal, the source communication core sends the second data to the source routing node and creates a release signal for the source communication core.

3. The low-latency chip-level optoelectronic hybrid integrated network communication method according to claim 2, characterized in that, The operation process of the XY-YX adaptive routing algorithm includes: When the source routing node receives the routing request signal, it compares the X coordinates of the target routing node and the source routing node using the XY routing algorithm, and then compares the Y coordinates of the target routing node and the source routing node to obtain the first output port for outputting the signal. When the first output port is blocked, the Y coordinates of the target routing node and the source routing node are compared by the YX routing algorithm, and then the X coordinates of the target routing node and the source routing node are compared to obtain the second output port for outputting the signal. When both the first output port and the second output port are blocked, the number of blocking times of the first output port and the second output port are compared. The blocking information of the output port with fewer blocking times is loaded onto the NAK signal and returned to the source communication core.

4. The low-latency chip-level optoelectronic hybrid integrated network communication method according to claim 3, characterized in that, When both the first output port and the second output port are blocked, the blocking counts of the first output port and the second output port are compared, and the blocking information of the output port with fewer blocking counts is loaded onto the NAK signal and returned to the source communication core. The method further includes: When the source communication core receives the NAK signal, it buffers the second data into the source communication core. Based on the blocking information in the NAK signal, a corresponding re-request delay is generated; After re-requesting the delay, the routing request signal is sent again to the source routing node.

5. The low-latency chip-level optoelectronic hybrid integrated network communication method according to claim 1, characterized in that, The low-latency chip-level optoelectronic hybrid integrated network includes: multiple dies, each die having multiple cluster structures on its upper surface; each cluster structure having multiple communication cores and one routing node; and each die having a signal processing unit, multiple optical transmitters, and multiple photodetectors on its lower surface; the signal processing unit is electrically connected to the multiple optical transmitters and multiple photodetectors. It also includes: a substrate, the substrate comprising an inner ring optical waveguide bus, an outer ring optical waveguide bus and multiple optical interfaces; the inner ring optical waveguide bus and the outer ring optical waveguide bus are provided with optical signals of multiple wavelengths; the substrate is located below multiple dies, and each die is provided with two optical interfaces.

6. The low-latency chip-level optoelectronic hybrid integrated network communication method according to claim 5, characterized in that, The multiple clustered routing nodes are interconnected via metal interconnects.

7. The low-latency chip-level optoelectronic hybrid integrated network communication method according to claim 5, characterized in that, The multiple clustered routing nodes are connected to the signal processing unit on the lower surface of the die via TSV.

8. The low-latency chip-level optoelectronic hybrid integrated network communication method according to claim 5, characterized in that, Each die has two optical interfaces underneath; one interface is connected to the inner ring optical waveguide bus, and the other interface is connected to the outer ring optical waveguide bus.

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