Processor emission queue design method based on data dependence and branch prediction confidence

Abstract

The invention provides a processor transmission queue design method based on data dependence and branch prediction confidence, which comprises the following steps that: a transmission queue in a processor acquires a new enqueue instruction, and allocates an idle transmission queue list item; when the new enqueued instruction enters the transmitting queue, judging whether an instruction on which the new enqueued instruction depends exists in the transmitting queue or not by utilizing a source operand register number of the new enqueued instruction, and if so, adding one to the priority of the instruction on which the new enqueued instruction depends in the transmitting queue; judging whether the correct probability of the branch instruction in the new enqueue instruction is lower than a preset value or not, and if yes, adding one to the priorities of all instructions under the branch where the new enqueue instruction is located in the transmitting queue; the branch prediction confidence is the probability of whether the branch instruction is predicted correctly; and selecting a ready instruction with the highest priority from all idle instructions in the transmission queue list item, and sending the selected instruction to a functional unit in the processor for execution.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor micro-architecture and circuit automatic design, and particularly relates to a processor dispatch queue design method and device based on data dependency and branch prediction confidence, an electronic device, a computer readable storage medium and a computer program product. BACKGROUND

[0002] The dispatch queue is an important component in the out-of-order processor, which is used to temporarily store instructions whose operands are not ready, and select appropriate instructions to be dispatched to the functional units in the processor for execution. The main logic of the dispatch queue can be divided into the allocation logic of instructions entering the dispatch queue and the selection logic of instruction dispatch. In the actual execution process of the out-of-order processor, different instruction execution will bring different performance. Early processors mainly use some hardware to implement relatively easy selection strategies, such as determining a fixed priority according to the position of the instruction in the dispatch queue, preferentially selecting the head or tail of the instruction for dispatch, or randomly selecting by generating a pseudo-random number through hardware. Most of the current designs determine the priority based on the order of the instructions, i.e., the Oldest-First strategy, which can achieve the optimal performance in most cases and basically meets the data flow dependency. However, the Oldest-First strategy needs to be implemented by a multi-stage comparator, and when the capacity of the dispatch queue is large, the selection circuit of the dispatch queue will have a large area overhead and delay. The area overhead mainly refers to the selection circuit of the dispatch queue. If the Oldest-First strategy is used, assuming that the dispatch queue has 64 entries, if it is implemented by a tree-shaped comparator, it needs 6 stages and 63 comparators, which has a large overhead. If a dispatch queue needs to dispatch multiple instructions, it needs to select multiple oldest instructions, which further increases the complexity.

[0003] The existing dynamic scheduling selection scheme of the dispatch queue is difficult to balance the area and performance, and can only manually summarize the rules, which is difficult to directly implement complex functions such as the Oldest-First strategy.

[0004] In the prior art, the selection strategy using a fixed priority lacks flexibility and can cause starvation, resulting in a certain performance loss. Although the random selection strategy avoids the worst case, it also loses some optimization space. The Oldest-First strategy needs a large number of comparators and is difficult to directly implement. The dispatch queue implemented by manually writing RTL code is not conducive to parameterized design.

[0005] In addition, the dynamic scheduling of the dispatch queue has an advantage over the static scheduling of the compiler in that it can utilize some micro-architecture information that only exists during the actual execution of the processor, such as branch prediction, Cache, etc. The above manually designed techniques do not fully utilize the processor micro-architecture information. Summary of the Invention

[0006] The purpose of this invention is to address the difficulty in balancing performance and area when selecting circuits in launch queue design, making it impossible to implement complex selection strategies. Humans excel at fitting a specific, functionally correct circuit, but for fitting complex functions that are difficult to implement directly, they often have to rely on manually summarizing patterns.

[0007] To address the shortcomings of existing technologies, such as Figure 2 As shown, this invention proposes a processor launch queue design method based on data dependency and branch prediction confidence, including:

[0008] The allocation process involves the processor's launch queue acquiring new enqueue instructions and allocating available launch queue entries.

[0009] The data dependency utilization step involves using the source operand register number of the newly enqueued instruction to determine whether there is an instruction that the newly enqueued instruction depends on in the issue queue. If so, the priority of the instruction that the newly enqueued instruction depends on in the issue queue is incremented by one.

[0010] The branch prediction confidence utilization step involves determining whether the correct probability of the branch instruction in the newly enqueued instruction is lower than a preset value based on the branch prediction confidence of the branch instruction output by the branch predictor in the processor front-end pipeline, or by obtaining the branch prediction confidence of the branch instruction through a saturation counter. If so, the priority of all instructions under the branch in which the newly enqueued instruction is located in the issue queue is incremented by one. The branch prediction confidence is the probability of whether the branch instruction is predicted correctly.

[0011] The instruction selection step involves selecting the highest-priority ready instruction from all idle instructions in the launch queue list and sending it to the functional unit in the processor for execution.

[0012] The processor launch queue design method based on data dependency and branch prediction confidence, wherein the allocation step includes:

[0013] The launch queue temporarily stores all instructions to be executed. When a new instruction is enqueued, an idle launch queue list entry is searched, and the new instruction is written to that idle launch queue list entry. An idle launch queue list entry refers to an entry in the launch queue that does not contain any valid instructions. A valid instruction is an instruction that exists in the launch queue list entry but has not been launched.

[0014] The processor launch queue design method based on data dependency and branch prediction confidence, wherein the branch prediction confidence acquisition step includes:

[0015] Based on the type information carried by the instructions in the issue queue, a branch instruction is selected from the issue queue. The branch predictor in the processor front-end pipeline outputs the prediction confidence of the branch instruction, increasing the priority of branch instructions with weak jumps and weak non-jumps based on the prediction confidence; or

[0016] The prediction steps include:

[0017] The back-end execution unit uses a separate memory to store the branch prediction information for each branch instruction. Each entry in this memory is a 2-bit saturation counter, which is addressed using the low-order bit of the instruction PC. When the branch execution unit BRU finishes executing a branch instruction, if it finds that the prediction is correct and the corresponding saturation counter is not saturated, it increments by 1. If the prediction is incorrect, the corresponding saturation counter is cleared to zero. The branch instruction reads this memory to obtain the branch prediction information during the decoding stage.

[0018] like Figure 3 As shown, this invention also proposes a processor launch queue design device based on data dependency and branch prediction confidence, including:

[0019] The allocation module retrieves new enqueue instructions from the processor's launch queue and allocates available launch queue entries.

[0020] The data dependency utilization module uses its source operand register number to determine whether there is an instruction that the newly enqueued instruction depends on in the launch queue when the new enqueued instruction enters the launch queue. If there is, the priority of the instruction that the newly enqueued instruction depends on in the launch queue is incremented by one.

[0021] The branch prediction confidence utilization module determines whether the probability of the correct branch instruction in the newly enqueued instruction is lower than a preset value based on the branch prediction confidence of the branch instruction output by the branch predictor in the front-end pipeline of the processor, or by obtaining the branch prediction confidence of the branch instruction through a saturation counter. If so, the priority of all instructions under the branch where the newly enqueued instruction is located in the launch queue is incremented by one. The branch prediction confidence is the probability of whether the branch instruction is predicted correctly.

[0022] The instruction selection module selects the highest-priority ready instruction from all idle instructions in the launch queue list and sends it to the functional unit in the processor for execution.

[0023] The processor launch queue design apparatus based on data dependency and branch prediction confidence, wherein the allocation module includes:

[0024] The launch queue temporarily stores all instructions to be executed. When a new instruction is enqueued, an idle launch queue list entry is searched, and the new instruction is written to that idle launch queue list entry. An idle launch queue list entry refers to an entry in the launch queue that does not contain any valid instructions. A valid instruction is an instruction that exists in the launch queue list entry but has not been launched.

[0025] The processor launch queue design device based on data dependency and branch prediction confidence, wherein the branch prediction confidence acquisition module includes:

[0026] Based on the type information carried by the instructions in the issue queue, a branch instruction is selected from the issue queue. The branch predictor in the processor front-end pipeline outputs the prediction confidence of the branch instruction, increasing the priority of branch instructions with weak jumps and weak non-jumps based on the prediction confidence; or

[0027] The prediction module includes:

[0028] The back-end execution unit uses a separate memory to store the branch prediction information for each branch instruction. Each entry in this memory is a 2-bit saturation counter, which is addressed using the low-order bit of the instruction PC. When the branch execution unit BRU finishes executing a branch instruction, if it finds that the prediction is correct and the corresponding saturation counter is not saturated, it increments by 1. If the prediction is incorrect, the corresponding saturation counter is cleared to zero. The branch instruction reads this memory to obtain the branch prediction information during the decoding stage.

[0029] The present invention also proposes a client for the processor launch queue design apparatus based on data dependency and branch prediction confidence.

[0030] The present invention also proposes an electronic device, including the aforementioned processor launch queue design apparatus based on data dependency and branch prediction confidence, the electronic device being connected to an information display device for displaying the priority of instructions with user-set display parameters, attributes, or through an artificial intelligence model.

[0031] The present invention also proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the processor launch queue design method based on data dependency and branch prediction confidence.

[0032] The present invention also proposes a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, it implements the steps of the processor launch queue design method based on data dependency and branch prediction confidence.

[0033] As can be seen from the above solutions, the advantages of the present invention are:

[0034] The launch queue design of this invention can improve processor performance from two aspects: data flow dependency and reducing branch prediction penalty, based on instruction dependency confidence and branch prediction confidence.

[0035] This intelligent launch queue generation system can automatically generate launch queue circuit design code corresponding to the existing black box circuit generation algorithm. Attached Figure Description

[0036] Figure 1 This is the overall hardware design diagram of the launch queue of the present invention;

[0037] Figure 2 This is a flowchart of the method of the present invention;

[0038] Figure 3 This is a block diagram of the device of the present invention;

[0039] Figure 4 This is a schematic diagram of the structure of the first electronic device of the present invention;

[0040] Figure 5 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0041] Figure 6 This is a schematic diagram of the structure of the second electronic device of the present invention.

[0042] Figure label:

[0043] A - First electronic device;

[0044] B-Processor launch queue design device based on data dependency and branch prediction confidence;

[0045] C-Data acquisition equipment;

[0046] D-Information display device;

[0047] 1000 - Second electronic device;

[0048] Ⅰ-Computational Unit;

[0049] II-ROM;

[0050] III-RAM;

[0051] N-bus;

[0052] V-Interface;

[0053] VI - Input Unit;

[0054] VII - Output Unit;

[0055] VIII - Storage medium;

[0056] IX - Communication Unit. Detailed Implementation

[0057] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0058] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0059] The processor described in this invention is the control center of an electronic device. It can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of this invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0060] Alternatively, the processor can perform various functions of the electronic device by running or executing software programs stored in memory, and by calling data stored in memory.

[0061] In a specific implementation, as one example, the processor may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include servers, desktop computers, laptops, smartphones, tablets, embedded computers, etc., where the embedded computer includes vehicles and robots, etc.

[0062] The memory is used to store the software program that executes the solution of the present invention, and the execution is controlled by the processor. For specific implementation methods, please refer to the above method embodiments, which will not be repeated here.

[0063] It should be noted that the structure of the electronic device shown in the accompanying drawings of this invention does not constitute a limitation thereof. The actual knowledge structure recognition device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0064] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0065] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0066] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0067] It should also be understood that, in various embodiments of the present invention, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0068] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0069] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0070] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0071] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] While researching processor launch queues, the inventors discovered that existing launch queue selection strategies suffer from compromises due to significant area overhead. Their research demonstrated that appropriate launch queue selection can improve performance, but these functionalities are difficult to implement in hardware design. Furthermore, during their research on automated processor design, the inventors found that existing automated circuit design algorithms can fit a circuit for a specific function with a certain degree of accuracy. By controlling relevant parameters, they achieved a trade-off between area and functional accuracy, automatically designing a black-box circuit to achieve an approximate function.

[0073] The inventors therefore designed an intelligent design scheme for automatically designing launch queues using an automatic circuit design algorithm. The scheme comprises three parts: an allocation circuit, a priority update circuit, and a selection circuit. The priority update circuit comprehensively considers instruction dependencies and branch prediction confidence. Using a configurable parameter dynamic scheduling simulator, and based on the provided input / output data, the inventors employ existing automatic circuit generation algorithms to intelligently generate launch queue circuits with different parameters (number of allocation items, number of launch queue items, number of launch commands) and varying degrees of precision.

[0074] In summary, to achieve the above-mentioned technical effects, the present invention proposes the following key technical points:

[0075] Key point 1: The design of a launch queue. The main circuit of the launch queue is divided into three parts: allocation circuit, which allocates new entries for newly enqueued instructions; priority update circuit, which updates the launch queue according to the enqueued instruction information (instruction dependency confidence and branch prediction confidence); and instruction selection circuit, which selects the highest priority instructions from the ready instructions according to their priority.

[0076] Key point 2: The intelligent generation system for the launch queue integrates existing black-box circuit generation algorithms based on IO data. It can configure the parameters corresponding to the launch queue (number of allocation items, number of launch queue items, number of launch commands), and can adjust the parameters corresponding to the automatic circuit generation algorithm to change the fitting accuracy of the launch queue selection strategy, thereby balancing area and performance.

[0077] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

[0078] 1. Design of the transmit queue allocation circuit and instruction selection circuit

[0079] The allocation circuit assigns a free entry to the launch queue for each newly enqueued instruction. Each bit represents whether an entry is valid. A vector can then be used to represent the free and valid entries in the launch queue. The sequence number of the free entry is output using either a fixed priority method or a random allocation method. Because this part of the design logic is relatively simple, a 100% accuracy rate is required. This design can achieve 100% accuracy within existing automatic design algorithms.

[0080] An idle launch queue entry refers to an entry in the launch queue that does not contain a valid instruction. A valid entry means that there is still an unlaunched instruction in the corresponding entry of the launch unit. The launch queue temporarily stores all unexecuted instructions. When a new instruction is enqueued, an idle entry needs to be found, and the new instruction is written to that entry.

[0081] The instruction selection circuit selects one or more ready instructions with the highest priority based on their priority. To prevent execution from violating data dependencies due to circuit accuracy issues, instruction selection is divided into two stages. The first stage selects all ready instructions, requiring 100% accuracy. The second stage selects the instructions to be issued based on their priority; errors in this stage do not affect the correctness of the program's execution result, thus tolerating a certain probability of error, making it suitable for implementation using automated design algorithms. Instruction priority is typically represented using a two-bit saturated counter because the small number of bits minimizes latency and area overhead when comparing priorities.

[0082] An idle issue queue entry refers to an entry without a valid instruction; a ready instruction is one whose operands are ready. For RISC instruction sets, each entry in the issue queue has two bits indicating whether its source operand is ready, i.e., whether the preceding instruction has completed the computation of the current instruction's source operand. When both bits are 1, it indicates that the instruction is ready; therefore, this circuit is equivalent to selecting a position that is 1 from a sequence of 0s and 1s.

[0083] 2. Instruction Dependency Mechanism Design

[0084] The issue queue priority designed in this invention considers the number of times an instruction is locally dependent. This feature mainly reflects the data flow relationship of instructions in the program; instructions with more dependencies will have higher priority. The number of times an instruction is locally dependent refers to the number of times the instruction's operation result is directly dependent on it within the processor's instruction window. Although the length of the dependency chain is more important for dynamic scheduling than the number of dependencies, it is difficult to determine whether multiple instructions have continuous dependencies within a single cycle. However, determining the number of times an instruction is dependent on it is relatively easy. Issue queues typically adopt a content-addressable (CAM) structure. When an instruction enters the issue queue, its source operand register number is compared in parallel with the destination register number of each entry in the issue queue to address the instructions it directly depends on.

[0085] Instructions being dependent on each other means that the destination register number of the current instruction is equal to the source register number of the newly enqueued instruction. When a new instruction enters the issue queue, its source register is compared with the destination register of each instruction in the issue queue in parallel, and a mask is output to update its priority. This priority is implemented through a saturation counter, reflecting the number of times the instruction is dependent within the current instruction window. A Reduced Instruction Set Computing (RISC) computer's computation instructions generally include one destination register and two source registers. If the destination register number of a preceding instruction is equal to one of the source register numbers of the current instruction, it indicates that there is a data dependency between these two instructions; the dependent instruction can only be executed after the dependent instruction is executed.

[0086] 3. Branch Prediction Confidence Mechanism Design

[0087] Branch prediction confidence predicts the probability that a branch instruction is correct. It can be given directly by the branch predictor in the processor front-end pipeline or obtained through a saturation counter. When the prediction is successful, the counter is incremented by 1 if it is not saturated, and when the prediction is wrong, the counter is decremented by 1 if it is not 0.

[0088] The micro-operations of the instructions entering the launch queue have all been decoded and carry their type information, so it is possible to directly determine whether the instruction type is a branch instruction.

[0089] The branch prediction confidence here considers two designs. One is entirely managed by the branch prediction unit, which does not output a single bit of the prediction result (jump or no jump), but outputs the prediction confidence as a numerical value. For example, for a classic two-bit saturation counter design, the branch predictor can output the value of the 2-bit saturation counter. This value will flow into the back-end execution unit along with its corresponding instruction. In this case, we directly use this value as the branch prediction confidence. In the 2-bit saturation counter, 01 and 10 correspond to "weak jump" and "weak no jump," respectively. We consider these as possible errors and increase their priority. The advantage of having the branch predictor in the processor front-end pipeline directly provide the branch confidence is that most branch prediction methods themselves have some values ​​representing "prediction confidence," and directly using these values ​​can avoid additional storage overhead.

[0090] Another design, independent of the branch predictor implementation, uses a separate memory in the backend to store branch prediction confidence. Each entry in this memory is a 2-bit saturation counter. We use low-order addressing of the instruction program (PC). When the Branch Execution Unit (BRU) executes a branch instruction, it calculates whether the branch instruction jumps and the corresponding jump address. Then, it compares the branch prediction result stored in memory to determine if the prediction is correct. If the prediction is correct and the corresponding saturation counter is not saturated, it increments by 1; otherwise, it resets the saturation counter to zero. The branch prediction result can come from the branch predictor, which directly writes a definite branch prediction result to the branch cache. The branch prediction result includes whether to jump / not jump and the predicted jump address. The branch instruction can read this memory to obtain the branch prediction confidence during the decoding stage. The advantage of obtaining branch confidence by adding a saturation counter is that it does not depend on the implementation of the branch predictor.

[0091] In the tag-based branch recovery mechanism, each instruction is assigned a tag. The tag can be used to identify the instructions under the corresponding branch. Although some instructions may not have a dependency relationship with the instructions in the branch, the number of instructions that are dependent on is also a feature we consider. Therefore, in this branch, the instructions that are dependent on by the branch instructions often have a higher priority.

[0092] 4. Instruction Priority Update Design

[0093] The priority update circuit updates the instruction priority based on various characteristics of the newly enqueued instruction. First, the priority of all instructions that the newly enqueued instruction depends on is incremented by 1, thus prioritizing the execution of the critical path in the instruction computation. If the newly enqueued instruction is a potentially erroneous branch instruction, then the priority of all instructions with the same tag is incremented by 1. This facilitates the rapid calculation of the correct fetch address of the branch instruction with the predicted error, allowing the processor to quickly resume the correct execution path. Since this update only affects the instruction issue priority and does not disrupt the data dependencies between instructions, the priority update can tolerate a certain probability of error, making it suitable for implementation using automated design algorithms.

[0094] When an erroneous branch instruction exists in the instruction pipeline, it means that all instructions following that instruction are on the wrong path. In other words, the CPU is doing useless work at this point. We need to quickly calculate the branch prediction error information for that branch instruction and provide the correct jump address to the instruction fetch unit. Therefore, we need to prioritize calculating branch instructions that are more likely to err. Since the value of this branch instruction depends on other computed instructions, we increment the priority of all instructions with the same tag by 1. This is similar to the previous determination of instruction dependencies. We then compare the tags of all instructions in parallel with the tag of the newly enqueued branch instruction and output a mask.

[0095] The overall hardware design of the launch queue is as follows: Figure 1 As shown, in the intelligent design system of this invention, the input / output width, priority update strategy details and circuit accuracy of each part can be flexibly configured, and three main combinational logic circuits can be automatically generated.

[0096] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0097] like Figure 3 As shown, the present invention also proposes a processor launch queue design device B based on data dependency and branch prediction confidence, comprising:

[0098] The allocation module retrieves new enqueue instructions from the processor's launch queue and allocates available launch queue entries.

[0099] The data dependency utilization module uses its source operand register number to determine whether there is an instruction that the newly enqueued instruction depends on in the launch queue when the new enqueued instruction enters the launch queue. If there is, the priority of the instruction that the newly enqueued instruction depends on in the launch queue is incremented by one.

[0100] The branch prediction confidence utilization module determines whether the probability of the correct branch instruction in the newly enqueued instruction is lower than a preset value based on the branch prediction confidence of the branch instruction output by the branch predictor in the front-end pipeline of the processor, or by obtaining the branch prediction confidence of the branch instruction through a saturation counter. If so, the priority of all instructions under the branch where the newly enqueued instruction is located in the launch queue is incremented by one. The branch prediction confidence is the probability of whether the branch instruction is predicted correctly.

[0101] The instruction selection module selects the highest-priority ready instruction from all idle instructions in the launch queue list and sends it to the functional unit in the processor for execution.

[0102] The processor launch queue design apparatus based on data dependency and branch prediction confidence, wherein the allocation module includes:

[0103] The launch queue temporarily stores all instructions to be executed. When a new instruction is enqueued, an idle launch queue list entry is searched, and the new instruction is written to that idle launch queue list entry. An idle launch queue list entry refers to an entry in the launch queue that does not contain any valid instructions. A valid instruction is an instruction that exists in the launch queue list entry but has not been launched.

[0104] The processor launch queue design device based on data dependency and branch prediction confidence, wherein the branch prediction confidence acquisition module includes:

[0105] Based on the type information carried by the instructions in the issue queue, a branch instruction is selected from the issue queue. The branch predictor in the processor front-end pipeline outputs the prediction confidence of the branch instruction, increasing the priority of branch instructions with weak jumps and weak non-jumps based on the prediction confidence; or

[0106] The prediction module includes:

[0107] The back-end execution unit uses a separate memory to store the branch prediction information for each branch instruction. Each entry in this memory is a 2-bit saturation counter, which is addressed using the low-order bit of the instruction PC. When the branch execution unit BRU finishes executing a branch instruction, if it finds that the prediction is correct and the corresponding saturation counter is not saturated, it increments by 1. If the prediction is incorrect, the corresponding saturation counter is cleared to zero. The branch instruction reads this memory to obtain the branch prediction information during the decoding stage.

[0108] The present invention also proposes a client for accessing the processor launch queue design apparatus based on data dependency and branch prediction confidence.

[0109] like Figure 4As shown, in another embodiment of the present invention, a first electronic device A is also proposed, which includes the aforementioned processor launch queue design device B based on data dependency and branch prediction confidence.

[0110] like Figure 5 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to acquire new queuing instructions, and the information display device D is used to display the branch prediction confidence and instruction priority obtained by the present invention.

[0111] The information display device D can process and organize the data output by the first electronic device A based on an information display mechanism to improve the readability of the data. This information display mechanism can be manually preset, for example, visualizing the data output by the first electronic device A. It can present the user with the specified key information based on user-defined display parameters and / or attributes, such as the data range and font, color, and scrolling options. Users can access this information more quickly without needing to navigate to secondary pages or scroll through pages, saving them time and effort. Alternatively, the information display mechanism can be an artificial intelligence (AI) display model that learns the user's key information interests based on past usage habits, such as viewing time, click count, and edit count, and automatically presents rich and necessary key information.

[0112] The present invention also provides a computer program product, which includes a computer program that can be stored on a readable storage medium. When the computer program is executed by a processor, the computer is able to execute the processor launch queue design method based on data dependency and branch prediction confidence provided by the above methods.

[0113] In another embodiment, the present invention also proposes a storage medium VIII for storing a computer program that executes the processor launch queue design method based on data dependency and branch prediction confidence. It should be understood that the storage medium in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0114] Figure 6 A schematic block diagram of a second electronic device 1000 that can be used to implement embodiments of the present invention is shown. The second electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein. The second electronic device 1000 may be the same as or different from the first electronic device A.

[0115] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from storage medium VIII into random access memory (RAM) III. The RAM III may also store various programs and data required for the operation of the device 1000. The computing unit I, ROM II, and RAM III are interconnected via bus IV. An input / output (I / O) interface V is also connected to bus IV.

[0116] Multiple components in the second electronic device 1000 are connected to I / O interface V, including: input unit VI, such as a keyboard, mouse, etc.; output unit VII, such as various types of displays, speakers, etc.; storage medium VIII, such as a disk, optical disk, etc.; and communication unit IX, such as a network card, modem, wireless transceiver, etc. Communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0117] The computing unit I can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S4. For example, in some embodiments, the methods can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to perform methods by any other suitable means (e.g., by means of firmware).

[0118] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A processor launch queue design method based on data dependency and branch prediction confidence, characterized in that, include: The allocation process involves the processor's launch queue acquiring new enqueue instructions and allocating available launch queue entries. The data dependency utilization step involves using the source operand register number of the newly enqueued instruction to determine whether there is an instruction that the newly enqueued instruction depends on in the issue queue. If so, the priority of the instruction that the newly enqueued instruction depends on in the issue queue is incremented by one. The branch prediction confidence utilization step involves determining whether the correct probability of the branch instruction in the newly enqueued instruction is lower than a preset value based on the branch prediction confidence of the branch instruction output by the branch predictor in the processor front-end pipeline, or by obtaining the branch prediction confidence of the branch instruction through a saturation counter. If so, the priority of all instructions under the branch in which the newly enqueued instruction is located in the issue queue is incremented by one. The branch prediction confidence is the probability of whether the branch instruction is predicted correctly. The instruction selection step involves selecting the highest-priority ready instruction from all idle instructions in the launch queue list and sending it to the functional unit in the processor for execution.

2. The processor launch queue design method based on data dependency and branch prediction confidence as described in claim 1, characterized in that, The allocation process includes: The launch queue temporarily stores all instructions to be executed. When a new instruction is enqueued, an idle launch queue list entry is searched, and the new instruction is written to that idle launch queue list entry. An idle launch queue list entry refers to an entry in the launch queue that does not contain any valid instructions. A valid instruction is an instruction that exists in the launch queue list entry but has not been launched.

3. The processor launch queue design method based on data dependency and branch prediction confidence as described in claim 1, characterized in that, The steps for obtaining confidence in this branch prediction include: Based on the type information carried by the instructions in the issue queue, a branch instruction is selected from the issue queue. The branch predictor in the processor front-end pipeline outputs the prediction confidence of the branch instruction, increasing the priority of branch instructions with weak jumps and weak non-jumps based on the prediction confidence; or The prediction steps include: The back-end execution unit uses a separate memory to store the branch prediction information for each branch instruction. Each entry in this memory is a 2-bit saturation counter, which is addressed using the low-order bit of the instruction PC. When the branch execution unit BRU finishes executing a branch instruction, if it finds that the prediction is correct and the corresponding saturation counter is not saturated, it increments by 1. If the prediction is incorrect, the corresponding saturation counter is cleared to zero. The branch instruction reads this memory to obtain the branch prediction information during the decoding stage.

4. A processor launch queue design device based on data dependency and branch prediction confidence, characterized in that, include: The allocation module retrieves new enqueue instructions from the processor's launch queue and allocates available launch queue entries. The data dependency utilization module uses its source operand register number to determine whether there is an instruction that the newly enqueued instruction depends on in the launch queue when the new enqueued instruction enters the launch queue. If there is, the priority of the instruction that the newly enqueued instruction depends on in the launch queue is incremented by one. The branch prediction confidence utilization module determines whether the probability of the correct branch instruction in the newly enqueued instruction is lower than a preset value based on the branch prediction confidence of the branch instruction output by the branch predictor in the front-end pipeline of the processor, or by obtaining the branch prediction confidence of the branch instruction through a saturation counter. If so, the priority of all instructions under the branch where the newly enqueued instruction is located in the launch queue is incremented by one. The branch prediction confidence is the probability of whether the branch instruction is predicted correctly. The instruction selection module selects the highest-priority ready instruction from all idle instructions in the launch queue list and sends it to the functional unit in the processor for execution.

5. The processor launch queue design apparatus based on data dependency and branch prediction confidence as described in claim 4, characterized in that, The allocation module includes: The launch queue temporarily stores all instructions to be executed. When a new instruction is enqueued, an idle launch queue list entry is searched, and the new instruction is written to that idle launch queue list entry. An idle launch queue list entry refers to an entry in the launch queue that does not contain any valid instructions. A valid instruction is an instruction that exists in the launch queue list entry but has not been launched.

6. The processor launch queue design apparatus based on data dependency and branch prediction confidence as described in claim 4, characterized in that, This branch's confidence acquisition module includes: Based on the type information carried by the instructions in the issue queue, a branch instruction is selected from the issue queue. The branch predictor in the processor front-end pipeline outputs the prediction confidence of the branch instruction, increasing the priority of branch instructions with weak jumps and weak non-jumps based on the prediction confidence; or The prediction module includes: The back-end execution unit uses a separate memory to store the branch prediction information for each branch instruction. Each entry in this memory is a 2-bit saturation counter, which is addressed using the low-order bit of the instruction PC. When the branch execution unit BRU finishes executing a branch instruction, if it finds that the prediction is correct and the corresponding saturation counter is not saturated, it increments by 1. If the prediction is incorrect, the corresponding saturation counter is cleared to zero. The branch instruction reads this memory to obtain the branch prediction information during the decoding stage.

7. A client for any of the processor launch queue design apparatuses based on data dependency and branch prediction confidence as described in claims 4-6.

8. An electronic device, characterized in that, The device includes a processor launch queue design apparatus based on data dependency and branch prediction confidence as described in claims 4-6. The electronic device may be connected to an information display device, which is used to display the priority of instructions by user-set display parameters, attributes, or through an artificial intelligence model.

9. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the processor launch queue design method based on data dependency and branch prediction confidence as described in any one of claims 1-3.

10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the processor launch queue design method based on data dependency and branch prediction confidence as described in any of claims 1-3.

Images