A metal-oxide-semiconductor field effect transistor and a method of fabricating the same

Abstract

The application provides a metal-oxide semiconductor field effect transistor and a preparation method thereof. The metal-oxide semiconductor field effect transistor comprises an active region and a terminal region. A first field limiting ring and a second field limiting ring are prepared in an epitaxial layer located in the terminal region. The doping concentration of the doping ions in the second field limiting ring is greater than the doping concentration of the doping ions in the first field limiting ring. The junction depth of the second field limiting ring is less than the junction depth of the first field limiting ring. The second field limiting ring is set as a shallow-junction high-doping-concentration field limiting ring relative to the first field limiting ring, and the corresponding field oxide layer is set, so that the fixed charges and movable charges in the terminal region field oxide layer can be effectively shielded, the terminal region depletion layer is prevented from shrinking, the reliability of the device in a high-voltage scene is improved, the device withstand voltage is improved in combination with the first field ring, and the operation performance and operation stability of the device are simultaneously improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductors, and in particular relates to a metal-oxide-semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] Power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are widely used in almost all applications requiring power supply, voltage, and current control, such as switching power supplies, DC / DC converters, surge suppression, motor drives, motor speed control, and industrial control. They provide essential guarantees for the stable operation of various electronic systems. In existing MOSFET devices, the maximum electric field at the device surface, which transitions from the active region to the termination region, determines the device's breakdown voltage due to the surface curvature effect. Therefore, special structural designs are typically employed on the surface or within the device to increase the radius of curvature, reduce the curvature effect, lower the peak surface electric field, and improve the surface breakdown voltage.

[0003] In the prior art, the structure of the termination region using the composite field limiting ring (FLR) and field plate (FP) can improve the breakdown voltage. However, the oxide layer of the termination region is prone to problems such as the introduction of fixed charge and mobile charge, which can lead to a decrease in breakdown voltage and affect the reliability of the device. On the other hand, the termination region structure using the composite junction extension (JTE) and field plate (FP) can reduce the surface electric field and improve the device breakdown voltage. However, this structure is more sensitive to charge, and the phenomenon of breakdown voltage being affected by charge is more obvious, resulting in low stability. Summary of the Invention

[0004] This application provides a metal-oxide-semiconductor field-effect transistor and its fabrication method, which can solve the problem in the prior art where the structure of the terminal region can improve the breakdown voltage, but the oxide layer of the terminal region is prone to introduce fixed charge and movable charge, which causes the breakdown voltage to decrease and affects the reliability of the device.

[0005] In a first aspect, embodiments of this application provide a metal-oxide-semiconductor field-effect transistor (MOSFET), which includes an active region and a termination region, wherein the termination region includes:

[0006] Substrate;

[0007] An epitaxial layer is located on one side surface of a substrate. First field-limiting ring regions are arranged at intervals in the epitaxial layer along a first direction from the active region to the terminal region. A first field-limiting ring is provided in the first field-limiting ring region. The first field-limiting ring is located in a region formed by extending a portion of the length from the side surface of the epitaxial layer facing away from the substrate along the direction pointing towards the substrate.

[0008] A field oxide layer is located on the side surface of the epitaxial layer facing away from the substrate, and a first opening is formed in the field oxide layer at the first field limiting ring.

[0009] Metal field plate, the metal field plate covers the first field limiting ring at the first opening;

[0010] The terminal area also includes a second field-limited ring area, which is located to the side of the first field-limited ring area along the first direction and is located in the field oxide layer covered area; a second field-limited ring is provided in the second field-limited ring area, which is located to the side of the first field-limited ring.

[0011] The doping concentration of the second field-limited ring is greater than that of the first field-limited ring, and the junction depth of the second field-limited ring is less than that of the first field-limited ring.

[0012] In one feasible implementation, the width of the second field limiting ring in the outer second field limiting ring region along the first direction in the epitaxial layer is greater than or equal to the width of the second field limiting ring in the inner second field limiting ring region.

[0013] In one feasible implementation, along the first direction in the epitaxial layer, the width of the second field-limiting loop in the second field-limiting loop region gradually increases.

[0014] In one feasible implementation, the number of second field limiting rings in the second field limiting ring region located on the outer side of the epitaxial layer along the first direction is greater than or equal to the number of second field limiting rings in the second field limiting ring region located on the inner side.

[0015] In one feasible implementation, along the first direction in the epitaxial layer, the number of second field-limiting loops in the second field-limiting loop region gradually increases.

[0016] In one feasible implementation, the terminal area further includes:

[0017] A polycrystalline silicon field plate and an isolation dielectric layer are located at each first opening, and each of them covers a portion of the first field limiting ring at the first opening to form a second opening. A metal field plate covers the first field limiting ring at the second opening.

[0018] The polycrystalline silicon field plate extends in a first direction, covering a portion of the field oxide layer adjacent to the first opening;

[0019] The insulating dielectric layer extends in a second direction, covering the field oxide layer adjacent to the first opening, and also covering part of the polysilicon field plate; the second direction is opposite to the first direction;

[0020] The metal field plate extends along the first direction to cover the polycrystalline silicon field plate, and also extends to cover part of the isolation dielectric layer.

[0021] In one feasible implementation, the aforementioned terminal area further includes a stop ring and a stop ring field plate;

[0022] The stop ring is located in the epitaxial layer along the first direction, in the outer region of all the first and second field limiting rings; the field oxide layer forms a stop ring opening at the stop ring, and the stop ring field plate covers the stop ring at the stop ring opening.

[0023] In one feasible implementation, the aforementioned metal field plate covers the first field limiting ring at the first opening and also covers a portion of the field oxide layer adjacent to the first opening.

[0024] Secondly, embodiments of this application provide a method for fabricating a metal-oxide-semiconductor field-effect transistor, the metal-oxide-semiconductor field-effect transistor including an active region and a termination region, the method comprising:

[0025] A substrate is provided; the substrate includes a substrate and an epitaxial layer disposed on one side surface of the substrate;

[0026] An active functional layer is fabricated in the active region;

[0027] In the epitaxial layer of the terminal region, a first field-limiting ring region is prepared along a first direction from the active region to the terminal region, and a second field-limiting ring region is prepared on the side of the first field-limiting ring region along the first direction; a first field-limiting ring is provided in the first field-limiting ring region, and the first field-limiting ring is located in the region formed by extending a portion of the length from the surface of the epitaxial layer facing away from the substrate along the direction pointing towards the substrate; a second field-limiting ring is provided in the second field-limiting ring region, and the second field-limiting ring is located on the side of the first field-limiting ring.

[0028] After the first field-limited ring region is fabricated, a field oxide layer and a metal field plate are fabricated on the epitaxial layer of the terminal region facing away from the substrate. The field oxide layer covers the second field-limited ring and forms a first opening at the first field-limited ring. The metal field plate covers the first field-limited ring at the first opening. The doping concentration of the second field-limited ring is greater than that of the first field-limited ring, and the junction depth of the second field-limited ring is less than that of the first field-limited ring.

[0029] In one feasible implementation, the above-described method involves preparing a first field-limiting loop region spaced apart in the epitaxial layer of the terminal region along a first direction from the active region to the terminal region, and preparing a second field-limiting loop region on the side of the first field-limiting loop region along the first direction, comprising:

[0030] A first patterned photoresist is prepared on the surface of the epitaxial layer in the terminal region facing away from the substrate; the first patterned photoresist forms a first patterned photoresist opening in the first field-limiting ring region;

[0031] Ions are implanted into the first field-confined ring region along the opening of the first patterned photoresist to form the first field-confined ring.

[0032] On the surface of the epitaxial layer forming the first field-limiting ring facing away from the substrate, a second patterned photoresist is prepared; the second patterned photoresist forms a second patterned photoresist opening in the second field-limiting ring region; the first field-limiting ring region and the second field-limiting ring region are arranged alternately along the first direction;

[0033] Ions are implanted into the second field-confined ring region along the opening of the second patterned photoresist to form the second field-confined ring.

[0034] The metal-oxide-semiconductor field-effect transistor and its fabrication method of this application are described. By setting a first field-limiting ring and a second field-limiting ring in the epitaxial layer located in the terminal region, and the doping concentration of doped ions in the second field-limiting ring is greater than that in the first field-limiting ring, and the junction depth of the second field-limiting ring is smaller than that of the first field-limiting ring, the second field-limiting ring is set as a shallow junction high-doping concentration field-limiting ring relative to the first field-limiting ring, and is set in a corresponding field oxide layer, which can effectively shield the fixed charge and movable charge in the field oxide layer of the terminal region, avoid the shrinkage of the depletion layer in the terminal region, improve the reliability of the device under high voltage scenarios, and improve the device breakdown voltage by combining the first field-effect ring, thus realizing the simultaneous improvement of the device's operating performance and operating stability. Attached Figure Description

[0035] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the terminal region of a device with a composite structure of a field limiting ring and a field plate.

[0037] Figure 2 This is a schematic diagram of the terminal region of a device with a junction terminal extension and a field plate composite structure.

[0038] Figure 3 This is a schematic diagram of the structure of the terminal region within a metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the internal termination region of another metal-oxide-semiconductor field-effect transistor provided in this application embodiment;

[0040] Figure 5 This is a schematic diagram of the internal termination region of another metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application;

[0041] Figure 6 This is a schematic flowchart of a method for fabricating a metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application;

[0042] Figure 7 This is a schematic flowchart of a method for preparing a first-field confined ring and a second-field confined ring according to an embodiment of this application;

[0043] Figure 8 This is a flowchart illustrating a method for fabricating a metal-oxide-semiconductor field-effect transistor according to an embodiment of this application;

[0044] Figure 9 This is an example diagram of the structure of a metal-oxide-semiconductor field-effect transistor after the fabrication of the first field-limiting ring in the internal termination region, as provided in an embodiment of this application.

[0045] Figure 10 This is an example diagram of the structure of a metal-oxide-semiconductor field-effect transistor after fabricating a second field-limiting ring in the internal termination region, as provided in an embodiment of this application.

[0046] Figure 11 This is an example diagram of the structure of a metal-oxide-semiconductor field-effect transistor after a field oxide layer with a first opening has been formed in the internal terminal region of the transistor provided in this application.

[0047] Figure 12 This is an example diagram of the structure of a metal-oxide-semiconductor field-effect transistor after the internal termination region has been fabricated, as provided in the embodiments of this application.

[0048] 101-Field confinement ring, 102-Field confinement ring field plate, 103-Field oxide layer, 104-Source field plate, 105-Main junction, 106-Substrate, 107-Epipolar layer;

[0049] 201-Terminal Extension;

[0050] 301-First field limiting ring, 302-Second field limiting ring, 303-Polycrystalline silicon field plate, 304-Isolation dielectric layer, 305-Metal field plate, 306-Stop ring, 307-Stop ring field plate, 308-Back metal;

[0051] 901 - N-type epitaxial layer, 902 - first patterned photoresist;

[0052] 1001 - Second patterned photoresist. Detailed Implementation

[0053] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0055] In existing MOSFET devices, the transition region from the active region to the terminal region is characterized by a larger maximum electric field on the surface than inside due to the surface curvature effect of the planar junction. This means that the device's breakdown voltage is determined by the surface breakdown voltage. Therefore, special structural designs are typically used on the surface or inside the device to increase the radius of curvature and reduce the curvature effect, thereby lowering the peak surface electric field, increasing the surface breakdown voltage, and ultimately improving the device's breakdown voltage.

[0056] Existing technologies utilize a composite structure of a fabricated field limiting ring 101 (FLR) and a field plate (FP) to improve the breakdown voltage at the device surface. (See reference...) Figure 1 , Figure 1This is a schematic diagram of a device termination region with a composite structure of a field limiting ring and a field plate. The termination region includes a field limiting ring 101, a field limiting ring field plate 102, a field oxide layer 103, a source field plate 104, a main junction 105, a substrate 106, and an epitaxial layer 107. The field oxide layer 103 at this termination region easily introduces fixed and mobile charges, leading to a decrease in the breakdown voltage of the device surface and instability in the device's breakdown voltage characteristics, affecting its reliability. Alternatively, a termination region structure utilizing a combination of a junction termination extension 201 (JTE) and a field plate (FP) can reduce the surface electric field of the device and improve its breakdown voltage. (See reference...) Figure 2 , Figure 2 This is a schematic diagram of the terminal region of a device with a junction termination extension and a field plate composite structure. The terminal region includes a junction termination extension 201, a field limiting ring field plate 102, a field oxide layer 103, a source field plate 104, a main junction 105, a substrate 106, and an epitaxial layer 107. This terminal region structure makes the device more sensitive to the charge introduced by the field oxide layer 103, and the breakdown voltage is more significantly affected by the charge, leading to reduced stability.

[0057] To address the problem of unstable voltage withstand capability in existing devices, this application provides a metal-oxide-semiconductor field-effect transistor and its fabrication method.

[0058] This application establishes a first field-limiting ring and a second field-limiting ring in the epitaxial layer located in the terminal region. The doping concentration of the doped ions in the second field-limiting ring is greater than that in the first field-limiting ring, and the junction depth of the second field-limiting ring is less than that of the first field-limiting ring. By setting the second field-limiting ring as a shallow junction with a high doping concentration relative to the first field-limiting ring, and setting it in a corresponding field oxide layer, it can effectively shield the fixed and mobile charges in the field oxide layer of the terminal region, avoid the shrinkage of the depletion layer in the terminal region, improve the reliability of the device under high voltage scenarios, and improve the device's withstand voltage by combining the first field-effect ring. This achieves a simultaneous improvement in the device's operating performance and stability.

[0059] The metal-oxide-semiconductor field-effect transistors provided in the embodiments of this application will be described below.

[0060] Figure 3 This illustration shows a schematic diagram of the structure of a terminal region within a metal-oxide-semiconductor field-effect transistor according to an embodiment of this application. Figure 3 As shown, the metal-oxide-semiconductor field-effect transistor may include an active region and a termination region, and the termination region may include the following structure:

[0061] Substrate 106;

[0062] Epitaxial layer 107 is located on one side surface of substrate 106. First field limiting ring 301 regions are arranged at intervals in epitaxial layer 107 along a first direction from the active region to the terminal region. First field limiting ring 301 is disposed in the first field limiting ring 301 region. The first field limiting ring 301 is located in the region formed by extending a portion of the length from the side surface of epitaxial layer 107 facing away from substrate 106 along the direction pointing to substrate 106.

[0063] Field oxide layer 103 is located on the side surface of epitaxial layer 107 facing away from substrate 106, and a first opening is formed in the field oxide layer 103 corresponding to the first field limiting ring 301.

[0064] Metal field plate 305, metal field plate 305 covers the first field limiting ring 301 at the first opening;

[0065] The terminal area also includes a second field limiting ring 302 area, which is located on the side of the first field limiting ring 301 area along the first direction and is located in the field oxide layer 103 covered area; a second field limiting ring 302 is provided in the second field limiting ring 302 area, which is located on the side of the first field limiting ring 301.

[0066] The doping concentration of the second field-limiting ring 302 is greater than that of the first field-limiting ring 301, and the junction depth of the second field-limiting ring 302 is less than that of the first field-limiting ring 301.

[0067] In this embodiment, a first field-limiting ring 301 and a second field-limiting ring 302 are fabricated in the epitaxial layer 107 located in the terminal region. The doping concentration of doped ions in the second field-limiting ring 302 is greater than that in the first field-limiting ring 301, and the junction depth of the second field-limiting ring 302 is less than that of the first field-limiting ring 301. The second field-limiting ring 302 is set as a shallow junction high-doping concentration field-limiting ring relative to the first field-limiting ring 301, and is set corresponding to the field oxide layer 103. This can effectively shield the fixed charge and movable charge in the field oxide layer 103 in the terminal region, avoid the shrinkage of the depletion layer in the terminal region, improve the reliability of the device under high voltage scenarios, and improve the device's withstand voltage by combining the first field-effect ring. This achieves a simultaneous improvement in the device's operating performance and operating stability.

[0068] Each structure is explained in detail below:

[0069] The metal-oxide-semiconductor field-effect transistor in this application can specifically be configured as a vertical double-diffuse metal-oxide-semiconductor (VDMOS). In the embodiments of this application, a first field-limiting ring 301 is generally provided in a first field-limiting ring 301 region, and multiple first field-limiting ring 301 regions are generally provided at intervals in the terminal region along the first direction. That is, multiple first field-limiting rings 301 are arranged at intervals in the terminal region along the first direction. This application focuses on the fact that the terminal region also includes a second field-limiting ring 302 region. The second field-limiting ring 302 region is located next to the first field-limiting ring 301 region. Both the first field-limiting ring 301 and the second field-limiting ring 302 are obtained by doping ions of the corresponding conductivity type on the side of the epitaxial layer 107 facing away from the substrate 106. Therefore, the first field-limiting ring 301 and the second field-limiting ring 302 are both located in the region formed by the length of the portion extending in the direction pointing towards the substrate 106 on the surface of the epitaxial layer 107 facing away from the substrate 106. It should be noted that the length of the first field limiting ring 301 extending from the surface of the epitaxial layer 107 away from the substrate 106 in the direction pointing towards the substrate 106 is greater than the length of the second field limiting ring 302 extending from the surface of the epitaxial layer 107 away from the substrate 106 in the direction pointing towards the substrate 106. That is, the first field limiting ring 301 forms a deep junction after being doped with ions, while the second field limiting ring 302 forms a shallow junction after being doped with ions. Furthermore, the doping concentration of the second field limiting ring 302 is greater than the doping concentration of the first field limiting ring 301. By utilizing the shallow junction and highly doped second field limiting ring 302 between adjacent first field limiting rings 301, a structure is formed that shields the field oxide layer 103 to contain fixed charges and movable charges. Furthermore, the breakdown voltage at the conventional terminal region fluctuates with changes in the charge density in the field oxide layer 103. The second field limiting ring 302 provided in this embodiment reduces the influence of the charge density in the field oxide layer 103 on the breakdown voltage by shielding the effects of fixed and movable charges in the field oxide layer 103. This solves the problem that the breakdown voltage is easily affected by the charge in the field oxide layer 103 and fluctuates in the prior art, thereby improving the stability of the breakdown voltage in the terminal region.

[0070] In this embodiment, the field oxide layer 103 is located on the side of the epitaxial layer 107 facing away from the substrate 106. This field oxide layer 103 should correspond to the second field limiting ring 302 to ensure that the second field limiting ring 302 can shield the charge in the field oxide layer 103 from affecting the shrinkage of the depletion region. Specifically, when the direction of the epitaxial layer 107 facing away from the substrate 106 is considered the upper side, the second field limiting ring 302 can be located directly below the field oxide layer 103, or it can be covered by the field oxide layer 103. A first opening is formed in the field oxide layer 103 corresponding to the first field limiting ring 301. This first opening is used to connect to the metal field plate 305, so that the first field limiting ring 301 is connected to the outside through the metal field plate 305. Figure 3 As shown, a main junction 105 is provided at the boundary between the active region and the terminal region, and a source field plate 104 correspondingly connecting the main junction is provided. Additionally, a back metal 308 is provided on the surface of the substrate 106 facing away from the epitaxial layer 107 in this metal-oxide-semiconductor field-effect transistor. Furthermore, in this embodiment, the substrate 106, epitaxial layer 107, and cutoff ring 306 can be configured as a first conductivity type, while the first field-limiting ring 301 and the second field-limiting ring 302 can be configured as a second conductivity type. This embodiment of the application... Figure 3 A polycrystalline silicon field plate 303 and an isolation dielectric layer 304 can also be set in the middle.

[0071] In one feasible embodiment, to improve the shielding effect on the charge in the field oxide layer 103 and enhance the reliability of the device under high-voltage conditions, reference can be made to... Figure 4 , Figure 4 This is a schematic diagram of the internal termination region of another metal-oxide-semiconductor field-effect transistor provided in this application embodiment. The width of the second field limiting ring 302 located on the outer side of the epitaxial layer 107 along the first direction can be set to be greater than or equal to the width of the second field limiting ring 302 located on the inner side.

[0072] In this embodiment, the width of the second field limiting ring 302 located on the outer side along the first direction is greater than or equal to the width of the second field limiting ring 302 located on the inner side. This precisely adapts to the electric field distribution gradient along the first direction in the terminal region. By setting differentiated widths of the second field limiting rings 302, the uniformity of the electric field in the terminal region is improved, enhancing the flexibility of the second field limiting rings 302 when used for charge shielding and strengthening the charge shielding effect of the second field limiting rings 302. This improves the voltage withstand capability and stability of the metal-oxide-semiconductor field-effect transistor. Figure 4This diagram illustrates a configuration for the width of the second field limiting ring 302. From left to right, the first four second field limiting rings 302 have the same width; the fifth second field limiting ring 302 has an increased width; and the sixth second field limiting ring 302 has a width greater than the fifth second field limiting ring 302. It should be noted that... Figure 4 The setting of the second limit ring 302 in the middle is only an example, and it can be set in other ways in practice.

[0073] In one feasible embodiment, in order to improve the ease of fabrication of the second field limiting ring 302 and its adaptability to devices while ensuring the shielding effect on the charge in the field oxide layer 103, the width of the second field limiting ring 302 in the region of the second field limiting ring 302 in the epitaxial layer 107 along the first direction can be arranged to gradually increase.

[0074] The electric field in the terminal region gradually decreases along the first direction mentioned above. That is, the electric field strength on the side of the terminal region closer to the active region is greater than the electric field strength on the side of the terminal region farther from the active region. Therefore, on the side of the terminal region closer to the active region, the charge interference area is concentrated. At this time, setting a second field limiting ring 302 with a smaller width can achieve shielding of the charge in the field oxide layer 103. However, if the width of the second field limiting ring 302 is too large, it will lead to over-covering of the strong electric field area, which may conflict with the effect of the first field limiting ring 301 in dispersing the electric field, resulting in the problem of secondary concentration of the local electric field. On the side of the terminal region farther from the active region, the electric field strength is smaller and the charge interference area is dispersed. At this time, setting a second field limiting ring 302 with a larger width can achieve shielding of the charge in the field oxide layer 103, avoiding the situation where the width of the second field limiting ring 302 is too small to effectively shield the charge, thus improving the shielding effect of the charge in the field oxide layer 103. In this embodiment, the width of each second field limiting ring 302 is set to gradually increase along the first direction to adapt to the characteristic of the step-like change of the electric field in the terminal region, thereby improving the adaptability and convenience of the preparation of the second field limiting ring 302, and ultimately ensuring the shielding effect on the charge in the field oxide layer 103 and improving the uniformity of the electric field.

[0075] In one feasible embodiment, to improve the shielding effect on the charge in the field oxide layer 103 and to enhance the flexible fabrication of the second field limiting ring 302 in the device, reference can be made to... Figure 5 , Figure 5 This is a schematic diagram of the internal termination region of another metal-oxide-semiconductor field-effect transistor provided in this application embodiment. The number of second field-limiting rings 302 located on the outer side of the epitaxial layer 107 along the first direction can be set to be greater than or equal to the number of second field-limiting rings 302 located on the inner side.

[0076] In this embodiment, the electric field strength is high and the charge is dense on the side of the terminal region closer to the active region. A small number of second field limiting rings 302 can be used to shield the charge in the field oxide layer 103. On the side of the terminal region farther from the active region, the electric field strength is low and the charge is dispersed. Therefore, a larger number of second field limiting rings 302 are needed to improve the shielding effect and increase the flexibility of the fabrication of the second field limiting rings 302, ultimately improving the electric field uniformity of the terminal region. Figure 5 This diagram illustrates a method for setting the number of second field limiting rings 302 in the second field limiting ring 302 region. Along the left-to-right direction, the first four second field limiting ring 302 regions have the same number of second field limiting rings 302, while the number of second field limiting rings 302 increases in the fifth and sixth second field limiting ring 302 regions. It should be noted here that... Figure 5 The setting of the second limit ring 302 in the middle is also just an example, and it can be set in other ways in practice.

[0077] In one feasible embodiment, in order to ensure the ease of fabrication of the second field limiting ring 302 and at the same time ensure the effect of the device against charge interference, the number of the second field limiting ring 302 in the region of the second field limiting ring 302 in the epitaxial layer 107 along the first direction can be gradually increased.

[0078] In this embodiment, the number of second field limiting rings 302 within each second field limiting ring 302 region gradually increases along the first direction to adapt to the step-like changes in the electric field within the terminal region, improve the adaptability to the electric field within the terminal region, improve the shielding effect of the second field limiting rings 302 on charges, and improve the uniformity of the electric field within the terminal region.

[0079] In one feasible embodiment, in order to reduce the device's sensitivity to the charge of the field oxide layer 103 and maintain the stability of the device's breakdown voltage, the aforementioned termination region may further include:

[0080] Polysilicon field plate 303 and isolation dielectric layer 304 are located at each first opening, and each of them covers a portion of the first field limiting ring 301 at the first opening to form a second opening. Metal field plate 305 covers the first field limiting ring 301 at the second opening.

[0081] The polycrystalline silicon field plate 303 extends in a first direction and covers a portion of the field oxide layer 103 adjacent to the first opening;

[0082] The isolation dielectric layer 304 extends in a second direction, covering the field oxide layer 103 adjacent to the first opening, and also covering a portion of the polysilicon field plate 303; the second direction is opposite to the first direction.

[0083] The metal field plate 305 extends along the first direction to cover the polycrystalline silicon field plate 303, and also extends to cover part of the isolation dielectric layer 304.

[0084] In this embodiment, a polysilicon field plate 303 and an isolation dielectric layer 304 are provided. Both the polysilicon field plate 303 and the metal field plate 305 are connected to the first field limiting ring 301. The rightmost boundary of the polysilicon field plate 303 and the rightmost boundary of the metal field plate 305 are isolated by the isolation dielectric layer 304. This achieves a different potential at the rightmost boundary of the polysilicon field plate 303 and the rightmost boundary of the metal field plate 305, thus constructing a multi-level potential gradient. This precisely optimizes the electric field distribution at the terminal region and enhances the shielding effect on the charge in the field oxide layer 103, avoiding the concentration of the boundary electric field and improving the withstand voltage stability and reliability.

[0085] In one feasible embodiment, in order to regulate the electric field distribution, suppress parasitic effects, and improve the withstand voltage stability of the device, the aforementioned terminal region further includes a cutoff ring 306 and a cutoff ring field plate 307.

[0086] The stop ring 306 is located in the epitaxial layer 107 along the first direction, in the outer region of all the first field limiting rings 301 and the second field limiting rings 302; the field oxide layer 103 forms a stop ring opening at the stop ring 306, and the stop ring field plate 307 covers the stop ring 306 at the stop ring opening.

[0087] In this embodiment, the cutoff ring 306 and the epitaxial layer 107 have the same conductivity type. By anchoring the depletion region boundary of the terminal region, the depletion region is prevented from extending excessively outward, thus avoiding irregular overflow of electric field lines. The cutoff ring field plate 307 covers the cutoff ring 306 at the cutoff ring opening. The potential of the cutoff ring 306 is fixed by the metal field plate 305, stabilizing the potential reference of the boundary electric field. This ensures that the electric field lines are uniformly distributed inside the cutoff ring 306 and do not diffuse outward, thereby completely eliminating the risk of concentration of the boundary electric field, further reducing the surface peak electric field, blocking parasitic current paths, and suppressing parasitic effects.

[0088] In one feasible embodiment, in order to facilitate the preparation of the metal field plate 305 and reduce the preparation difficulty, the metal field plate 305 can be configured to cover the first field limiting ring 301 at the first opening and cover a portion of the field oxide layer 103 adjacent to the first opening.

[0089] In this embodiment, when the metal field plate 305 is connected to the first field limiting ring 301, in addition to covering the first opening, it can also cover the structure of the area adjacent to the first opening, such as covering part of the field oxide layer 103, which can reduce the difficulty of preparing the metal field plate 305 and improve the preparation efficiency.

[0090] The metal-oxide-semiconductor field-effect transistor provided in this application includes a substrate 106; an epitaxial layer 107 located on one side surface of the substrate 106, wherein first field limiting ring 301 regions are spaced apart in the epitaxial layer 107 along a first direction from the active region to the terminal region; a first field limiting ring 301 is disposed in the first field limiting ring 301 region, the first field limiting ring 301 being located in a region formed by extending a portion of its length in the direction pointing towards the substrate 106 from the side surface of the epitaxial layer 107 facing away from the substrate 106; and a field oxide layer 103 located on the side surface of the epitaxial layer 107 facing away from the substrate 106, and the field oxide layer 103 is further disposed thereon. 3. A first opening is formed at the first field limiting ring 301; a metal field plate 305 covers the first field limiting ring 301 at the first opening; the terminal region also includes a second field limiting ring 302 region, which is located beside the first field limiting ring 301 region along the first direction and is located in the field oxide layer 103 covered region; a second field limiting ring 302 is provided in the second field limiting ring 302 region, which is located beside the first field limiting ring 301; the doping concentration of the second field limiting ring 302 is greater than the doping concentration of the first field limiting ring 301, and the junction depth of the second field limiting ring 302 is less than the junction depth of the first field limiting ring 301.

[0091] In this embodiment, a first field-limiting ring 301 and a second field-limiting ring 302 are fabricated in the epitaxial layer 107 located in the terminal region. The doping concentration of doped ions in the second field-limiting ring 302 is greater than that in the first field-limiting ring 301, and the junction depth of the second field-limiting ring 302 is less than that of the first field-limiting ring 301. The second field-limiting ring 302 is set as a shallow junction high-doping concentration field-limiting ring relative to the first field-limiting ring 301, and is set corresponding to the field oxide layer 103. This can effectively shield the fixed charge and movable charge in the field oxide layer 103 in the terminal region, avoid the shrinkage of the depletion layer in the terminal region, improve the reliability of the device under high voltage scenarios, and improve the device's withstand voltage by combining the first field-effect ring. This achieves a simultaneous improvement in the device's operating performance and operating stability.

[0092] Furthermore, this embodiment improves the shielding effect on the charge in the field oxide layer 103 by setting the width of the second field limiting ring 302 in the outer region of the epitaxial layer 107 along the first direction to be greater than or equal to the width of the second field limiting ring 302 in the inner region of the epitaxial layer 107, thereby improving the reliability of the device under high voltage conditions. By setting the width of the second field limiting ring 302 in the outer region of the epitaxial layer 107 along the first direction to gradually increase, the shielding effect on the charge in the field oxide layer 103 is maintained while improving the ease of fabrication of the second field limiting ring 302 and its adaptability to the device. By setting the number of second field limiting rings 302 in the outer region of the epitaxial layer 107 along the first direction to be greater than or equal to the number of second field limiting rings 302 in the inner region of the epitaxial layer 107, the shielding effect on the charge in the field oxide layer 103 is improved, and the flexibility of fabrication of the second field limiting ring 302 is increased, ultimately improving the terminal device's performance. The electric field uniformity of the region is improved; by setting the second field limiting ring 302 in the epitaxial layer 107 along the first direction, the number of second field limiting rings 302 in the region gradually increases, improving the adaptability to the electric field in the terminal region and improving the shielding effect of the second field limiting rings 302 on charges; by setting the rightmost boundary of the polysilicon field plate 303 and the isolation dielectric layer 304 to be isolated by the isolation dielectric layer 304, the potential at the rightmost boundary of the polysilicon field plate 303 is different from the potential at the rightmost boundary of the metal field plate 305, thus constructing a multi-level electric field. The potential gradient precisely optimizes the electric field distribution at the terminal region, while enhancing the shielding effect on the charge in the field oxide layer 103, avoiding the concentration of the boundary electric field, and improving the withstand voltage stability and reliability. The cutoff ring 306 is used to anchor the depletion region boundary of the terminal region, preventing the depletion region from extending excessively outward and avoiding the irregular overflow of electric field lines. By setting the metal field plate 305 to cover the first field limiting ring 301 at the first opening and to cover part of the field oxide layer 103 adjacent to the first opening, the ease of fabrication of the metal field plate 305 is improved.

[0093] To make the embodiments of this application easier to understand, this application also provides a specific application scenario embodiment, which can be referred to above. Figure 4 or Figure 5 , Figure 4 This is a schematic diagram of the internal termination region of another metal-oxide-semiconductor field-effect transistor provided in this application embodiment; Figure 5 This is a schematic diagram of the structure of a termination region within a metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application. The metal-oxide-semiconductor field-effect transistor includes an active region and a termination region, wherein the termination region includes:

[0094] Substrate 106;

[0095] Epitaxial layer 107 is located on one side surface of substrate 106. First field limiting ring 301 regions are arranged at intervals in epitaxial layer 107 along a first direction from the active region to the terminal region. First field limiting ring 301 is disposed in the first field limiting ring 301 region. The first field limiting ring 301 is located in the region formed by extending a portion of the length from the side surface of epitaxial layer 107 facing away from substrate 106 along the direction pointing to substrate 106.

[0096] Field oxide layer 103 is located on the side surface of epitaxial layer 107 facing away from substrate 106, and a first opening is formed in the field oxide layer 103 corresponding to the first field limiting ring 301.

[0097] metal field plate 305;

[0098] A polysilicon field plate 303 and an isolation dielectric layer 304 are located at each first opening, each correspondingly covering a portion of the first field limiting ring 301 at the first opening to form a second opening. A metal field plate 305 covers the first field limiting ring 301 at the second opening. The polysilicon field plate 303 extends in a first direction, covering a portion of the field oxide layer 103 adjacent to the first opening. The isolation dielectric layer 304 extends in a second direction, covering the field oxide layer 103 adjacent to the first opening, and also covering a portion of the polysilicon field plate 303. The second direction is opposite to the first direction. The metal field plate 305 extends along the first direction, covering the polysilicon field plate 303, and also extends to cover a portion of the isolation dielectric layer 304.

[0099] The stop ring 306 and the stop ring 306 field plate are located in the epitaxial layer 107 along the first direction, in the outer region of all the first field limiting rings 301 and the second field limiting rings 302; the field oxide layer 103 has a stop ring opening at the stop ring 306, and the stop ring 306 field plate covers the stop ring 306 at the stop ring opening.

[0100] The terminal area also includes a second field limiting ring 302 area, which is located on the side of the first field limiting ring 301 area along the first direction and is located in the field oxide layer 103 covered area; a second field limiting ring 302 is provided in the second field limiting ring 302 area, which is located on the side of the first field limiting ring 301.

[0101] The doping concentration of the second field-limiting ring 302 is greater than that of the first field-limiting ring 301, and the junction depth of the second field-limiting ring 302 is less than that of the first field-limiting ring 301.

[0102] In the epitaxial layer 107, along the first direction, the width of the second field limiting ring 302 located on the outer side of the second field limiting ring 302 region is greater than or equal to the width of the second field limiting ring 302 located on the inner side of the second field limiting ring 302 region, and / or, the number of second field limiting rings 302 located on the outer side of the second field limiting ring 302 region along the first direction of the epitaxial layer 107 is greater than or equal to the number of second field limiting rings 302 located on the inner side of the second field limiting ring 302 region;

[0103] The metal field plate 305 covers the first field limiting ring 301 at the first opening and also covers a portion of the field oxide layer 103 adjacent to the first opening.

[0104] Figure 6 This is a schematic flowchart illustrating a method for fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) according to an embodiment of this application. As shown in the figure, the MOSFET includes an active region and a termination region. The method may include:

[0105] S601: Provides a substrate; the substrate includes a substrate and an epitaxial layer disposed on one side surface of the substrate;

[0106] S602: Fabricate an active functional layer in the active region;

[0107] S603: In the epitaxial layer of the terminal region, a first field-limiting ring region is prepared along a first direction from the active region to the terminal region, and a second field-limiting ring region is prepared on the side of the first field-limiting ring region along the first direction; a first field-limiting ring is provided in the first field-limiting ring region, and the first field-limiting ring is located in the region formed by extending a portion of the length from the surface of the epitaxial layer facing away from the substrate along the direction pointing to the substrate; a second field-limiting ring is provided in the second field-limiting ring region, and the second field-limiting ring is located on the side of the first field-limiting ring.

[0108] S604: After the first field-limiting ring region is fabricated, a field oxide layer and a metal field plate are fabricated on the epitaxial layer of the terminal region facing away from the substrate; the field oxide layer covers the second field-limiting ring and forms a first opening at the first field-limiting ring; the metal field plate covers the first field-limiting ring at the first opening; the doping concentration of the second field-limiting ring is greater than that of the first field-limiting ring, and the junction depth of the second field-limiting ring is less than that of the first field-limiting ring.

[0109] In the embodiments of this application, the epitaxial layer is generally prepared by epitaxial growth on one side surface of the substrate. The preparation of the active functional layer at the corresponding active region of the substrate can be based on existing techniques related to the required structure, and is not limited in the embodiments of this application. Furthermore, the structures in the embodiments of this application have already been described in the aforementioned metal-oxide-semiconductor field-effect transistors, and will not be repeated here.

[0110] To ensure the successful fabrication of the first and second field-limiting loops, the process involves fabricating spaced-apart first field-limiting loop regions along a first direction from the active region to the terminal region in the epitaxial layer of the terminal region, and fabricating second field-limiting loop regions alongside the first field-limiting loop regions along the first direction. This process may include the following steps. For details, please refer to [link / reference]. Figure 7 , Figure 7 This is a schematic flowchart of a method for preparing a first-field confined ring and a second-field confined ring, provided in an embodiment of this application.

[0111] S701: A first patterned photoresist is prepared on the surface of the epitaxial layer in the terminal region facing away from the substrate; the first patterned photoresist forms a first patterned photoresist opening at the first field-limiting ring region;

[0112] S702: Ions are implanted into the first field-confined ring region along the opening of the first patterned photoresist to form the first field-confined ring;

[0113] S703: On the surface of the epitaxial layer forming the first field-limiting ring facing away from the substrate, a second patterned photoresist is prepared; the second patterned photoresist forms a second patterned photoresist opening in the second field-limiting ring region; the first field-limiting ring region and the second field-limiting ring region are arranged alternately along the first direction;

[0114] S704: Ions are implanted into the second field-confined ring region along the opening of the second patterned photoresist to form the second field-confined ring.

[0115] In this embodiment, by preparing a first patterned photoresist and a second patterned photoresist, the first field-limiting ring and the second field-limiting ring are prepared respectively, ensuring that the first field-limiting ring and the second field-limiting ring are successfully prepared.

[0116] The method for fabricating a metal-oxide-semiconductor field-effect transistor using the embodiments of this application includes: S601: providing a substrate; the substrate includes a substrate and an epitaxial layer disposed on one side surface of the substrate; S602: fabricating an active functional layer at an active region; S603: in the epitaxial layer of the terminal region, a first field-limiting ring region spaced apart is fabricated along a first direction from the active region to the terminal region, and a second field-limiting ring region is fabricated beside the first field-limiting ring region along the first direction; a first field-limiting ring is disposed within the first field-limiting ring region, and the first field-limiting ring is located on the side surface of the epitaxial layer facing away from the substrate. In the region formed by extending a portion of the length in the direction pointing towards the substrate; a second field limiting ring is provided in the second field limiting ring region, and the second field limiting ring is located next to the first field limiting ring; S604: After the first field limiting ring region is prepared, a field oxide layer and a metal field plate are prepared on the surface of the epitaxial layer of the terminal region facing away from the substrate; the field oxide layer covers the second field limiting ring and forms a first opening at the first field limiting ring; the metal field plate covers the first field limiting ring at the first opening; the doping concentration of the second field limiting ring is greater than the doping concentration of the first field limiting ring, and the junction depth of the second field limiting ring is less than the junction depth of the first field limiting ring.

[0117] This embodiment of the application fabricates a first field-limiting ring and a second field-limiting ring in the epitaxial layer located in the terminal region. The doping concentration of the dopant ions in the second field-limiting ring is greater than that in the first field-limiting ring, and the junction depth of the second field-limiting ring is smaller than that of the first field-limiting ring. By setting the second field-limiting ring as a shallow junction, high-doping-concentration field-limiting ring relative to the first field-limiting ring, and corresponding to the field oxide layer, it can effectively shield the fixed and mobile charges in the field oxide layer of the terminal region, avoid the shrinkage of the depletion layer in the terminal region, and improve the reliability of the device under high-voltage scenarios. Combined with the first field-effect ring to improve the device's withstand voltage, this embodiment of the application achieves simultaneous improvement in device performance and operational stability. In addition, this embodiment of the application fabricates a first patterned photoresist and a second patterned photoresist to respectively complete the fabrication of the first and second field-limiting rings, ensuring the successful fabrication of the first and second field-limiting rings.

[0118] To make the embodiments of this application easier to understand, this application also provides a specific application scenario embodiment, wherein the method for fabricating a metal-oxide-semiconductor field-effect transistor may specifically include the following steps. (See reference...) Figure 8 , Figure 8 This is a flowchart illustrating a method for fabricating a metal-oxide-semiconductor field-effect transistor according to an embodiment of this application.

[0119] S801: P-type ion implantation and annealing are performed on the N-type epitaxial layer 901 in the provided substrate using a first patterned photoresist 902 to form a first field-limiting ring 301.

[0120] The structure prepared by step S801 is as follows Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor after the first field-limiting ring is fabricated in the internal terminal region, as provided in an embodiment of this application.

[0121] S802: P-type heavily doped ions are implanted and annealed using the second patterned photoresist 1001 to form the second field confinement ring 302.

[0122] The structure prepared by step S802 is as follows Figure 10 As shown, Figure 10 This is a schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor after the fabrication of a second field-limiting ring in the internal terminal region, as provided in an embodiment of this application.

[0123] S803: N-type heavily doped ions are implanted using a third patterned photoresist to form a cutoff ring 306.

[0124] S804: An initial field oxide layer is grown on the upper surface of the N-type epitaxial layer 901 by thermal oxidation.

[0125] S805: The initial field oxide layer is etched using the fourth patterned photoresist to obtain the field oxide layer 103 with the first opening.

[0126] The structure prepared by step S805 is as follows Figure 11 As shown, Figure 11 This is a schematic diagram of the structure of a metal-oxide-semiconductor field-effect transistor after a field oxide layer with a first opening has been formed in the terminal region of the transistor provided in this application.

[0127] S806: Prepare polycrystalline silicon field plate 303, isolation dielectric layer 304 and metal field plate 305, and evaporate to form back metal 308.

[0128] The structure prepared by step S806 is as follows Figure 12 As shown, Figure 12 This is an example diagram of the structure of a metal-oxide-semiconductor field-effect transistor after the fabrication of the internal termination region, as provided in an embodiment of this application. The structure also includes a stop ring field plate 307 and a source field plate 104.

[0129] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A metal-oxide-semiconductor field-effect transistor, characterized in that, The metal-oxide-semiconductor field-effect transistor includes an active region and a termination region, wherein the termination region includes: Substrate; An epitaxial layer is located on one side surface of the substrate. First field limiting ring regions are arranged at intervals in the epitaxial layer along a first direction from the active region to the terminal region. A first field limiting ring is disposed in the first field limiting ring region. The first field limiting ring is located in a region formed by extending a portion of the length from the side surface of the epitaxial layer facing away from the substrate along the direction pointing to the substrate. A field oxide layer is located on the side surface of the epitaxial layer facing away from the substrate, and a first opening is formed in the field oxide layer at the first field limiting ring. A metal field plate, the metal field plate covering the first field limiting ring at the first opening; The terminal area further includes a second field-limiting ring region, which is located beside the first field-limiting ring region along the first direction and corresponds to the field oxide layer coverage area; a second field-limiting ring is disposed within the second field-limiting ring region, which is located beside the first field-limiting ring; when the direction of the epitaxial layer away from the substrate is taken as the upper side, the second field-limiting ring is located directly below the field oxide layer, or the second field-limiting ring is covered by the field oxide layer; The doping concentration of the second field-limiting ring is greater than that of the first field-limiting ring, and the junction depth of the second field-limiting ring is less than that of the first field-limiting ring.

2. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, In the epitaxial layer, along the first direction, the width of the second field limiting ring in the outer second field limiting ring region is greater than or equal to the width of the second field limiting ring in the inner second field limiting ring region.

3. The metal-oxide-semiconductor field-effect transistor according to claim 2, characterized in that, Along the first direction in the epitaxial layer, the width of the second field limiting ring gradually increases in the second field limiting ring region.

4. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, In the epitaxial layer, along the first direction, the number of second field limiting rings in the second field limiting ring region located on the outer side is greater than or equal to the number of second field limiting rings in the second field limiting ring region located on the inner side.

5. The metal-oxide-semiconductor field-effect transistor according to claim 4, characterized in that, Along the first direction in the epitaxial layer, the number of second field-limiting loops in the second field-limiting loop region gradually increases.

6. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The terminal area also includes: A polycrystalline silicon field plate and an isolation dielectric layer are located at each of the first openings, each correspondingly covering a portion of the first field limiting ring at the first opening to form a second opening, and the metal field plate covers the first field limiting ring at the second opening; The polycrystalline silicon field plate extends in the first direction and covers the portion of the field oxide layer adjacent to the first opening; The insulating dielectric layer extends in a second direction, covering the field oxide layer adjacent to the first opening, and also covering a portion of the polycrystalline silicon field plate; the second direction is opposite to the first direction. The metal field plate extends along the first direction to cover the polycrystalline silicon field plate, and also extends to cover a portion of the isolation dielectric layer.

7. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The terminal area also includes a stop ring and a stop ring field plate; The cutoff ring is located in the epitaxial layer along the first direction, in the outer region of all the first field limiting rings and the second field limiting rings; The field oxide layer corresponds to the formation of a stop ring opening at the stop ring, and the stop ring field plate covers the stop ring at the stop ring opening.

8. The metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The metal field plate covers the first field limiting ring at the first opening and also covers the portion of the field oxide layer adjacent to the first opening.

9. A method for fabricating a metal-oxide-semiconductor field-effect transistor, characterized in that, The metal-oxide-semiconductor field-effect transistor includes an active region and a termination region, and the method includes: A substrate is provided; the substrate includes a substrate and an epitaxial layer disposed on one side surface of the substrate; An active functional layer is fabricated in the active region; In the epitaxial layer of the terminal region, a first field-limiting ring region is prepared along a first direction from the active region to the terminal region, and a second field-limiting ring region is prepared on the side of the first field-limiting ring region along the first direction; a first field-limiting ring is disposed in the first field-limiting ring region, and the first field-limiting ring is located in a region formed by extending a portion of the length from the surface of the epitaxial layer facing away from the substrate along the direction pointing to the substrate; a second field-limiting ring is disposed in the second field-limiting ring region, and the second field-limiting ring is located on the side of the first field-limiting ring. After the first field-limiting ring region is fabricated, a field oxide layer and a metal field plate are fabricated on the surface of the epitaxial layer in the terminal region facing away from the substrate. The field oxide layer covers the second field-limiting ring and forms a first opening at the first field-limiting ring. When the direction of the epitaxial layer facing away from the substrate is taken as the upper side, the second field-limiting ring is located directly below the field oxide layer, or the second field-limiting ring is covered by the field oxide layer. The metal field plate covers the first field-limiting ring at the first opening. The doping concentration of the second field-limiting ring is greater than the doping concentration of the first field-limiting ring, and the junction depth of the second field-limiting ring is less than the junction depth of the first field-limiting ring.

10. The method for fabricating a metal-oxide-semiconductor field-effect transistor according to claim 9, characterized in that, In the epitaxial layer of the terminal region, a first field-limiting loop region is prepared along a first direction from the active region to the terminal region, and a second field-limiting loop region is prepared on the side of the first field-limiting loop region along the first direction, including: A first patterned photoresist is prepared on the surface of the epitaxial layer in the terminal region facing away from the substrate; the first patterned photoresist forms a first patterned photoresist opening at the first field-limiting ring region; Ions are implanted into the first field-limiting ring region along the first patterned photoresist opening to form the first field-limiting ring. A second patterned photoresist is prepared on the surface of the epitaxial layer that forms the first field limiting ring, facing away from the substrate; the second patterned photoresist forms a second patterned photoresist opening in the second field limiting ring region; the first field limiting ring region and the second field limiting ring region are arranged alternately along the first direction; Ions are implanted into the second field-limiting ring region along the second patterned photoresist opening to form the second field-limiting ring.

Images