Resonant frequency locking circuit device, control method, apparatus, medium and product thereof

Abstract

Embodiments of the present application provide a resonant frequency locking circuit device, which can be applied to the technical field of integrated circuit chip control, and is specifically applied to resonant frequency locking of a target load. The resonant frequency locking circuit device comprises a self-oscillation loop with a gain greater than or equal to 1, which is composed of a signal generation module, a signal processing module, a control generation module and a signal updating module. The signal generation module is used for performing two-stage integral processing on a current load signal of the target load to generate a two-stage integral signal; the signal processing module is used for performing waveform conversion and phase conversion processing on the two-stage integral signal to generate a current phase shift signal; wherein the current phase shift signal realizes 360° phase shift relative to the current load signal; a first capacitor of the signal generation module is connected in series with the target load, and the other end thereof is connected to an output end of the signal updating module. The present application further provides a control method, equipment, storage medium and program product of the resonant frequency locking circuit device.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip control technology, specifically to the field of chip driver circuit technology, and more specifically to a resonant frequency locking circuit device and its control method, equipment, medium and product. Background Technology

[0002] In order to maintain the optimal operating level of core control chips, various portable electronic products (such as mobile phones and tablets) and high-precision technologies (such as lithography technology and artificial intelligence technology) have placed higher demands on the heat dissipation capabilities of their chips. For the heat dissipation of these integrated circuit chips, two methods are typically employed: active and passive. Active cooling is generally significantly more effective than passive cooling. Active cooling often relies on chip-level micro-piezoelectric ceramic air pumps and micro-cooling fans. For example, micro-piezoelectric ceramic air pumps primarily utilize the piezoelectric drive principle, using the high-frequency vibration of an electrically controlled ceramic plate to drive airflow within a cavity, thereby achieving precise microfluidic delivery and heat dissipation for the corresponding chip. This method offers advantages such as miniaturization, low power consumption, low noise, low vibration, fast response, and high reliability.

[0003] Existing active cooling methods typically employ miniature air pumps or miniature fans. To maintain optimal operating levels, their resonant frequency must be consistently maintained at the resonant point (i.e., the intrinsic resonant frequency), a process known as frequency locking. Traditional frequency locking schemes primarily rely on fixed-frequency open-loop pulse width modulation (PWM) or digital sampling of the input current to achieve the resonant point (intrinsic resonant frequency) at maximum output power. However, these driving methods lack an adaptive frequency locking mechanism, resulting in an inability to dynamically adjust the frequency. Furthermore, digital sampling leads to higher system power consumption and increased circuit costs. Even existing feedback control methods based on phase-locked loops (PLLs) suffer from relatively complex control loops, high costs, poor stability, slow response speeds, and large circuit sizes, making them difficult to widely adapt to the needs of small-scale, high-efficiency applications. Summary of the Invention

[0004] Addressing at least one of the technical problems of existing resonant frequency locking schemes used in piezoelectric ceramic air pumps and micro fans for high-precision chips, such as poor frequency locking capability, high energy loss, low overall efficiency, poor frequency locking stability, high cost due to circuit complexity, and large size, embodiments of the present invention propose a resonant frequency locking circuit device and its control method, equipment, medium, and product. This provides a stable and dynamically adjustable novel frequency locking architecture, aiming to ensure the locking of the resonant frequency by achieving a 360° phase shift of the voltage phase or current phase of the target load (such as piezoelectric ceramic air pumps, micro fans, and other loads based on RLC circuit models or RLC-like circuit models), thereby achieving stable maintenance of the maximum power of the target load and compensating for the gap in chip heat dissipation capacity caused by the inability of existing process technology to reach the top level.

[0005] Another aspect of the present invention provides a resonant frequency locking circuit device for locking the resonant frequency of a target load, comprising a signal generation module, a signal processing module, a control generation module, and a signal update module. The signal generation module performs two-stage integration processing on the current load signal at one end of the target load to generate a two-stage integrated signal. The input terminal of the signal processing module is connected to the output terminal of the signal generation module, and performs waveform conversion and phase conversion processing on the two-stage integrated signal to generate a current phase-shifted signal; wherein the current phase-shifted signal achieves a 360° phase shift relative to the current load signal. The input terminal of the control generation module is connected to the output terminal of the signal processing module, and generates at least one control signal based on the current phase-shifted signal. The input terminal of the signal update module is connected to the output terminal of the control generation module, and updates the current load signal based on at least one control signal. The signal generation module, signal processing module, control generation module, and signal update module constitute a self-oscillating loop with a gain greater than or equal to 1 to achieve resonant frequency locking. The signal generation module includes a first capacitor, one end of which is connected to one end of the target load and in series with the target load, and the other end of which is connected to the output terminal of the signal update module.

[0006] According to one embodiment of the present invention, the resonant frequency locking circuit device further includes a signal output module. The signal output module is connected in parallel with the target load and is used to provide feedback on the direction of the current load signal.

[0007] According to one embodiment of the present invention, a first capacitor is used to perform a first-stage integration phase shift on the current load signal to generate a first-stage phase-shifted signal; wherein, the signal generation module further includes an integrator processor. The input terminal of the integrator processor is connected to both ends of the first capacitor in a differential input form, and is used to perform a second-stage integration phase shift on the first-stage phase-shifted signal to generate a second-stage phase-shifted signal, wherein the second-stage phase-shifted signal is a two-stage integration signal.

[0008] According to one embodiment of the present invention, the integrator processor includes an integrator amplifier and a second capacitor. A first input terminal of the integrator amplifier is connected to one end of a first capacitor, and the other end of the integrator amplifier is connected to the other end of the first capacitor; one end of the second capacitor is connected to the output terminal of the integrator amplifier, and the other end of the second capacitor is grounded.

[0009] According to one embodiment of the present invention, the signal processing module further includes a comparator. The first input terminal of the comparator is connected to the output terminal of the integrator processor, and its second input terminal is connected to a preset reference signal. The comparison result between the preset reference signal and the second-stage phase-shift signal is used to output a waveform-converted phase-shift signal.

[0010] According to one embodiment of the present invention, the signal processing module further includes a first inverter. The input terminal of the first inverter is connected to the output terminal of the comparator, and is used to perform phase inversion processing on the waveform-converted phase-shift signal to generate the current phase-shift signal.

[0011] According to one embodiment of the present invention, the control generation module includes a second inverter, a first driver, a second driver, and a full-bridge converter. The input terminal of the second inverter is connected to the output terminal of the first inverter, and is used to invert the current phase-shift signal to generate an inverted control signal; the input terminal of the first driver is connected to the output terminal of the second inverter, and is used to generate a first drive signal and a second drive signal based on the inverted control signal; the input terminal of the second driver is connected to the output terminal of the first inverter, and is used to generate a third drive signal and a fourth drive signal based on the current phase-shift signal.

[0012] According to one embodiment of the present invention, the first driver includes two inverters connected in parallel, and the second driver includes two inverters connected in parallel.

[0013] According to one embodiment of the present invention, the signal update module includes a full-bridge converter. The input terminal of the full-bridge converter is correspondingly connected to the output terminal of the first driver and the output terminal of the second driver, and is used to control a preset input power supply connected to the full-bridge converter to update the current load signal applied to the target load according to the first driving signal, the second driving signal, the third driving signal and the fourth driving signal.

[0014] According to an embodiment of the present invention, a full-bridge converter includes a first P-type transistor, a first N-type transistor, a second P-type transistor, and a second N-type transistor. The gate of the first P-type transistor is connected to the first output terminal of a first driver, its source is connected to a preset input power supply, and its drain is connected to a first capacitor, used to control the conduction and disconnection of the first P-type transistor according to a first drive signal. The gate of the first N-type transistor is connected to the second output terminal of the first driver, its source is grounded, and its drain is connected to the drain of the first P-type transistor, used to control the conduction and disconnection of the first N-type transistor according to a second drive signal. The gate of the second P-type transistor is connected to the first output terminal of a second driver, its source is connected to a preset input power supply, and its drain is connected to a target load, used to control the conduction and disconnection of the second P-type transistor according to a third drive signal. The gate of the second N-type transistor is connected to the second output terminal of the second driver, its source is grounded, and its drain is connected to the drain of the second P-type transistor, used to control the conduction and disconnection of the second N-type transistor according to a fourth drive signal.

[0015] Another aspect of the present invention provides a control method for the above-described resonant frequency locking circuit device, applied to the resonant frequency locking of a target load. The resonant frequency locking circuit device includes a signal generation module, a signal processing module, a control generation module, and a signal update module, forming a self-oscillating loop with a gain greater than or equal to 1. The control method includes: performing two-stage integration processing on the current load signal at one end of the target load to generate a two-stage integrated signal; performing waveform conversion and phase conversion processing on the two-stage integrated signal to generate a current phase-shifted signal; wherein the current phase-shifted signal achieves a 360° phase shift relative to the current load signal; generating at least one control signal based on the current phase-shifted signal; and updating the current load signal based on the at least one control signal to achieve resonant frequency locking.

[0016] Another aspect of the present invention provides an electronic device including one or more processors and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to perform the control method of the resonant frequency locking circuit device described above.

[0017] Another aspect of the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the control method of the resonant frequency locking circuit device described above.

[0018] Another aspect of the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the control method of the above-described resonant frequency locking circuit device.

[0019] The resonant frequency locking circuit device and its control method provided in this invention can at least partially solve the technical problems of high energy loss, low overall efficiency, poor frequency locking stability, high cost and large size caused by circuit complexity in related technologies, and thus can achieve at least one of the following technical effects:

[0020] (1) First, by constructing a 360° phase-shifted frequency-locking feedback loop, the resonant frequency of the target load can be accurately locked, which can realize an adaptive frequency-locking mechanism with higher response speed, effectively ensure the maximum working efficiency of the target load, significantly improve the working efficiency and working stability of the target load, and at the same time, it can dynamically adjust the frequency-locking of the target LC resonant frequency according to the individual characteristics and life changes of the target load, realize automatic tracking and stable driving of the resonant frequency, further ensure its frequency-locking stability, and achieve the effect of dynamic frequency-locking.

[0021] (2) In addition, in the resonant frequency locking circuit device in the embodiments of the present invention, the more complex circuit design usually used in the existing digital sampling and phase-locked loop frequency locking scheme can be directly eliminated, thereby effectively avoiding additional power loss and efficiency loss caused by the presence of complex circuit components, greatly saving costs, further improving the operating power of the target load (such as a piezoelectric ceramic air pump), and greatly improving working efficiency.

[0022] (3) Furthermore, the application of ADC converter and MCU microcontroller can be eliminated. On this basis, there is no need for other circuit components to cooperate with them. This greatly simplifies the composition of the frequency locking circuit structure. Efficient and accurate frequency locking dynamic control can be achieved based only on basic circuit components such as integral phase shift and drive bridge. This further reduces the power consumption caused by complex circuit components in the system, and also significantly reduces the circuit cost and overall circuit size (such as the area occupied).

[0023] (4) It can avoid the signal acquisition components or circuit design such as inductive resistors used in existing frequency locking technology. Moreover, through the series design of the first capacitor and the target load, it can simultaneously realize the dual functions of the first-stage integration processing and integration signal sampling, thereby greatly reducing the circuit complexity, further reducing the circuit cost and area occupied. At the same time, it can also improve the frequency locking control response speed and stability of the system frequency locking control loop, and further reduce the circuit power consumption, making the circuit simpler and more efficient. It can also ensure the dynamic automatic tracking frequency locking effect and realize the stable driving of the target load.

[0024] (5) Because the first capacitor can be connected in series with the target load, even if the two input terminals of the integrating amplifier are connected to the first capacitor in the form of differential input, the interference of DC signal and high-frequency noise can be effectively eliminated, and the error amplification caused by the first-stage integration phase shift process can also be avoided. In this way, the circuit design of signal isolation and bias processing that must be added in the existing frequency locking scheme can also be effectively eliminated, further simplifying the circuit design. While ensuring the automatic frequency locking effect, the integration phase shift module is simplified to the extreme.

[0025] Therefore, the resonant frequency locking circuit device and its control method described in the embodiments of the present invention can be more widely adapted to the needs of small and high-efficiency scenarios. Even under the current chip manufacturing process level, it can be better applied to high-precision electronic products (such as micro heat sinks for automotive chips or mobile phone chips) or equipment (such as micro heat sinks for extreme ultraviolet light source chips in lithography machines), so that its chips can achieve the same or even better operating capabilities as chips with higher chip manufacturing processes, and have a very wide range of product applications.

[0026] Therefore, the resonant frequency locking circuit device and its control method based on the embodiments of the present invention can provide a dynamic frequency locking technology that is more efficient, more stable, lower power consumption, lower cost, more practical, and easier to implement and promote compared with existing frequency locking schemes. It can accurately lock the optimal resonant frequency of existing micro heat dissipation devices such as piezoelectric ceramic air pumps, and has extremely important practical value and economic benefits.

[0027] It should be understood that the above general description and the following specific embodiments are merely exemplary and illustrative, and do not limit the scope of the invention. Attached Figure Description

[0028] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0029] Figure 1A A schematic diagram illustrating a circuit structure of a resonant frequency locking circuit device according to an embodiment of the present invention is shown.

[0030] Figure 1B This schematically illustrates another circuit structure diagram of a resonant frequency locking circuit device according to an embodiment of the present invention;

[0031] Figure 2 The diagram illustrates an application scenario of the resonant frequency locking circuit device, control method, apparatus, medium, and program product according to embodiments of the present invention.

[0032] Figure 3A flowchart illustrating a control method for a resonant frequency lock-in circuit device according to an embodiment of the present invention is shown schematically; and

[0033] Figure 4 A block diagram of an electronic device suitable for implementing a control method for a resonant frequency locking circuit device according to an embodiment of the present invention is shown schematically.

[0034] The accompanying drawings mentioned above are part of the specification of embodiments of the present invention, illustrating exemplary embodiments of the invention. The drawings, together with the description in the specification, serve to illustrate the principles of the embodiments of the present invention. It should be understood that the above general description with reference to the drawings and the following detailed description are merely exemplary and illustrative, and do not limit the scope of the invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the spirit of the contents disclosed in the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the technology taught in the present invention without departing from the spirit and scope of the present invention.

[0036] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0037] The terms "first," "second," etc., used in this invention do not specifically refer to any order or sequence, nor are they intended to limit the invention; they are merely used to distinguish elements or operations described using the same technical terms.

[0038] The directional terms used in this invention, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this invention.

[0039] The terms “comprising,” “including,” “having,” “containing,” etc., used in this invention are all open-ended terms, meaning that they include but are not limited to.

[0040] The term "and / or" as used in this invention includes any or all combinations of the things mentioned.

[0041] In this invention, "multiple" includes "two" and "more than two"; in this invention, "multiple groups" includes "two groups" and "more than two groups".

[0042] The terms "approximately," "about," etc., used in this invention are intended to modify any quantity or error that may vary slightly, but these slight variations or errors do not change the essence of the quantity or error. Generally, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in some embodiments, 5% in some embodiments, or other values. Those skilled in the art should understand that the aforementioned values ​​can be adjusted according to actual needs and are not limited thereto.

[0043] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0044] When expressions such as "at least one of A, B, and C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When expressions such as "at least one of A, B, or C" are used, they should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). A person skilled in the art should also understand that any conjunction and / or phrase that substantially arbitrarily indicates two or more optional items, whether in the specification, claims, or drawings, should be understood to indicate the possibility of including one of these items, either of these items, or both items. For example, the phrase “A or B” should be understood as including the possibility of “A” or “B”, or “A and B”.

[0045] Piezoelectric ceramic pumps are widely used in heat dissipation, air inflation, and other applications, and their resonant characteristics can effectively improve energy transfer efficiency. The general electrical model of a conventional piezoelectric ceramic pump can typically be equivalent to a parallel connection of multiple series LC branches and one series RC branch. When the pump reaches its inherent resonant frequency, it exhibits characteristics of minimum phase shift, minimum impedance, maximum output power, and maximum energy conversion efficiency.

[0046] Therefore, in the field of driving micro heat sinks for chips such as piezoelectric ceramic air pumps, when these target loads operate at their intrinsic resonant frequency (resonant point), it can ensure that the input and output power of the load are maximized simultaneously, thus achieving the optimal chip operating level. However, the resonant frequency is extremely sensitive to changes in mass production process deviations, load variations, power supply disturbances, and environmental parameters (such as temperature, device aging, etc.). Traditional driving circuits often cannot guarantee that the output frequency is consistent with the resonant point for a long time, causing the system to deviate from the optimal operating point, resulting in power loss, efficiency reduction, and even device damage.

[0047] To ensure that the load devices of these miniature chip heat sinks always operate near their resonant points, frequency locking (i.e., frequency locking) needs to be implemented in the drive circuits of these loads. Currently, the most common driving methods include fixed-frequency open-loop pulse width modulation (PWM) and methods that determine the resonant frequency at maximum output power by digitally sampling the input current. However, the above-mentioned traditional methods generally lack adaptive frequency locking mechanisms, cannot effectively and directly obtain the resonant frequency of the load, and cannot dynamically adjust the frequency according to changes in the load (such as aging), thus easily causing resonance misalignment. Furthermore, the resonant frequency, impedance, temperature drift, and other indicators of the load will also have individual differences during mass production, and the resonant power of the load will lead to a decrease in system efficiency due to issues such as output voltage amplitude or long-term aging. Traditional digital sampling requires analog-to-digital conversion circuits and digital computing modules (such as analog-to-digital converters, microcontrollers, and drivers), resulting in high system power consumption and circuit costs. Although some drive circuits introduce feedback control methods such as phase-locked loops, their control loops are relatively complex, have slow response speeds, and are costly, making it difficult to widely adapt to the needs of small, high-efficiency scenarios.

[0048] The existing resonant frequency locking schemes used in piezoelectric ceramic air pumps and micro fans for high-precision chips suffer from at least one of the following technical problems: poor frequency locking capability, high energy loss, low overall efficiency, poor frequency locking stability, and high cost and large size due to circuit complexity. Although some frequency locking technologies can achieve corresponding dynamic frequency locking and adaptive driving effects, they still have the problem of complex design of integral circuit modules or integral phase shift circuits. As a result, they still cannot achieve lower energy consumption, faster response, higher power and higher efficiency output, and it is also difficult to further simplify the structure.

[0049] To address at least one of the problems existing in the aforementioned frequency locking technologies, embodiments of the present invention propose a resonant frequency locking circuit device and its control method, equipment, medium, and product, thereby providing a stable and dynamically adjustable novel frequency locking architecture. This aims to ensure automatic tracking and locking of the resonant frequency by achieving a 360° phase shift of the voltage or current phase of the target load (such as piezoelectric ceramic air pumps, micro fans, etc., based on RLC or RLC-like circuit models). This achieves stable maintenance of the maximum power and efficiency of the target load, thus compensating for the gap in chip heat dissipation capacity caused by the inability of existing process technology to reach top-tier levels. Simultaneously, it greatly simplifies the integrating circuit, further reducing circuit energy consumption, improving circuit response speed, enhancing circuit stability, and providing a smaller circuit footprint, while ensuring higher efficiency and higher power output.

[0050] To enable those skilled in the art to have a clearer understanding of the resonant frequency locking circuit device and its control method according to the embodiments of the present invention, the following further provisions are provided. Figures 1A-4 Explanation.

[0051] like Figure 1A and Figure 1B As shown, another aspect of the present invention provides a resonant frequency locking circuit device 100 for locking the resonant frequency of a target load P, wherein the resonant frequency locking circuit device 100 includes a signal generation module 110, a signal processing module 120, a control generation module 130, and a signal update module 140.

[0052] The signal generation module 110 is used to perform two-stage integration processing on the current load signal at one end of the target load P to generate a two-stage integrated signal;

[0053] The input terminal of the signal processing module 120 is connected to the output terminal of the signal generation module 110, and is used to perform waveform conversion and phase conversion processing on the two-stage integrated signal to generate the current phase-shifted signal; wherein, the current phase-shifted signal achieves a 360° phase shift relative to the current load signal;

[0054] The input terminal of the control generation module 130 is connected to the output terminal of the signal processing module 120, and is used to generate at least one control signal based on the current phase shift signal;

[0055] The input terminal of the signal update module 140 is connected to the output terminal of the control generation module 130, and is used to update the current load signal according to at least one control signal;

[0056] The signal generation module 110, signal processing module 120, control generation module 130 and signal update module 140 constitute a self-oscillating loop with a gain greater than or equal to 1 to achieve resonant frequency locking. The signal generation module includes a first capacitor 111, one end of which is connected to one end of the target load P and is connected in series with the target load P. The other end of the first capacitor 111 is connected to the output terminal of the signal update module 140.

[0057] In this embodiment of the invention, the target load P can be a load device based on an RLC circuit model or a similar RLC circuit model, such as a piezoelectric ceramic air pump or a micro fan. The target load P (e.g., a piezoelectric ceramic air pump) typically has its own inherent resonant frequency (i.e., intrinsic resonant frequency). Under a constant input voltage, when the actual operating frequency of the target load P is lower than its intrinsic resonant frequency, its output power (e.g., the mechanical exhaust power of the piezoelectric ceramic air pump) decreases, and the phase of its input current advances the phase of the input voltage. Conversely, when the actual operating frequency of the target load P is higher than its intrinsic resonant frequency, its output power also decreases, and the phase of its input current lags behind the phase of the input voltage. Therefore, only when the actual operating frequency of the target load P is equal to its intrinsic resonant frequency does its output power reach its maximum, and the phase of its input current is equal to or substantially equal to its voltage phase.

[0058] The target load P can be driven to operate through the signal update module 140, specifically by connecting a preset input power supply V. HV The signal update module 140 applies a drive electrical signal to the target load P to enable the target load P to start and maintain operation. The current load signal can be the actual electrical signal of the target load P at the current moment, such as the current signal or voltage signal flowing through the target load P at the current moment.

[0059] The signal generation module 110 is mainly used to acquire the current load signal and perform two phase shifts, resulting in a 180° phase shift and forming a two-stage integrated signal. That is, the two-stage integrated signal has a 180° phase shift relative to the current load signal. Specifically, the first capacitor 111 of the signal generation module 110 is mainly used for the first-stage phase shift processing of the current load signal, achieving at least a 90° phase shift.

[0060] In the signal generation module 110, the first capacitor 111 is connected in series between the signal update module 140 and the target load P. This effectively replaces the traditional electrical signal sensing unit (such as a sensing resistor), directly realizing the first-stage integration processing of the current load signal flowing through the target load P, forming a two-stage integrated signal that can be processed in the second stage, resulting in a 90° phase shift. Therefore, in the signal generation module 110 of this embodiment, the signal acquisition components or circuit designs such as sensing resistors used in existing frequency locking technologies can be avoided. Moreover, through the series design of the first capacitor 111 and the target load P, the dual functions of first-stage integration processing and integrated signal sampling can be achieved simultaneously, thereby greatly reducing circuit complexity, further reducing circuit cost and footprint, improving the frequency locking control response speed and stability of the system's frequency locking control loop, further reducing circuit power consumption, making the circuit simpler and more efficient, and ensuring dynamic automatic tracking frequency locking effect to achieve stable driving of the target load P.

[0061] The signal processing module 120 is mainly used to perform waveform conversion and phase conversion processing on the two-stage integral signals output by the signal generation module 110. The waveform conversion can change the waveform of the two-stage integral signals, for example, converting a sine wave (sin waveform) to a square wave, or vice versa, without specific limitations. In this embodiment of the invention, the input waveforms of the current load signal and the corresponding two-stage integral signals can be sine waves, while the two-stage integral signals, after waveform conversion processing, can be transformed into square wave signals. The signal after waveform conversion processing differs from the two-stage integral signals only in waveform; its amplitude, period, and other signal characteristics remain unchanged.

[0062] Furthermore, the signal processing module 120 can perform phase conversion processing on the signal after waveform conversion, so that the final current phase-shifted signal can produce a 180° phase inversion effect relative to the two-stage integral signal. In this way, the current phase-shifted signal can have a 180° phase shift compared to the two-stage integral signal, and a 360° phase shift relative to the original current load signal. Therefore, this current phase-shifted signal is used as the driving signal for the subsequent control generation module 130. Finally, the signal generation module 110, signal processing module 120, control generation module 130 and signal update module 140 together form a self-oscillating loop with a gain greater than or equal to 1. This ensures that the waveforms of the current phase-shifted signal and the original input current load signal are completely superimposed to form a positive excitation loop. Moreover, the design of the loop gain greater than or equal to 1 also ensures that the signal can at least maintain the original signal amplitude in each cycle. Subsequently, the amplitude exponential growth can be limited by nonlinear elements (such as inverters with saturation characteristics) to achieve the final dynamic equilibrium state, forming a self-oscillating loop based on positive feedback.

[0063] The control generation module 130 is mainly used to output at least one control signal to the signal update module 140 according to the current phase shift signal. The at least one control signal enables the signal update module 140 to adjust and update the drive signal applied to the target load P, thereby realizing the update of the current load signal.

[0064] The signal update module 140 can be connected to a preset input power supply V. HV It can respond to at least one control signal provided by the control generation module 130 to realize the control of the preset input power supply V. HV The input control adjusts and updates the drive signal applied to the target load P, thereby updating the current load signal.

[0065] In summary, by utilizing the self-oscillating positive feedback loop jointly formed by the signal generation module 110, signal processing module 120, control generation module 130, and signal update module 140, the current load signal of the detected target load P can be dynamically and adaptively updated. This ensures that the target load P always operates at its actual intrinsic frequency under its current state. Regardless of individual differences in the target load P (such as load changes during mass production, power supply disturbances, and changes in environmental parameters), or any changes in the circuit operating environment (such as changes in external temperature) or internal circuit aging leading to adjustments in the actual intrinsic frequency, it can always maintain its actual intrinsic frequency under the corresponding state. This achieves automatic summation and stable driving of the resonant frequency, ensuring the locking of the actual intrinsic frequency of the target load P. The circuit feedback control response speed is faster, the frequency locking effect is more stable and reliable, and the target load P is always kept operating in its optimal state (maximum power output and maximum efficiency output).

[0066] Therefore, this eliminates the disadvantages of complex circuit structure, high circuit cost, and high energy consumption inherent in traditional drive circuits or traditional frequency locking designs. It is evident that the resonant frequency locking circuit device 100 of this embodiment can effectively solve at least one of the aforementioned problems existing in the prior art, possessing advantages such as more stable and accurate frequency locking capability, lower energy consumption, and higher overall efficiency. Furthermore, the overall circuit design is simpler, the circuit size is smaller, and the cost is lower, making it effectively applicable to target loads in small, high-efficiency, high-precision chips, such as piezoelectric ceramic air pumps and micro fans, which are loads based on RLC circuit models or RLC-like circuit models.

[0067] like Figure 1A and Figure 1B As shown, according to an embodiment of the present invention, the resonant frequency locking circuit device 100 further includes a signal output module 150.

[0068] The signal output module 150 is connected in parallel with the target load P to provide feedback on the direction of the current load signal.

[0069] The signal output module 150 can be used to output the direction (e.g., high or low level) of the current load signal of the target load P to the signal generation module 110. Specifically, the signal output module 150 can be a feedback circuit module composed of certain circuit elements, or a signal feedback circuit element or assembly formed by a single or a few circuit elements (e.g., resistors). The signal output module 150 can be connected in parallel with the target load P and can provide a feedback electrical signal to the signal generation module 110.

[0070] When the target load P is implemented based on an RLC circuit model, it typically has three circuit elements: inductor, capacitor, and resistor. The capacitor cannot provide feedback of a DC (Direct Current) signal (a DC start-up signal is usually required before startup). However, the signal output module 150 can provide a feedback electrical signal to the signal generation module 110 to indicate the direction of application of the aforementioned DC start-up signal, thereby establishing negative (or positive) feedback in the equivalent circuit of the target load P. For example... Figure 1A As shown, negative feedback can be understood as follows: if the signal output module 150 provides a low-frequency feedback signal, it means that the initial electrical signal on the right side of the target load P is a high-level signal. In order to ensure that the target load P maintains its inherent frequency, the current load signal of the target load P should be updated through the aforementioned self-oscillation loop to pull down the initial signal on the right side of the target load P. Conversely, it can pull up the initial signal on the right side of the target load P, which will not be elaborated here.

[0071] Therefore, the direction of the DC starting signal applied to the target load P can be indicated very simply by the signal output module 150, thereby enabling the corresponding negative feedback (or positive feedback) regulation to be achieved using the self-oscillating loop described above.

[0072] like Figure 1A and Figure 1B As shown, according to an embodiment of the present invention, the first capacitor 111 is used to perform a first-stage integration phase shift on the current load signal to generate a first-stage phase-shifted signal; wherein, the signal generation module 110 further includes an integration processor 112.

[0073] The input terminal of the integrator processor 112 is connected to the two ends of the first capacitor 111 in a differential input form, and is used to perform a second-stage integration phase shift on the first-stage phase shift signal to generate a second-stage phase shift signal, wherein the second-stage phase shift signal is the two-stage integrated signal.

[0074] The first capacitor 111 is connected in series between the target load P and the first output terminal of the signal update module 140. It can perform a first-stage integral phase shift on the current load signal of the target load P detected at the current moment, forming a first-stage phase-shifted signal. The first-stage phase-shifted signal has a 90° phase shift relative to the original current load signal.

[0075] For the first-stage phase-shift signal, a second-stage phase shift can be achieved through the integrator processor 112, resulting in another 90° phase shift and generating a second-stage phase-shift signal. At this point, the second-stage phase-shift signal has a 90° phase shift relative to the first-stage phase-shift signal and a 180° phase shift relative to the original current load signal. The integrator processor 112 can be connected to the first capacitor 111 via differential input to receive the input of the first-stage phase-shift signal.

[0076] Therefore, based on the first capacitor 111, the integrator 112 can further achieve a 90° phase shift of the first-stage phase-shift signal, ultimately achieving a 180° phase shift relative to the original input current load signal. Similar to the first capacitor 111, the integrator 112 can also be a circuit element or integrator circuit used to perform integrated phase shifting of electrical signals, such as a capacitor, an integrating amplifier, or a circuit structure composed of these elements. The integrated phase shifting process can also simultaneously perform high-frequency filtering on both the current load signal and the first-stage phase-shift signal. The first capacitor 111 can also effectively isolate the DC signal, effectively avoiding negative impacts on the second-stage integrated phase shifting process (such as increased error).

[0077] like Figure 1A and Figure 1B As shown, according to an embodiment of the present invention, the first capacitor 111 is specifically a capacitor element, which can be connected at one end to the target load P and at the other end to the first output terminal of the signal update module 140, so that the first-level integration processing of the current load signal on the target load P can be realized simultaneously while effectively isolating the DC signal.

[0078] Therefore, by connecting the first capacitor 111 in series with the target load P, the dual functions of first-stage integration processing and integration signal sampling can be achieved simultaneously. Moreover, it can effectively avoid the error amplification of the two-stage integration signals of the integrator processor 112. This eliminates the need for DC signal isolation and signal bias processing modules in the entire loop, thereby further simplifying the circuit structure, reducing circuit power consumption, and improving circuit stability and responsiveness while ensuring the accuracy of signal integration and phase shift processing.

[0079] like Figure 1A and Figure 1B As shown, according to an embodiment of the present invention, the integrator 112 includes an integrator amplifier 210 and a second capacitor 220.

[0080] The first input terminal of the integrating amplifier 210 is connected to one end of the first capacitor 111, and the other end of the amplifier is connected to the other end of the first capacitor 111.

[0081] One end of the second capacitor 220 is connected to the output of the integrating amplifier 111, and the other end is grounded to G.

[0082] By using a design where the first capacitor 111 is connected in series with the target load P, the two input terminals of the integrator amplifier 210, even when connected to the first capacitor 111 via differential inputs, can effectively eliminate interference from DC signals and high-frequency noise, and avoid error amplification during the first-stage integration phase shift process. This also effectively eliminates the need for signal isolation and bias processing circuitry required in existing frequency locking schemes, further simplifying the circuit design. While ensuring automatic frequency locking performance, this design achieves extreme simplification of the integration phase shift module.

[0083] In this process, the first-stage phase-shift signal from the first capacitor 111 is input to the integrator amplifier 210 via differential input. With the integration processing of the second capacitor 220, the integrator 112 performs a second phase-shift integration on the first-stage phase-shift signal, generating a second-stage phase-shift signal with a 90° phase shift relative to the first-stage phase-shift signal. That is, the second-stage phase-shift signal achieves a 180° phase shift relative to the current load signal, while also achieving high-frequency noise filtering. Specifically, the differential voltage corresponding to the first-stage phase-shift signal can be converted into a current signal by the integrator amplifier 210, and then integrated again by the second capacitor 220 to generate a voltage signal on the second capacitor 220 as the second-stage phase-shift signal, i.e., a two-stage integrated signal.

[0084] like Figure 1A and Figure 1B As shown, according to one embodiment of the present invention, the signal processing module 120 further includes a comparator 121.

[0085] The first input terminal of comparator 121 is connected to the output terminal of integrator processor 112, and its second input terminal is connected to a preset reference signal V. R Preset reference signal V R The comparison result of the second-stage phase-shift signal is used to convert the output waveform into a phase-shift signal.

[0086] Comparator 121 (i.e., Comparator) can convert the preset reference signal V input to the second input terminal. RAs a reference electrical signal (such as a reference voltage) for waveform conversion phase shift signal, the aforementioned second-stage phase shift signal is compared with the preset reference signal V. R The comparison is performed when the second-stage phase shift signal is higher than the preset reference signal V. R When the second-stage phase shift signal is lower than the preset reference signal V, comparator 121 can output a high level; conversely, when the second-stage phase shift signal is lower than the preset reference signal V, comparator 121 can output a high level. R When the time interval between the high and low levels is reached, comparator 121 can output a low level. Therefore, by utilizing the duty cycle of the high and low levels (i.e., the proportion of the total cycle), a waveform conversion phase shift signal can be output as the comparison result between the two. At this time, comparator 121 can convert the second-stage phase shift signal of the sine wave waveform into a waveform conversion phase shift signal of the square wave waveform. The preset reference signal V... R The actual comparator type and specifications, as well as the actual needs of waveform conversion phase shift signals, can be adaptively adjusted, which will not be elaborated here.

[0087] Therefore, the waveform-converted phase-shifted signal differs from the second-stage phase-shifted signal only in its waveform; its amplitude, period, and other signal characteristics remain unchanged. In this case, the comparator 121 can be used as a signal generator or a square wave generator. Thus, by using the comparator 121, waveform conversion can be achieved while preserving the signal characteristics as accurately as possible, effectively avoiding signal distortion.

[0088] like Figure 1A and Figure 1B As shown, according to one embodiment of the present invention, the signal processing module 120 further includes a first inverter 122.

[0089] The input of the first inverter 122 is connected to the output of the comparator 121, and is used to perform phase inversion processing on the waveform-converted phase-shift signal to generate the current phase-shift signal.

[0090] To further meet the 360° phase shift requirement and achieve the self-oscillating loop effect, the waveform-converted phase-shifted signal output from the comparator 121 can be inverted again by the first inverter 122. This results in the generated current phase-shifted signal having a 180° phase shift relative to the waveform-converted phase-shifted signal. Therefore, the current phase-shifted signal has a 360° phase shift relative to the original input current load signal, but still maintains its in-phase characteristic (i.e., returns to the original phase), thus completing one original-path oscillation process. The first inverter 122 can be implemented using an inverter (Phase Inverter) or similar inversion circuit elements or modules, which will not be elaborated further.

[0091] Therefore, based on the two integral phase shifts mentioned above, a current phase-shifted signal with waveform characteristics consistent with the current load signal but different waveform and a 360° phase shift is further output. It can be seen that during the integral phase shift, waveform conversion, and phase inversion processes, high-frequency noise over-filtering of the current load signal is achieved, effectively preventing signal interference. At the same time, it ensures a 360° phase shift difference between the current phase-shifted signal and the original current load signal, and its waveform also meets the drive input signal requirements of the control generation module 130, thus ensuring the frequency locking effect of the self-oscillation loop with a faster response.

[0092] like Figure 1A and Figure 1B As shown, according to an embodiment of the present invention, the control generation module 130 includes a second inverter 131, a first driver 132, and a second driver 133.

[0093] The input terminal of the second inverter 131 is connected to the output terminal of the first inverter 122, and is used to invert the current phase shift signal to generate an inverted control signal.

[0094] The input terminal of the first driver 132 is connected to the output terminal of the second inverter 131, and is used to generate a first drive signal and a second drive signal according to the inversion control signal;

[0095] The input terminal of the second driver 133 is connected to the output terminal of the first inverter 131, and is used to generate the third drive signal and the fourth drive signal according to the current phase shift signal.

[0096] The second inverter 131 can be implemented using an inverter or a circuit element that performs similar electrical signal inversion processing, so that the inverted signal has a 180° phase difference relative to the current phase-shifted signal. The first driver 132 and the second driver 133 can be used to increase the signal driving capability of the driving signals (first driving signal, second driving signal, third driving signal, and fourth driving signal) of the input signal update module 140. Specifically, this increase in signal driving capability can be understood as significantly shortening the charging time from 0V to the target voltage (such as the transistor threshold voltage) for a certain driving element (such as a transistor) of the signal update module 140. For example, a transistor that normally requires 1 second to charge from 0V to 1V can achieve the same charging effect from 0V to 1V in only 0.1 seconds under the drive of the first driver 132 and the second driver 133.

[0097] like Figure 1A and Figure 1B As shown, according to an embodiment of the present invention, the first driver 132 includes two inverters connected in parallel, and the second driver 133 includes two inverters connected in parallel.

[0098] The first driver 132 can be implemented using two inverters connected in parallel. This ensures that, with the same inverting control signal input, two drive signals, namely the first drive signal and the second drive signal, can be output in parallel through the two inverters. If the two inverters are circuit elements of the same specification, the first drive signal and the second drive signal can be the same signal.

[0099] Similarly, the second driver 133 can be implemented using two inverters connected in parallel. This ensures that, with the same current phase shift signal input, two drive signals, namely the third drive signal and the fourth drive signal, can be output in parallel through the two inverters. If the two inverters are circuit elements of the same specification, the third drive signal and the fourth drive signal can be the same signal.

[0100] The second inverter 131 ensures that the input signals of the first driver 132 and the second driver 133 are of different phases; that is, the inverting control signal input to the first driver 132 has a 180° phase difference with respect to the current phase shift signal input to the second driver 133. Therefore, when the inverters are of the same specification, the first and second drive signals can be electrical signals of the same phase. Similarly, the third and fourth drive signals can be electrical signals of the same phase, and the phases of the first and second drive signals can be opposite to those of the third and fourth drive signals.

[0101] Therefore, by means of the above-described design of the first driver 132 and the second driver 133, efficient and precise drive control of the signal update module 140 can be effectively achieved based on the first drive signal, the second drive signal, the third drive signal and the fourth drive signal.

[0102] like Figure 1A and Figure 1B As shown, according to one embodiment of the present invention, the signal update module 140 includes a full-bridge converter.

[0103] The input terminals of the full-bridge converter are correspondingly connected to the output terminals of the first driver 132 and the second driver 133, and are used to control the preset input power supply V external to the full-bridge converter according to the first drive signal, the second drive signal, the third drive signal, and the fourth drive signal. HV Update the current load signal applied to the target load P.

[0104] In this embodiment of the invention, the full-bridge converter may have at least four input terminals, respectively used to receive the first and second driving signals output by the first driver 132, and the third and fourth driving signals output by the second driver 133. Thus, the full-bridge converter can, by driving the first, second, third, and fourth driving signals respectively, achieve output modulation of the driving electrical signals at both ends toward the target load P, i.e., update the current load signal, for example, one end is OUT+ and the other end is OUT-, specifically OUT+=10V and OUT-=-10V square wave signal. Therefore, by using this full-bridge converter, a relatively lower preset input power supply V can be used. HV A higher drive voltage matching the target load P is achieved through a dual-ended power supply. Specifically, for example, a preset input power supply V... IN If the voltage is 10V, then the drive voltage matched to the target load P can reach 20V.

[0105] The full-bridge converter can achieve drive control of the target load P by means of at least a number of transistors corresponding to the first drive signal, the second drive signal, the third drive signal, and the fourth drive signal, which can be used to update the current load signal on the target load P.

[0106] like Figure 1A and Figure 1B As shown, according to an embodiment of the present invention, the full-bridge converter includes a first P-type transistor M1, a first N-type transistor M2, a second P-type transistor M3, and a second N-type transistor M4.

[0107] The gate of the first P-type transistor M1 is connected to the first output terminal of the first driver 132, and its source is connected to the preset input power supply V. HV Its drain is connected to the first capacitor 111, which is used to control the conduction and disconnection of the first P-type transistor M1 according to the first drive signal;

[0108] The gate of the first N-type transistor M2 is connected to the second output terminal of the first driver 132, its source is grounded, and its drain is connected to the drain of the first P-type transistor M1, which is used to control the conduction and disconnection of the first N-type transistor M2 according to the second drive signal.

[0109] The gate of the second P-type transistor M3 is connected to the first output terminal of the second driver 133, and its source is connected to the preset input power supply V. HV Its drain is connected to the target load P, and it is used to control the conduction and disconnection of the second P-type transistor M3 according to the third drive signal;

[0110] The gate of the second N-type transistor M4 is connected to the second output terminal of the second driver 133, its source is grounded, and its drain is connected to the drain of the second P-type transistor M3, which is used to control the conduction and disconnection of the second N-type transistor M4 according to the fourth drive signal.

[0111] In one embodiment of the present invention, the first P-type transistor M1 and the second P-type transistor M3 of the full-bridge converter can be PMOS transistors, and the first N-type transistor M2 and the second N-type transistor M4 can be NMOS transistors. Specifically, the MOS transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET), the PMOS transistor can be a P-type doped MOS transistor, and the NMOS transistor can be an N-type doped MOS transistor.

[0112] Specifically, for the first P-type transistor M1 and the second P-type transistor M3 of the PMOS transistors, when their gate voltage is high, they are in the off state and no current is conducted (i.e., open state); when their gate voltage is low, they are in the on state and current is conducted (i.e., on state). Conversely, for the first N-type transistor M2 and the second N-type transistor M4 of the NMOS transistors, when their gate voltage is high, they are in the on state and current is conducted (i.e., on state); when their gate voltage is low, they are in the off state and no current is conducted (i.e., open state).

[0113] Therefore, as Figure 1A and Figure 1B As shown, the frequency locking implementation process of the resonant frequency locking circuit device 100 of an embodiment of the present invention can be specifically described in the following detailed description.

[0114] (1) The negative feedback process that can be reflected in the startup process of the above target load P.

[0115] First, connect the preset input power supply V. HV The full-bridge converter applies a drive signal to both ends of the target load P. At this time, the signal output module 150 can indicate the direction of application of the drive signal to both ends of the target load P.

[0116] For example, when the signal output module 150 feeds back a high level at one end of the target load P closest to the first capacitor 111 (i.e., the first capacitor), and a low level at the other end of the target load P furthest from the first capacitor 111, then it is determined that the end of the first capacitor 111 closest to the target load P is at a low level, and the other end of the first capacitor 111 furthest from the target load P is at a high level. It should be understood by those skilled in the art that "closer" or "farthest" does not refer to spatial structure, but rather to the connection relationship of the circuit.

[0117] At this time, the first input terminal of the integrating amplifier 210 of the integrating processor 112 corresponds to the low-level input of the first-stage phase-shift signal, and the second input terminal of the integrating amplifier 210 corresponds to the high-level input of the first-stage phase-shift signal, so as to generate the second-stage phase-shift signal and input it to the signal processing module 120. The signal processing module 120 performs waveform conversion on the second-stage phase-shift signal through the comparator 121, and outputs a low-level waveform-converted phase-shift signal of a square wave. After the waveform-converted phase-shift signal is inverted by the first inverter 122 of the signal processing module 120, a high-level current phase-shift signal is obtained.

[0118] At this time, the current phase shift signal input to the control generation module 130 is inverted again by the second inverter 131, resulting in a low-level inverted control signal input to the first driver 132. The first driver 132 then outputs two high-level first drive signals and a second drive signal. At this time, the first P-type transistor M1 of the full-bridge converter enters or remains in an off state upon receiving the high-level first drive signal (preset input power supply V). HV The input from the first P-type transistor M1 is disconnected, and the first N-type transistor M2 enters or remains in the conducting state when it receives the second high-level drive signal (one end of the first capacitor 111, which is far from the target load P, is grounded by means of the first N-type transistor M2), so that the end of the target load P that is close to the first capacitor 111 can be pulled down.

[0119] Simultaneously, a high-level current phase shift signal is input to the second driver 133, which then outputs two low-level third and fourth drive signals. At this time, the second P-type transistor M3 of the full-bridge converter enters or remains in the on state upon receiving the low-level third drive signal (preset input power supply). HV The second P-type transistor M3 is connected to the target load P, and when the second N-type transistor M4 receives the low-level fourth drive signal, it enters or remains in the off state (so that the other end of the target load P, which is far from the first capacitor 111, cannot be grounded, and is only connected to the preset input power supply V through the second P-type transistor M3). HV Therefore, it is possible to pull up the target load P that is far away from the first capacitor 111.

[0120] The above describes the negative feedback modulation process generated during the startup of the target load P.

[0121] (2) The positive feedback process that can be manifested in the working process of the above target load P.

[0122] When the signal output module 150 can report that the end of the target load P near the first capacitor 111 is at a low level and the other end of the target load P far away from the first capacitor 111 is at a high level, it determines that the end of the first capacitor 111 near the target load P is at a high level and the other end of the first capacitor 111 far away from the target load P is at a low level.

[0123] At this time, the first input terminal of the integrating amplifier 210 corresponds to the high-level input of the first-stage phase-shift signal, and the second input terminal of the integrating amplifier 210 corresponds to the low-level input of the first-stage phase-shift signal, which is used to generate the second-stage phase-shift signal and input it to the signal processing module 120. The signal processing module 120 performs waveform conversion on the second-stage phase-shift signal through the comparator 121, and outputs a high-level waveform-converted phase-shift signal of a square wave. After the waveform-converted phase-shift signal is inverted by the first inverter 122 of the signal processing module 120, a low-level current phase-shift signal is obtained.

[0124] At this time, the current phase shift signal input to the control generation module 130 is inverted again by the second inverter 131, resulting in a high-level inverted control signal input to the first driver 132. The first driver 132 then outputs two low-level first drive signals and a second drive signal. At this time, the first P-type transistor M1 of the full-bridge converter enters or remains in the on state upon receiving the low-level first drive signal (preset input power supply V). HV (The first P-type transistor M1 is connected to the first capacitor 111), and the first N-type transistor M2 enters or remains in the off state when it receives the low-level second drive signal (the end of the first capacitor 111 that is far away from the target load P cannot be grounded through the first N-type transistor M2), so it is possible to pull up the end of the target load P that is close to the first capacitor 111.

[0125] Simultaneously, a low-level current phase shift signal is input to the second driver 133, which then outputs two high-level third and fourth drive signals. At this time, the second P-type transistor M3 of the full-bridge converter enters or remains in an off state upon receiving the high-level third drive signal (preset input power supply V). HV Disconnect the second P-type transistor M3 from the target load P), and when the second N-type transistor M4 receives the high-level fourth drive signal, it enters or remains in the conducting state (so that the other end of the target load P far away from the first capacitor 111 can be grounded), thus enabling the pull-down of the other end of the target load P far away from the first capacitor 111.

[0126] The above describes the positive feedback modulation process generated by the target load P during its operation.

[0127] In this way, based on the 360° integral phase shift of the signal generation module 110 and the signal processing module 120, a self-oscillating loop with a gain greater than 1 can be realized by combining the control generation module 130 and the signal update module 140. This allows the actual operation of the target load P to be always stable and dynamically maintained at the current intrinsic resonant frequency of the target load P. The design of the entire circuit has a higher response speed and maintains the best working efficiency of the target load P. The circuit structure is simple and does not need to consider the individual characteristic differences or aging of the target load P due to various reasons.

[0128] It should be noted that, as an improvement to an embodiment of the present invention, Figure 1A The control generation module 130 shown can further incorporate one or more inverters (such as inverter 134) to achieve inversion processing of the current phase shift signal or inverted control signal, as described above. Figure 1B The resonant frequency locking circuit device 100' shown can adaptively adjust the connection position of the second driver 133 according to the connection relationship of the inverter 134, the second inverter 131, and the first inverter 122. Specifically, it only needs to meet the above-mentioned positive feedback and negative feedback adjustment process, and no specific restrictions are made here.

[0129] The resonant frequency locking circuit device and its control method provided in this invention can at least partially solve the technical problems of high energy loss, low overall efficiency, poor frequency locking stability, high cost and large size caused by circuit complexity in related technologies, and thus can achieve at least one of the following technical effects:

[0130] (1) First, by constructing a 360° phase-shifted frequency-locking feedback loop, the resonant frequency of the target load can be accurately locked, which can realize an adaptive frequency-locking mechanism with higher response speed, effectively ensure the maximum working efficiency of the target load, significantly improve the working efficiency and working stability of the target load, and at the same time, it can dynamically adjust the frequency-locking of the target LC resonant frequency according to the individual characteristics and life changes of the target load, realize automatic tracking and stable driving of the resonant frequency, further ensure its frequency-locking stability, and achieve the effect of dynamic frequency-locking.

[0131] (2) In addition, in the resonant frequency locking circuit device in the embodiments of the present invention, the more complex circuit design usually used in the existing digital sampling and phase-locked loop frequency locking scheme can be directly eliminated, thereby effectively avoiding additional power loss and efficiency loss caused by the presence of complex circuit components, greatly saving costs, further improving the operating power of the target load (such as a piezoelectric ceramic air pump), and greatly improving working efficiency.

[0132] (3) Furthermore, the application of ADC converter and MCU microcontroller can be eliminated. On this basis, there is no need for other circuit components to cooperate with them. This greatly simplifies the composition of the frequency locking circuit structure. Efficient and accurate frequency locking dynamic control can be achieved based only on basic circuit components such as integral phase shift and drive bridge. This further reduces the power consumption caused by complex circuit components in the system, and also significantly reduces the circuit cost and overall circuit size (such as the area occupied).

[0133] (4) It can avoid the signal acquisition components or circuit design such as inductive resistors used in existing frequency locking technology. Moreover, through the series design of the first capacitor and the target load, it can simultaneously realize the dual functions of the first-stage integration processing and integration signal sampling, thereby greatly reducing the circuit complexity, further reducing the circuit cost and area occupied. At the same time, it can also improve the frequency locking control response speed and stability of the system frequency locking control loop, and further reduce the circuit power consumption, making the circuit simpler and more efficient. It can also ensure the dynamic automatic tracking frequency locking effect and realize the stable driving of the target load.

[0134] (5) Because the first capacitor can be designed in series with the target load, even if the two input terminals of the integrating amplifier are connected to the first capacitor in the form of differential input, the interference of DC signal and high-frequency noise can be effectively eliminated, and the error amplification caused by the first-stage integration phase shift process can also be avoided. In this way, the circuit design of signal isolation and bias processing that must be added in the existing frequency locking scheme can also be effectively eliminated, further simplifying the circuit design. While ensuring the automatic frequency locking effect, the integration phase shift module is simplified to the extreme.

[0135] Therefore, the resonant frequency locking circuit device and its control method described in the embodiments of the present invention can be more widely adapted to the needs of small and high-efficiency scenarios. Even under the current chip manufacturing process level, it can be better applied to high-precision electronic products (such as micro heat sinks for automotive chips or mobile phone chips) or equipment (such as micro heat sinks for extreme ultraviolet light source chips in lithography machines), so that its chips can achieve the same or even better operating capabilities as chips with higher chip manufacturing processes, and have a very wide range of product applications.

[0136] Therefore, the resonant frequency locking circuit device and its control method based on the embodiments of the present invention can provide a dynamic frequency locking technology that is more efficient, more stable, lower power consumption, lower cost, more practical, and easier to implement and promote compared with existing frequency locking schemes. It can accurately lock the optimal resonant frequency of existing micro heat dissipation devices such as piezoelectric ceramic air pumps, and has extremely important practical value and economic benefits.

[0137] Based on the above-described resonant frequency locking circuit device, the present invention also provides a control method for the resonant frequency locking circuit device. The following will be combined with... Figure 2-3 The control method is described in detail.

[0138] Figure 2 The diagram illustrates an application scenario of the control method, apparatus, device, medium, and program product of the resonant frequency locking circuit device according to an embodiment of the present invention.

[0139] like Figure 2 As shown, application scenario 200 according to this embodiment may include terminal devices 201, 202, and 203, a network 204, and a server 205. Network 204 serves as a medium for providing a communication link between terminal devices 201, 202, and 203 and server 205. Network 204 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0140] Users can use terminal devices 201, 202, and 203 to interact with server 205 via network 204 to receive or send messages, etc. Various communication client applications can be installed on terminal devices 201, 202, and 203, such as shopping applications, web browser applications, search applications, instant messaging tools, email clients, social media platform software, etc. (for example only).

[0141] Terminal devices 201, 202, and 203 can be various electronic devices with displays that support web browsing, including but not limited to smartphones, tablets, laptops, and desktop computers.

[0142] Server 205 can be a server that provides various services, such as a backend management server that supports websites browsed by users using terminal devices 201, 202, and 203 (for example only). The backend management server can analyze and process data such as received user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal devices.

[0143] It should be noted that the control method of the resonant frequency locking circuit device provided in the embodiments of the present invention can generally be executed by server 205. Correspondingly, the control device of the resonant frequency locking circuit device provided in the embodiments of the present invention can generally be located in server 205. The control method of the resonant frequency locking circuit device provided in the embodiments of the present invention can also be executed by a server or server cluster that is different from server 205 and capable of communicating with terminal devices 201, 202, 203 and / or server 205. Correspondingly, the control device of the resonant frequency locking circuit device provided in the embodiments of the present invention can also be located in a server or server cluster that is different from server 205 and capable of communicating with terminal devices 201, 202, 203 and / or server 205.

[0144] It should be understood that Figure 2 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0145] The following will be based on Figure 2 The described scene, through Figure 3 The control method of the resonant frequency locking circuit device according to the disclosed embodiments will be described in detail.

[0146] like Figure 3 As shown, one aspect of an embodiment of the present invention provides the above-described... Figure 1A The control method of the resonant frequency locking circuit device 100 shown is applied to the resonant frequency locking of the target load. The resonant frequency locking circuit device includes a signal generation module, a signal processing module, a control generation module, and a signal update module, which are used to form a self-oscillating loop with a gain greater than or equal to 1. The control method includes operations S301 to S303.

[0147] In operation S301, the current load signal at one end of the target load is subjected to two-stage integration processing to generate a two-stage integrated signal.

[0148] In operation S302, waveform conversion and phase conversion are performed on the two-stage integral signal to generate the current phase-shifted signal; wherein, the current phase-shifted signal achieves a 360° phase shift relative to the current load signal;

[0149] In operation S303, at least one control signal is generated based on the current phase shift signal; and

[0150] In operation S304, the current load signal is updated according to at least one control signal to achieve resonant frequency locking.

[0151] To enable those skilled in the art to understand the above-mentioned Figure 1AThe control method of the resonant frequency locking circuit device 100 in the embodiment of the present invention can be more clearly understood. In conjunction with a specific implementation case where the target load is a piezoelectric ceramic air pump, the operation process S311-S315 of this control method is explained in detail as follows:

[0152] The resonant frequency locking circuit device 100 of this embodiment proposes an automatic frequency locking drive circuit architecture suitable for piezoelectric ceramic air pumps. It includes a signal update module 140 composed of a first capacitor 111, an integrating amplifier 210, a second capacitor 220, a comparator 121, a first inverter 122, a second inverter 131, a first driver 132, a second driver 133, and a full-bridge converter. Specific connection methods can be found in conjunction with the foregoing description and references. Figure 1A As shown, details will not be elaborated here. Simultaneously, a resistor can be connected in parallel with the piezoelectric ceramic pump P as a signal feedback element. This architecture can detect the phase shift generated by the drive signal passing through the piezoelectric ceramic pump, locking the drive circuit clock at the intrinsic resonant frequency of the piezoelectric ceramic pump, thereby ensuring that the piezoelectric ceramic pump P always maintains maximum power output and maximum efficiency output.

[0153] In operation 311, the full-bridge converter is connected to the piezoelectric ceramic air pump P at both ends, and the preset input power supply V can be used. HV The piezoelectric ceramic air pump P (which can be specifically represented as an LC series circuit model) is powered from both ends.

[0154] Subsequently, in operation S312, the current passing through the piezoelectric ceramic air pump P is integrated on the first capacitor 111 and a phase shift of nearly 90 degrees is achieved, generating a first-stage phase-shift signal.

[0155] Then, in operation S313, the voltage signal of the first-stage phase-shift signal after the first-stage integration can be differentially input to the positive and negative input terminals of the integrating amplifier 210, and the negative input terminal of the integrating amplifier 210 can be connected to the power input OUT+ port of the piezoelectric ceramic air pump. Through the differential input structure, the differential voltage corresponding to the first-stage phase-shift signal on the first capacitor 111 can be converted into current and then integrated in the second stage on the second capacitor 220 to obtain a voltage signal with a 180-degree phase shift compared to the piezoelectric ceramic air pump P as the second-stage phase-shift signal, i.e., a two-stage integrated signal.

[0156] Furthermore, in operation S314, the voltage signal on the second capacitor 220 serves as the second-stage phase shift signal, which enters comparator 121 and is compared with the preset reference signal V. R The comparison is performed to generate a square wave control signal as a waveform conversion phase shift signal.

[0157] Finally, in operation S315, the aforementioned waveform-converted phase-shift signal is again inverted by the first inverter 122 to generate the current phase-shift signal. This current phase-shift signal is input to the second inverter 131 (which outputs to the first driver 132 after inversion) and the second driver 133. The first driver 132 controls the on / off switching of the first P-type transistor M1 and the first N-type transistor M2 of the full-bridge converter, and the second driver 133 controls the on / off switching of the second P-type transistor M3 and the second N-type transistor M4 of the full-bridge converter.

[0158] In this process, the current of the piezoelectric ceramic pump P is converted into voltage through the first capacitor 111, resulting in a 90° phase shift. The output current of the integrator amplifier 210 of the integrator processor 112 is integrated across the second capacitor 220 to form a capacitor voltage, which then acts as the second-stage phase shift signal, generating another 90° phase shift. At this point, the current signal from the piezoelectric ceramic pump P has a 180° phase shift. The second-stage phase shift signal from the second capacitor 220 enters the comparator 121 to generate a square wave signal, which is then inverted by the first inverter 122 to generate the current phase shift signal. This current phase shift signal has a 360° phase shift relative to the current signal of the piezoelectric ceramic pump P. Finally, the first driver 132 and the second driver 133 of the control generation module 130 are used as single-channel drive circuits to drive the four transistors of the full-bridge converter to turn off or on. Therefore, the differential voltage between OUT- and OUT+ in the signal update module 140 achieves a 360° phase shift through the loop, forming positive feedback. Simultaneously, the loop has a gain greater than 1, enabling self-oscillation.

[0159] At this point, when the aforementioned frequency-locked self-oscillating circuit controls the piezoelectric ceramic pump P to operate at its actual intrinsic resonant frequency, the phase shift between the voltage and current of the piezoelectric ceramic pump P is minimized, the impedance is minimized, and the output power is maximized. Therefore, the piezoelectric ceramic pump P itself possesses a resonant frequency selection function similar to that of an RLC circuit. Since the two-stage integration of the first capacitor 111 and the second capacitor 220 generates a 180-degree phase shift, coupled with the 180-degree inverting logic of the inverting drive section, the entire system can maintain a 360-degree phase shift between the driving voltage and current of the piezoelectric ceramic pump only when operating at the actual intrinsic resonant frequency.

[0160] Therefore, the energy at non-resonant frequencies continuously attenuates due to the loop phase shift deviating from 360 degrees, while the energy at resonant frequencies, due to the 360-degree phase shift of the entire loop, is continuously amplified through frequency selection, maintaining frequency lock. Thus, this system can lock the system's operating frequency to the actual intrinsic resonant frequency of the piezoelectric ceramic pump, ensuring that the piezoelectric ceramic pump always maintains maximum power and efficiency output. When operating at the resonant frequency, the piezoelectric ceramic pump exhibits purely resistive characteristics.

[0161] In summary, the resonant frequency locking circuit device of this invention can automatically detect and lock the optimal operating frequency of the target load resonant circuit by constructing a 360° phase-shifted frequency-locked feedback self-oscillating loop, avoiding frequency drift away from the resonant point, greatly improving load efficiency, and enhancing the steady-state performance of the system under actual operating conditions. Furthermore, this resonant frequency locking circuit device mainly consists of an integrator, a comparator, and an inverter, resulting in a simple overall circuit structure and clearer control links. Compared to traditional phase-locked loop (PLL) solutions, it has lower circuit complexity and lower implementation costs, making it particularly suitable for miniaturized, low-cost applications. It also meets the requirement of locking the target load resonant frequency, locking the system operating point at the optimal operating point, reducing losses, ensuring system circuit stability, and maintaining a low overall cost.

[0162] Therefore, the resonant frequency locking circuit device of the present invention can provide a frequency-locked drive circuit architecture. By introducing a frequency-locked loop and an adaptive control method, it can automatically track the actual resonant point of the target load, lock the drive circuit at the resonant frequency, and always maintain the system's highest power and highest efficiency output, thereby achieving automatic tracking and stable drive of the resonant frequency and improving system efficiency and reliability.

[0163] The beneficial effects of the control method of the resonant frequency locking circuit device 100 in the above embodiments of the present invention can be referred to the relevant description of the resonant frequency locking circuit device 100, which will not be repeated here.

[0164] Figure 4 A block diagram of an electronic device suitable for implementing a control method for a resonant frequency locking circuit device according to an embodiment of the present invention is shown schematically.

[0165] The electronic device provided in the embodiments of the present invention includes one or more processors and a memory, wherein the memory is used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute the control method of the resonant frequency locking circuit device.

[0166] like Figure 4As shown, an electronic device 400 according to an embodiment of the present invention includes a processor 401, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 402 or a program loaded from a storage portion 408 into a random access memory (RAM) 403. The processor 401 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 401 may also include onboard memory for caching purposes. The processor 401 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0167] RAM 403 stores various programs and data required for the operation of electronic device 400. Processor 401, ROM 402, and RAM 403 are interconnected via bus 404. Processor 401 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 402 and / or RAM 403. It should be noted that the programs may also be stored in one or more memories other than ROM 402 and RAM 403. Processor 401 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0168] According to an embodiment of the present invention, the electronic device 400 may further include an input / output (I / O) interface 405, which is also connected to a bus 404. The electronic device 400 may also include one or more of the following components connected to the I / O interface 405: an input section 406 including a keyboard, mouse, etc.; an output section 407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to the I / O interface 405 as needed. A removable medium 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 410 as needed so that computer programs read from it can be installed into the storage section 408 as needed.

[0169] The present invention also provides a computer-readable storage medium storing executable instructions thereon, which, when executed by a processor, cause the processor to perform the control method of the resonant frequency locking circuit device described above.

[0170] The computer-readable storage medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0171] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 402 and / or RAM 403 and / or one or more memories other than ROM 402 and RAM 403 described above.

[0172] Embodiments of the present invention also include a computer program product comprising a computer program that, when executed by a processor, implements the control method of the resonant frequency locking circuit device described above.

[0173] The computer program includes program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the methods provided in the embodiments of the present invention.

[0174] When the computer program is executed by the processor 401, it performs the functions defined in the system / apparatus of this embodiment of the invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0175] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via communication section 409, and / or installed from removable medium 411. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0176] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 409, and / or installed from removable medium 411. When the computer program is executed by processor 401, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0177] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0178] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0179] Furthermore, all actions involving the acquisition of information, signals, or data in this invention are carried out in compliance with the relevant data protection laws, regulations, and policies of the country where the invention is located, and with the authorization granted by the owner of the corresponding device.

[0180] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0181] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A resonant frequency locking circuit device, used for locking the resonant frequency of a target load, characterized in that, include: The signal generation module is used to perform two-stage integration processing on the current load signal at one end of the target load to generate a two-stage integrated signal. The signal processing module, whose input is connected to the output of the signal generation module, is used to perform waveform conversion and phase conversion processing on the two-stage integrated signal to generate a current phase-shifted signal; wherein, the current phase-shifted signal achieves a 360° phase shift relative to the current load signal; A control generation module, whose input is connected to the output of the signal processing module, is used to generate at least one control signal based on the current phase shift signal. A signal update module, whose input is connected to the output of the control generation module, is used to update the current load signal according to the at least one control signal; The signal generation module, signal processing module, control generation module, and signal update module constitute a self-oscillating loop with a gain greater than or equal to 1 to achieve the resonant frequency locking; wherein, the signal generation module includes: A first capacitor, one end of which is connected to one end of the target load and in series with the target load, and the other end of which is connected to the output of the signal update module, is used to perform a first-stage integral phase shift on the current load signal to generate a first-stage phase shift signal. An integrator processor is configured to perform a second-stage integration phase shift on the first-stage phase-shift signal to generate a second-stage phase-shift signal, wherein the second-stage phase-shift signal is the two-stage integrated signal, and the integrator processor includes: An integrating amplifier, wherein its first input terminal is connected to one end of the first capacitor, and its other end is connected to the other end of the first capacitor; The second capacitor has one end connected to the output of the integrating amplifier and the other end grounded.

2. The resonant frequency locking circuit device according to claim 1, characterized in that, Also includes: A signal output module is connected in parallel with the target load to provide feedback on the direction of the current load signal.

3. The resonant frequency locking circuit device according to claim 2, characterized in that, The signal processing module includes: The comparator has its first input terminal connected to the output terminal of the integrator processor, and its second input terminal connected to a preset reference signal. The comparison result between the preset reference signal and the second-stage phase shift signal is used to output a waveform-converted phase shift signal.

4. The resonant frequency locking circuit device according to claim 3, characterized in that, The signal processing module further includes: The first inverter, whose input is connected to the output of the comparator, is used to perform phase inversion processing on the waveform-converted phase-shift signal to generate the current phase-shift signal.

5. The resonant frequency locking circuit device according to claim 4, characterized in that, The control generation module includes: The second inverter, whose input is connected to the output of the first inverter, is used to invert the current phase shift signal and generate an inverting control signal. A first driver, whose input is connected to the output of the second inverter, is used to generate a first driving signal and a second driving signal according to the inverting control signal. The second driver, whose input is connected to the output of the first inverter, is used to generate a third driving signal and a fourth driving signal based on the current phase shift signal.

6. The resonant frequency locking circuit device according to claim 5, characterized in that, The first driver includes two inverters connected in parallel, and the second driver includes two inverters connected in parallel.

7. The resonant frequency locking circuit device according to claim 5 or 6, characterized in that, The signal update module includes: A full-bridge converter, whose input terminals are connected to the output terminals of the first driver and the second driver respectively, is used to control the preset input power supply connected to the full-bridge converter to update the current load signal applied to the target load according to the first drive signal, the second drive signal, the third drive signal and the fourth drive signal.

8. The resonant frequency locking circuit device according to claim 7, characterized in that, The full-bridge converter includes: The first P-type transistor has its gate connected to the first output terminal of the first driver, its source connected to the preset input power supply, and its drain connected to the first capacitor, and is used to control the conduction and disconnection of the first P-type transistor according to the first drive signal. The first N-type transistor has its gate connected to the second output terminal of the first driver, its source grounded, and its drain connected to the drain of the first P-type transistor. It is used to control the conduction and disconnection of the first N-type transistor according to the second drive signal. The second P-type transistor has its gate connected to the first output terminal of the second driver, its source connected to the preset input power supply, and its drain connected to the target load. It is used to control the conduction and disconnection of the second P-type transistor according to the third drive signal. The second N-type transistor has its gate connected to the second output terminal of the second driver, its source grounded, and its drain connected to the drain of the second P-type transistor. It is used to control the conduction and disconnection of the second N-type transistor according to the fourth drive signal.

9. A control method for a resonant frequency locking circuit device according to any one of claims 1-8, applied to resonant frequency locking of a target load, characterized in that, The resonant frequency locking circuit device includes a signal generation module, a signal processing module, a control generation module, and a signal update module, used to form a self-oscillating loop with a gain greater than or equal to 1. The control method includes: The current load signal at one end of the target load is subjected to two-stage integration processing to generate a two-stage integrated signal; The two-stage integral signals are subjected to waveform conversion and phase conversion processing to generate a current phase-shifted signal; wherein, the current phase-shifted signal is phase-shifted by 360° relative to the current load signal; Generate at least one control signal based on the current phase shift signal; and The current load signal is updated according to the at least one control signal to achieve the resonant frequency locking.

10. An electronic device, comprising: One or more processors; Memory, used to store one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method of claim 9.

11. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method of claim 9.

12. A computer program product comprising a computer program that, when executed by a processor, implements the method of claim 9.

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