Instruction set design method for matrix on-line parallel general-purpose computing
Patent Information
- Application Number
- CN202512043924.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-05-01
AI Technical Summary
Existing technologies struggle to achieve both versatility and performance in matrix computation within deep learning processors, especially given the low computational efficiency across different tasks.
Design a variable-length instruction set that controls the cyclic reuse of short instructions through long instructions, configures instruction length, type, and behavior model, and optimizes instruction encoding format to meet the needs of online parallel computing.
It realizes online parallel matrix computation in deep learning processors that balances versatility and performance, reduces instruction fetch overhead, optimizes instruction length, and improves computational efficiency.
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Figure CN121957685A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of instruction set coding technology, specifically relating to an instruction set design method for matrix online parallel general-purpose computing. Background Technology
[0002] Most computations in popular deep learning algorithms can be transformed into general matrix multiplication, which makes the design of general-purpose deep learning processors possible. When faced with different computational tasks, processor resources can be reused, requiring only additional compilation optimization of computation instructions according to the computation order to improve computational efficiency and support different types of matrix computations. Typical operators in deep learning algorithms are as follows.
[0003] Standard convolutional layer. In neural network inference, convolutional layers are used for feature extraction. The calculation process of a standard convolutional layer can be formulaically represented as follows:
[0004]
[0005] Among them, F out (j) represents the feature data of the j-th output channel of the convolutional layer, bias(j) represents the bias data of the j-th output channel, and C in Let W(j,k) be the number of input channels, and W(j,k) be the weight data of the j-th output channel and the k-th input channel. Let F be the weight data of the j-th output channel and the k-th input channel. in (k) represents the feature data of the kth input channel, and * represents two-dimensional correlation calculation.
[0006] Fully connected layers. In neural network inference, fully connected layers are used for classification. The computation process of a fully connected layer can be formulaically represented as follows:
[0007]
[0008] Among them, F out (j) represents the feature data of the j-th output channel of the fully connected layer, bias(j) represents the bias data of the j-th output channel, and C in Let W(j,k) be the number of input channels, and W(j,k) be the weight data of the j-th output channel and the k-th input channel. Let F be the weight data of the j-th output channel and the k-th input channel. in (k) represents the feature data of the kth input channel, and x represents multiplication.
[0009] General matrix multiplication. General matrix multiplication is a commonly used matrix operator in attention mechanisms. The calculation process of general matrix multiplication can be formalized as follows:
[0010]
[0011] Where C is an m×p matrix, A is an m×n matrix, and B is an n×p matrix. Summary of the Invention
[0012] The purpose of this invention is to provide an instruction set design method for online parallel general-purpose matrix computation. Addressing the large-scale matrix computation requirements in deep learning algorithms, and fully considering the characteristic that most deep learning matrix computation operators can be transformed into general-purpose matrix multiplications of different scales, a variable-length instruction set design method is proposed. By changing the loop parameters in the instructions according to the computational scale, the effect of using a single long instruction to control multiple short instructions in a loop can be achieved, thus achieving the goal of balancing versatility and performance requirements in the design of deep learning processors using this instruction set architecture.
[0013] This method first configures an instruction length requirement model based on the common computational characteristics of matrix operators in deep learning algorithms. Specifically, it designs a variable-length instruction set, where long instructions handle control, and short instructions handle reusable loops. Short instructions can control parallel computation of small batches of data. Next, it configures an instruction type requirement model, designing the function of each instruction in the instruction set to meet general requirements. Then, it configures a behavior model for each instruction, clarifying the behavior controlled by each field in the instruction. Finally, it designs the encoding format for each instruction, clarifying the arrangement of each field. Based on the instruction encoding format requirements, iteratively designs the instruction length and the length of each field to ensure that the instructions meet the performance requirements of online parallel computing within the constraints of hardware resources and computational scale.
[0014] The specific implementation steps are as follows:
[0015] 1) Configuration instruction length requirement model
[0016] The design incorporates a variable-length instruction set (VLS), where long instructions handle control, and short instructions are reused cyclically under the control of the long instructions, thus reducing instruction fetch overhead. Short instructions are the smallest unit of on-chip computation and can control the parallel computation of small batches of data.
[0017] 2) Configuration instruction type requirement model
[0018] Long instructions include LOAD, STORE, GEMM, ALU, and FINISH. The LOAD instruction is used to load short instructions or computational data from off-chip cache to on-chip. The STORE instruction is used to transfer on-chip computation results to off-chip cache. The GEMM instruction is used for matrix multiplication calculations. The ALU is used for matrix arithmetic logic calculations.
[0019] Short instructions include the GEMM UOP instruction and the ALU UOP instruction. GEMM UOP is a short instruction used by deep learning processors for online parallel computations of matrix multiplication types, while ALU UOP is a short instruction used by deep learning processors for online parallel computations of matrix arithmetic logic types.
[0020] 3) Configure the behavior model for each long instruction.
[0021] Clearly define the behavior controlled by each field in a long command.
[0022] Both the LOAD and STORE instructions are data transfer instructions, differing only in the direction of data transfer. The fields for both instructions have the same function. These include: the op field (to distinguish long instructions); the dependency field (to explicitly define the dependencies between long instructions); the memid field (to specify the data transfer source or destination); the bankid field (to specify the storage block where the transferred data resides in the data transfer source or destination); the sramOffset field (to specify the base address of the transferred data in the storage block); and the dramOffset field (to specify the base address of the transferred data in the off-chip cache). Data is transferred in units of tensors, grouped into sets of xsize tensors. The ysize field specifies the number of tensor groups to be transferred in the y-direction, and the xsize field specifies... The x-axis specifies the number of tensors to be transmitted, and xstride specifies the number of tensors in the interval between each group of tensors. Zero padding is a common operation in deep learning algorithms. ypad0 is the number of zero-padding tensors to be added before each ysize group of tensors is read in the y-axis, ypad1 is the number of zero-padding tensors to be added after each ysize group of tensors is read in the y-axis, xpad0 is the number of zero-padding tensors to be added before each xsize group of tensors is read in consecutively, and xpad1 is the number of zero-padding tensors to be added after each xsize group of tensors is read in consecutively. Reserved fields are allowed.
[0023] For GEMM instructions, the `op` field distinguishes long instruction types; the `dependency` field explicitly defines the dependencies between each long instruction; the `uop_begin` field defines the starting address of the short instruction to be executed in the short instruction cache; the `uop_end` field defines the ending address of the short instruction to be executed in the short instruction cache; the `lp_0` field specifies the number of times the outer loop needs to iterate through the short instructions; the `lp_1` field specifies the number of times the inner loop needs to iterate through the short instructions; the `acc_0` field specifies the increment of the intermediate result base address after each outer loop iteration; and the `acc_1` field specifies the number of times the inner loop needs to iterate through the short instructions. The `inp_0` field specifies the number of intermediate result base addresses accumulated after each inner loop iteration; the `inp_1` field specifies the number of input feature base addresses accumulated after each inner loop iteration; the `wgt_0` field specifies the number of weight base addresses accumulated after each outer loop iteration; the `wgt_1` field specifies the number of weight base addresses accumulated after each inner loop iteration; the `needBias` field specifies whether the bias value needs to be accumulated during the calculation of this instruction; the `biasOffset` field specifies the address index of the accumulated bias value in the bias cache; reserved fields are allowed.
[0024] For ALU instructions, the `op` field is used to distinguish long instruction types; the dependency field is used to explicitly define the dependencies between each long instruction during execution; the `uop_begin`, `uop_end`, `lp_0`, and `lp_1` fields have the same meaning as GEMM instructions; the `dst_0` field specifies the increment of the destination base address after each outer loop iteration; the `dst_1` field specifies the increment of the destination base address after each inner loop iteration; the `src_0` field specifies the increment of the source base address after each outer loop iteration; the `src_1` field specifies the increment of the source base address after each inner loop iteration; the `alp_op` field is used to select the arithmetic and logical operations to be performed; `alu_imm` is the immediate numeric field; reserved fields are allowed.
[0025] 4) Configure the behavior model for each short instruction.
[0026] Clearly define the behavior controlled by each field in the short command.
[0027] For the GEMM UOP instruction, the accIdx field is used to calculate the index of the intermediate result in the on-chip cache; the inpIdx field is used to calculate the index of the input feature in the on-chip cache; the wgtIdx field is used to calculate the index of the weight in the on-chip cache; the skew field is used to specify the bankid offset required when reading the input feature; the first field is used to specify whether this is the first accumulation operation for an output feature address; the final field is used to specify whether this is the last accumulation operation for an output feature address; the coreEn field is the computation enable flag for the computation core; reserved fields are allowed.
[0028] For the ALU UOP instruction, dstBankid is used to specify the destination cache block number in the output feature cache; dst is used to calculate the destination address in the cache block; srcBankid is used to specify the source cache block number in the output feature cache; src is used to calculate the source data address in the cache block; isFirst is used to specify whether this arithmetic logic operation is being performed for a destination address for the first time; useImm is used to specify whether an immediate value is used; reserved fields are allowed.
[0029] 5) Design the encoding format for each long instruction.
[0030] Clearly defining the arrangement of fields in long instructions facilitates decoding by deep learning processors, specifically as follows: Figure 2 As shown.
[0031] 6) Design the encoding format for each short instruction.
[0032] Clearly defining the arrangement of fields in short instructions facilitates decoding by deep learning processors, specifically as follows: Figure 3 As shown.
[0033] 7) Based on the requirements of the long instruction encoding format, iteratively design the length of the long instruction and the length of each field.
[0034] Constrained by on-chip computing and storage resources, and considering the computational scale of deep learning algorithms, the length of long instructions and the length of each field are iteratively designed.
[0035] 8) Based on the short instruction encoding format requirements, iteratively design the short instruction length and the length of each field.
[0036] Constrained by on-chip computing and storage resources, and considering the computational scale of deep learning algorithms, the short instruction length and the length of each field are iteratively designed.
[0037] The beneficial effects of this invention are as follows:
[0038] 1) This invention addresses the problem of online parallel general-purpose matrix computation in deep learning algorithms by proposing a variable-length instruction set design method. By using loop parameters in the instructions, a single long instruction controls multiple calculations of a small number of short instructions, achieving the goal of completing massive computations with a small number of instructions and reducing instruction fetch overhead.
[0039] 2) This invention obtains on-chip data addresses through short instruction decoding calculation, reducing the length of address information in instructions, simplifying on-chip address logic, and optimizing instruction length;
[0040] 3) Based on the general matrix calculation mode in deep learning algorithms, this invention designs the instruction set, fully develops the data-level parallelism capability during matrix calculation, and realizes flexible online calculation of deep learning processors when processing different neural networks. Attached Figure Description
[0041] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.
[0042] Figure 1 This is a flowchart of the instruction set design method for matrix-oriented online parallel general-purpose computing disclosed in this invention;
[0043] Figure 2 This is a diagram illustrating the encoding format of each long instruction. This diagram distinguishes the length and meaning of each field in a long instruction; see the embodiment for details.
[0044] Figure 3 This is a diagram illustrating the encoding format of each short instruction. The diagram distinguishes the length and meaning of each field in the short instruction; see the implementation example for details. Detailed Implementation
[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0046] The specific implementation steps are as follows:
[0047] 1) Configuration instruction length requirement model
[0048] The design incorporates a variable-length instruction set (VLS), where long instructions handle control, and short instructions are reused cyclically under the control of the long instructions, thus reducing instruction fetch overhead. Short instructions are the smallest unit of on-chip computation and can control the parallel computation of small batches of data.
[0049] 2) Configuration instruction type requirement model
[0050] Long instructions include LOAD, STORE, GEMM, ALU, and FINISH. The LOAD instruction is used to load short instructions or computational data from off-chip cache to on-chip. The STORE instruction is used to transfer on-chip computation results to off-chip cache. The GEMM instruction is used for matrix multiplication calculations. The ALU is used for matrix arithmetic logic calculations.
[0051] Short instructions include the GEMM UOP instruction and the ALU UOP instruction. GEMM UOP is a short instruction used by deep learning processors for online parallel computations of matrix multiplication types, while ALU UOP is a short instruction used by deep learning processors for online parallel computations of matrix arithmetic logic types.
[0052] 3) Configure the behavior model for each long instruction.
[0053] Clearly define the behavior controlled by each field in a long command.
[0054] Both the LOAD and STORE instructions are data transfer instructions, differing only in the direction of data transfer. The fields for both instructions have the same function. These include: the op field (to distinguish long instructions); the dependency field (to explicitly define the dependencies between long instructions); the memid field (to specify the data transfer source or destination); the bankid field (to specify the storage block where the transferred data resides in the data transfer source or destination); the sramOffset field (to specify the base address of the transferred data in the storage block); and the dramOffset field (to specify the base address of the transferred data in the off-chip cache). Data is transferred in units of tensors, grouped into sets of xsize tensors. The ysize field specifies the number of tensor groups to be transferred in the y-direction, and the xsize field specifies... The x-axis specifies the number of tensors to be transmitted, and xstride specifies the number of tensors in the interval between each group of tensors. Zero padding is a common operation in deep learning algorithms. ypad0 is the number of zero-padding tensors to be added before each ysize group of tensors is read in the y-axis, ypad1 is the number of zero-padding tensors to be added after each ysize group of tensors is read in the y-axis, xpad0 is the number of zero-padding tensors to be added before each xsize group of tensors is read in consecutively, and xpad1 is the number of zero-padding tensors to be added after each xsize group of tensors is read in consecutively. Reserved fields are allowed.
[0055] For GEMM instructions, the `op` field distinguishes long instruction types; the `dependency` field explicitly defines the dependencies between each long instruction; the `uop_begin` field defines the starting address of the short instruction to be executed in the short instruction cache; the `uop_end` field defines the ending address of the short instruction to be executed in the short instruction cache; the `lp_0` field specifies the number of times the outer loop needs to iterate through the short instructions; the `lp_1` field specifies the number of times the inner loop needs to iterate through the short instructions; the `acc_0` field specifies the increment of the intermediate result base address after each outer loop iteration; and the `acc_1` field specifies the number of times the inner loop needs to iterate through the short instructions. The `inp_0` field specifies the number of intermediate result base addresses accumulated after each inner loop iteration; the `inp_1` field specifies the number of input feature base addresses accumulated after each inner loop iteration; the `wgt_0` field specifies the number of weight base addresses accumulated after each outer loop iteration; the `wgt_1` field specifies the number of weight base addresses accumulated after each inner loop iteration; the `needBias` field specifies whether the bias value needs to be accumulated during the calculation of this instruction; the `biasOffset` field specifies the address index of the accumulated bias value in the bias cache; reserved fields are allowed.
[0056] For ALU instructions, the `op` field is used to distinguish long instruction types; the dependency field is used to explicitly define the dependencies between each long instruction during execution; the `uop_begin`, `uop_end`, `lp_0`, and `lp_1` fields have the same meaning as GEMM instructions; the `dst_0` field specifies the increment of the destination base address after each outer loop iteration; the `dst_1` field specifies the increment of the destination base address after each inner loop iteration; the `src_0` field specifies the increment of the source base address after each outer loop iteration; the `src_1` field specifies the increment of the source base address after each inner loop iteration; the `alp_op` field is used to select the arithmetic and logical operations to be performed; `alu_imm` is the immediate numeric field; reserved fields are allowed.
[0057] 4) Configure the behavior model for each short instruction.
[0058] Clearly define the behavior controlled by each field in the short command.
[0059] For the GEMM UOP instruction, the accIdx field is used to calculate the index of the intermediate result in the on-chip cache; the inpIdx field is used to calculate the index of the input feature in the on-chip cache; the wgtIdx field is used to calculate the index of the weight in the on-chip cache; the skew field is used to specify the bankid offset required when reading the input feature; the first field is used to specify whether this is the first accumulation operation for an output feature address; the final field is used to specify whether this is the last accumulation operation for an output feature address; the coreEn field is the computation enable flag for the computation core; reserved fields are allowed.
[0060] For the ALU UOP instruction, dstBankid is used to specify the destination cache block number in the output feature cache; dst is used to calculate the destination address in the cache block; srcBankid is used to specify the source cache block number in the output feature cache; src is used to calculate the source data address in the cache block; isFirst is used to specify whether this arithmetic logic operation is being performed for a destination address for the first time; useImm is used to specify whether an immediate value is used; reserved fields are allowed.
[0061] 5) Design the encoding format for each long instruction.
[0062] Clearly defining the arrangement of fields in long instructions facilitates decoding by deep learning processors, specifically as follows: Figure 2 As shown.
[0063] 6) Design the encoding format for each short instruction.
[0064] Clearly defining the arrangement of fields in short instructions facilitates decoding by deep learning processors, specifically as follows: Figure 3 As shown.
[0065] 7) Based on the requirements of the long instruction encoding format, iteratively design the length of the long instruction and the length of each field.
[0066] Constrained by on-chip computing and storage resources, and considering the computational scale of deep learning algorithms, the length of long instructions and the length of each field are iteratively designed. Each long instruction is designed to be 128 bits long.
[0067] The LOAD instruction and the STORE instruction have the same format, with the following bits from high to low: op field (3 bits), dependency field (14 bits), memid field (3 bits), bankid field (6 bits), sramOffset field (10 bits), dramOffset field (32 bits), ysize field (16 bits), xsize field (16 bits), xstride field (16 bits), ypad0 field (3 bits), ypad1 field (3 bits), xpad0 field (3 bits), and xpad1 field (3 bits).
[0068] For GEMM instructions, from high to low bits are: op field (3 bits), dependency field (4 bits), uop_begin field (14 bits), uop_end field (14 bits), lp_0 field (10 bits), lp_1 field (10 bits), acc_0 field (10 bits), acc_1 field (10 bits), inp_0 field (10 bits), inp_1 field (10 bits), wgt_0 field (10 bits), wgt_1 field (10 bits), needBias field (1 bit), biasOffset field (8 bits), and reserved field (4 bits).
[0069] For ALU instructions, from high to low bits, the following are the fields: op (3 bits), dependency field (4 bits), uop_begin (14 bits), uop_end (14 bits), lp_0 (10 bits), lp_1 (10 bits), dst_0 (10 bits), dst_1 (10 bits), src_0 (10 bits), src_1 (10 bits), alu_op (3 bits), alu_imm (16 bits), and reserved field (14 bits).
[0070] The high byte's 3-bit opcode defines the FINISH instruction, and subsequent fields of this instruction are meaningless.
[0071] 8) Based on the short instruction encoding format requirements, iteratively design the short instruction length and the length of each field.
[0072] Constrained by on-chip computing and storage resources, and considering the computational scale of deep learning algorithms, the short instruction length and the length of each field are iteratively designed. Each short instruction is designed to be 32 bits long.
[0073] For the GEMM UOP instruction, from high to low bits are: accIdx field 16 bits, inpIdx field 16 bits, wgtIdx field 16 bits, skew field 4 bits, first field 1 bit, final field 1 bit, coreEn field 8 bits, and reserved field 2 bits.
[0074] For the ALU UOP instruction, the bits from high to low are: dstBankid (6 bits), dst (16 bits), srcBankid (6 bits), src (16 bits), isFirst (1 bit), useImm (1 bit), and reserved (18 bits).
[0075] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for designing an instruction set for matrix-based online parallel general-purpose computation, characterized in that, Includes the following steps: 1) Configure instruction length requirement model; 2) Configure instruction type requirement model; 3) Configure the behavior model for each long instruction; 4) Configure the behavior model for each short instruction; 5) Design the encoding format for each long instruction; 6) Design the encoding format for each short instruction; 7) Based on the requirements of the long instruction encoding format, iteratively design the length of the long instruction and the length of each field; 8) Based on the short instruction encoding format requirements, iteratively design the short instruction length and the length of each field.
2. The instruction set design method for matrix-oriented online parallel general-purpose computing according to claim 1, characterized in that, The design incorporates a variable-length instruction set, where long instructions are responsible for control, and short instructions are reused cyclically under the control of long instructions, thereby reducing instruction fetch overhead. The short instructions are the smallest unit of on-chip computation and can control the parallel computation of small batches of data.
3. The instruction set design method for matrix-oriented online parallel general-purpose computing according to claim 1 or 2, characterized in that, The long instructions include LOAD, STORE, GEMM, ALU, and FINISH instructions; wherein, the LOAD instruction is used to load short instructions or computation data from off-chip cache to on-chip; the STORE instruction is used to transfer on-chip computation results to off-chip cache; the GEMM instruction is used for matrix multiplication type computation; and the ALU is used for matrix arithmetic logic type computation.
4. The instruction set design method for matrix-oriented online parallel general-purpose computing according to any one of claims 1-3, characterized in that, The short instructions include the GEMM UOP instruction and the ALU UOP instruction; wherein, the GEMM UOP is a short instruction used by the deep learning processor to perform online parallel computation of matrix multiplication type, and the ALU UOP is a short instruction used by the deep learning processor to perform online parallel computation of matrix arithmetic logic type.
5. A method for designing an instruction set for matrix-based online parallel general-purpose computation according to claim 3 or 4, characterized in that, Both the LOAD and STORE instructions are data transmission instructions, differing only in the direction of data transmission. All fields in both instructions have the same function, including the op field, which distinguishes long instruction types. The dependency field explicitly specifies the dependencies between long instructions during execution; the memid field specifies the source or destination of data transmission; the bankid field specifies the storage block where the transmitted data resides in the data transmission source or destination; the sramOffset field specifies the base address of the transmitted data in the storage block; the dramOffset field specifies the base address of the transmitted data in the off-chip cache; data is transmitted in units of tensors, grouped into xsize tensors, with the ysize field specifying the number of tensor groups to be transmitted in the y-direction, and the xsize field specifying the number of tensors to be transmitted. The number of tensors in the x-direction, xstride is used to specify the number of tensors in the interval between each group of tensors; zero padding is a common operation in deep learning algorithms. ypad0 is the number of tensor groups with all zeros to be padded before each ysize group of tensors is read in the y-direction, ypad1 is the number of tensor groups with all zeros to be padded after each ysize group of tensors is read in the y-direction, xpad0 is the number of tensor groups with all zeros to be padded before each xsize group of tensors is read in consecutively, and xpad1 is the number of tensor groups with all zeros to be padded after each xsize group of tensors is read in consecutively. Reserved fields are allowed.
6. The instruction set design method for matrix-oriented online parallel general-purpose computing according to claims 3-5, characterized in that, For the GEMM instruction, the op field is used to distinguish long instruction types; The dependency fields are used to explicitly define the dependencies between each long instruction during execution; the `uop_begin` field defines the starting address of the short instruction to be executed in the short instruction cache; the `uop_end` field defines the ending address of the short instruction to be executed in the short instruction cache; the `lp_0` field specifies the number of times the outer loop needs to iterate over the short instructions; the `lp_1` field specifies the number of times the inner loop needs to iterate over the short instructions; the `acc_0` field specifies the increment of the intermediate result base address after each outer loop iteration; and the `acc_1` field specifies the increment of the intermediate result base address after each inner loop iteration. The following fields specify the cumulative base address of the intermediate results; the inp_0 field specifies the cumulative base address of the input feature after each outer loop iteration; the inp_1 field specifies the cumulative base address of the input feature after each inner loop iteration; the wgt_0 field specifies the cumulative weight base address after each outer loop iteration; the wgt_1 field specifies the cumulative weight base address after each inner loop iteration; the needBias field specifies whether the bias value needs to be accumulated during the calculation of this instruction; the biasOffset field specifies the address index of the accumulated bias value in the bias cache; reserved fields are allowed.
7. A method for designing an instruction set for matrix-oriented online parallel general-purpose computation according to any one of claims 3-6, characterized in that, For the ALU instructions, the op field is used to distinguish long instruction types; The dependency fields are used to explicitly define the dependencies between long instructions during execution; the uop_begin, uop_end, lp_0, and lp_1 fields have the same meaning as the GEMM instruction; the dst_0 field specifies the increment of the destination base address after each outer loop iteration; the dst_1 field specifies the increment of the destination base address after each inner loop iteration; the src_0 field specifies the increment of the source base address after each outer loop iteration; the src_1 field specifies the increment of the source base address after each inner loop iteration; the alp_op field is used to select the arithmetic and logical operations to be performed; alu_imm is the immediate numeric field; reserved fields are allowed.
8. The instruction set design method for matrix-oriented online parallel general-purpose computing according to any one of claims 4-7, characterized in that, For the GEMM UOP instruction, the accIdx field is used to calculate the index of the intermediate result in the on-chip cache; the inpIdx field is used to calculate the index of the input feature in the on-chip cache; the wgtIdx field is used to calculate the index of the weight in the on-chip cache; the skew field is used to specify the bankid offset required when reading the input feature; the first field is used to specify whether an accumulation operation is performed for an output feature address for the first time; the final field is used to specify whether an accumulation operation is performed for an output feature address for the last time; the coreEn field is the computation enable flag for the computation core; reserved fields are allowed.
9. A method for designing an instruction set for matrix-oriented online parallel general-purpose computation according to any one of claims 4-8, characterized in that, For the ALU UOP instruction, dstBankid is used to specify the destination cache block number in the output feature cache; dst is used to calculate the destination address in the cache block; srcBankid is used to specify the source cache block number in the output feature cache; src is used to calculate the source data address in the cache block; isFirst is used to specify whether this arithmetic logic operation is being performed for a destination address for the first time; useImm is used to specify whether an immediate value is used; reserved fields are allowed.
10. A method for designing an instruction set for matrix-oriented online parallel general-purpose computation according to any one of claims 1-9, characterized in that, Clearly defining the arrangement of fields in long instructions facilitates decoding by deep learning processors; clearly defining the arrangement of fields in short instructions also facilitates decoding by deep learning processors.
11. A method for designing an instruction set for matrix-oriented online parallel general-purpose computation according to any one of claims 3-10, characterized in that, Constrained by on-chip computing and storage resources, and considering the computational scale of deep learning algorithms, the length of long instructions and the length of each field are iteratively designed; the length of each long instruction is designed to be 128 bits. The LOAD instruction and the STORE instruction have the same format, and from high to low bits, they are: op field 3 bits, dependency field 14 bits, memid field 3 bits, bankid field 6 bits, sramOffset field 10 bits, dramOffset field 32 bits, ysize field 16 bits, xsize field 16 bits, xstride field 16 bits, ypad0 field 3 bits, ypad1 field 3 bits, xpad0 field 3 bits, xpad1 field 3 bits; For the GEMM instruction, from high to low bits, the following are the fields: op (3 bits), dependency field (4 bits), uop_begin (14 bits), uop_end (14 bits), lp_0 (10 bits), lp_1 (10 bits), acc_0 (10 bits), acc_1 (10 bits), inp_0 (10 bits), inp_1 (10 bits), wgt_0 (10 bits), wgt_1 (10 bits), needBias (1 bit), biasOffset (8 bits), and reserved field (4 bits). For the ALU instruction, from high to low bits, the following are the fields: op (3 bits), dependency field (4 bits), uop_begin (14 bits), uop_end (14 bits), lp_0 (10 bits), lp_1 (10 bits), dst_0 (10 bits), dst_1 (10 bits), src_0 (10 bits), src_1 (10 bits), alu_op (3 bits), alu_imm (16 bits), and reserved field (14 bits). The high byte's 3-bit opcode defines the FINISH instruction, and subsequent fields of this instruction are meaningless.
12. The instruction set design method for matrix-oriented online parallel general-purpose computing according to claims 4-11, characterized in that, Constrained by on-chip computing and storage resources, and considering the computational scale of deep learning algorithms, the short instruction length and the length of each field are iteratively designed; the length of each short instruction is designed to be 32 bits. For the GEMM UOP instruction, from high to low bits, the accIdx field is 16 bits, the inpIdx field is 16 bits, the wgtIdx field is 16 bits, the skew field is 4 bits, the first field is 1 bit, the final field is 1 bit, the coreEn field is 8 bits, and the reserved field is 2 bits. For the ALU UOP instruction, from high to low bits, the fields are: dstBankid (6 bits), dst (16 bits), srcBankid (6 bits), src (16 bits), isFirst (1 bit), useImm (1 bit), and reserved (18 bits).