A dual antenna radio frequency channel isolation circuit for a satellite transceiver

Abstract

The application discloses a kind of satellite transceiver's dual antenna radio frequency channel isolation circuit, comprising: circuit board, main input port, slave input port and signal processing chip;The input circuit of main input port is divided into two ways on the front of circuit board;First road passes to the back of circuit board and is divided into first subcircuit and second subcircuit;First subcircuit is connected to the back B3M frequency conversion processing circuit by first intermediate layer;Second subcircuit is connected with B1M frequency conversion processing circuit;Second input circuit passes to the back and is connected with auxiliary frequency conversion circuit;The input circuit of slave input port passes to the back and is divided into third input circuit and fourth input circuit;Third input circuit passes to the front and is connected with B3S frequency conversion processing circuit;Fourth input circuit is connected to the front B1S frequency conversion processing circuit by second intermediate layer.The present application carries out frequency conversion processing to slave input signal and main input signal respectively on the front and back of circuit board, reduces the direct coupling and radiation interference between signals.

Description

Technical Field

[0001] This invention relates to the field of satellite positioning technology, and in particular to a dual-antenna radio frequency channel isolation circuit for a satellite transceiver. Background Technology

[0002] Multi-channel RF front-ends for satellite communication / satellite navigation typically require simultaneous access to two master-slave interfaces (e.g., master and slave antennas), with each interface covering two RF bands, resulting in a total of four RF inputs participating in subsequent orientation / positioning processing. These devices are widely used in high-precision GNSS orientation, RTK positioning, and satellite communication earth stations, and have extremely high requirements for channel isolation, phase consistency, and noise floor.

[0003] Traditional PCB implementations often employ the arrangement of processing circuits for different frequency bands on the same board surface, suppressing coupling by increasing trace spacing, partitioning layouts, and using shielding cavities. To suppress coupling, it is often necessary to increase the board size and isolation spacing, leading to increased cost and assembly complexity. The board size is also relatively large. Furthermore, in master-slave collaboration or master antenna positioning scenarios, existing designs often experience signal leakage / coupling to the slave interface (and vice versa) when a signal is input to the master interface, resulting in self-interference and in-band spurious signals. This introduces phase / amplitude errors in directional calculations or master antenna positioning, significantly affecting measurement accuracy and stability. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a dual-antenna radio frequency channel isolation circuit for a satellite transceiver. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A first aspect of the present invention provides a dual-antenna radio frequency channel isolation circuit for a satellite transceiver, comprising: a circuit board, a main input port, a slave input port, and a first signal processing chip;

[0006] The input circuit of the main input port is divided into a first input circuit and a second input circuit on the front side of the circuit board; the first input circuit passes through the circuit board and connects to the back side of the circuit board, and is divided into a first sub-circuit and a second sub-circuit on the back side of the circuit board.

[0007] The first sub-circuit is connected to the B3M frequency conversion processing circuit on the back side through the first intermediate layer of the circuit board; the second sub-circuit is connected to the B1M frequency conversion processing circuit on the back side, and the B3M frequency conversion processing circuit and the B1M frequency conversion processing circuit pass through to the front side and are connected to the first signal processing chip.

[0008] The second input circuit is connected to the auxiliary frequency converter circuit;

[0009] The input circuit from the input port passes through the circuit board and connects to the back of the circuit board, where it is divided into a third input circuit and a fourth input circuit.

[0010] The third input circuit passes through to the front and is connected to the front B3S frequency conversion processing circuit; the fourth input circuit is connected to the front B1S frequency conversion processing circuit through the second intermediate layer of the circuit board; the B3S frequency conversion processing circuit and the B1S frequency conversion processing circuit are connected to the first signal processing chip.

[0011] The distance between the position where the input circuit of the main input port enters the circuit board and the main input port, and the distance between the position where the input circuit of the secondary input port enters the circuit board and the secondary input port, are both preset lengths.

[0012] In one embodiment of the present invention, the circuit board is provided with a main capacitor, a first main via, and a second main via;

[0013] One end of the first main via and the second main via are connected to the front side of the circuit board, and the other end is connected to the back side of the circuit board;

[0014] The first input circuit extends through the first main via to the back of the circuit board and is divided into a first sub-circuit and a second sub-circuit.

[0015] The second input circuit is connected to the auxiliary frequency converter circuit through the main capacitor and the second main via.

[0016] In one embodiment of the present invention, the first input circuit is connected to one end of the first main via, and the other end of the first main via is connected to the first sub-circuit and the second sub-circuit.

[0017] The circuit board is also provided with a third main via, a fourth main via, a fifth main via, and a sixth main via.

[0018] One end of the third and fourth main vias is connected to the back of the circuit board, and the other end is connected to the first intermediate layer of the circuit board; one end of the fifth and sixth main vias is connected to the back of the circuit board, and the other end is connected to the front of the circuit board.

[0019] The first sub-circuit is connected to one end of the third main via, the other end of the third main via is connected to the first intermediate layer, the first intermediate layer is connected to the other end of the fourth main via, and one end of the fourth main via is connected to the B3M frequency conversion processing circuit.

[0020] The B1M frequency conversion processing circuit and the B3M frequency conversion processing circuit are respectively connected to the first signal processing chip through the fifth main via and the sixth main via.

[0021] In one embodiment of the present invention, the B1M frequency conversion processing circuit is connected to one end of the fifth main via, and the other end of the fifth main via is connected to the first signal processing chip;

[0022] The B3M frequency conversion processing circuit is connected to one end of the sixth main via, and the other end of the sixth main via is connected to the first signal processing chip.

[0023] In one embodiment of the present invention, the second input circuit is connected to the main capacitor, the main capacitor is connected to one end of the second main via, and the other end of the second main via is connected to the auxiliary frequency conversion processing circuit.

[0024] In one embodiment of the present invention, the circuit board is further provided with a first via, one end of the first via being connected to the front side of the circuit board and the other end being connected to the back side of the circuit board;

[0025] The input circuit from the input port passes through the first via to the back of the circuit board and is divided into a third input circuit and a fourth input circuit.

[0026] In one embodiment of the present invention, the circuit board is further provided with a second via, one end of the second via being connected to the front side of the circuit board and the other end being connected to the back side of the circuit board;

[0027] The third input circuit is connected to the B3S frequency conversion processing circuit through the second via.

[0028] In one embodiment of the present invention, the circuit board is further provided with a third via and a fourth via;

[0029] The third via is connected to the back of the circuit board at one end and to the second intermediate layer of the circuit board at the other end; the fourth via is connected to the second intermediate layer of the circuit board at one end and to the front of the circuit board at the other end.

[0030] The fourth input circuit is connected to one end of the third via, the other end of the third via is connected to the second intermediate layer of the circuit board, the second intermediate layer is connected to one end of the fourth via, and the other end of the fourth via is connected to the B1S frequency conversion processing circuit.

[0031] In one embodiment of the present invention, a plurality of connecting intermediate layers are provided between the first intermediate layer and the second intermediate layer, and the first intermediate layer is close to the front side of the circuit board;

[0032] Multiple ground holes are provided between the first sub-circuit and the fourth input circuit, and between the second sub-circuit and the third input circuit;

[0033] The ground hole extends from the back of the circuit board toward the location near the second intermediate layer.

[0034] In one embodiment of the present invention, the auxiliary frequency conversion circuit includes: a B2b frequency band frequency conversion processing circuit and an S-band frequency conversion processing circuit.

[0035] The beneficial effects of this invention are:

[0036] This invention performs frequency conversion processing on the front and back sides of the circuit board for the primary and secondary input signals, respectively. This physical isolation significantly increases the spatial distance between the primary and secondary signal paths, substantially reducing direct coupling and radiated interference between signals. This ensures the purity of signals involved in directional calculations or primary antenna positioning, greatly improving the system's direction-finding and positioning accuracy. Simultaneously, by isolating two frequency bands of the same input signal through an intermediate layer to suppress coupling, and by physically separating these two frequency bands in the vertical dimension, intermodulation distortion or harmonic interference caused by different frequency bands within the same interface during processing is effectively avoided. This not only guarantees the independence and integrity of dual-band signals within a single interface but also further purifies the RF environment and improves the signal-to-noise ratio of the receiving link. This invention, while ensuring high isolation, achieves a compact arrangement of complex four-channel RF input and frequency division processing functions on a limited board surface, which is beneficial for miniaturization and lightweight design of the device, reducing production costs and assembly difficulty.

[0037] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0038] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0039] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0040] Figure 1 A schematic diagram of the front structure of a circuit board for a dual-antenna radio frequency channel isolation circuit of a satellite transceiver provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of the back structure of a circuit board for a dual-antenna radio frequency channel isolation circuit of a satellite transceiver provided in an embodiment of the present invention. Detailed Implementation

[0042] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0043] like Figure 1 and Figure 2 As shown, this embodiment of the invention provides a dual-antenna RF channel isolation circuit for a satellite transceiver, including: a circuit board, a main input port 10, a slave input port 20, and a first signal processing chip 30. The main input port 10 is connected to the main antenna to input the main signal, and the slave input port 20 is connected to the slave antenna to input the slave signal. The main signal and the slave signal are the same signal, and both the main signal and the slave signal need to be frequency-converted to two frequency points, B3 and B1.

[0044] The input circuit of the main input port 10 is divided into a first input circuit and a second input circuit on the front side 40 of the circuit board. The first input circuit passes through the circuit board and connects to the back side 50 of the circuit board, where it is divided into a first sub-circuit and a second sub-circuit 35. The input circuit of the main input port 10 is divided into two branches: the first input circuit and the second input circuit. These two branches have the same function as the input circuit of the main input port 10, both used for signal transmission. The first input circuit is further divided into two branches: the first sub-circuit and the second sub-circuit 35. These two branches have the same function as the first input circuit, both used for signal transmission.

[0045] The first sub-circuit is connected to the B3M frequency conversion processing circuit 11 on the back side 50 through the first intermediate layer of the circuit board; the second sub-circuit 35 is connected to the B1M frequency conversion processing circuit 12 on the back side 50, and the B3M frequency conversion processing circuit 11 and the B1M frequency conversion processing circuit 12 pass through to the front side 40 and are connected to the first signal processing chip 30.

[0046] Here, the B3M frequency conversion processing circuit 11 and the B1M frequency conversion processing circuit 12 are located on the back side 50 of the circuit board. The main signal input from the main input port 10 undergoes frequency conversion processing on the back side 50 of the circuit board, generating B3M and B1M frequency signals respectively through the B3M and B1M frequency conversion processing circuits 11 and 12. The signal from the first sub-circuit also passes through the first intermediate layer before entering the frequency conversion processing circuit, while the signal from the second sub-circuit 35 undergoes frequency conversion processing directly without passing through the intermediate layer. Therefore, the signals from the first sub-circuit and the second sub-circuit 35 can be decoupled and isolated to prevent mutual interference.

[0047] The second input circuit is connected to the auxiliary frequency converter circuit. The auxiliary frequency converter circuit includes a B2b band frequency converter processing circuit 33 and an S band frequency converter processing circuit 34 located on the back 50 of the circuit board.

[0048] The input circuit from input port 20 passes through the circuit board and connects to the back side 50 of the circuit board. On the back side 50 of the circuit board, it is divided into a third input circuit and a fourth input circuit. The input circuit from input port 20 is divided into two branches, the third input circuit and the fourth input circuit. These two branches have the same function as the input circuit from input port 20, which is used to transmit signals.

[0049] The third input circuit passes through the circuit board and connects to the B3S frequency conversion processing circuit 21 on the front side 40; the fourth input circuit connects to the B1S frequency conversion processing circuit 22 on the front side 40 through the second intermediate layer of the circuit board. The B3S frequency conversion processing circuit 21 and the B1S frequency conversion processing circuit 22 are connected to the first signal processing chip 30. Here, the B3S frequency conversion processing circuit 21 and the B1S frequency conversion processing circuit 22 are located on the front side 40 of the circuit board. The signals input from the input port 20 are frequency converted on the front side 40 of the circuit board, and the B3S frequency point and B1S frequency point signals are generated by the B3S frequency conversion processing circuit 21 and the B1S frequency conversion processing circuit 22, respectively.

[0050] Here, the slave signal from input port 20 undergoes frequency conversion processing on the front side 40 of the circuit board, thereby decoupling and isolating it from the frequency conversion processing of the main input port 10, preventing mutual interference between the main and slave signals. Specifically, the input circuit of input port 20 splits into two paths after entering the back side 50 from the front side 40 of the circuit board, and then re-enters the front side 40 for frequency conversion. This differs from the main signal of main input port 10, which is split into two paths on the front side 40 and further divided into two sub-circuits (first and second sub-circuits 35) on the back side 50 for frequency conversion. Therefore, decoupling and isolation between the main and slave signals are achieved.

[0051] The distance between the position of the input circuit of the main input port 10 entering the circuit board and the main input port 10, and the distance between the position of the input circuit of the input port 20 entering the circuit board and the input port 20, are both preset lengths L.

[0052] Here, the distance L from the input circuit of the input port to the circuit board is small, thereby reducing the signal input distance and avoiding interference caused by excessive transmission distance and too many components. Preferably, L = 3.56 mm.

[0053] Specifically, the circuit board is provided with a main capacitor 13, a first main via 14, and a second main via 15.

[0054] One end of the first main via 14 and one end of the second main via 15 are connected to the front side 40 of the circuit board, and the other end of the first main via 14 and the other end of the second main via 15 are connected to the back side 50 of the circuit board. The first main via 14 and the second main via 15 connect the front side 40 and the back side 50 of the circuit board.

[0055] The first input circuit extends through the first main via 14 to the back 50 of the circuit board, dividing into a first sub-circuit and a second sub-circuit 35. The first input circuit is connected to one end of the first main via 14 (located on the front 40), and the other end of the first main via 14 (located on the back 50) connects to the first sub-circuit and the second sub-circuit 35. The second input circuit is connected to the auxiliary frequency converter circuit through the main capacitor 13 and the second main via 15.

[0056] In this embodiment, the first input circuit and the second input circuit are located on the front side 40 of the circuit board. The first input circuit extends to the back side 50 of the circuit board through the first main via 14. The second input circuit passes through the main capacitor 13, which is then connected to the second main via 15, which extends to the back side 50 of the circuit board. The first input circuit and the second input circuit enter the back side 50 of the circuit board with different circuit structures, thereby achieving isolation and preventing mutual interference.

[0057] In this embodiment, the second input circuit is connected to the main capacitor 13, the main capacitor 13 is connected to one end of the second main via 15 (located on the front side 40), and the other end of the second main via 15 (located on the back side 50) is connected to the auxiliary frequency conversion processing circuit (located on the back side 50).

[0058] Furthermore, the circuit board is also provided with a third main via 16, a fourth main via 17, a fifth main via 18 and a sixth main via 19.

[0059] One end of the third main via 16 and one end of the fourth main via 17 are connected to the back surface 50 of the circuit board, and the other ends of the third main via 16 and the fourth main via 17 are connected to the first intermediate layer of the circuit board. The third main via 16 and the fourth main via 17 connect the back surface 50 of the circuit board and the first intermediate layer. One end of the fifth main via 18 and one end of the sixth main via 19 are connected to the back surface 50 of the circuit board, and the other ends of the fifth main via 18 and the sixth main via 19 are connected to the front surface 40 of the circuit board. The fifth main via 18 and the sixth main via 19 connect the front surface 40 of the circuit board and the back surface 50 of the circuit board.

[0060] The first sub-circuit is connected to one end of the third main via 16 (located on the back side 50), the other end of the third main via 16 (located on the first intermediate layer) is connected to the first intermediate layer, the first intermediate layer is connected to the other end of the fourth main via 17 (located on the first intermediate layer), and one end of the fourth main via 17 (located on the back side 50) is connected to the B3M frequency converter processing circuit 11. The second sub-circuit 35 is connected to the B1M frequency converter processing circuit 12.

[0061] The B1M frequency converter processing circuit 12 and the B3M frequency converter processing circuit 11 are connected to the first signal processing chip 30 through the fifth main via 18 and the sixth main via 19, respectively. The B1M frequency converter processing circuit 12 is connected to one end of the fifth main via 18 (located on the back side 50), and the other end of the fifth main via 18 (located on the front side 40) is connected to the first signal processing chip 30. The B3M frequency converter processing circuit 11 is connected to one end of the sixth main via 19 (located on the back side 50), and the other end of the sixth main via 19 (located on the front side 40) is connected to the first signal processing chip 30.

[0062] In this embodiment, the first input circuit forms two branch circuits at one end of the back surface 50 through the first main via 14, namely the first sub-circuit and the second sub-circuit 35. The first sub-circuit is connected to the frequency converter circuit through the first intermediate layer, and the second sub-circuit 35 is directly connected to the frequency converter circuit. The two identical signals are input to the frequency converter circuit through different circuits, thereby preventing mutual interference between the first sub-circuit and the second sub-circuit 35.

[0063] Furthermore, the circuit board is also provided with a first via 23, one end of which is connected to the front side 40 of the circuit board, and the other end of which is connected to the back side 50 of the circuit board.

[0064] The input circuit from input port 20 passes through the first via 23 to the back 50 of the circuit board and is divided into a third input circuit and a fourth input circuit.

[0065] The circuit board is also provided with a second via 24, one end of which is connected to the front side 40 of the circuit board, and the other end of which is connected to the back side 50 of the circuit board.

[0066] The third input circuit is connected to the B3S frequency converter processing circuit 21 on the front side 40 via the second via 24. The third input circuit is connected to one end of the second via 24 (located on the back side 50), and the other end of the second via 24 (located on the front side 40) is connected to the B3S frequency converter processing circuit 21. The third input circuit passes through the circuit board from the back side 50 to the front side 40 and then enters the frequency converter circuit.

[0067] The circuit board also has a third via 25 and a fourth via 26. One end of the third via 25 is connected to the back surface 50 of the circuit board, and the other end is connected to the second intermediate layer of the circuit board. The third via 25 connects the back surface 50 and the second intermediate layer of the circuit board. One end of the fourth via 26 is connected to the second intermediate layer of the circuit board, and the other end is connected to the front surface 40 of the circuit board. The fourth via 26 connects the second intermediate layer and the front surface 40 of the circuit board.

[0068] The fourth input circuit is connected to one end of the third via 25 (located on the back side 50), the other end of the third via 25 (located on the second intermediate layer) is connected to the second intermediate layer of the circuit board, the second intermediate layer is connected to one end of the fourth via 26 (located on the second intermediate layer), and the other end of the fourth via 26 (located on the front side 40) is connected to the B1S frequency conversion processing circuit 22.

[0069] In this embodiment, the third input circuit and the fourth input circuit are connected to the frequency converter circuit through different circuit structures. The third input circuit and the fourth input circuit can form mutual isolation when transmitting signals to avoid mutual interference.

[0070] Here, the B3S frequency conversion processing circuit 21 and the B1S frequency conversion processing circuit 22 are directly connected to the first signal processing chip 30, while the B3M frequency conversion processing circuit 11 and the B1M frequency conversion processing circuit 12 are connected to the first signal processing chip 30 through vias. In addition to introducing the lines into the front side 40, the different circuit connection structures can avoid mutual interference between the main signal and the slave signal after frequency conversion.

[0071] Furthermore, multiple connecting intermediate layers are provided between the first intermediate layer and the second intermediate layer, with the first intermediate layer located near the front side 40 of the circuit board. The multiple connecting intermediate layers between the first and second intermediate layers prevent interference between circuits connected to the first and second intermediate layers, thus preventing interference between the first sub-circuit and the fourth input circuit. Since the master and slave signals are identical before frequency conversion, and also identical after frequency conversion, mutual interference must be avoided.

[0072] Multiple ground vias 27 are provided between the first sub-circuit and the fourth input circuit, and between the second sub-circuit 35 and the third input circuit. The ground vias 27 extend from the back surface 50 of the circuit board towards the second intermediate layer. The first and second sub-circuits 35 transmit main signals, while the third and fourth input circuits transmit slave signals. Therefore, the main and slave signals are effectively isolated by the ground vias 27, which are blind vias. The circuit board structure consists of a front surface 40, a first intermediate layer, multiple connecting intermediate layers, a second intermediate layer, multiple additional intermediate layers, and a back surface 50. The ground vias 27 pass through the multiple additional intermediate layers from the back surface 50 and do not reach the second intermediate layer. Trace routing is required between the first and second intermediate layers. Preferably, similar ground vias 27 can be provided between frequency converter circuits and between circuits to form isolation.

[0073] Optionally, the circuit board is also provided with a seventh main via 31 and an eighth main via 32.

[0074] One end of the seventh main via 31 is connected to the back 50 of the circuit board, and the other end of the seventh main via 31 is connected to the front 40 of the circuit board. One end of the eighth main via 32 is connected to the front 40 of the circuit board, and the other end of the eighth main via 32 is connected to the back 50 of the circuit board.

[0075] The second input circuit, after passing through the second main via 15, splits into two sub-circuits: a third sub-circuit 36 ​​and a fourth sub-circuit 37. The third sub-circuit 36 ​​is connected to the B2b band frequency conversion processing circuit 33, which in turn is connected to the second signal processing chip 60. The second signal processing chip 60 is located on the back 50 of the circuit board. These two branches, the third sub-circuit 36 ​​and the fourth sub-circuit 37, have the same function as the second input circuit: signal transmission.

[0076] The fourth sub-circuit 37 is connected to one end of the seventh main via 31 (located on the back side 50), and the other end of the seventh main via 31 (located on the front side 40) is connected to the S-band frequency conversion processing circuit 34 through the S-band preprocessing circuit 38 on the front side 40. Specifically, the other end of the seventh main via 31 (located on the front side 40) is connected to one end of the S-band preprocessing circuit 38, the other end of the S-band preprocessing circuit 38 is connected to one end of the eighth main via 32 (located on the front side 40), the other end of the eighth main via 32 (located on the back side 50) is connected to the S-band frequency conversion processing circuit 34, and the S-band frequency conversion processing circuit 34 is connected to the second signal processing chip 60. The S-band preprocessing circuit 38 is located on the front side 40 of the circuit board.

[0077] The main signal input from the main input port 10 is processed by the B2b frequency band conversion processing circuit 33 and the S-band frequency band conversion processing circuit 34 to generate B2b and S-band frequency point signals, respectively. The S-band preprocessing circuit 38 is used for signal preprocessing before the S-band frequency conversion processing, such as filtering and low-noise amplification.

[0078] Here, the third sub-circuit 36 ​​and the fourth sub-circuit 37 are connected to the frequency converter circuit through different circuit structures, which can prevent mutual interference and form isolation.

[0079] In practical applications of this invention, when the main path receives frequency point B3, there is no settlement of slave path signals; when the slave path receives frequency point B3, there is no settlement of main path signals; when the main path receives frequency point B1, there is no settlement of slave path signals; and when the slave path receives frequency point B1, there is no settlement of main path signals.

[0080] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0081] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0082] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0083] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0084] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0085] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A dual-antenna radio frequency channel isolation circuit for a satellite transceiver, characterized in that, include: Circuit board, main input port, slave input port and first signal processing chip; The input circuit of the main input port is divided into a first input circuit and a second input circuit on the front side of the circuit board; the first input circuit passes through the circuit board and connects to the back side of the circuit board, and is divided into a first sub-circuit and a second sub-circuit on the back side of the circuit board. The first sub-circuit is connected to the B3M frequency conversion processing circuit on the back side through the first intermediate layer of the circuit board; the second sub-circuit is connected to the B1M frequency conversion processing circuit on the back side, and the B3M frequency conversion processing circuit and the B1M frequency conversion processing circuit pass through to the front side and are connected to the first signal processing chip. The second input circuit is connected to the auxiliary frequency converter circuit; The input circuit from the input port passes through the circuit board and connects to the back of the circuit board, where it is divided into a third input circuit and a fourth input circuit. The third input circuit passes through to the front and is connected to the front B3S frequency conversion processing circuit; the fourth input circuit is connected to the front B1S frequency conversion processing circuit through the second intermediate layer of the circuit board; the B3S frequency conversion processing circuit and the B1S frequency conversion processing circuit are connected to the first signal processing chip. The distance between the position where the input circuit of the main input port enters the circuit board and the main input port, and the distance between the position where the input circuit of the secondary input port enters the circuit board and the secondary input port, are both preset lengths.

2. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 1, characterized in that, The circuit board is provided with a main capacitor, a first main via, and a second main via. One end of the first main via and the second main via are connected to the front side of the circuit board, and the other end is connected to the back side of the circuit board; The first input circuit extends through the first main via to the back of the circuit board and is divided into a first sub-circuit and a second sub-circuit. The second input circuit is connected to the auxiliary frequency converter circuit through the main capacitor and the second main via.

3. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 2, characterized in that, The first input circuit is connected to one end of the first main via, and the other end of the first main via is connected to the first sub-circuit and the second sub-circuit. The circuit board is also provided with a third main via, a fourth main via, a fifth main via, and a sixth main via; One end of the third main via and the fourth main via is connected to the back of the circuit board, and the other end is connected to the first intermediate layer of the circuit board; One end of the fifth main via and the sixth main via are connected to the back of the circuit board, and the other end is connected to the front of the circuit board. The first sub-circuit is connected to one end of the third main via, the other end of the third main via is connected to the first intermediate layer, the first intermediate layer is connected to the other end of the fourth main via, and one end of the fourth main via is connected to the B3M frequency conversion processing circuit. The B1M frequency conversion processing circuit and the B3M frequency conversion processing circuit are respectively connected to the first signal processing chip through the fifth main via and the sixth main via.

4. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 3, characterized in that, The B1M frequency conversion processing circuit is connected to one end of the fifth main via, and the other end of the fifth main via is connected to the first signal processing chip; The B3M frequency conversion processing circuit is connected to one end of the sixth main via, and the other end of the sixth main via is connected to the first signal processing chip.

5. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 2, characterized in that, The second input circuit is connected to the main capacitor, the main capacitor is connected to one end of the second main via, and the other end of the second main via is connected to the auxiliary frequency conversion processing circuit.

6. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 1, characterized in that, The circuit board is also provided with a first via, one end of which is connected to the front side of the circuit board and the other end is connected to the back side of the circuit board; The input circuit from the input port extends through the first via to the back of the circuit board and is divided into a third input circuit and a fourth input circuit.

7. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 6, characterized in that, The circuit board is also provided with a second via, one end of which is connected to the front side of the circuit board and the other end is connected to the back side of the circuit board; The third input circuit is connected to the B3S frequency conversion processing circuit through the second via.

8. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 7, characterized in that, The circuit board is also provided with a third via and a fourth via; The third via is connected to the back of the circuit board at one end and to the second intermediate layer of the circuit board at the other end; the fourth via is connected to the second intermediate layer of the circuit board at one end and to the front of the circuit board at the other end. The fourth input circuit is connected to one end of the third via, the other end of the third via is connected to the second intermediate layer of the circuit board, the second intermediate layer is connected to one end of the fourth via, and the other end of the fourth via is connected to the B1S frequency conversion processing circuit.

9. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 1, characterized in that, A plurality of connecting intermediate layers are provided between the first intermediate layer and the second intermediate layer, and the first intermediate layer is close to the front side of the circuit board; Multiple ground holes are provided between the first sub-circuit and the fourth input circuit, and between the second sub-circuit and the third input circuit; The ground hole extends from the back of the circuit board toward the location near the second intermediate layer.

10. The dual-antenna RF channel isolation circuit for a satellite transceiver as described in claim 8, characterized in that, The auxiliary frequency conversion circuit includes: a B2b frequency band frequency conversion processing circuit and an S-band frequency conversion processing circuit.

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