Semiconductor device and preparation method thereof
By using wafer-level flip-chip bonding and pillar structure between the transistor section and the passive device section, the problems of miniaturization and high cost of HBT PA chips are solved, achieving efficient device integration and low-cost production.
Patent Information
- Application Number
- CN202610214307.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-13
- Publication Date
- 2026-05-12
AI Technical Summary
Existing HBT PA chips have limitations in device structure, material system, or manufacturing process, making it difficult to meet the miniaturization requirements of wireless communication devices, and the large amount of gold used leads to high costs.
By using wafer-level flip-chip bonding between the transistor section and the passive device section, increasing the accommodation space with the use of bumps, reducing the device size, and replacing part of the gold with poly(p-phenylene benzodioxazole) material, multiple heterojunction bipolar transistor devices and passive devices can be interconnected, thereby improving integration and production efficiency.
This enables the miniaturization and cost reduction of HBT PA chips, improves integration and production efficiency, and avoids damage to the device structure during the bonding process.
Smart Images
Figure CN122028781A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology
[0002] In modern wireless communication systems, the radio frequency (RF) front-end module is the core component for signal transmission and reception, and its performance directly determines the quality and efficiency of wireless communication. The RF front-end module typically includes key components such as filters, amplifiers, bipolar transistors, and antenna switches, which together constitute the signal reception and transmission link. In the transmission link, the power amplifier (PA) is responsible for amplifying the signal output from the RF transceiver to drive the antenna and achieve effective signal radiation. Its role is crucial; therefore, the performance of the power amplifier, such as output power, linearity, efficiency, and reliability, is a key factor affecting the overall performance of the communication equipment.
[0003] Currently, power amplifiers used in communication equipment can be mainly divided into power amplifiers based on their core device structure: those based on field-effect transistors (FETs) and those based on bipolar junction transistors (BJTs). Heterojunction bipolar transistors (HBTs), as a special type of bipolar transistor, have been widely used in the field of radio frequency power amplifiers due to their significant advantages such as high current density, high power gain, good linearity, and ease of monolithic integration, especially in applications with stringent requirements for high frequency and high efficiency. HBT power amplifier chips (HBT PA chips) have become one of the mainstream solutions for the front-end modules of the transmit link in modern mobile communication, satellite communication, and wireless local area network systems.
[0004] Existing HBT PA chips have limitations in device structure, material system, or manufacturing process, and urgently need innovative improvements to develop chips that can improve integration while ensuring performance and reliability, in order to meet the growing miniaturization needs of wireless communication devices. Summary of the Invention
[0005] This application provides a semiconductor device and its fabrication method, which improves integration and facilitates chip miniaturization.
[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In one aspect of this application, a method for fabricating a semiconductor device is provided, comprising: forming a passive device region, comprising: providing a first wafer, the first wafer including a plurality of passive device regions; forming a first pad, a second pad, a third pad and a capacitor structure on the passive device regions, wherein the second pad is electrically connected to the capacitor structure; The transistor forming section includes: providing a second wafer; forming a plurality of heterojunction bipolar transistor devices; and bonding the plurality of heterojunction bipolar transistor devices at predetermined locations on the second wafer; wherein forming the heterojunction bipolar transistor devices includes: providing a substrate; forming a device structure on the substrate, the device structure including: a first collector, a first base electrode, and a first emitter electrode; forming a first interconnect metal structure on the substrate, the first interconnect metal structure being electrically connected to the first collector electrode; forming a second interconnect metal structure on the substrate, the second interconnect metal structure being electrically connected to the first base electrode; and forming a third interconnect metal structure on the substrate, the third interconnect metal structure being electrically connected to the first emitter electrode. The transistor section is bonded to the passive device section, and multiple heterojunction bipolar transistor devices correspond to multiple passive device regions respectively. The first interconnect metal structure is bonded to the first pad, the second interconnect metal structure is bonded to the second pad, and the third interconnect metal structure is bonded to the third pad.
[0007] In some feasible implementations, forming the first interconnect metal structure includes: forming a first protrusion located on a substrate; forming a first interconnect metal layer covering the first protrusion, the first interconnect metal layer being connected to a first collector; Forming the second interconnect metal structure includes: forming a second protrusion located on a substrate; forming a second interconnect metal layer covering the second protrusion, wherein the second interconnect metal layer is connected to a first base electrode; Forming a third interconnect metal structure includes: forming a third protrusion located on a substrate; forming a third interconnect metal layer covering the third protrusion, wherein the third interconnect metal layer is connected to a first emitter electrode.
[0008] In some feasible implementations, forming the passive device section further includes: forming a fourth pad and a first trace layer on the passive device region, wherein the fourth pad is used for collector voltage input and the first trace layer connects the first pad and the fourth pad.
[0009] In some feasible implementations, forming the passive device section further includes forming a fifth pad and a second trace layer on the passive device area, wherein the fifth pad is used for radio frequency signal input and the second trace layer connects the capacitor structure and the fifth pad.
[0010] In some feasible implementations, forming a heterojunction bipolar transistor device further includes: forming a fourth interconnect metal structure on a substrate, the fourth interconnect metal structure being electrically connected to a first base electrode; The passive device section also includes: forming a sixth pad on the passive device area, the sixth pad being used for base DC bias voltage input; The bonding of the transistor section to the passive device section also includes bonding the fourth interconnect metal structure to the sixth pad.
[0011] In some feasible implementations, forming the fourth interconnect metal structure includes: forming a fourth protrusion located on a substrate; forming a fourth interconnect metal layer covering the fourth protrusion, the fourth interconnect metal layer being connected to the first base electrode.
[0012] In some feasible implementations, the first protrusion, the second protrusion, the third protrusion, and the fourth protrusion have a first height, and the device structure has a second height, with the first height being higher than the second height.
[0013] In some feasible implementations, the ratio of the first height to the second height ranges from 2:1 to 6:1.
[0014] In some feasible implementations, forming the passive device section further includes: forming interconnect vias in the passive device region, penetrating the first wafer, the interconnect vias being used for grounding, and the interconnect vias being electrically connected to a third interconnect metal structure.
[0015] In some feasible implementations, the material of the first protrusion, the second protrusion, the third protrusion, and the fourth protrusion includes poly(p-phenylenebenzodioxazole).
[0016] In some feasible implementations, forming the passive device section further includes forming an eighth pad and a ninth pad on the passive device area; The heterojunction bipolar transistor device further includes: forming a second collector, a second base electrode, and a second emitter electrode; forming a fifth interconnect metal structure located on the substrate and electrically connected to the second collector electrode; forming a sixth interconnect metal structure located on the substrate and electrically connected to the second base electrode; wherein the third interconnect metal structure is also electrically connected to the second emitter electrode. The fifth interconnect metal structure is bonded to the eighth pad, and the sixth interconnect metal structure is bonded to the ninth pad.
[0017] In some feasible implementations, after bonding the transistor portion to the passive device portion, the process includes: removing the second wafer; and dicing the passive device portion to obtain a plurality of semiconductor devices.
[0018] In another aspect of the embodiments of this application, a semiconductor device is provided, which is prepared by any of the semiconductor device preparation methods described above.
[0019] This application provides a method for fabricating a semiconductor device, in which multiple heterojunction bipolar transistor devices are bonded to predetermined positions on a second wafer to form a transistor section. The first, second, and third interconnect metal structures of the transistor section are respectively bonded to the first, second, and third pads of the passive device section. Through wafer-level flip-chip bonding between the transistor section and the passive device section, the multiple heterojunction bipolar transistor devices are interconnected with the passive device structures of multiple passive device regions on the passive device section, reducing device size, increasing integration density, and facilitating chip miniaturization. In addition, the second wafer enables the batch bonding of heterojunction bipolar transistor devices to the passive device section, improving production efficiency.
[0020] Furthermore, by providing protrusions on the substrate of the heterojunction bipolar transistor device, the accommodating space between the transistor section and the passive device section is increased, thus avoiding damage to the device structure during the bonding process. Attached Figure Description
[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application; Figure 2 This is a schematic diagram of the passive device section in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 3 A schematic diagram of the geometric layout of a heterojunction bipolar transistor device in a method for fabricating a semiconductor device according to an embodiment of this application; Figure 4 This is a schematic diagram of the transistor section in a method for fabricating a semiconductor device according to an embodiment of this application; Figure 5 This is a schematic diagram of the geometric layout of the passive device region on the passive device section in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 6 This is a schematic diagram of the geometric layout of a bonding wafer in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 7 for Figure 6 A schematic diagram of a partial cross-sectional structure along the AA1 direction; Figure 8 for Figure 6A schematic diagram of a partial cross-sectional structure along the BB1 direction.
[0023] Icons: 10 - First wafer; 11 - Passive device area; 112 - First pad; 113 - Second pad; 114 - Third pad; 115 - Capacitor structure; 116 - Fourth pad; 117 - First routing layer; 118 - Second routing layer; 119 - Fifth pad; 120 - Sixth pad; 121 - Interconnect via; 122 - Seventh pad; 125 - Third routing layer; 126 - First insulating layer; 127 - Second insulating layer; 20 - Second wafer ; 21-Heterojunction bipolar transistor device; 211-Substrate; 212-First interconnect metal layer; 213-Second interconnect metal layer; 214-Third interconnect metal layer; 215-First collector; 216-First base electrode; 217-First emitter electrode; 218-First emitter layer; 219-First base layer; 220-Fourth interconnect metal layer; 231-First protrusion; 232-Second protrusion; 233-Third protrusion; 234-Fourth protrusion. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. It should be noted that, in the absence of conflict, the various features in the embodiments of this application can be combined with each other, and the combined embodiments are still within the protection scope of this application.
[0025] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and therefore should not be construed as limiting this application. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0026] HBT power amplifier chips consist of active devices and passive devices such as thin-film resistors, capacitors, and inductors. Currently, active and passive devices need to be fabricated and integrated separately on gallium arsenide substrates. The arrangement of various devices results in a large substrate planar size for gallium arsenide, making it difficult to meet the miniaturization requirements of signal amplification modules in IoT, mobile phones, and base stations. Moreover, to ensure efficient signal transmission from both active and passive devices, gold is typically used as the conductive material for on-chip interconnects and the back metal of the chip. The extensive use of gold keeps the chip cost high, making it difficult to effectively cover a wider range of application needs.
[0027] Based on this, embodiments of this application propose a method for fabricating a semiconductor device, such as... Figure 1 As shown, the preparation method includes: S101, forming a passive device section, including: providing a first wafer, the first wafer including a plurality of passive device regions; forming a first pad, a second pad, a third pad and a capacitor structure on the passive device regions, wherein the second pad is electrically connected to the capacitor structure.
[0028] S102, forming a transistor section, comprising: providing a second wafer; forming a plurality of heterojunction bipolar transistor devices; and bonding the plurality of heterojunction bipolar transistor devices at predetermined locations on the second wafer; wherein forming the heterojunction bipolar transistor devices comprises: providing a substrate; forming a device structure on the substrate, the device structure comprising: a first collector, a first base electrode, and a first emitter electrode; forming a first interconnect metal structure on the substrate, the first interconnect metal structure being electrically connected to the first collector electrode; forming a second interconnect metal structure on the substrate, the second interconnect metal structure being electrically connected to the first base electrode; and forming a third interconnect metal structure on the substrate, the third interconnect metal structure being electrically connected to the first emitter electrode.
[0029] S103. The transistor section is joined to the passive device section, and the multiple heterojunction bipolar transistor devices correspond to the multiple passive device regions respectively. The first interconnect metal structure is joined to the first pad, the second interconnect metal structure is joined to the second pad, and the third interconnect metal structure is joined to the third pad.
[0030] Reference Figure 2 As shown, forming a passive device section includes: providing a first wafer 10, the first wafer 10 including a plurality of passive device regions 11, such as... Figure 2 As shown, multiple passive device regions 11 are arranged in an array.
[0031] Reference Figure 3 As shown, forming a passive device section further includes: forming a first pad 112, a second pad 113, a third pad 114 and a capacitor structure 115 on each passive device area 11, wherein the second pad 113 is electrically connected to the capacitor structure 115.
[0032] It should be noted that the specific number of the first pad 112 and capacitor structure 115, as well as their arrangement on the passive device area 11, can be specifically arranged and set according to the chip requirements of the layout design.
[0033] In this embodiment, the material of the first wafer 10 includes glass. In another embodiment, the material of the first wafer includes one of the following: silicon, sapphire, or spinel.
[0034] In this embodiment, the first wafer 10 has a size of 8 inches. In another embodiment, the first wafer has a size of 12 inches.
[0035] Reference Figure 4 As shown, the transistor forming section includes: providing a second wafer 20; forming a plurality of heterojunction bipolar transistor devices 21; and bonding the plurality of heterojunction bipolar transistor devices 21 to predetermined positions on the second wafer 20.
[0036] Reference Figure 5 and Figure 7 As shown, forming a heterojunction bipolar transistor device 21 includes: providing a substrate 211; forming a device structure on the substrate 211, the device structure including: a first collector 215, a first base electrode 216, and a first emitter electrode 217; forming a first interconnect metal structure on the substrate 211, the first interconnect metal structure being electrically connected to the first collector 215; forming a second interconnect metal structure on the substrate 211, the second interconnect metal structure being electrically connected to the first base electrode 216; and forming a third interconnect metal structure on the substrate 211, the third interconnect metal structure being electrically connected to the first emitter electrode 217.
[0037] In this embodiment, the heterojunction bipolar transistor device 21 further includes: forming a protective layer to cover the device structure, wherein the protective layer exposes a portion of the first interconnect metal structure, the second interconnect metal structure, and the third interconnect metal structure.
[0038] In this embodiment, multiple device structures are formed on the substrate 211; the substrate 211 is cut to obtain multiple heterojunction bipolar transistor devices 21, each heterojunction bipolar transistor device 21 including a device structure.
[0039] In this embodiment, the material of the substrate 211 includes gallium arsenide.
[0040] In this embodiment, the device structure further includes: a first base layer 219 located on a substrate 211; a first emitter layer 218 located on the first base layer 219; wherein, a first collector 215 is located on the substrate 211, a first base electrode 216 is located on the first base layer 219, and a first emitter 217 is located on the first emitter layer 218.
[0041] In another embodiment, the device structure is an inverted HBT device structure, including: an emitter layer on a substrate; a base layer on the emitter layer; a collector layer on the base layer; an emitter electrode on the emitter layer; a base electrode on the base layer; and a collector electrode on the collector layer.
[0042] In this embodiment, the size of the second wafer 20 is the same as that of the first wafer 10.
[0043] Reference Figure 6 As shown, the transistor section and the passive device section are joined together, and multiple heterojunction bipolar transistor devices 21 correspond to multiple passive device regions 11 respectively. Among them, the first interconnect metal structure is joined to the first pad 112, the second interconnect metal structure is joined to the second pad 113, and the third interconnect metal structure is joined to the third pad 114.
[0044] It should be noted that when the transistor section is joined to the passive device section, the projections of the plurality of heterojunction bipolar transistor devices 21 on the transistor section onto the passive device section are respectively located within the plurality of passive device regions 11.
[0045] After the transistor section and the passive device section are joined, the first interconnect metal structure is interconnected with the first pad 112 to correspond to the input of the collector voltage (Vcc); the second interconnect metal structure is interconnected with the second pad 113 to correspond to the input of the radio frequency (RF) signal; and the third interconnect metal structure is interconnected with the third pad 114 to correspond to the emitter ground of the heterojunction bipolar transistor device 21.
[0046] This embodiment saves space occupied by passive devices that need to be set on the surface of gallium arsenide substrate by transferring the passive device region 11 to the first wafer 10, thereby reducing the size of gallium arsenide devices and saving material costs of semiconductor devices.
[0047] The present application provides a method for fabricating a semiconductor device by bonding multiple heterojunction bipolar transistor devices 21 to predetermined positions on a second wafer 20. By performing wafer-level flip-chip bonding between the transistor section and the passive device section, the multiple heterojunction bipolar transistor devices 21 are interconnected with the passive device structures of multiple passive device regions 11 on the passive device section, thereby reducing device size, increasing integration, and facilitating chip miniaturization. In addition, the second wafer 20 enables the batch bonding of heterojunction bipolar transistor devices 21 to the passive device section, thereby improving production efficiency.
[0048] Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure along the A-A1 direction within the area circled in yellow. Figure 8 for Figure 6 A schematic diagram of the cross-sectional structure along the B-B1 direction within the area circled in yellow.
[0049] In this embodiment, forming the first interconnect metal structure includes: forming a first protrusion 231 located on the substrate 211; forming a first interconnect metal layer 212 covering the first protrusion 231, and the first interconnect metal layer 212 being connected to the first collector 215.
[0050] Reference Figure 7As shown, the first protrusion 231 is located at the position corresponding to the first pad 112, and the first interconnect metal layer 212 is correspondingly connected to the first pad 112.
[0051] In this embodiment, forming the second interconnect metal structure includes: forming a second protrusion 232 located on the substrate 211; forming a second interconnect metal layer 213 covering the second protrusion 232, and the second interconnect metal layer 213 being connected to the first base electrode 216.
[0052] Reference Figure 8 As shown, the second protrusion 232 is located at the position corresponding to the second pad 113, and the second interconnect metal layer 213 is correspondingly connected to the second pad 113.
[0053] In this embodiment, forming the third interconnect metal structure includes: forming a third protrusion 233 located on the substrate 211; forming a third interconnect metal layer 214 covering the third protrusion 233, and the third interconnect metal layer 214 being connected to the first emitter electrode 217.
[0054] Reference Figure 8 As shown, the third protrusion 233 is located at the position corresponding to the third pad 114, and the third interconnect metal layer 214 is correspondingly connected to the third pad 114.
[0055] The first protrusion 231, the second protrusion 232, and the third protrusion 233 are located at the positions corresponding to the bonding of the transistor section and the passive device section, so as to play the role of raising the dimensions during the bonding process of the transistor section and the passive device section, increasing the accommodation space between the transistor section and the passive device section, and avoiding damage to the device structure during the bonding process.
[0056] like Figure 3 As shown, the passive device section further includes: forming a fourth pad 116 and a first trace layer 117 on the passive device area 11, wherein the fourth pad 116 is used for collector voltage input, and the first trace layer 117 connects the first pad 112 and the fourth pad 116.
[0057] In this embodiment, forming a passive device section further includes: forming a second wiring layer 118 and a fifth pad 119 on the passive device region 11, wherein the fifth pad 119 is used for radio frequency signal input, and the second wiring layer 118 connects the capacitor structure 115 and the fifth pad 119.
[0058] In this embodiment, as Figure 5 As shown, the heterojunction bipolar transistor device 21 further includes: forming a fourth interconnect metal structure located on the substrate 211, the fourth interconnect metal structure being electrically connected to the first base electrode 216.
[0059] Forming the fourth interconnect metal structure includes: forming a fourth protrusion 234 located on the substrate 211; forming a fourth interconnect metal layer 220 covering the fourth protrusion 234, wherein the fourth interconnect metal layer 220 is connected to the first base electrode 216.
[0060] In this embodiment, the first protrusion 231, the second protrusion 232, the third protrusion 233, and the fourth protrusion 234 have the same height.
[0061] like Figure 3 As shown, the passive device section further includes: forming a sixth pad 120 on the passive device area 11, the sixth pad 120 being used for base DC bias voltage input.
[0062] like Figure 6 As shown, bonding the transistor section to the passive device section further includes bonding the fourth interconnect metal structure to the sixth pad 120, and after bonding, the fourth interconnect metal layer 220 is connected to the sixth pad 120.
[0063] In this embodiment, as Figure 5 As shown, the device structure further includes: forming a second base layer on the substrate 211; forming a second emitter layer on the second base layer; forming a second collector on the substrate 211; forming a second base electrode on the second base layer; and forming a second emitter electrode on the second emitter layer.
[0064] In this embodiment, the fourth interconnect metal structure is electrically connected to the first base electrode 216 and the second base electrode.
[0065] In this embodiment, forming the passive device section further includes: forming a seventh pad 122 on the passive device region 11, which is electrically connected to the sixth pad 120. The base DC bias voltage is input through the seventh pad 122, and the base DC bias voltage is realized by electrically connecting each base electrode of the device structure through the sixth pad 120 and the fourth interconnect metal structure.
[0066] In this embodiment, the heterojunction bipolar transistor device 21 further includes: forming a fifth interconnect metal structure on the substrate 211 and electrically connecting it to the second collector electrode; and forming a sixth interconnect metal structure on the substrate 211 and electrically connecting it to the second base electrode.
[0067] The passive device area 11 also includes an eighth pad and a ninth pad, with the fifth interconnect metal structure corresponding to the eighth pad and the sixth interconnect metal structure corresponding to the ninth pad.
[0068] In this embodiment, the first trace layer 117 connects the first pad 112 and the eighth pad. Combined with... Figure 6It can be seen that the collector voltage is input through the fourth pad 116. The fourth pad 116 on the passive device section is interconnected with each collector through the first trace layer 117 to shunt the current to each collector of the device structure and realize the collector voltage input.
[0069] In this embodiment, the passive device area 11 includes multiple capacitor structures 115, which are electrically connected to the second pad 113 and the ninth pad, and the second trace layer 118 connects the multiple capacitor structures 115.
[0070] The fifth pad 119 receives the radio frequency signal, which is electrically connected to multiple capacitor structures 115 through the second trace layer 118 and shunt to each base electrode to realize the radio frequency signal input of each base electrode of the device structure.
[0071] In this embodiment, the third interconnect metal structure is also electrically connected to the second emitter electrode.
[0072] In another embodiment, the heterojunction bipolar transistor device further includes a seventh interconnect metal structure electrically connected to the second emitter electrode; the passive device region further includes a tenth pad, to which the seventh interconnect metal structure is correspondingly bonded.
[0073] In this embodiment, forming the passive device section further includes: forming an interconnect via 121 in the passive device region 11, penetrating the first wafer 10, the interconnect via 121 being used for grounding, and the interconnect via 121 being electrically connected to the third interconnect metal layer 214.
[0074] In this embodiment, the third interconnect metal structure electrically connects multiple emitter electrodes of the device structure and interconnects them to the third pad 114 through interconnect via 121. The third interconnect metal structure and the third pad 114 are interconnected accordingly, and the emitter of the heterojunction bipolar transistor device is grounded through the third interconnect metal structure.
[0075] In this embodiment, the first protrusion 231, the second protrusion 232, the third protrusion 233, and the fourth protrusion 234 have a first height h1, and the device structure of the heterojunction bipolar transistor device has a second height h2, wherein the first height h1 is higher than the second height h2. It should be noted that the second height h2 is the distance between the surface of the device structure and the surface of the substrate 211.
[0076] In some feasible implementations, the ratio of the first height h1 to the second height h2 ranges from 2:1 to 6:1.
[0077] For example, such as Figure 7 As shown, the first height h1 is 5 micrometers and the second height h2 is 1.5 micrometers.
[0078] In this embodiment, the first protrusion 231, the second protrusion 232, the third protrusion 233, and the fourth protrusion 234 are formed by photolithography. In another embodiment, the protrusions are formed by etching or stripping processes.
[0079] In this embodiment, the processes for forming the first interconnect metal layer 212, the second interconnect metal layer 213, the third interconnect metal layer 214, and the fourth interconnect metal layer 220 include sputtering and electroplating processes. In another embodiment, the process for forming the interconnect metal layers includes vapor deposition.
[0080] It should be noted that, in order to improve the stability of electrical signal conduction, gold target sputtering and electroplating can be used to form interconnect metal layers, which greatly saves the amount of gold material used. Compared with the traditional method of forming interconnects with copper pillars or by additionally preparing a gold interconnect layer outside the copper pillars, this method further saves the material cost of semiconductor devices.
[0081] In some feasible embodiments, the first protrusion 231, the second protrusion 232, the third protrusion 233, and the fourth protrusion 234 are made of poly(p-phenylenebenzodioxazole) (PBO). Specifically, the PBO protrusions are formed through a coating, exposure, development, and baking process.
[0082] The protruding pillars made of PBO material have excellent support capacity, good structural stability, strong chemical stability, and high temperature resistance. They can maintain stable support performance during the formation of interconnect metal layers and subsequent processes.
[0083] In this embodiment, refer to Figure 7 As shown, the passive device section further includes: a third wiring layer 125 formed on a first wafer 10, the third wiring layer 125 connecting the first wiring layer 117 and the interconnect via 121; a second insulating layer 127 formed on the third wiring layer 125, the first wiring layer 117 and the second wiring layer 118 located on the second insulating layer 127; a first insulating layer 126 formed on the first wiring layer 117; a window exposing the first wiring layer 117 formed in the first insulating layer 126, and a first pad 112 interconnecting with the first wiring layer 117 formed within the window. The insulating layers, such as the first insulating layer 126 and the second insulating layer 127, are typically made of polyimide, and the wiring layers, such as the first wiring layer 117 and the third wiring layer 125, are typically made of copper.
[0084] In some feasible implementations, after bonding the transistor portion to the passive device portion, the process includes: removing the second wafer 20; and dicing the passive device portion to obtain a plurality of semiconductor devices.
[0085] In another aspect of the embodiments of this application, a semiconductor device is provided, which is prepared by the semiconductor device preparation method of any of the foregoing embodiments.
[0086] The semiconductor device fabricated using the method described in this application is obtained by wafer-level flip-chip bonding of the transistor section and the passive device section, followed by dicing. The passive device section includes multiple passive device regions 11, on which a first pad 112, a capacitor structure 115, a second pad 113, and a third pad 114 are formed. The second pad 112 is electrically connected to the capacitor structure 115. Multiple heterojunction bipolar transistor devices 21 are bonded on the second wafer 20. The heterojunction bipolar transistor device 21 includes: a first collector 215, a first base electrode 216, a first emitter electrode 217, a first interconnect metal structure electrically connected to the first collector 215, a second interconnect metal structure electrically connected to the first base electrode 216, and a third interconnect metal structure electrically connected to the first emitter electrode 217.
[0087] After bonding the transistor section to the passive device section, multiple heterojunction bipolar transistor devices 21 correspond to multiple passive device regions 11. The first interconnect metal structure, the second interconnect metal structure, and the third interconnect metal structure are respectively bonded to the first pad 112, the second pad 113, and the third pad 114. Specifically, the first interconnect metal layer 212 is connected to the first pad 112, the second interconnect metal layer 213 is connected to the second pad 113, and the third interconnect metal layer 214 is connected to the third pad 114. Wafer-level flip-chip bonding enables the interconnection of multiple heterojunction bipolar transistor devices 21 with the passive device structures of multiple passive device regions 11 on the passive device section, reducing device size, increasing integration density, and facilitating chip miniaturization. In addition, the second wafer 20 enables the batch bonding of heterojunction bipolar transistor devices 21 to the passive device section, improving production efficiency. Furthermore, by providing protrusions on the substrate of the heterojunction bipolar transistor device 21, the accommodating space between the transistor section and the passive device section is increased, thus avoiding damage to the device structure during the bonding process.
[0088] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: Forming a passive device section includes: providing a first wafer, the first wafer including a plurality of passive device regions; forming a first pad, a second pad, a third pad, and a capacitor structure on the passive device regions, wherein the second pad is electrically connected to the capacitor structure; A transistor forming section includes: providing a second wafer; forming a plurality of heterojunction bipolar transistor devices; and bonding the plurality of heterojunction bipolar transistor devices at predetermined locations on the second wafer; wherein forming the heterojunction bipolar transistor devices includes: providing a substrate; forming a device structure on the substrate, the device structure including: a first collector, a first base electrode, and a first emitter electrode; forming a first interconnect metal structure on the substrate, the first interconnect metal structure being electrically connected to the first collector electrode; forming a second interconnect metal structure on the substrate, the second interconnect metal structure being electrically connected to the first base electrode; and forming a third interconnect metal structure on the substrate, the third interconnect metal structure being electrically connected to the first emitter electrode. The transistor section is bonded to the passive device section, and the plurality of heterojunction bipolar transistor devices correspond to the plurality of passive device regions respectively. The first interconnect metal structure is bonded to the first pad, the second interconnect metal structure is bonded to the second pad, and the third interconnect metal structure is bonded to the third pad.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming the first interconnect metal structure includes: forming a first protrusion located on the substrate; forming a first interconnect metal layer covering the first protrusion, wherein the first interconnect metal layer is connected to the first collector. Forming the second interconnect metal structure includes: forming a second protrusion located on the substrate; forming a second interconnect metal layer covering the second protrusion, wherein the second interconnect metal layer is connected to the first base electrode; Forming the third interconnect metal structure includes: forming a third protrusion located on the substrate; forming a third interconnect metal layer covering the third protrusion, wherein the third interconnect metal layer is connected to the first emitter electrode.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The passive device section further includes: forming a fourth pad and a first trace layer on the passive device area, wherein the fourth pad is used for collector voltage input, and the first trace layer connects the first pad and the fourth pad.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The passive device section further includes forming a fifth pad and a second trace layer on the passive device area, wherein the fifth pad is used for radio frequency signal input and the second trace layer connects the capacitor structure and the fifth pad.
5. The method for fabricating a semiconductor device according to claim 2, characterized in that, The heterojunction bipolar transistor device further includes: forming a fourth interconnect metal structure located on the substrate, wherein the fourth interconnect metal structure is electrically connected to the first base electrode; The passive device section further includes: forming a sixth pad on the passive device area, the sixth pad being used for base DC bias voltage input; The bonding of the transistor portion to the passive device portion further includes bonding the fourth interconnect metal structure to the sixth pad.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, Forming the fourth interconnect metal structure includes: forming a fourth protrusion located on the substrate; forming a fourth interconnect metal layer covering the fourth protrusion, wherein the fourth interconnect metal layer is connected to the first base electrode.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The first protrusion, the second protrusion, the third protrusion, and the fourth protrusion have a first height, and the device structure has a second height, wherein the first height is higher than the second height.
8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The ratio of the first height to the second height ranges from 2:1 to 6:
1.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of the passive device section further includes: forming an interconnect via in the passive device region, penetrating the first wafer, the interconnect via being used for grounding, and the interconnect via being electrically connected to the third interconnect metal structure.
10. The method for fabricating a semiconductor device according to claim 6, characterized in that, The first protrusion, the second protrusion, the third protrusion, and the fourth protrusion are made of poly(p-phenylenebenzodioxazole).
11. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of the passive device section further includes: forming an eighth pad and a ninth pad on the passive device area; The heterojunction bipolar transistor device further includes: forming a second collector, a second base electrode, and a second emitter electrode; forming a fifth interconnect metal structure located on the substrate and electrically connected to the second collector electrode; forming a sixth interconnect metal structure located on the substrate and electrically connected to the second base electrode; wherein the third interconnect metal structure is also electrically connected to the second emitter electrode; The fifth interconnect metal structure is bonded to the eighth pad, and the sixth interconnect metal structure is bonded to the ninth pad.
12. The method for fabricating a semiconductor device according to claim 1, characterized in that, After bonding the transistor portion to the passive device portion, the process includes: removing the second wafer; and dicing the passive device portion to obtain a plurality of the semiconductor devices.
13. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1-12.