A gaussian lightly doped source junctionless tunneling field effect transistor and a single particle irradiation effect simulation optimization method thereof

Abstract

The application discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor, comprising: source region, pocket area, channel region, drain region, polar grid, control grid, source, drain, first dielectric layer, second dielectric layer and third dielectric layer;Source region is connected with source and pocket area, and adopts Gauss light doping InAs material;Pocket area is connected with channel region, and is InAs / GaAsSb heterojunction structure;Channel region is connected with drain region;Drain region is connected with drain;First dielectric layer is located on the two sides of source region;Polar grid is located on the first dielectric layer;Second dielectric layer is located on the two sides of a part of channel region;Third dielectric layer is located on the two sides of another part of channel region;Control grid, including tunneling gate and auxiliary gate.The application further discloses a kind of Gauss light doping source junctionless type tunneling field effect transistor's single particle irradiation effect simulation optimization method, can provide more comprehensive simulation data, and device optimization effect is better.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a Gaussian lightly doped source junctionless tunneling field-effect transistor and its single-particle irradiation effect simulation optimization method. Background Technology

[0002] In nanoscale integrated circuits, leakage current increases exponentially with the continuous shrinking of device feature sizes and the increasing integration density. TFET devices, due to their tunneling mechanism, exhibit low leakage current and good subthreshold characteristics, making them highly suitable for low-power circuit applications. Therefore, early-stage irradiation reliability studies of TFET devices are of great significance.

[0003] Currently, Lili Ding et al. from the University of Padua, Italy, have conducted irradiation studies on Si-based TFETs, using 10-keV X-rays as the irradiation source. Their results show that under irradiation, the oxide trap charge in the gate dielectric changes, leading to alterations in the device's threshold voltage and tunneling voltage. However, this change degrades significantly under high electrical stress conditions; in experiments, the degradation of the device's electrical characteristics could not be observed at Vgs=3.0V. This study also compared Si-based TFETs with FDSOI nMOSFETs, showing that TFET devices exhibit superior radiation resistance compared to FDSOI devices. Avashesh Dubey et al. conducted total iodizing dose (TID) simulation studies on SOI TFETs. Their results indicate that the threshold voltage drift and interface trap charge generated by irradiation are not negligible and have a significant impact on the device's electrical performance.

[0004] The irradiation damage mechanism of TFET devices differs from that of MOSFETs. Therefore, irradiation studies of TFETs are of great guiding significance for the practical application of this type of device. Researchers at Park University and the University of Tehran conducted circuit-level simulations of the single-event irradiation damage mechanism of III-V compound semiconductor TFET devices. However, this simulation method is relatively simple and, due to device structure limitations, yields limited experimental data, resulting in poor optimization performance for TFET devices. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a Gaussian lightly doped source junctionless tunneling field-effect transistor and its single-event irradiation effect simulation optimization method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A first aspect of the present invention provides a Gaussian lightly doped source-free tunneling field-effect transistor, comprising: a source region, a pocket region, a channel region, a drain region, a polarization gate, a control gate, a source electrode, a drain electrode, a first dielectric layer, a second dielectric layer, and a third dielectric layer;

[0007] The source region is connected to the source electrode at one end and to one side of the pocket region at the other end, and is made of Gaussian lightly doped InAs material.

[0008] The pocket region is connected to one end of the channel region on the other side and is an InAs / GaAsSb heterojunction structure.

[0009] The channel region is connected at one end to one end of the drain region, and is made of N-type heavily doped GaAsSb material.

[0010] The other end of the drain region is connected to the drain electrode;

[0011] The first dielectric layer is located on both sides of the source region;

[0012] The polarization gate is located on the first dielectric layer;

[0013] The second dielectric layer is located on both sides of a portion of the channel region, connected to the third dielectric layer, and located between the first dielectric layer and the third dielectric layer;

[0014] The third dielectric layer is located on both sides of another portion of the channel region;

[0015] The control gate includes a tunneling gate and an auxiliary gate;

[0016] The tunneling gate is located on the second dielectric layer, the auxiliary gate is located on the third dielectric layer, and the work function of the tunneling gate is greater than that of the auxiliary gate.

[0017] In one embodiment of the present invention, the doping peak value of the source region is 1×10⁻⁶. 19 cm -3 The voltage at the source is zero.

[0018] In one embodiment of the present invention, the doping concentration of the pocket region is 1×10⁻⁶. 19 cm -3 .

[0019] In one embodiment of the present invention, the doping concentration of the channel region is 1×10⁻⁶. 19 cm -3 .

[0020] In one embodiment of the present invention, the drain region is made of N-type heavily doped GaAsSb material with a doping concentration of 1×10⁻⁶.19 cm -3 The voltage at the drain is 1.0V.

[0021] In one embodiment of the present invention, the first dielectric layer and the second dielectric layer are both made of HfO2, and the third dielectric layer is made of SiO2.

[0022] A second aspect of the present invention provides a simulation optimization method for the single-event irradiation effect of a Gaussian lightly doped source junctionless tunneling field-effect transistor, used to determine various parameters of the field-effect transistor provided in the first aspect of the present invention, including the following steps:

[0023] Step 1: Conduct electrical characteristic simulation experiments on the Gaussian lightly doped source junctionless tunneling field-effect transistor to determine the initial parameter information of the field-effect transistor;

[0024] Step 2: Based on the initial parameter information, set the device bias condition of the field-effect transistor for the single-event irradiation effect simulation experiment to the off state;

[0025] Step 3: Perform transient simulation of single-particle incident from the auxiliary gate based on multiple different LET values, preset incident angle, preset incident completion time, preset drain bias voltage, preset incident depth and the initial parameter information.

[0026] Step 4: Perform transient simulation of single-particle incident based on preset LET values, the initial parameter information, multiple different incident angles, multiple different incident positions, multiple different incident depths, multiple different incident completion times, and multiple different drain bias voltages.

[0027] Step 5: Based on the preset LET value, the preset incident angle, the preset incident completion time, the preset drain bias voltage, multiple different material types of the third dielectric layer, multiple different gate lengths of the tunneling gate, multiple different total thicknesses of the field-effect transistors, and multiple different incident depths, perform transient simulation from the drain incident single particle to determine the target material type of the third dielectric layer, the target gate length of the tunneling gate, and the target total thickness of the field-effect transistor.

[0028] In one embodiment of the present invention, the plurality of different LET values ​​include: 1 MeV.cm 2 / mg, 2MeV.cm 2 / mg, 4 MeV.cm 2 / mg, 6 MeV.cm 2 / mg, 8 MeV.cm 2 / mg and 10 MeV.cm 2 / mg;

[0029] The preset incident angle is 90°, the preset incident completion time is 2ps, the preset drain bias voltage is 0.5V, and the preset incident depth is 5nm.

[0030] In one embodiment of the present invention, the preset LET value is 10 MeV.cm 2 / mg;

[0031] The various incident angles include 0°, 30°, 45°, 60° and 90°;

[0032] The plurality of different incident locations include: the polarization gate, the pocket region, the tunneling gate, the interface between the second dielectric layer and the third dielectric layer, the auxiliary gate, and the drain region;

[0033] The various incident completion times include: 0ps, 2ps, 4ps, 6ps, 8ps, and 10ps;

[0034] The various drain bias voltages include: 0.2V, 0.4V, 0.5V, 0.6V, and 0.8V;

[0035] The material types of the various third dielectric layers include: SiO2, Si3N4, Al2O3, and HfO2;

[0036] The lengths of the various tunneling gates include those increasing from 3 nm to 17 nm in 2 nm increments.

[0037] The total thickness of the plurality of different field-effect transistors includes an increase from 5 nm to 10 nm, in increments of 1 nm.

[0038] The various different incident depths include those increasing from 1 nm to 5 nm in 1 nm increments.

[0039] The beneficial effects of this invention are:

[0040] First, the Gaussian lightly doped source junctionless tunneling field-effect transistor of the present invention has three main structural features: First, an InAs / GaAsSb heterojunction is used between the source and channel regions. This heterojunction can generate an internal polarization electric field caused by the mismatch in the zincblende crystal lattice structure, which can promote electron tunneling between the source and channel regions and increase the conduction current. Second, the source region is lightly doped with Gaussian materials. Lightly doped sources have a certain effect on improving the electrical performance of the device, and the diffusion of impurities can be simulated by using a Gaussian distribution. Third, the tunneling gate (TG) and the auxiliary gate (AG) are made of metal materials with different work functions. By rationally selecting the work functions of the two, the conduction current and turn-off current can be optimized simultaneously, thereby improving the on / off ratio.

[0041] Secondly, the single-event irradiation simulation optimization method for Gaussian lightly doped source junctionless tunneling field-effect transistors (TFETs) of this invention supplements and expands the research content on single-event irradiation effect of TFETs. It can analyze in detail the single-event irradiation effect brought about by different LET values, the variation law of single-event irradiation effect with different incident angles, incident positions, incident completion times, and drain bias voltages, as well as the optimization relationship between single-event irradiation effect and tunneling gate, total device thickness, and incident depth. It can obtain more comprehensive simulation experimental data, and the device optimization effect is better. Therefore, this invention has certain practical guiding significance for the single-event irradiation characteristics and optimization of TFET devices.

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the structure of a Gaussian lightly doped source junctionless tunneling field-effect transistor provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a 90° incident angle for a simulation optimization method of single-particle irradiation effect of a Gaussian lightly doped source junctionless tunneling field-effect transistor provided in an embodiment of the present invention.

[0045] Figure 3 This diagram illustrates multiple different incident positions of a simulation optimization method for the single-particle irradiation effect of a Gaussian lightly doped source junctionless tunneling field-effect transistor, provided as an embodiment of the present invention.

[0046] Explanation of reference numerals in the attached figures:

[0047] 10 - Source; 20 - Source region; 30 - Pocket region; 40 - Channel region; 50 - Drain region; 60 - Drain; 70 - Polarized gate; 81 - Tunneling gate; 82 - Auxiliary gate; 91 - First dielectric layer; 92 - Second dielectric layer; 93 - Third dielectric layer. Detailed Implementation

[0048] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0049] Example 1

[0050] like Figure 1 As shown, a Gaussian lightly doped source-junctionless tunneling field-effect transistor includes: a source 10, a source region 20, a pocket region 30, a channel region 40, a drain region 50, a polarization gate 70, a control gate, a drain 60, a first dielectric layer 91, a second dielectric layer 92, and a third dielectric layer 93.

[0051] One end of the source region 20 is connected to the source electrode 10, and the other end of the source region 20 is connected to one side of the pocket region 30. The source region 20 is made of Gaussian lightly doped InAs material with a doping peak of 1×10⁻⁶. 19 cm -3 The voltage at source 10 is zero.

[0052] The other side of pocket region 30 is connected to one end of channel region 40, and pocket region 30 is an InAs / GaAsSb heterojunction structure; pocket region 30 is uniformly doped with a doping concentration of 1×10⁻⁶. 19 cm -3 .

[0053] The other end of the channel region 40 is connected to one end of the drain region 50, and the channel region 40 is made of uniformly doped N-type heavily doped GaAsSb material with a doping concentration of 1×10⁻⁶. 19 cm -3 .

[0054] The other end of the drain region 50 is connected to the drain electrode 60; the drain region 50 is made of uniformly doped N-type heavily doped GaAsSb material with a doping concentration of 1×10⁻⁶. 19 cm -3 The voltage at the drain 60 is 1.0V.

[0055] The first dielectric layer 91 is located on both sides of the source region 20, and the polarization gate 70 is located on the first dielectric layer 91. The polarization gate 70, located in the source region 20, is made of a metallic material with a high work function, which induces the formation of P... + Source region 20, bias voltage is zero.

[0056] The second dielectric layer 92 is located on both sides of a portion of the channel region 40. The second dielectric layer 92 is connected to the third dielectric layer 93 and is located between the first dielectric layer 91 and the third dielectric layer 93. The third dielectric layer 93 is located on both sides of the other portion of the channel region 40. The channel region 40 uses a heterogeneous dielectric. The second dielectric layer 92 and the third dielectric layer 93 are made of different materials. The first dielectric layer 91 and the second dielectric layer 92 are both made of HfO2, while the third dielectric layer 93 is made of SiO2.

[0057] The control gate is located in channel region 40 and is divided into two parts: the tunneling gate TG and the auxiliary gate AG; the bias voltage VGS = 2V. The tunneling gate 81 is located on the second dielectric layer 92, and the auxiliary gate 82 is located on the third dielectric layer 93. The work function Φ of the tunneling gate 81 is... M1 The work function Φ is greater than that of the auxiliary gate 82. M2 Tunneling gate 81 is located near pocket area 30, and auxiliary gate 82 is located near leak area 50.

[0058] In this embodiment, an InAs / GaAsSb heterojunction is used between the source region 20 and the channel region 40. This heterojunction generates an internal polarization electric field due to the lattice mismatch of the zincblende crystal, which promotes electron tunneling between the source region 20 and the channel region 40. The source region 20 is lightly doped with Gaussian doping. Light doping can improve the electrical performance of the device. In this invention, the source region 20 is still lightly doped, but a Gaussian distribution is used to simulate the possible diffusion of impurities. The control gate is divided into two parts: a tunneling gate 81 and an auxiliary gate 82. These are made of metal materials with different work functions. By rationally selecting the work functions of both, the on-current and off-current can be optimized simultaneously.

[0059] Preferably, the source region 20 has a length of 20 nm, the pocket region 30 has a length of 5 nm, the channel region 40 has a length of 20 nm, the drain region 50 has a length of 20 nm, the tunnel gate 81 and the auxiliary gate 82 have lengths of 3 nm and 17 nm respectively, and the total thickness of the field-effect transistor is 5 nm.

[0060] Example 2

[0061] A simulation optimization method for single-event irradiation effect of a Gaussian lightly doped source junctionless tunneling field-effect transistor, used to determine various parameters of the field-effect transistor in Example 1, includes the following steps:

[0062] Step 1: Conduct an electrical characteristic simulation experiment on the field-effect transistor to determine the initial parameter information of the field-effect transistor.

[0063] Specifically, in Example 1, where device parameters were not yet determined, the source 10 and polarization gate 70 of the field-effect transistor were grounded, the drain 60 was biased to VDS=1.0V, and the tunneling gate 81 and auxiliary gate 82 were shorted and biased to VGS=2.0V. Then, a scan of process and device parameters was performed to clarify the influence of changes in the work function of the polarization gate 70, the tunneling gate 81, the auxiliary gate 82, and the doping concentration on the electrical characteristics, and to determine the optimal initial parameter information. This initial parameter information included the length, thickness, doping concentration, dielectric material, gate work function, current, and voltage of each part of the device.

[0064] Step two: Based on the initial parameter information, the field-effect transistor is set to the off state for the single-event irradiation effect simulation experiment. The single-event effect mainly studies the influence of incident heavy ions on device performance. This influence originates from the transient current caused by non-equilibrium electron-hole pairs generated during incidence. Therefore, the simulation bias condition is selected as the device off state, i.e., Vgs=0V, Vds=0.5V, and the initial parameter information is set.

[0065] Step 3: Based on multiple different LET values, preset incident angles, preset incident completion times, preset drain bias voltages, preset incident depths, and initial parameter information, transient simulations are performed on a single particle incident from the auxiliary gate 82. This allows us to obtain the transient current variation curves of the drain 60 over time, the charge variation curves over time, the electric field variation curves along the cutline direction, and the potential variation curves along the cutline direction, providing data support for the practical application and simulation research of the device.

[0066] Among them, such as Figure 2 As shown, the preset incident angle is set to 90°, the preset incident completion time is 2 ps, the preset drain bias voltage is 0.5 V, and the preset incident depth is 5 nm. LET is selected as 1 MeV.cm. 2 / mg, 2MeV.cm 2 / mg, 4 MeV.cm 2 / mg, 6 MeV.cm 2 / mg, 8 MeV.cm 2 / mg and 10 MeV.cm 2 Transient simulation was performed using / mg. An incident angle of 0° corresponds to the parallel control gate incident angle, and an incident angle of 90° corresponds to the incident angle of the vertical tunneling gate 81. The duration of the transient simulation was 40 ps.

[0067] Step four: Perform transient simulation of single-particle incident events based on preset LET values, initial parameter information, multiple different incident angles, multiple different incident positions, multiple different incident depths, multiple different incident completion times, and multiple different drain bias voltages. Specifically, the simulation bias conditions are selected as device off-state, i.e., Vgs=0V, Vds=0.5V, and a fixed LET of 10 MeV.cm is set. 2 / mg, set initial parameter information, and set the incident angles of 0°, 30°, 45°, 60° and 90° respectively. The incident angle follows... Figure 2 The arrows in the diagram change direction from small to large, respectively setting the incident positions of the polarization gate 70, pocket region 30, tunneling gate 81, second dielectric layer 92 and third dielectric layer 93, auxiliary gate 82 and drain region 50, as shown below. Figure 3The incident positions are selected sequentially to the right of the source 10 shown. The incident depth is increased from 1nm to 5nm in 1nm increments. The incident completion times are set to 0ps, 2ps, 4ps, 6ps, 8ps, and 10ps respectively. The drain bias voltages are set to 0.2V, 0.4V, 0.5V, 0.6V, and 0.8V respectively. The simulation is carried out in an orthogonal experimental manner to observe the output waveform of the single-event irradiation effect. The characteristics of the single-event irradiation effect under different incident angles, different incident positions, different incident completion times, and different drain bias voltages are clarified, providing data support for the practical application of the device and simulation research.

[0068] Step 5: Further optimize the field-effect transistor (FET): Based on preset LET values, preset incident angles, preset incident completion times, preset drain bias voltages, multiple different material types of the third dielectric layer 93, multiple different gate lengths of the tunneling gate 81, multiple different total thicknesses of the FET, and multiple different incident depths, perform transient simulations with a single particle incident from the drain 60 to determine the target material type of the third dielectric layer 93, the target gate length of the tunneling gate 81, and the target total thickness of the FET. Specifically, select the device off state for the simulation bias conditions, i.e., Vgs=0V, Vds=0.5V, and set LET=10 MeV.cm. 2 The parameters are: / mg, incident angle 90°, preset incident completion time 2ps, and preset drain bias voltage 0.5V. In the initial parameter settings, except for the material type of the third dielectric layer 93, the gate length of the tunneling gate 81, and the total thickness of the field-effect transistor, other information is the same as the corresponding settings in steps three and four. SiO2, Si3N4, Al2O3, and HfO2 are set as the material types of the third dielectric layer 93, the gate length of the tunneling gate 81 is increased from 3nm to 17nm in 2nm increments, the total thickness of the field-effect transistor is increased from 5nm to 10nm in 1nm increments, and the incident depth is increased from 1nm to 5nm in 1nm increments. Simulation is performed using an orthogonal experimental method, with the optimization objective being the minimization of pulse current. The transient simulation time is 40ps, resulting in the optimized target material type of the third dielectric layer 93, the target gate length of the tunneling gate 81, and the target total thickness of the field-effect transistor.

[0069] The target gate length of the optimized device is 3nm, the maximum incident depth is the target total thickness, the target total thickness of the field-effect transistor is 5nm, and the target material of the third dielectric layer 93 is SiO2.

[0070] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0071] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0072] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0073] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0074] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0075] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A Gaussian lightly doped source junctionless tunneling field-effect transistor, characterized in that, include: Source region (20), pocket region (30), channel region (40), drain region (50), polarization gate (70), control gate, source (10), drain (60), first dielectric layer (91), second dielectric layer (92) and third dielectric layer (93); The source region (20) is connected to the source electrode (10) at one end and to one side of the pocket region (30) at the other end, and is made of Gaussian lightly doped InAs material. The pocket region (30) is connected to one end of the channel region (40) on the other side, and is an InAs / GaAsSb heterojunction structure; The channel region (40) is connected at one end to one end of the drain region (50) and is made of N-type heavily doped GaAsSb material; The other end of the drain region (50) is connected to the drain electrode (60); The first dielectric layer (91) is located on both sides of the source region (20); The polarization gate (70) is located on the first dielectric layer (91); The second dielectric layer (92) is located on both sides of a portion of the channel region (40), connected to the third dielectric layer (93), and located between the first dielectric layer (91) and the third dielectric layer (93); The third dielectric layer (93) is located on both sides of another part of the channel region (40); The control gate includes a tunneling gate (81) and an auxiliary gate (82); The tunneling gate (81) is located on the second dielectric layer (92), the auxiliary gate (82) is located on the third dielectric layer (93), and the work function of the tunneling gate (81) is greater than that of the auxiliary gate (82).

2. The Gaussian lightly doped source junctionless tunneling field-effect transistor according to claim 1, characterized in that, The doping peak value of the source region (20) is 1×10 19 cm -3 The voltage of the source (10) is zero.

3. The Gaussian lightly doped source junctionless tunneling field-effect transistor according to claim 2, characterized in that, The doping concentration of the pocket region (30) is 1×10⁻⁶. 19 cm -3 .

4. A Gaussian lightly doped source junctionless tunneling field-effect transistor according to claim 2, characterized in that, The doping concentration of the channel region (40) is 1×10⁻⁶. 19 cm -3 .

5. A Gaussian lightly doped source junctionless tunneling field-effect transistor according to claim 1, characterized in that, The drain region (50) is made of N-type heavily doped GaAsSb material with a doping concentration of 1×10⁻⁶. 19 cm -3 The voltage of the drain (60) is 1.0V.

6. A Gaussian lightly doped source junctionless tunneling field-effect transistor according to claim 1, characterized in that, The first dielectric layer (91) and the second dielectric layer (92) are both made of HfO2, and the third dielectric layer (93) is made of SiO2.

7. A simulation and optimization method for single-event irradiation effect of a Gaussian lightly doped source junctionless tunneling field-effect transistor, characterized in that, The method for determining the parameters of the field-effect transistor as described in claim 1 includes the following steps: Step 1: Conduct an electrical characteristic simulation experiment on the field-effect transistor as described in claim 1 to determine the initial parameter information of the field-effect transistor; Step 2: Based on the initial parameter information, set the device bias condition of the field-effect transistor for the single-event irradiation effect simulation experiment to the off state; Step 3: Based on multiple different LET values, preset incident angle, preset incident completion time, preset drain bias voltage, preset incident depth and the initial parameter information, transient simulation is performed on the single particle incident from the auxiliary gate (82). Step 4: Perform transient simulation of single-particle incident based on preset LET values, the initial parameter information, multiple different incident angles, multiple different incident positions, multiple different incident depths, multiple different incident completion times, and multiple different drain bias voltages. Step 5: Based on the preset LET value, the preset incident angle, the preset incident completion time, the preset drain bias voltage, the material types of multiple different third dielectric layers (93), the gate lengths of multiple different tunneling gates (81), the total thicknesses of multiple different field-effect transistors, and multiple different incident depths, a transient simulation is performed to irradiate a single particle from the drain (60) to determine the target material type of the third dielectric layer (93), the target gate length of the tunneling gate (81), and the target total thickness of the field-effect transistor.

8. The single-event irradiation effect simulation optimization method for a Gaussian lightly doped source junctionless tunneling field-effect transistor according to claim 7, characterized in that, The various LET values ​​include: 1 MeV.cm 2 / mg, 2MeV.cm 2 / mg, 4MeV.cm 2 / mg, 6MeV.cm 2 / mg, 8MeV.cm 2 / mg and 10MeV.cm 2 / mg; The preset incident angle is 90°, the preset incident completion time is 2ps, the preset drain bias voltage is 0.5V, and the preset incident depth is 5nm.

9. The single-event irradiation effect simulation and optimization method for a Gaussian lightly doped source junctionless tunneling field-effect transistor according to claim 7, characterized in that, The preset LET value is 10 MeV.cm 2 / mg; The various incident angles include 0°, 30°, 45°, 60° and 90°; The multiple different incident locations include: the polarization gate (70), the pocket region (30), the tunneling gate (81), the interface between the second dielectric layer (92) and the third dielectric layer (93), the auxiliary gate (82), and the drain region (50); The various incident completion times include: 0ps, 2ps, 4ps, 6ps, 8ps, and 10ps; The various drain bias voltages include: 0.2V, 0.4V, 0.5V, 0.6V, and 0.8V; The material types of the various third dielectric layers (93) include: SiO2, Si3N4, Al2O3 and HfO2; The gate lengths of the plurality of different tunneling gates (81) include: increasing from 3 nm to 17 nm in 2 nm increments; The total thickness of the plurality of different field-effect transistors includes an increase from 5 nm to 10 nm, in increments of 1 nm. The various different incident depths include those increasing from 1 nm to 5 nm in 1 nm increments.

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