Semiconductor device and manufacturing method thereof
By forming an electron trapping layer between the inner liner and the capacitor dielectric layer, interface electrons are trapped, solving the imprinting effect problem caused by the built-in electric field in ferroelectric memory and improving the reliability and storage performance of the device.
Patent Information
- Application Number
- CN202411643691.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2026-05-15
AI Technical Summary
In ferroelectric memories, the built-in electric field formed by the movement of electrons at the interface causes a coercive field shift, resulting in an imprinting effect that affects device reliability and storage performance.
An electron trapping layer is formed between the inner liner and the capacitor dielectric layer. The first and second electron trapping layers are formed by implanting metal ions to trap interface electrons to eliminate the built-in electric field and reduce the imprinting effect.
It significantly reduces the imprinting effect, improves the reliability and storage performance of semiconductor devices, and enhances storage performance.
Smart Images
Figure CN122054594A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method. Background Technology
[0002] Ferroelectric random access memory (FRAM) is a novel type of memory that combines the easy-to-write characteristics of DRAM and SRAM with the non-volatility of Flash and EEPROM. It can retain data without requiring a refresh circuit. In related technologies, because ferroelectric memory capacitors contain a large number of oxygen vacancies, when a working voltage is applied to the upper or lower plates of the ferroelectric capacitor, the zero-valent oxygen vacancies V at the dielectric interface... O It will undergo electron removal to become a positive divalent oxygen vacancy V. O 2+ (V O -2e - →V O 2+ The electrons that are removed become interface electrons. The movement of these interface electrons creates a built-in electric field at the interface, causing a significant shift in the coercive field of the ferroelectric dielectric along the voltage axis. As a result, some of the iron domains in the ferroelectric dielectric cannot flip, and the residual polarization intensity is greatly reduced, leading to a severe imprinting effect that affects the reliability of the ferroelectric memory. Summary of the Invention
[0003] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0004] One aspect of this application provides a method for manufacturing a semiconductor device, comprising: forming a first electrode layer; forming a first liner layer on the first electrode layer; forming a capacitor dielectric layer on the first liner layer; forming a second liner layer on the capacitor dielectric layer; forming a second electrode layer on the second liner layer; wherein a first electron trapping layer is formed in a top region of the first liner layer for trapping interface electrons at the interface between the first liner layer and the capacitor dielectric layer, and / or a second electron trapping layer is formed in a bottom region of the second liner layer for trapping interface electrons at the interface between the second liner layer and the capacitor dielectric layer.
[0005] For example, after forming the first liner layer and before forming the capacitor dielectric layer, metal ions are implanted into the first liner layer to form a first electron trapping layer in the top region of the first liner layer; and / or after forming the second liner layer and before forming the second electrode layer, metal ions are implanted into the second liner layer to form a second electron trapping layer in the bottom region of the second liner layer.
[0006] For example, the first electrode layer, the first inner liner layer, the second inner liner layer, and the second electrode layer comprise titanium nitride.
[0007] For example, the first electrode layer and the second electrode layer are formed using a physical vapor deposition process.
[0008] For example, the first liner layer and the second liner layer are formed using an atomic layer deposition process.
[0009] For example, an annealing process is further performed after the metal ion implantation to form the first electron trapping layer and / or the second electron trapping layer.
[0010] For example, the metal ions include at least one selected from titanium ions, aluminum ions, magnesium ions, zinc ions, niobium ions, lanthanum ions, neodymium ions, and cerium ions.
[0011] For example, the capacitor dielectric layer comprises a ferroelectric material.
[0012] For example, the ferroelectric material includes Hf 1-x Zr x O2.
[0013] Another aspect of this application provides a semiconductor device prepared using the semiconductor device manufacturing method described above.
[0014] According to the semiconductor device and manufacturing method provided in this application, by using an electron trapping layer between the liner layer and the capacitor dielectric layer, the interface electrons formed at the interface between the liner layer and the capacitor dielectric layer are eliminated, thereby reducing the imprinting effect of the semiconductor device, improving the reliability of the semiconductor device, and improving the storage performance of the semiconductor device. Attached Figure Description
[0015] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0016] In the attached image:
[0017] Figure 1 A schematic diagram of the hysteresis loop of hafnium oxide doped with it;
[0018] Figure 2 For related technologies Hf 1-x Zr x A schematic diagram showing the polarization versus voltage curves of an O2-based ferroelectric capacitor structure.
[0019] Figure 3 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application;
[0020] Figure 4A-4L A schematic cross-sectional view of a semiconductor device manufacturing method according to an illustrative embodiment of this application is shown, showing the device obtained by sequentially implementing the manufacturing method of the semiconductor device.
[0021] Figure 5 This is a schematic diagram showing the polarization versus voltage curve of a capacitor according to an embodiment of this application.
[0022] Figure 6 A circuit netlist diagram of a 1T1C cell structure according to an illustrative embodiment of this application is shown. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this application more apparent, exemplary embodiments according to this application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein. Based on the embodiments of this application described herein, all other embodiments obtained by those skilled in the art without inventive effort should fall within the protection scope of this application.
[0024] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.
[0025] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art.
[0026] To fully understand this application, a detailed structure will be presented in the following description to illustrate the technical solution proposed in this application. Optional embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0027] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0028] Ferroelectric memory is a novel type of memory that combines the non-volatility of ROM with the non-volatility of RAM, offering advantages such as high durability, high-speed read / write speeds, and low power consumption. The core component of ferroelectric memory is the ferroelectric capacitor, which typically employs a metal-insulator-metal (MIM) structure. The top and bottom metal layers serve as capacitor electrodes, with a ferroelectric thin film material in between. New materials, such as zirconium-doped hafnium oxide, exhibit ferroelectric effects. Figure 1 As shown, under the action of the external electric field of the upper and lower electrodes of the dielectric, the iron domains of the hafnium oxide material exhibit different polarization states with different directions of electric field. At the same time, the dielectric of the capacitor changes with the change of polarization state. Thus, the amount and polarity of the stored charge in the capacitor change with the polarization direction and magnitude of the capacitor. Furthermore, since the polarization intensity of the material can still be maintained when the external electric field is removed, the capacitor has a non-volatile charge storage capability, realizing data storage.
[0029] The imprinting effect of ferroelectric capacitance affects Hf 1-x Zr x The most important factor for the reliability of O2-based ferroelectric memory is when Hf 1- x Zr x After an O2-based ferroelectric capacitor develops an imprinting effect, the iron domains cannot flip and remain in the same state, ultimately preventing the writing of new data and causing the writing of "0" or "1" to fail. For example... Figure 2 As shown, the main manifestation is a decrease in the remanent polarization intensity 2Pr, and a shift in the coercive field (+Ec and -Ec) along the positive direction of the voltage axis. Because there are a large number of oxygen vacancies at the interfaces between the ferroelectric thin film material and the upper and lower plates of the ferroelectric memory, when a working voltage is applied to the upper or lower plates of the ferroelectric capacitor, the zero-valent oxygen vacancies V at the ferroelectric thin film material... O It will undergo electron removal to become a positive divalent oxygen vacancy V. O 2+ (V O -2e - →V O 2+ The electrons that are removed become interface electrons. The movement of these interface electrons creates a built-in electric field at the interface, causing a significant shift in the coercive field of the ferroelectric dielectric along the voltage axis. As a result, some of the iron domains in the ferroelectric dielectric cannot flip, and the residual polarization intensity is greatly reduced, leading to a severe imprinting effect that affects the reliability of the ferroelectric memory.
[0030] To improve the reliability of semiconductor devices, this application provides a method for manufacturing semiconductor devices, such as... Figure 3 As shown, the method for manufacturing a semiconductor device includes:
[0031] Step S110: Form the first electrode layer;
[0032] Step S120: Form a first inner liner layer on the first electrode layer;
[0033] Step S130: Form a capacitor dielectric layer on the first inner liner layer;
[0034] Step S140: Form a second inner liner layer on the capacitor dielectric layer;
[0035] Step S150: Form a second electrode layer on the second inner liner layer;
[0036] A first electron trapping layer is formed in the top region of the first inner liner to trap interface electrons at the interface between the first inner liner and the capacitor dielectric layer, and / or a second electron trapping layer is formed in the bottom region of the second inner liner to trap interface electrons at the interface between the second inner liner and the capacitor dielectric layer.
[0037] The semiconductor device manufacturing method provided in this application can eliminate interface electrons formed at the interface between the liner layer and the capacitor dielectric layer by forming an electron trapping layer between the liner layer and the capacitor dielectric layer, which greatly reduces the imprinting effect of the semiconductor device, improves the reliability of the semiconductor device, and improves the storage performance of the semiconductor device.
[0038] Example 1
[0039] Below, for reference Figures 4A to 4L The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figures 4A to 4L A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an embodiment of this application is shown.
[0040] The semiconductor device described above can be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of this application is explained and illustrated mainly by taking the case of a ferroelectric memory as the semiconductor device.
[0041] For example, the method for manufacturing the semiconductor device of this application includes the following steps:
[0042] First, a substrate 200 is provided, on which a transistor 201 is formed. This yields... Figure 4A The structure shown.
[0043] As an example, transistor 201 may be a selector switch transistor.
[0044] Exemplarily, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can also be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate. The substrate 200 also includes a shallow trench isolation structure (not shown).
[0045] For example, forming a transistor 201 on a substrate 200 may include the following steps:
[0046] A gate dielectric layer (not shown) is formed on the upper surface of the substrate 200. Specifically, the gate dielectric layer can be formed by thermal oxidation, physical vapor deposition or chemical vapor deposition, etc. The gate dielectric layer includes, but is not limited to, a silicon oxide layer.
[0047] A gate material layer is formed on the upper surface of the gate dielectric layer. Specifically, the gate material layer can be formed by physical vapor deposition or chemical vapor deposition. The gate material layer includes, but is not limited to, a doped polysilicon layer or a metal layer.
[0048] The gate material layer and the gate dielectric layer are etched to form the gate 2011; sidewalls can also be formed on both sides of the gate 2011. Specifically, physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes can be used to form the sidewalls, which include, but are not limited to, silicon oxide layers, silicon nitride layers, or ONO structures (i.e., stacked structures of silicon oxide layers, silicon nitride layers, and silicon oxide layers); the gate 2011 is subsequently used as a word line (WL).
[0049] Ion implantation is performed on the substrate 200 based on the gate 2011 and the sidewalls to form the source 2012 and the drain 2013 on both sides of the gate 2011, respectively.
[0050] In one example, after forming the source 2012 and drain 2013, a step of forming metal silicide on the upper surfaces of the source 2012 and drain 2013 may also be included. By forming metal silicide on the upper surfaces of the source 2012 and drain 2013, the contact resistance between the source 2012 and drain 2013 and the conductive plugs from which they are led out can be reduced.
[0051] Next, as follows Figure 4BAs shown, a dielectric layer 202 is formed covering the transistor 201.
[0052] Exemplarily, the dielectric layer 202 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the dielectric layer 202 can be an insulating material such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride; this application is not limited in this regard. Exemplarily, after forming the dielectric layer 202, the method further includes planarizing the dielectric layer 202. Exemplarily, non-limiting examples of this planarization method include mechanical planarization or chemical mechanical polishing planarization. Exemplarily, before planarization, the thickness of the dielectric layer 202 ranges from 6000 Å to 7000 Å; after planarization, the thickness of the dielectric layer 202 ranges from 3000 Å to 3500 Å.
[0053] Then as Figure 4C As shown, a conductive plug communicating with the drain 2013 can be formed in the dielectric layer 202. For example, the dielectric layer 202 is etched to form a first interconnect via penetrating the dielectric layer 202. Specifically, the first interconnect via is formed using a dry etching process or the like. The first interconnect via is filled to form a first conductive plug 203. Specifically, the first conductive plug 203 is formed using an electroplating process or the like. The material of the first conductive plug 203 includes, but is not limited to, tungsten or copper. This allows the bottom of the first conductive plug 203 to be electrically connected to the drain 2013 of the transistor 201 (or the metal silicide on the surface of the drain 2013).
[0054] Next, proceed to step S110, as follows: Figure 4D As shown, a first electrode layer 2041 is formed on the dielectric layer 202.
[0055] For example, the thickness of the first electrode layer 2041 ranges from 20 to 30 nm. The material of the first electrode layer 2041 includes titanium nitride.
[0056] For example, the first electrode layer 2041 can be formed using various deposition methods commonly used in the art, such as physical vapor deposition (PVD).
[0057] Next, proceed to step S120, as follows: Figure 4D As shown, a first inner liner layer 2042 is formed on the first electrode layer 2041.
[0058] For example, the thickness of the first inner liner 2042 ranges from 1 to 2 nm. The material of the first inner liner 2042 includes titanium nitride.
[0059] For example, the first liner 2042 can be formed using various deposition methods commonly used in the art, such as atomic layer deposition (ALD).
[0060] Next, as Figure 4E As shown, metal ions are implanted into the first inner liner 2042 to form a first electron trapping layer 2043 in the top region of the first inner liner 2042.
[0061] For example, after the metal ions are implanted, an annealing process is also performed to promote the uniform distribution of the implanted metal ions to form a first electron trapping layer 2043.
[0062] For example, the metal ions include at least one of titanium ions, aluminum ions, magnesium ions, zinc ions, niobium ions, lanthanum ions, neodymium ions, and cerium ions.
[0063] As an example, for a first inner liner 2042 with a thickness ranging from 1 to 2 nm, step S130 specifically includes: vertically implanting metal ions into the first inner liner 2042, wherein the metal ion implantation energy is 25 to 50 keV and the metal ion implantation dose is 4 to 6 × 10⁻⁶. 10 cm -2 The first electron trapping layer 2043 is formed by high-temperature treatment using a rapid thermal processing technology.
[0064] It should be noted that, since the injection energy is 25 to 50 keV, metal ions will not pass through the first inner liner 2042 to reach the lower surface of the first inner liner 2042.
[0065] Preferably, metal ions can be injected using a medium-current injector, and the metal ions can be, but are not limited to, Ti. 4+ Al 3 + Mg 2+ Zn 5+ 、Nb 5+ La 3+ 、Nd 3+ Ce 4+ One or more of the following. The high-temperature treatment temperature is 600℃~700℃, and the treatment time is 10S~30S.
[0066] Next, step S130 is performed to form a capacitor dielectric layer on the first inner liner layer. Since a first trapping layer has already been formed in the top region of the first inner liner layer, forming a capacitor dielectric layer on the first inner liner layer is as follows: Figure 4F As shown, a capacitor dielectric layer 2044 is formed on the first electron trapping layer.
[0067] Exemplarily, the capacitor dielectric layer 2044 comprises a ferroelectric material. Specifically, the capacitor dielectric layer 2044 comprises zirconium-doped hafnium oxide (HZO, Hf). 1-x Zr x Hafnium oxide (HfO) is an extension of hafnium oxide (HfO)-based ferroelectric materials and is a novel type of ferroelectric material. Compared to traditional ferroelectric materials, the components of HfO... 1-x Zr x Hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) have been used as gate oxides in MOSFETs (Metal-O-Semiconductor Field-Effect Transistors) and DRAMs (Dynamic Random Access Memory). Therefore, HZO ferroelectric materials are well-compatible with CMOS (Complementary Metal-O-Semiconductor) processes and exhibit strong ferroelectricity even at ultra-thin thicknesses of around 10 nm, demonstrating excellent scalability. Furthermore, based on ultra-thin thicknesses, HfO2... 1-x Zr x O2 also exhibits significant advantages in ferroelectricity and erase / write speed. For example, the thickness of the capacitor dielectric layer 2044 ranges from 8 to 10 nm, such as 8 nm, 9 nm, 10 nm, etc., wherein the doping ratio of zirconium, hafnium, and oxygen is 0.4:0.4:1 to 0.6:0.6:2, more specifically, the doping ratio of zirconium, hafnium, and oxygen is 0.4:0.4:1, 0.5:0.5:2, or 0.6:0.6:2.
[0068] For example, various deposition methods commonly used in the art can be used to sequentially form the capacitor dielectric layer 2044, such as atomic layer deposition (ALD) to form the capacitor dielectric layer 2044.
[0069] It should be noted that when the zero-valent oxygen vacancy V at the interface between the capacitor dielectric layer 2044 and the first inner liner layer 2042... O The oxygen vacancy V undergoes electron removal to become positive divalent. O 2+ The interface electrons formed during the process will interact with the injected metal ions M n+ Combined into M (n-1)+ (M n+ +e - →M (n-1)+ This eliminates the built-in electric field formed by the movement of interface electrons at the interface, thus avoiding the imprinting effect.
[0070] Next, as Figure 4F As shown, a second inner liner layer 2046 is formed on the first electron trapping layer.
[0071] For example, the thickness of the second inner liner 2046 is in the range of 1 to 2 nm, and the material of the second inner liner 2046 includes titanium nitride.
[0072] For example, the second liner 2046 can be formed using various deposition methods commonly used in the art, such as atomic layer deposition (ALD).
[0073] Next, as Figure 4G As shown, metal ions are implanted into the second inner liner 2046 to form a second electron trapping layer 2045 in the bottom region of the second inner liner 2046.
[0074] For example, after the metal ions are implanted, an annealing process is also performed to promote the uniform distribution of the implanted metal ions to form a second electron trapping layer 2045.
[0075] For example, the metal ions include at least one of titanium ions, aluminum ions, magnesium ions, zinc ions, niobium ions, lanthanum ions, neodymium ions, and cerium ions.
[0076] For example, for a second inner liner 2046 with a thickness ranging from 1 to 2 nm, step S160 specifically includes: vertically implanting metal ions into the second inner liner 2046, wherein the metal ion implantation energy is 130 to 150 keV and the metal ion implantation dose is 4 to 6 * 10⁻⁶. 9 cm -2 A rapid thermal processing technique is used to perform high-temperature treatment to form the second electron trapping layer 2045.
[0077] It should be noted that, since the injection energy is 130-150 keV, it can ensure that the injected metal ions pass through the upper region of the second inner liner 2046 and reach the vicinity of the interface between the second inner liner 2046 and the capacitor dielectric layer 2044, thereby forming the second electron trapping layer 2045 in the bottom region of the second inner liner.
[0078] Preferably, metal ions can be vertically injected using a high-current injector. The metal ions can be, but are not limited to, Ti. 4 + Al 3+ Mg 2+ Zn 5+ 、Nb 5+ La 3+ 、Nd 3+ Ce 4+ One or more of the following. The high-temperature treatment temperature is 600℃~700℃, and the treatment time is 10S~30S.
[0079] For example, the metal ions in the first electron trapping layer and the metal ions in the second electron trapping layer may be the same or different, and can be set as needed.
[0080] Next, proceed to step S170, as follows: Figure 4H As shown, a second electrode layer 2047 is formed on the second inner liner layer 2046.
[0081] For example, the thickness of the second electrode layer 2047 is in the range of 20 to 30 nm, and the material of the second electrode layer 2047 includes titanium nitride.
[0082] For example, the first electrode layer 2041 and the first inner liner layer 2042 can be formed sequentially using various deposition methods commonly used in the art, such as physical vapor deposition (PVD) to form the second electrode layer 2047.
[0083] Specifically, the first electrode layer 2041, the first inner liner layer 2042, the first electron trapping layer 2043, the capacitor dielectric layer 2044, the second electron trapping layer 2045, the second inner liner layer 2046, and the second electrode layer 2047 are patterned to form a capacitor 204 electrically connected to the transistor 201 via the first conductive plug 203. For example... Figure 5 As shown, the coercive field of capacitor 204 in this application has a smaller offset along the voltage axis, and the residual polarization intensity 2Pr decreases less, greatly reducing the imprinting effect. High-temperature reliability testing was performed on 239 dies. In related technologies, the number of dies passing the high-temperature reliability test for semiconductor devices is 99, while the number of dies passing the high-temperature reliability test for the semiconductor device formed in this application embodiment is 226. Therefore, the high-temperature reliability yield of the semiconductor device formed in this application embodiment is higher than that of semiconductor devices in related technologies.
[0084] Then as Figure 4I As shown, an isolation layer 205 covering the dielectric layer 202 and the capacitor 204 can be formed on the dielectric layer 202 and the capacitor 204.
[0085] For example, the isolation layer 205 may be made of silicon nitride to prevent subsequent processes from causing physical damage or chemical corrosion to the dielectric layer 202 and the capacitor 204, thereby ensuring the reliability of the semiconductor device.
[0086] Then as Figure 4J As shown, a first intermetallic insulating layer 206 covering the isolation layer 205 can be formed on the isolation layer 205.
[0087] For example, an intermetallic insulating layer 206 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
[0088] Then as Figure 4KAs shown, a conductive plug communicating with the capacitor 204 can be formed in the first intermetallic insulating layer 206. Exemplarily, the first intermetallic insulating layer 206 is etched and the isolation layer 205 is etched to form a second interconnecting via penetrating the first intermetallic insulating layer 206 and the isolation layer 205. Specifically, the second interconnecting via is formed using a dry etching process or the like. The second interconnecting via is filled to form a second conductive plug 207. Specifically, the second conductive plug 207 is formed using an electroplating process or the like. The material of the second conductive plug 207 includes, but is not limited to, tungsten or copper. This allows the bottom of the second conductive plug 207 to be electrically connected to the second electrode layer 2047 of the capacitor 204. A third conductive plug 208 can be formed penetrating the first intermetallic insulating layer 206, the isolation layer 205, and the dielectric layer 202. The specific method for forming the third conductive plug 208 is the same as that for the second conductive plug 207, and will not be described again here.
[0089] Then as Figure 4L As shown, a plate line (PL) 209 can be formed above the second conductive plug 207, a first conductive layer 210 can be formed above the third conductive plug 208, a second intermetallic insulating layer 211 can be formed covering the first intermetallic insulating layer 206, the plate line 209 and the first conductive layer 210, a fourth conductive plug 212 connected to the first conductive layer 210 can be formed in the second intermetallic insulating layer 211, and a bit line (BL) 213 connected to the fourth conductive plug 212 can be formed above the second intermetallic insulating layer 211.
[0090] In one example, transistor 201 and ferroelectric capacitor can jointly form a 1T1C (1 Transistor-1 Capacitor) cell structure, wherein the polysilicon gate layer in the gate 2011 of transistor 201 serves as the WL. The circuit netlist diagram of this 1T1C cell structure is shown below. Figure 6 As shown. For example, by controlling WL to select the ferroelectric capacitor, BL and PL apply positive and negative voltages to the ferroelectric capacitor respectively. Since the intermediate capacitor dielectric layer 2044 has ferroelectric properties, it forms different iron domains (polarizations) under positive and negative electric fields. These iron domains will not disappear when the external electric field is removed, thereby enabling the ferroelectric capacitor to store different charges and realize the storage function.
[0091] This concludes the introduction of the key steps in the manufacturing method of the semiconductor device of the present invention. For complete device manufacturing, multiple other processes may be required, which will not be elaborated here.
[0092] It is worth mentioning that the order of the above steps is only for example. Without conflict, the order of the above steps can be changed or performed alternately.
[0093] Example 2
[0094] This application also provides a semiconductor device, which is prepared using the semiconductor device manufacturing method described above.
[0095] Example 3
[0096] This application also provides an electronic device, including the semiconductor device as described above or a semiconductor device obtained by the manufacturing method of the semiconductor device described above.
[0097] The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or it can be an intermediate product with the above-mentioned semiconductor devices, such as a mobile phone motherboard with the integrated circuit.
[0098] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.
[0099] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0100] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.
[0101] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0102] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.
[0103] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0104] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.
[0105] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules according to the embodiments of this application. This application can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.
[0106] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.
[0107] The above description is merely a specific embodiment or illustration of the embodiments of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. The scope of protection of this application shall be determined by the scope of the claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Form the first electrode layer; A first inner liner layer is formed on the first electrode layer; A capacitor dielectric layer is formed on the first inner liner layer; A second inner liner layer is formed on the capacitor dielectric layer; A second electrode layer is formed on the second inner liner layer; Wherein, a first electron trapping layer is formed in the top region of the first inner liner layer to trap interface electrons at the interface between the first inner liner layer and the capacitor dielectric layer, and / or, a second electron trapping layer is formed in the bottom region of the second inner liner layer to trap interface electrons at the interface between the second inner liner layer and the capacitor dielectric layer.
2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After the formation of the first liner layer and before the formation of the capacitor dielectric layer, metal ions are implanted into the first liner layer to form a first electron trapping layer in the top region of the first liner layer; and / or, after the formation of the second liner layer and before the formation of the second electrode layer, metal ions are implanted into the second liner layer to form a second electron trapping layer in the bottom region of the second liner layer.
3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, The metal ions include at least one of titanium ions, aluminum ions, magnesium ions, zinc ions, niobium ions, lanthanum ions, neodymium ions, and cerium ions.
4. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, The process includes annealing after metal ion implantation to form the first electron trapping layer and / or the second electron trapping layer.
5. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The first electrode layer, the first inner liner layer, the second inner liner layer, and the second electrode layer comprise titanium nitride.
6. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The first electrode layer and the second electrode layer are formed using a physical vapor deposition process.
7. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The first inner liner layer and the second inner liner layer are formed using an atomic layer deposition process.
8. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The capacitor dielectric layer comprises a ferroelectric material.
9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The ferroelectric material includes Hf 1- x Zr x O2.
10. A semiconductor device, characterized in that, It is prepared by the manufacturing method of any one of claims 1-9.