Method of forming semiconductor device

Abstract

The method includes forming a first multilayer stack and a second multilayer stack. The first multilayer stack includes a first plurality of sacrificial layers and a first plurality of semiconductor nanostructures disposed alternately. The second multilayer stack includes a second plurality of sacrificial layers and a second plurality of semiconductor nanostructures disposed alternately. The first plurality of sacrificial layers and the second plurality of sacrificial layers are replaced with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively. The third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes. The method further includes removing the third plurality of sacrificial layers to form a first recess; forming a first gate stack in the first recess; removing the fourth plurality of sacrificial layers to form a second groove; and forming a second gate stack in the second recess. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest component, which allows more components to be integrated into a given area. However, as the size of the smallest component decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first multilayer stack, including: a first plurality of sacrificial layers; and a first plurality of semiconductor nanostructures, wherein the first plurality of sacrificial layers and the first plurality of semiconductor nanostructures are alternately disposed; forming a second multilayer stack, including: a second plurality of sacrificial layers; and a second plurality of semiconductor nanostructures, wherein the second plurality of sacrificial layers and the second plurality of semiconductor nanostructures are alternately disposed; replacing the first plurality of sacrificial layers and the second plurality of sacrificial layers with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively, wherein the third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes; removing the third plurality of sacrificial layers to form a first trench; forming a first gate stack in the first trench; removing the fourth plurality of sacrificial layers to form a second trench; and forming a second gate stack in the second trench.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first plurality of sacrificial layers between a first plurality of semiconductor nanostructures in a first forming process; forming a second plurality of sacrificial layers between a second plurality of semiconductor nanostructures in a second forming process, wherein the first forming process and the second forming process are separate processes; forming a first source / drain region on opposite sides of the first plurality of semiconductor nanostructures; forming a second source / drain region on opposite sides of the second plurality of semiconductor nanostructures; removing the first plurality of sacrificial layers and the second plurality of sacrificial layers in the same etching process to form a first groove and a second groove, respectively, wherein the first plurality of sacrificial layers comprises a material different from the second plurality of sacrificial layers; forming a first gate stack filling the first groove; and forming a second gate stack filling the second groove.

[0006] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first transistor, including: forming a first semiconductor nanostructure over a semiconductor substrate, wherein the first semiconductor nanostructure has a first internal stress; forming a first source region and a first drain region connected to the first semiconductor nanostructure on opposite sides of the first semiconductor nanostructure, wherein the first source region and the first drain region have a second internal stress less than the first internal stress; and forming a first gate stack, wherein the first gate stack includes a first portion, and wherein, in a first cross-section of the first semiconductor nanostructure, the first portion of the first gate stack completely surrounds the first semiconductor nanostructure, and wherein, the first portion of the first gate stack has a third internal stress less than the first internal stress. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figures 1 to 4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B and Figures 9 to 22 A cross-sectional view is shown of an intermediate stage in the formation of a die stack according to some embodiments.

[0009] Figure 23The differences in the dimensions of the internal spacers according to some embodiments are shown.

[0010] Figure 24 The differences in the shape of the internal spacers according to some embodiments are shown.

[0011] Figure 25 A process flow for forming nanostructured transistors according to some embodiments is shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] A gate-all-around (GAA) transistor (also known as a nanostructure transistor) and a method for fabricating the same are provided. According to some embodiments, a sacrificial layer is formed between semiconductor nanostructures to apply desired stress to the semiconductor nanostructures, which form the channel of the GAA transistor. According to some embodiments, the sacrificial layer in the formation of an n-type GAA transistor is formed to apply tensile stress to the respective semiconductor nanostructure. The stress is memorized by the nanostructures during and after the formation of the source / drain regions. The sacrificial layer is then removed to form a replacement gate stack.

[0015] The embodiments discussed herein are intended to provide examples of how the subject matter of the embodiments of this disclosure can be made or used, and modifications that can be made while remaining within the scope of consideration of the different embodiments will be readily understood by those skilled in the art. Throughout the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. While method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0016] Figures 1 to 22 A cross-sectional view of an intermediate stage in the formation of a GAA transistor according to some embodiments of the present disclosure is shown. The corresponding process is also schematically reflected in... Figure 25 The process flow shown is as follows.

[0017] refer to Figure 1 A perspective view of wafer 10 is shown. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, etc., while other substrates and / or structures may be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, etc. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0018] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are shown as follows: Figure 25 Process 202 in the process flow 200 shown. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0019] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes a semiconductor, such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. The deposition of the first layer 22A (e.g., SiGe) can be achieved through epitaxial growth, and the corresponding deposition methods can be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed in approximately... Peace Treaty The first thickness is within the range between [specific thicknesses]. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0020] According to some embodiments, the second material of the second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these materials, etc., wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is formed of silicon-germanium, the second layer 22B may be formed of silicon, or vice versa.

[0021] According to some embodiments, first layers 22A have the same or similar thicknesses, and second layers 22B have the same or similar thicknesses. First layers 22A may also have the same thickness as or a different thickness than the second layers 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is optionally referred to throughout as sacrificial layer 22A. According to an alternative embodiment, the second layer 22B is sacrificed and removed in a subsequent process.

[0022] According to some embodiments, some pad oxide layers and hard mask layers (not shown) may be formed on top of the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0023] refer to Figure 2 In the etching process, portions of the multilayer stack 22 and the underlying substrate 20 are patterned to form trenches 23. The corresponding process is shown as follows: Figure 25 Process 204 in the process flow 200 shown. Trench 23 extends into substrate 20. The remainder of the multilayer stack is hereinafter referred to as multilayer stack 22'. The lower multilayer stack 22', a portion of substrate 20, is retained and is hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. Semiconductor layer 22A is optionally referred to as a sacrificial layer, and semiconductor layer 22B is hereinafter optionally referred to as a nanostructure. A portion of multilayer stack 22' and the lower substrate strip 20' are collectively referred to as semiconductor strip 24.

[0024] In the embodiments shown above, the GAA transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0025] Figure 3 The formation of isolation region 26 is shown throughout the description; isolation region 26 is also referred to as a shallow trench isolation (STI) region. The corresponding process is shown as follows. Figure 25 Process 206 in the process flow 200 shown. STI region 26 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20, or may be deposited. The pad oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, etc. STI region 26 may also include a dielectric material above the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, may then be performed to flush the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes STI region 26.

[0026] Then, the STI region 26 is recessed such that the top portion of the semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of the STI region 26 to form a protruding fin 28. The protruding fin 28 includes the top portions of the multilayer stack 22' and the substrate strip 20'. Recessing the STI region 26 can be implemented by a dry etching process, wherein NF3 and NH3 are used, for example, as etching gases. Plasma can be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the STI region 26 is recessed by a wet etching process. For example, the etching chemicals may include HF.

[0027] refer to Figure 4 A dummy gate stack 30 and a gate spacer 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is shown as follows. Figure 25 Process 208 in the process flow 200 shown. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 above the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer or by depositing a dielectric layer such as a silicon oxide layer. The dummy gate electrode 34 may be formed, for example, using polycrystalline silicon or amorphous silicon, and may also use other materials such as amorphous carbon.

[0028] Each of the dummy gate stack 30 may also include one (or more) hard mask layers 36 above the dummy gate electrode 34. The hard mask layers 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon carbonitride oxycarbonate, or multiple layers thereof. The dummy gate stack 30 may span over one or more protruding fins 28 and the STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 28. The formation of the dummy gate stack 30 includes: forming a dummy gate dielectric layer; depositing a dummy gate electrode layer over the dummy gate dielectric layer; depositing one or more hard mask layers; and then patterning the formed layers by a patterning process.

[0029] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacer 38 is formed of a dielectric material, such as silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacer 38 may include: depositing one or more dielectric layers; and then performing an anisotropic etching process on the dielectric layers. The remaining portion of the dielectric layers constitutes the gate spacer 38.

[0030] Figure 5A and Figure 5B It shows Figure 4 The cross-sectional view of the structure shown is shown. Figure 5A It shows Figure 4 Reference section AA is shown, which cuts through the portion of the protruding fin 28 not covered by the gate stack 30 and the gate spacer 38, and is perpendicular to the gate length direction. Fin spacer 39 is also shown, located on the sidewall of the protruding fin 28. Figure 5B It shows Figure 4 The reference section BB is parallel to the longitudinal direction of the protruding fin 28.

[0031] refer to Figure 6A and Figure 6B The portion of the protruding fin 28 that is not directly located below the dummy gate stack 30 and the gate spacer 38 is recessed through an etching process to form a groove 42. The corresponding process is shown as follows. Figure 25 Process 210 in the process flow 200 shown. For example, a dry etching process can be performed using a mixture of C2F6, CF4, SO2, HBr, Cl2 and O2, or a mixture of HBr, Cl2, O2 and CH2F2, to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with the bottom of the multilayer semiconductor stack 22', or may be lower than the bottom of the multilayer semiconductor stack 22' (e.g., ...). Figure 6B (As shown in the diagram). The etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight.

[0032] Next step, refer to Figure 7A and Figure 7B The sacrificial layer 22A is removed by an etching process, leaving a gap 44 between adjacent nanostructures 22B. The corresponding process is shown as follows. Figure 25 Process 212 in the process flow 200 shown. Etching can be performed using isotropic etching processes such as wet etching or dry etching.

[0033] refer to Figure 8A and Figure 8B A (first) one-time intermediate layer 46 is formed to fill the spacers 44 and to separate the nanostructures 22B from each other. The corresponding process is shown as follows. Figure 25 Process 214 in process flow 200 shown. According to some embodiments, the disposable interposer layer 46 comprises an oxide such as silicon oxide, and thus may also be referred to as a disposable oxide interposer layer. According to other embodiments, other types of materials (such as SiON, Al2O3, etc.) that do not mix with the nanostructures 22B during subsequent formation of the source / drain regions may be used to form the disposable interposer layer. The disposable interposer layer 46 includes portions filling the gaps 44 between the nanostructures 22B and other portions outside the openings. The disposable interposer layer 46 may be formed using CVD, PECVD, ALD, flowable CVD, etc.

[0034] According to some embodiments, the disposable interposer layer 46 may not be used to apply stress to the corresponding upper and lower nanostructures 22B. For example, the density of the disposable interposer layer 46 can be very low, such as about 2.0 g / cm³. 3 Approximately 2.6 g / cm 3 Within the range between [specific ranges]. For example, the corresponding material may include silicon oxide.

[0035] According to an optional embodiment, the disposable intermediate layer 46 can be used to apply stress to the nanostructure 22B and can have a relatively higher density, such as about 2.6 g / cm³. 3 and approximately 4.5 g / cm 3 Within the range specified. Corresponding materials may include TiN, tungsten, etc.

[0036] refer to Figure 9According to some embodiments, wafer 10 (and the device die therein) includes two device regions 100A and 100B, and a one-time interposer layer 46 is deposited into device regions 100A and 100B. The structure in each of device regions 100A and 100B can be... Figure 8B The images shown are similar or substantially the same, and use... Figures 1 to 8A and Figure 8B It is formed using the processes described in the text. It should be understood that... Figure 9 As shown in the following figures, components such as the one-time interposer layer 46 may include a top portion above the gate stack 30, and the top portion may not be shown.

[0037] Each of device regions 100A and 100B can be a p-type device region and an n-type device region, used to form one of a p-type transistor and an n-type transistor. In the following discussion, it is assumed (unless otherwise discussed) that device region 100A is the p-type device region in which a p-type transistor (PFET) will be formed, and device region 100B is the n-type device region in which an n-type transistor (NFET) will be formed.

[0038] In other embodiments, device regions 100A and 100B can also be n-type device regions and p-type device regions, respectively, used to form n-type transistors and p-type transistors. In still other embodiments, device regions 100A and 100B can both be p-type device regions used to form p-type transistors or n-type device regions used to form n-type transistors.

[0039] refer to Figure 10 A hard mask 48 is deposited over a one-time interposer layer 46 and in device regions 100A and 100B. The corresponding process is shown as follows. Figure 25 Process 216 in the process flow 200 shown. The hard mask 48 can be formed by conformal deposition processes such as ALD, CVD, etc. The hard mask 48 can be formed of silicon nitride, aluminum oxide, etc., or include silicon nitride, aluminum oxide, etc.

[0040] An etching mask 50 is then formed, which may include photoresist. The etching mask 50 is patterned such that a portion of the hard mask 48 located in device region 100B is exposed through openings in the etching mask 50. A portion of the etching mask 50 located in device region 100A remains to cover the lower portion of the hard mask 48.

[0041] In subsequent processes, the same applies. Figure 10 As shown, etching process 52 is performed to remove the exposed portion of the hard mask 48 in device region 100B. The corresponding process is shown as follows. Figure 25 Process 218 in the process flow 200 shown. Then the etch mask 50 is removed. The resulting structure is... Figure 11 As shown in the diagram. Therefore, the portion of the disposable interposer layer 46 located in device region 100B is exposed, while the portion of the disposable interposer layer 46 located in device region 100A is protected by the hard mask 48.

[0042] In a subsequent process, an isotropic etching process is performed to remove the exposed portion of the one-time interposer layer 46 in device region 100B. The corresponding process is shown as follows. Figure 25 Process 220 in the process flow 200 shown. Spacing 44 is regenerated between the nanostructures 22B. The resulting structure is... Figure 12 As shown in the diagram. In the etching process, the hard mask 48 protects the portion of the disposable interposer layer 46 located in device region 100A from etching. Etching can be performed using either a dry etching process or a wet etching process. For example, when using dry etching, a mixture of NF3 and NH3 or a mixture of HF and NH3 can be used. When performing wet etching, an HF solution can be used.

[0043] After the etching process, the remaining hard mask 48 is removed, and the resulting structure is... Figure 13 The corresponding process is shown in the diagram. Figure 25 Process 222 in the process flow 200 shown.

[0044] refer to Figure 14 An etching process is performed to trim the disposable interposer layer 46 and make it laterally recessed. The etching process may include anisotropic etching and / or isotropic etching. The remaining portion of the dielectric layer 46 is referred to as the disposable interposer layer 46'. The corresponding process is shown as follows. Figure 25 Process 224 in the process flow 200 shown. Therefore, the transverse groove 54 is formed.

[0045] One-time intermediate layer 46' replaces sacrificial layer 22A ( Figure 6B ), and is therefore optionally referred to as a (replacement) sacrificial layer. When the disposable interposer 46' is formed of oxide, the disposable interposer 46' may also be referred to as a disposable oxide interposer (DOI) 46'.

[0046] Figure 15 The deposition of the (second) single-pass spacer layer 56 is shown. The corresponding process is shown as follows. Figure 25 Process 226 in the process flow 200 shown. According to some embodiments, the disposable spacer layer 56 is deposited using methods such as ALD, CVD, PECVD, etc. In device region 100A, the disposable interposer layer 56 is formed on the disposable interposer layer 46' and fills the groove 54 ( Figure 14 In device region 100B, a single-pass interposer layer 56 fills a gap 44. Figure 14 ).

[0047] The disposable spacer layer 56 is configured to apply a different stress to the corresponding channel region than that of the disposable intermediary layer 46' (and the disposable spacer layer 46). The difference in stress may include opposite stress types (one is compressive and the other is tensile), stresses of the same type but different magnitudes, or one is zero stress and the other is non-zero stress.

[0048] According to some embodiments, p-type transistors and n-type transistors will be formed in device regions 100A and 100B, respectively. Because the p-type transistor can use SiGe in the source / drain regions, and SiGe can apply high stress to the corresponding channel, the stress (if any) applied to the channel of the p-type transistor by the disposable spacer layer 46 may not significantly improve the performance of the p-type transistor. Therefore, stress may not be necessary for the disposable spacer layer 46. Thus, the disposable spacer layer 46 may not apply stress to the corresponding channel of the p-type transistor (or applies low stress, if any), and can therefore be formed with a low-density and loose structure, making it easy to remove.

[0049] On the other hand, the source / drain regions of an n-type transistor (e.g., formed in device region 100B) may not be able to apply high tensile stress to the channel of the n-type transistor. According to some embodiments, a disposable spacer layer 56 is configured to apply tensile stress to the corresponding channel of the n-type transistor.

[0050] According to some embodiments, the disposable spacer layer 56 may include or be formed of SiN, TiN, W, etc. Process conditions such as deposition rate, temperature, and atomic ratios of elements in these materials can be adjusted to apply desired stress (such as tensile stress) to the nanostructure 22B in the device region 100B.

[0051] It has been found that the internal stress of disposable spacer layers 46 and 56 may or may not be related to that of disposable spacers 46' and 56'. Figure 16 The stress applied to the corresponding upper and lower nanostructures 22B is the same. The stress applied by the bulk material of the disposable spacer layers 46 and 56 (which is deposited on the bulk semiconductor substrate) may also be different from the stress applied to the corresponding upper and lower nanostructures 22B by the disposable spacers 46' and 56'.

[0052] According to some embodiments, the bonding of disposable spacers 46' and 56' to the nanostructure 22B may be a major factor influencing the stress applied to the nanostructure 22B. The number of atomic layers of the bonding between the disposable spacers 46' and 56' and the nanostructure 22B may be a major factor in determining the type and magnitude of the stress. However, the internal stress of the disposable spacers 46' and 56' may not be a major factor influencing the stress applied to the nanostructure 22B. This means that when tensile stress is applied to the nanostructure 22B, the corresponding upper / lower disposable spacers 46' and 56' may have internal tensile stress, internal compressive stress, or no stress. Similarly, when compressive stress is applied to the nanostructure 22B, the corresponding upper / lower disposable spacers 46' and 56' may have internal tensile stress, internal compressive stress, or no stress.

[0053] Therefore, when an n-type transistor is formed in the device region 100B, and when the disposable spacer layer 56 applies tensile stress to the corresponding upper / lower nanostructures 22B in the device region 100B, the disposable spacer layer 56 itself can be formed to have internal tensile stress, internal compressive stress, or no stress.

[0054] To determine which material and forming process can apply the desired stress to the nanostructure 22B, experiments can be conducted to form a sample, and the stress in the nanostructure 22B can be measured, for example, by measuring the Si-Si atomic distance using nanobeam electron diffraction (NBD), thereby determining (calculating) the corresponding stress. Therefore, the desired material and forming process for forming the one-time intermediate layer 56 to achieve the desired stress (such as tensile stress) in the nanostructure 22B can be determined.

[0055] refer to Figure 16 An isotropic etching process is performed to remove and trim the disposable interposer layer 56 in device regions 100A and 100B, and to recess the disposable interposer layer 56 in device regions 100A and 100B. The corresponding process is shown as follows. Figure 25 Process 228 in process flow 200 shown. An etching chemical is selected to etch the one-time interposer layer 56, but not the one-time interposer layer 46'. Etching can be performed by a dry etching process or a wet etching process.

[0056] In the etching process, the disposable interposer layer 56 in device region 100A is removed. Disposable interposer layer 46' is exposed. In device region 100B, the disposable interposer layer 56 is trimmed, and the portion of the disposable interposer layer 56 outside the region between nanostructures 22B is removed. The remaining portion of the disposable interposer layer 56, referred to as disposable interposer layer 56', is also laterally recessed to form a lateral groove 60. The disposable interposer layer 56' replaces the sacrificial layer 22A. Figure 6B ), and is therefore optionally referred to as a (replacement) sacrificial layer. When the disposable interposer 56' is formed of oxide, the disposable interposer 56' may also be referred to as DOI 56'.

[0057] refer to Figure 17 An internal spacer layer 62 is deposited. The corresponding process is shown as follows. Figure 25 Process 230 in the process flow 200 shown. The deposition process may include conformal deposition processes such as ALD, CVD, etc. The material of the internal spacer layer 62 is selected to have good etch selectivity relative to the one-time interposers 46' and 56'. For example, the internal spacer layer 62 may include silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), silicon carbonitride (SiOC), etc., and any other suitable material may also be used, such as a low-k material with a k value of less than about 3.5. The deposition process is performed until all lateral grooves 54 and 60 are filled with the internal spacer layer 62.

[0058] refer to Figure 18 A finishing process is performed to finish a portion of the internal spacer layer 62. The remaining portions in the transverse grooves 54 and 60 are internal spacers 64A and 64B, respectively. The corresponding process is shown as follows. Figure 25 Process 232 in the process flow 200 shown. Internal spacers 64A and 64B are also referred to individually and collectively as internal spacers 64.

[0059] Figure 19 The diagram shows the formation of epitaxial isolation regions (also referred to as L0) 66A and 66B in device regions 100A and 100B, respectively. The corresponding process is shown as follows. Figure 25Process 234 in process flow 200 shown. According to some embodiments, epitaxial isolation regions 66A and 66B can be formed of silicon and may be free of p-type and n-type dopants. According to alternative embodiments, epitaxial isolation region 66A can be formed of SiGe having, for example, a low germanium atomic percentage of less than about 20%. Epitaxial isolation region 66A may be free of p-type dopants (such as boron) or doped with p-type dopants having a low boron concentration. Epitaxial isolation region 66B can be formed of Si or carbon-doped silicon. Epitaxial isolation region 66B may be free of n-type dopants such as phosphorus, or doped with n-type dopants such as phosphorus having a low phosphorus concentration.

[0060] According to some embodiments, dielectric isolation layers 67A and 67B may be formed at the bottom of the remaining source / drain recess 42. Alternatively, dielectric isolation layers 67A and 67B may not be formed. Therefore, dielectric isolation layers 67A and 67B are shown as dashed lines to indicate whether or not dielectric isolation layers 67A and 67B may be formed.

[0061] According to some embodiments, dielectric isolation layers 67A and 67B may include silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), etc. According to some embodiments, dielectric isolation layers 67A and 67B have a multilayer structure, for example, including a conformal silicon oxide pad and a silicon nitride region above the silicon oxide pad.

[0062] In some embodiments, dielectric isolation layers 67A are used in both the p-type device region 100A and the n-type device region 100B to reduce current leakage. In some embodiments, dielectric isolation layer 67B is formed in the n-type device region 100B, while no dielectric isolation layer is formed in the p-type device region 100A. This is because the dielectric isolation layer may affect the epitaxiality of the source / drain formation, as selective epitaxial regions may not be able to be formed from the dielectric material. Furthermore, p-type transistors tend to use the source / drain regions to provide stress, and it has been found that source / drain regions with dielectric isolation layers formed underneath may not provide sufficient stress, thus affecting the efficiency of the dielectric isolation layer in providing stress. Therefore, in some embodiments, the dielectric isolation layer is not formed in the p-type device region 100A, but is formed in the n-type device region 100B.

[0063] refer to Figure 20 Epitaxial source / drain regions 68A and 68B are formed in the groove 42 by selective epitaxy. The corresponding process is shown as follows. Figure 25Process 236 in the process flow 200 shown. Depending on whether the resulting transistor is a p-type or n-type transistor, p-type or n-type impurities can be doped in situ as epitaxy proceeds. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc., can be grown. According to some embodiments, the epitaxial source / drain region 68A can be a p-type region, for example, including boron-doped SiGe. The epitaxial source / drain region 68B can be an n-type region, for example, including phosphorus-doped Si or SiC.

[0064] Figure 21 A cross-sectional view of the structure after the formation of the contact etch stop layer (CESL) 72 and the interlayer dielectric (ILD) 74 is shown. The corresponding process is shown as follows. Figure 25 Process 238 in process flow 200 shown. CESL 72 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 74 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 74 can be formed from an oxygen-containing dielectric material, which can include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. CESL 72 and ILD 74 are planarized by a planarization process such as CMP or mechanical polishing.

[0065] Next, the dummy gate electrode 34 and dummy gate dielectric 32 (and hard mask 36, if remaining) are removed in one or more etching processes to form the recess 76, as shown. Figure 21 As shown in the figure. The corresponding process is shown as follows. Figure 25 Process 240 in the process flow 200 shown. According to some embodiments, the dummy gate electrode 34 and dummy gate dielectric 32 are removed by anisotropic and / or isotropic dry etching processes. Each recess 76 exposes a portion of the multilayer stack 22' and / or is located on top of a portion of the multilayer stack 22', which includes the future channel region in the subsequently completed transistor.

[0066] Then, the disposable intermediate layers 46' and 56' (sacrificial layers) are removed to extend the groove 76 between the nanostructures 22B. The corresponding process is shown as follows. Figure 25Process 242 in the process flow 200 shown. The disposable interposers 46' and 56' can be removed by performing an isotropic etching process, such as a dry etching process or a wet etching process using an etchant selective for the materials of the disposable interposers 46' and 56', while the nanostructure 22B and the substrate 20 remain relatively unetched compared to the disposable interposers 46' and 56'. Etching can include a shared etching process (where the disposable interposers 46' and 56' are etched) or separate etching processes (one for etching the interposer 46' and another for etching the disposable interposer 56').

[0067] It should be understood that the disposable interposers 46' and 56' are removed after the source / drain regions are formed. After the disposable interposers 46' and 56' are removed, the stress applied by them remains in the corresponding semiconductor nanostructure 22B. For example, when the disposable interposer 56' is formed to apply tensile stress to the corresponding nanostructure 22B in the device region 100B, after the disposable interposer 56' is removed, the semiconductor nanostructure 22B in the device region 100B has a memory of tensile stress and can have a higher stress than the internal stress of the source / drain regions 68B.

[0068] In subsequent processes, replacement gate stacks 84A and 84B are formed. The corresponding processes are shown as follows. Figure 25 Process 244 in process flow 200 shown. (Reference) Figure 22 This forms gate dielectrics 80 (including gate dielectrics 80A and 80B). According to some embodiments, each of the gate dielectrics 80 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed of or comprise silicon oxide, which may be deposited by a conformal deposition process such as ALD or CVD. According to some embodiments, the high-k dielectric layer includes one or more dielectric layers. For example, the high-k dielectric layer may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0069] Then, gate electrode 82 (including gate electrodes 82A and 82B) is formed. During formation, a conductive layer is first formed on the high-k dielectric layer to fill the remaining portion of the trench 76. Gate electrode 82 may include a metal-containing material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, although a single-layer gate electrode 82 is shown, gate electrode 82 may include any number of layers, any number of work function layers, and may include a filler material. Gate dielectric 80 and gate electrode 82 also fill the space between adjacent nanostructures 22B and the space between the bottom nanostructure 22B and the underlying substrate strip 20'.

[0070] After filling the recess 76, a planarization process, such as CMP or mechanical polishing, is performed to remove excess portions of the gate dielectric 80 and gate electrode 82 located above the top surface of the ILD 74. The gate electrode 82 and gate dielectric 80 are collectively referred to as the gate stack 84 (including gate stacks 84A and 84B) of the resulting nanoFET. Thus, GAA transistors 86A and 86B are formed.

[0071] According to some embodiments of the GAA transistor 86B being an n-type transistor, the source / drain region 68B may have low internal stress or no internal stress. The gate stack 84B also has low internal stress or no internal stress.

[0072] It should be understood that each of the nanostructures 22B (which is the channel of the GAA transistor 86B) is completely surrounded by a collective of components. This collective of components includes a gate stack 84B (which surrounds the nanostructure 22B when viewed in a vertical cross-section cut through it), source / drain regions 68B, and internal spacers 64B. The collective of components (referred to as 68B / 84B / 64B) can individually and collectively apply a first stress to the nanostructure 22B. However, the internal stress of the nanostructure 22B is memoryed by the interposer layer 56' (which has been removed) and is higher than the first stress. This is a unique characteristic of the GAA transistor 86B. The stress of the collective of components 68B / 84B / 64B can be determined, for example, by using an NBD.

[0073] According to some embodiments where the GAA transistor 86A is a p-type transistor, when the disposable interposer 46' is formed of a loose material, the disposable interposer 46' can apply very little or no stress to the channel region of the GAA transistor 86A, and the compressive stress in the channel region is applied by the source / drain region 68A. Optionally, the disposable interposer 46' can also apply compressive stress to the channel region of the GAA transistor 86A, and this compressive stress is also stored in the channel region after the disposable interposer 46' is removed.

[0074] Since both GAA transistors 86A and 86B are optional n-type transistors (or compressive stress), both the primary interposers 46' and 56' can apply tensile stress (or corresponding compressive stress) to the respective channel regions. However, the magnitudes of the stresses applied by the primary interposers 46' and 56' differ from each other, thereby allowing the performance of GAA transistors 86A and 86B to be tuned.

[0075] Because, as Figure 16 The grooves 54 and 60 shown are formed in separate processes, so the shape and lateral dimensions of groove 54 can be different from or the same as the shape and lateral dimensions of groove 60. For example, Figure 23 Regions 90-1 and 90-2 of two gate stacks and surrounding components of two GAA transistors are shown. One of regions 90-1 and 90-2 can be part of one of GAA transistors 86A and 86B, and the other is part of the other of GAA transistors 86A and 86B. According to some embodiments, region 90-1 is part of a p-type transistor, and region 90-2 is part of an n-type transistor. According to alternative embodiments, region 90-1 is part of an n-type transistor, and region 90-2 is part of a p-type transistor.

[0076] Correspondingly, width W1 can be greater than, equal to, or less than width W1', width W2 can be greater than, equal to, or less than width W2', and width W3 can be greater than, equal to, or less than width W3' in any combination. Widths W1, W2, W1', and W2' are the maximum and minimum lateral widths of the inner spacers 64 in regions 90-1 and 90-2. Widths W3 and W3' are the widths of the gate stacks 84 in regions 90-1 and 90-2, respectively. For example, there can be relationships W1'>W1, W2'<W2, and W3>W3'.

[0077] Figure 24 An embodiment is shown where the inner spacers 64 can have the same inner sidewall shape and different outer sidewall shapes. For example, the inner spacer 64 in region 90-1 can have a concave outer sidewall, and the inner spacer 64 in region 90-2 can have a convex outer sidewall.

[0078] Embodiments of the present disclosure have some advantageous features. By forming a single-use interlayer that applies stress to the channel region of a GAA transistor, the stress can be memorized in the channel region. This can be particularly effective in n-type transistors, where the stress applied by the source / drain regions is typically low. Additionally, different stresses can be applied to different transistors by different single-use interlayers, so that the performance of the transistors can be adjusted.

[0079] According to some embodiments of this disclosure, the method includes: forming a first multilayer stack, including: a first plurality of sacrificial layers; and a first plurality of semiconductor nanostructures, wherein the first plurality of sacrificial layers and the first plurality of semiconductor nanostructures are alternately disposed; forming a second multilayer stack, including: a second plurality of sacrificial layers; and a second plurality of semiconductor nanostructures, wherein the second plurality of sacrificial layers and the second plurality of semiconductor nanostructures are alternately disposed; replacing the first plurality of sacrificial layers and the second plurality of sacrificial layers with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively, wherein the third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes; removing the third plurality of sacrificial layers to form a first trench; forming a first gate stack in the first trench; removing the fourth plurality of sacrificial layers to form a second trench; and forming a second gate stack in the second trench.

[0080] In one embodiment, the first plurality of sacrificial layers and the second plurality of sacrificial layers comprise silicon germanium, and wherein the third plurality of sacrificial layers comprises silicon oxide. In another embodiment, the third plurality of sacrificial layers have a lower density than the fourth plurality of sacrificial layers. In another embodiment, the fourth plurality of sacrificial layers are configured to apply tensile stress to the second plurality of semiconductor nanostructures. In yet another embodiment, the third plurality of sacrificial layers are configured to apply a first stress to the first plurality of semiconductor nanostructures; and the fourth plurality of sacrificial layers are configured to apply a second stress to the second plurality of semiconductor nanostructures, wherein the second stress is greater than the first stress.

[0081] In one embodiment, the method further includes forming source and drain regions on opposite sides of the second plurality of semiconductor nanostructures, wherein, after forming the source and drain regions, a fourth plurality of sacrificial layers are removed. In another embodiment, the source and drain regions have a first internal stress, and the second plurality of semiconductor nanostructures have a second internal stress, wherein the first internal stress is less than the second internal stress.

[0082] In one embodiment, the second gate stack has a first internal stress, and the second plurality of semiconductor nanostructures have a second internal stress, wherein the first internal stress is less than the second internal stress. In another embodiment, the method further includes: laterally recessing a third plurality of sacrificial layers and a fourth plurality of sacrificial layers to form a lateral groove; and forming an internal spacer in the lateral groove. In another embodiment, the third plurality of sacrificial layers and the fourth plurality of sacrificial layers are laterally recessed to form the lateral groove in a separate etching process.

[0083] According to some embodiments of this disclosure, the method includes: forming a first plurality of sacrificial layers between a first plurality of semiconductor nanostructures in a first forming process; forming a second plurality of sacrificial layers between a second plurality of semiconductor nanostructures in a second forming process, wherein the first forming process and the second forming process are separate processes; forming a first source / drain region on opposite sides of the first plurality of semiconductor nanostructures; forming a second source / drain region on opposite sides of the second plurality of semiconductor nanostructures; removing the first plurality of sacrificial layers and the second plurality of sacrificial layers in the same etching process to form a first groove and a second groove, respectively, wherein the first plurality of sacrificial layers comprises a material different from the second plurality of sacrificial layers; forming a first gate stack filling the first groove; and forming a second gate stack filling the second groove.

[0084] In one embodiment, the first source / drain region is a p-type region, and the second source / drain region is an n-type region. In another embodiment, the first plurality of sacrificial layers are configured to apply a first stress to the first plurality of semiconductor nanostructures, and the second plurality of sacrificial layers are configured to apply a second stress to the second plurality of semiconductor nanostructures, wherein the second stress is a tensile stress. In yet another embodiment, the second plurality of sacrificial layers to which the tensile stress is applied have internal compressive stress.

[0085] In one embodiment, the second stress has an order of magnitude higher than the first stress. In another embodiment, the first plurality of sacrificial layers and the second plurality of sacrificial layers are dielectric layers, and the method further includes replacing the semiconductor sacrificial layer with the first plurality of sacrificial layers and the second plurality of sacrificial layers.

[0086] According to some embodiments of this disclosure, the method includes: forming a first transistor, including: forming a first semiconductor nanostructure over a semiconductor substrate, wherein the first semiconductor nanostructure has a first internal stress; forming a first source region and a first drain region connected to the first semiconductor nanostructure on opposite sides of the first semiconductor nanostructure, wherein the first source region and the first drain region have a second internal stress less than the first internal stress; and forming a first gate stack, wherein the first gate stack includes a first portion, and wherein, in a first cross-section of the first semiconductor nanostructure, the first portion of the first gate stack completely surrounds the first semiconductor nanostructure, and wherein, the first portion of the first gate stack has a third internal stress less than the first internal stress.

[0087] In an embodiment, the method further includes: forming a first pair of internal spacers located on and in contact with the first semiconductor nanostructure; and forming a second pair of internal spacers located below and in contact with the first semiconductor nanostructure, wherein the first pair of internal spacers and the second pair of internal spacers have a fourth internal stress less than the first internal stress.

[0088] In one embodiment, the method further includes forming a second transistor, comprising: a second semiconductor nanostructure located above a semiconductor substrate; a second source region and a second drain region located on opposite sides of the second semiconductor nanostructure and connected to the second semiconductor nanostructure, wherein the second source region, the second drain region, and the second semiconductor nanostructure have a second internal stress greater than the first internal stress; and a second gate stack including a second portion completely surrounding the second semiconductor nanostructure. In another embodiment, the first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0089] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first multilayer stack, including: a first plurality of sacrificial layers; and a first plurality of semiconductor nanostructures, wherein the first plurality of sacrificial layers and the first plurality of semiconductor nanostructures are alternately disposed; forming a second multilayer stack, including: a second plurality of sacrificial layers; and a second plurality of semiconductor nanostructures, wherein the second plurality of sacrificial layers and the second plurality of semiconductor nanostructures are alternately disposed; replacing the first plurality of sacrificial layers and the second plurality of sacrificial layers with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively, wherein the third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes; removing the third plurality of sacrificial layers to form a first trench; forming a first gate stack in the first trench; removing the fourth plurality of sacrificial layers to form a second trench; and forming a second gate stack in the second trench.

[0090] In some embodiments, the first plurality of sacrificial layers and the second plurality of sacrificial layers comprise silicon germanium, and wherein the third plurality of sacrificial layers comprises silicon oxide. In some embodiments, the third plurality of sacrificial layers have a lower density than the fourth plurality of sacrificial layers. In some embodiments, the fourth plurality of sacrificial layers are configured to apply tensile stress to the second plurality of semiconductor nanostructures. In some embodiments, the third plurality of sacrificial layers are configured to apply a first stress to the first plurality of semiconductor nanostructures; and the fourth plurality of sacrificial layers are configured to apply a second stress to the second plurality of semiconductor nanostructures, wherein the second stress is greater than the first stress. In some embodiments, the method further includes forming source regions and drain regions on opposite sides of the second plurality of semiconductor nanostructures, wherein the fourth plurality of sacrificial layers are removed after the source regions and drain regions are formed. In some embodiments, the source regions and drain regions have a first internal stress, and the second plurality of semiconductor nanostructures have a second internal stress, and the first internal stress is less than the second internal stress. In some embodiments, the second gate stack has a first internal stress, and the second plurality of semiconductor nanostructures have a second internal stress, and the first internal stress is less than the second internal stress. In some embodiments, the method further includes: laterally recessing the third plurality of sacrificial layers and the fourth plurality of sacrificial layers to form a lateral groove, wherein the third plurality of sacrificial layers and the fourth plurality of sacrificial layers are laterally recessed in a separate etching process to form the lateral groove; and forming an internal spacer in the lateral groove. In some embodiments, the fourth plurality of sacrificial layers comprises titanium nitride (TiN).

[0091] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first plurality of sacrificial layers between a first plurality of semiconductor nanostructures in a first forming process; forming a second plurality of sacrificial layers between a second plurality of semiconductor nanostructures in a second forming process, wherein the first forming process and the second forming process are separate processes; forming a first source / drain region on opposite sides of the first plurality of semiconductor nanostructures; forming a second source / drain region on opposite sides of the second plurality of semiconductor nanostructures; removing the first plurality of sacrificial layers and the second plurality of sacrificial layers in the same etching process to form a first groove and a second groove, respectively, wherein the first plurality of sacrificial layers comprises a material different from the second plurality of sacrificial layers; forming a first gate stack filling the first groove; and forming a second gate stack filling the second groove.

[0092] In some embodiments, the first source / drain region is a p-type region, and the second source / drain region is an n-type region. In some embodiments, the first plurality of sacrificial layers are configured to apply a first stress to the first plurality of semiconductor nanostructures, and the second plurality of sacrificial layers are configured to apply a second stress to the second plurality of semiconductor nanostructures, wherein the second stress is a tensile stress. In some embodiments, the second plurality of sacrificial layers comprises titanium nitride. In some embodiments, the second stress has an order of magnitude higher than the first stress. In some embodiments, the first plurality of sacrificial layers and the second plurality of sacrificial layers are dielectric layers, and the method further includes replacing the semiconductor sacrificial layers with the first plurality of sacrificial layers and the second plurality of sacrificial layers.

[0093] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a first transistor, including: forming a first semiconductor nanostructure over a semiconductor substrate, wherein the first semiconductor nanostructure has a first internal stress; forming a first source region and a first drain region connected to the first semiconductor nanostructure on opposite sides of the first semiconductor nanostructure, wherein the first source region and the first drain region have a second internal stress less than the first internal stress; and forming a first gate stack, wherein the first gate stack includes a first portion, and wherein, in a first cross-section of the first semiconductor nanostructure, the first portion of the first gate stack completely surrounds the first semiconductor nanostructure, and wherein, the first portion of the first gate stack has a third internal stress less than the first internal stress.

[0094] In some embodiments, the method further includes: forming a first pair of internal spacers located on and in contact with the first semiconductor nanostructure; and forming a second pair of internal spacers located below and in contact with the first semiconductor nanostructure, wherein the first pair of internal spacers and the second pair of internal spacers have a fourth internal stress less than the first internal stress. In some embodiments, the method further includes forming a second transistor, the second transistor comprising: a second semiconductor nanostructure located above the semiconductor substrate; a second source region and a second drain region located on opposite sides of the second semiconductor nanostructure and connected to the second semiconductor nanostructure, wherein the second source region, the second drain region, and the second semiconductor nanostructure have a second internal stress greater than the first internal stress; and a second gate stack including a second portion completely surrounding the second semiconductor nanostructure. In some embodiments, the first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0095] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Forming the first multilayer stack, comprising: The first multiple sacrificial layers; and The first plurality of semiconductor nanostructures, wherein the first plurality of sacrificial layers and the first plurality of semiconductor nanostructures are alternately disposed; Forming a second multilayer stack, comprising: The second multiple sacrificial layers; and The second plurality of semiconductor nanostructures, wherein the second plurality of sacrificial layers and the second plurality of semiconductor nanostructures are alternately arranged; The first plurality of sacrificial layers and the second plurality of sacrificial layers are replaced with a third plurality of sacrificial layers and a fourth plurality of sacrificial layers, respectively, wherein the third plurality of sacrificial layers and the fourth plurality of sacrificial layers are replaced in different processes; Remove the third plurality of sacrificial layers to form the first groove; A first gate stack is formed in the first groove; Remove the fourth plurality of sacrificial layers to form the second groove; and A second gate stack is formed in the second groove.

2. The method according to claim 1, wherein, The first plurality of sacrificial layers and the second plurality of sacrificial layers comprise silicon germanium, and wherein the third plurality of sacrificial layers comprises silicon oxide.

3. The method according to claim 1, wherein, The third plurality of sacrificial layers have a lower density than the fourth plurality of sacrificial layers.

4. The method according to claim 3, wherein, The fourth plurality of sacrificial layers are configured to apply tensile stress to the second plurality of semiconductor nanostructures.

5. The method according to claim 1, wherein: The third plurality of sacrificial layers are configured to apply a first stress to the first plurality of semiconductor nanostructures; and The fourth plurality of sacrificial layers are configured to apply a second stress to the second plurality of semiconductor nanostructures, wherein the second stress is greater than the first stress.

6. The method of claim 1, further comprising forming source regions and drain regions on opposite sides of the second plurality of semiconductor nanostructures, wherein, After the source region and the drain region are formed, the fourth plurality of sacrificial layers are removed.

7. The method according to claim 6, wherein, The source region and the drain region have a first internal stress, and the second plurality of semiconductor nanostructures have a second internal stress, wherein the first internal stress is less than the second internal stress.

8. The method according to claim 1, wherein, The second gate stack has a first internal stress, and the second plurality of semiconductor nanostructures have a second internal stress, wherein the first internal stress is less than the second internal stress.

9. A method for forming a semiconductor device, comprising: In the first forming process, a first plurality of sacrificial layers are formed between a first plurality of semiconductor nanostructures; In the second formation process, a second plurality of sacrificial layers are formed between the second plurality of semiconductor nanostructures, wherein the first formation process and the second formation process are separate processes; A first source / drain region is formed on opposite sides of the first plurality of semiconductor nanostructures; A second source / drain region is formed on the opposite sides of the second plurality of semiconductor nanostructures; In the same etching process, the first plurality of sacrificial layers and the second plurality of sacrificial layers are removed to form a first groove and a second groove, respectively, wherein the first plurality of sacrificial layers comprise a material different from the second plurality of sacrificial layers; Forming a first gate stack that fills the first recess; and A second gate stack is formed to fill the second groove.

10. A method of forming a semiconductor device, comprising: Forming the first transistor includes: A first semiconductor nanostructure is formed on a semiconductor substrate, wherein the first semiconductor nanostructure has a first internal stress; A first source region and a first drain region are formed on opposite sides of the first semiconductor nanostructure, connected to the first semiconductor nanostructure, wherein the first source region and the first drain region have a second internal stress less than the first internal stress; and A first gate stack is formed, wherein the first gate stack includes a first portion, and wherein, in a first cross-section of the first semiconductor nanostructure, the first portion of the first gate stack completely surrounds the first semiconductor nanostructure, and wherein, the first portion of the first gate stack has a third internal stress that is less than the first internal stress.

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