Preparation method of novel anti-bias-fixation chip

Abstract

The invention discloses a novel anti-bias-fixation chip preparation method, and relates to the technical field of semiconductor chip preparation, and the method comprises the steps: generating a growth column target morphological model based on target geometric parameters; preparing a growth column in the electrode area; comparing the three-dimensional contour information of the growth column with the target morphological model of the growth column to generate a morphological error matrix; correcting the etching track by using the morphological error matrix, and constructing an infiltration energy level gradient which is gradually increased from the center to the edge at the top end of the growth column; calculating thermodynamic stability values of the growth columns based on the infiltration energy level gradient, screening out qualified growth columns based on the thermodynamic stability values, and constructing a growth column array; and based on the growth column array, generating a self-alignment liquid bridge restoring force in a solid crystal melting stage, and inducing the chip to perform self-alignment posture correction to obtain the flip LED chip. According to the invention, active pose correction and high-precision anti-deviation preparation of the flip LED chip are realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip fabrication technology, and in particular to a novel method for fabricating anti-fixed bias chips. Background Technology

[0002] As microelectronic packaging technology evolves towards higher integration and miniaturization, flip-chip bonding has become a core method for achieving interconnects in high-performance semiconductor devices. In existing high-precision flip-chip packaging processes, the industry commonly uses eutectic bonding or solder paste reflow processes to achieve electrical connections between the chip and the substrate electrodes. These technologies typically rely on the mechanical alignment precision of high-precision die bonders, using vacuum nozzles to place the chip onto pre-coated solder pads. During this process, to ensure connection quality, metal bumps with specific height and composition are often pre-fabricated on the wafer surface, utilizing the surface tension of the molten solder in a liquid state to provide a certain degree of self-alignment.

[0003] However, existing growth pillar fabrication and die bonding processes exhibit significant limitations when fabricating chips with high aspect ratios or ultra-fine pitch requirements. Traditional processes often neglect the coupling relationship between the growth pillar geometry and the rheological properties of solder paste, leading to random morphological deviations in the microstructure of the growth pillars during the deposition of conductive metal materials. These deviations can trigger asymmetric evolution of liquid bridge morphology during the die bonding melting stage, resulting in uneven distribution of surface tension intended for bias correction. This easily leads to lateral stress imbalances, inducing bias, tilting, or rotational displacement of the chip. Because current technologies lack precise gradient control of the wetting energy level at the tip of the growth pillar, they cannot generate sufficiently robust and oriented self-aligning restoring forces in the molten state. This not only reduces the assembly yield of high-density chip arrays but also limits the thermodynamic stability of ultra-miniaturized chips at extreme sizes. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a novel die bonding self-alignment method for chip fabrication that solves the problems of insufficient die bonding self-alignment accuracy and chip displacement deviation.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a novel method for fabricating a solid bias-resistant chip, comprising, The surface topology parameters of the wafer to be processed are collected, and combined with the preset solder paste rheological properties, the target geometric parameters are calculated by the liquid bridge morphology evolution algorithm, and the growth column target morphology model is generated based on the target geometric parameters. The target morphology model of the growth column is converted into spatial coordinate instructions, and the deposition energy field is controlled to deposit metallic conductive materials in the electrode area of ​​the wafer to be processed. By dynamically adjusting the pulse frequency and energy distribution density, growth columns are prepared in the electrode area. The three-dimensional contour information of the growth column is extracted, and the three-dimensional contour information of the growth column is compared with the target morphological model of the growth column to generate a morphological error matrix. The etching trajectory is corrected by using the morphological error matrix and the energy distribution is controlled to create an increasing wetting energy gradient from the center to the edge at the top of the growth column. Based on the wetting energy level gradient, the thermodynamic stability values ​​of the growth columns are calculated, and qualified growth columns are selected based on the thermodynamic stability values, and a growth column array is constructed. Based on the growth column array, a self-aligned liquid bridge restoring force is generated during the die bonding and melting stage, which induces the chip to self-align and correct its orientation, thus obtaining a flip-chip LED.

[0008] As a preferred embodiment of the novel anti-fixed bias chip fabrication method of the present invention, the following steps are taken: The surface topological parameters of the wafer to be processed are collected, and combined with the preset solder paste rheological properties, the target geometric parameters are calculated using a liquid bridge morphology evolution algorithm. Based on the target geometric parameters, a target morphology model of the growth pillar is generated. Scan the electrode region of the wafer to be processed to obtain surface topology parameters, which are then used as spatial boundary conditions. The spatial boundary conditions are coupled with the preset solder paste rheological properties and input into the liquid bridge morphology evolution algorithm for convergence iteration to calculate the target geometric parameters. Based on the topological logic of the inverted frustum, the target geometric parameters are subjected to surface fitting and spatial discretization to generate a growth column target morphology model.

[0009] As a preferred embodiment of the novel anti-polarization chip fabrication method of the present invention, the specific steps of converting the growth column target morphology model into spatial coordinate commands and controlling the deposition energy field to deposit metallic conductive materials in the electrode region of the wafer to be processed are as follows. Using a slicing algorithm, the continuous geometric surface data in the growth column target morphology model is discretized into a lattice sequence to generate spatial coordinate instructions; The spatial coordinate command is transmitted to the control circuit, which controls the deposition energy field to align with the electrode area of ​​the wafer to be processed, determines the starting physical point of the accumulation of the metallic conductive material, and initiates the deposition.

[0010] In a preferred embodiment of the novel anti-fixed polarization chip fabrication method of the present invention, the step of fabricating growth columns in the electrode region by dynamically adjusting the pulse frequency and energy distribution density is as follows: Real-time monitoring of deposition height; based on the cross-sectional changes of the growth column target morphology model, the vertical growth rate of the metallic conductive material on the wafer to be processed is controlled by real-time calculation and adjustment of pulse frequency. While adjusting the pulse frequency, the energy distribution density is increased simultaneously according to the structural characteristics of the inverted frustum, and the spread of the metallic conductive material to the surrounding area is gradually increased to form the shape of the inverted frustum. The diameter-to-height ratio is monitored in real time. When the diameter-to-height ratio matches the target diameter-to-height ratio and the energy field of the top layer of the inverted frustum-shaped structure is released, a growth column is generated.

[0011] In a preferred embodiment of the novel anti-fixed bias chip fabrication method of the present invention, the target diameter-to-height ratio is obtained by calculating the ratio of the column height parameter of the growth column to the corresponding cross-sectional feature diameter parameter in the growth column target morphology model.

[0012] In a preferred embodiment of the novel anti-fixed bias chip fabrication method of the present invention, the steps of extracting the three-dimensional contour information of the growth column from the growth column, comparing the three-dimensional contour information of the growth column with the target morphological model of the growth column, and generating a morphological error matrix are as follows. Using the origin, axial direction, and electrode region boundary of the growth column target morphology model as coordinate references, three-dimensional sampling is performed on the growth column to generate three-dimensional contour information of the growth column; Using the coordinate datum as a unified reference, the three-dimensional contour information of the growth column is aligned with the target morphology model of the growth column in the execution space, and the registration parameters are obtained. Based on the correspondence between registration parameters and contour points and target surface, an error vector field is calculated on the sampled profile sequence to generate a morphological error matrix.

[0013] As a preferred embodiment of the novel anti-fixed bias chip fabrication method of the present invention, the contour point-target surface correspondence is obtained by performing nearest neighbor mapping on the contour points in the three-dimensional contour information of the growth column based on the registration parameters on the surface of the growth column target morphology model. The sampling profile sequence is formed by extracting the three-dimensional contour information of the growth column along the column height direction at a fixed step distance, based on the discrete height index in the target morphology model of the growth column.

[0014] As a preferred embodiment of the novel anti-solid bias chip fabrication method of the present invention, the steps of correcting the etching trajectory using a morphology error matrix and controlling the energy distribution to construct an increasing wetting energy level gradient from the center to the edge at the top of the growth column are as follows: The deviation components of each coordinate point are extracted from the shape error matrix and converted into compensation displacement vectors, which are then superimposed on the initial etching trajectory to calculate the corrected etching trajectory. The corrected etching trajectory is used as the sweeping guidance command for the energy beam. By adjusting the dwell time and duty cycle of the energy beam at different coordinate points, the energy distribution at the top of the growth column is controlled, thus constructing an infiltration energy level gradient that increases from the center to the edge.

[0015] As a preferred embodiment of the novel anti-solid polarization chip fabrication method of the present invention, the steps of calculating the thermodynamic stability value of the growth column based on the wetting energy level gradient, selecting qualified growth columns based on the thermodynamic stability value, and constructing a growth column array are as follows. The gradient distribution data of the wetting energy level gradient at the top of the growth column were collected, and the Gibbs surface free energy of the growth column under high temperature was calculated based on the gradient distribution data. The Gibbs surface free energy is converted into a functional minimizing the interfacial potential energy, and the interfacial potential energy minimization functional is solved to output the thermodynamic stability value. Based on thermodynamic stability values, growth columns with geometric deformation below the tolerance in high-temperature reflow soldering environment are identified as qualified growth columns. Extract the spatial coordinate information of each qualified growth column, verify the spatial overlap with the preset point matrix, remove unqualified sites, and perform physical point mapping on the electrode distribution map of the wafer to be processed to output the growth column array.

[0016] As a preferred embodiment of the novel anti-fixed bias chip fabrication method of the present invention, the step of generating a self-aligned liquid bridge restoring force during the die bonding and melting stage based on the growth column array, and inducing chip self-alignment and orientation correction to obtain a flip-chip LED, includes the following specific steps. During the die bonding and melting stage, the wetting energy level gradient at the top of the growth column array is used to induce the liquid solder to spread asymmetrically. The asymmetric spreading triggers the evolution of the liquid bridge morphology and generates a surface tension vector pointing towards the center of the electrode region. The surface tension vector is used to synthesize a self-aligned liquid bridge restoring force, which is then applied to the center of gravity of the flip-chip to be calibrated to calibrate the spatial pose of the flip-chip and obtain the flip-chip.

[0017] The beneficial effects of this invention are as follows: By coupling wafer topology and solder paste rheological properties, an inverted frustum growth column model is constructed, and a dynamic pulse energy field is used to achieve precise deposition of microstructures. Subsequently, a wetting energy level gradient increasing from the center to the edge is constructed at the top of the growth column and combined with thermodynamic stability screening, thereby inducing asymmetric spreading and self-aligned liquid bridge recovery force of liquid solder during the die bonding and melting stage, realizing active pose correction and high-precision anti-die bonding fabrication of flip-chip LEDs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a novel anti-fixed bias chip fabrication method.

[0020] Figure 2 A flowchart for generating the target morphological model of the growth column.

[0021] Figure 3 This is a flowchart for preparing a growth column.

[0022] Figure 4 This is a flowchart for self-alignment and pose correction. Detailed Implementation

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0025] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0026] Reference Figures 1-4 This is one embodiment of the present invention, which provides a novel method for fabricating an anti-fixed bias chip, comprising the following steps: S1. Collect the surface topology parameters of the wafer to be processed, and combine them with the preset solder paste rheological properties. Calculate the target geometric parameters through the liquid bridge morphology evolution algorithm, and generate the target morphology model of the growth column based on the target geometric parameters.

[0027] S1.1 Scan the electrode region of the wafer to be processed to obtain surface topology parameters, which are then used as spatial boundary conditions.

[0028] Furthermore, the electrode region of the wafer to be processed is scanned in three dimensions using an optical interferometer or a laser confocal scanner to obtain surface topology parameters. The surface topology parameters are then processed using coordinate system and data formatting operations and used as spatial boundary condition inputs for the liquid bridge morphology evolution algorithm to limit the calculation range of the target geometric parameters and provide convergence boundary constraints.

[0029] It should be noted that the surface topology parameters include at least the height distribution data of the electrode region, the boundary profile data, and the flatness, surface roughness, and edge slope parameters calculated from the height distribution data; wherein, flatness is used to characterize the surface shape deviation of the electrode region, surface roughness is used to characterize the amplitude of micro-undulations, the edge slope parameter is used to characterize the height change rate of the electrode edge, and the boundary profile data is used to define the geometric boundary range of the electrode region.

[0030] S1.2 Couple the spatial boundary conditions with the preset solder paste rheological properties and input them into the liquid bridge morphology evolution algorithm for convergence iteration to calculate the target geometric parameters; Furthermore, the boundary contour data, height distribution data, and edge slope parameters in the spatial boundary conditions are used as geometric constraints and contact line constraints for the liquid bridge. At the same time, the preset solder paste rheological properties (such as viscosity-shear rate relationship, yield stress, and surface tension) are used as material response constraints and uniformly written into the input parameter set of the liquid bridge morphology evolution algorithm. The input parameter set is imported into the liquid bridge morphology evolution algorithm for iterative calculation. The liquid bridge morphology is updated once in each iteration and a set of geometric parameters is output once. When the change in the set of geometric parameters output in two adjacent iterations both fall within the corresponding preset allowable error range, the liquid bridge morphology evolution algorithm is determined to have converged, and the target set of geometric parameters (which includes at least: column height parameter, cross-sectional feature diameter parameter, inverted frustum taper parameter, and fillet transition radius parameter) is output.

[0031] It should be noted that the principle of the liquid bridge morphology evolution algorithm is that, under the constraints of given spatial boundary conditions and solder paste rheological properties, based on the surface tension-driven interface curvature pressure balance (Young-Laplace) and combined with viscoelastic flow damping, the free interface of the liquid bridge gradually approaches the energy minimum state through numerical iteration, thereby deriving the corresponding target geometric parameters. The preset tolerance range (including column height tolerance, diameter tolerance, taper tolerance, and fillet tolerance) is set based on the surface topology parameter measurement accuracy, the forming resolution of the deposition etching process, and the tolerance range of the growth column diameter-to-height ratio and chip self-alignment deviation during flip-chip LED reflow soldering. Example values: column height tolerance ±1 micrometer, diameter tolerance ±2 micrometers, taper tolerance ±0.5 degrees, and fillet tolerance ±1 micrometer. The target geometric parameters are a set of topological constraints defined by the liquid bridge morphology evolution algorithm, which determine the mechanical behavior of the liquid bridge. These mainly include the sidewall inclination angle of the growth pillar (used to control the magnitude of the centripetal component after surface tension decomposition), the diameter ratio between the bottom and top (determining the stability of liquid bridge collapse or spreading), and the microscopic radius of curvature of the top surface (affecting the potential energy barrier of initial solder paste wetting). The preset solder paste rheological properties are set based on the requirements of the liquid bridge morphology evolution algorithm, combined with physical indicators such as the surface tension constant, viscosity parameters, and wetting angle of the solder paste in its heated molten state.

[0032] S1.3. Based on the topological logic of the inverted frustum, the target geometric parameters are subjected to surface fitting and spatial discretization to generate the target morphology model of the growth column.

[0033] Furthermore, based on the topological logic of the inverted frustum cone, the target geometric parameters are fitted to a surface to construct a continuous geometric surface. This continuous geometric surface is then converted into topologically related mesh or lattice data through spatial discretization. Finally, after integration, a growth column target morphology model is generated to guide subsequent deposition processing.

[0034] S2. The target morphology model of the growth column is converted into spatial coordinate instructions, and the deposition energy field is controlled to deposit metallic conductive materials in the electrode area of ​​the wafer to be processed. By dynamically adjusting the pulse frequency and energy distribution density, growth columns are prepared in the electrode area.

[0035] S2.1 Using the slicing algorithm, the continuous geometric surface data in the growth column target morphology model is discretized into a lattice sequence to generate spatial coordinate instructions; Furthermore, continuous geometric surface data is extracted from the growth column target morphology model, and the continuous geometric surface data is input into the slicing algorithm. The slicing algorithm is used to perform discretization and layering processing on the growth column target morphology model along the axial height to obtain the horizontal cross-sectional contour of each layer. Internal path filling and edge sampling are performed on the horizontal cross-sectional contour of each layer to generate a high-density dot matrix sequence. Finally, the dot matrix sequence is encapsulated into a spatial coordinate instruction with motion trajectory information.

[0036] It should be noted that the slicing algorithm is the core logic in 3D additive manufacturing and CNC machining. It uses a set of parallel planes with equal or variable spacing to cut and sample the 3D model, reducing the complexity of the continuous geometry into a series of ordered two-dimensional horizontal cross-sectional contours.

[0037] S2.2 Transmit spatial coordinate commands to the control circuit, control the deposition energy field to align with the electrode area of ​​the wafer to be processed, determine the starting physical point of the metal conductive material deposition, and start deposition.

[0038] Furthermore, the spatial coordinate command is transmitted to the control circuit, which parses the dot matrix sequence information in the spatial coordinate command to drive the deposition energy field to deflect and position, so that the deposition energy field is precisely aligned with the electrode area on the surface of the wafer to be processed, and locks the starting physical point of the accumulation of metal conductive material in the electrode area, thereby activating energy release and inducing the metal conductive material to perform the first layer deposition at the starting physical point.

[0039] S2.3 Real-time monitoring of deposition height; based on the cross-sectional changes of the growth column target morphology model, the vertical growth rate of the metallic conductive material on the wafer to be processed is controlled by real-time calculation and adjustment of the pulse frequency. Furthermore, during the deposition of the conductive metal material, the deposition height of the current deposition layer is monitored in real time; the deposition height of the current deposition layer is compared with the cross-sectional geometric parameters at the corresponding height position in the growth column target morphology model, and the vertical growth rate adjustment amount required to match the target morphology is calculated; based on the required vertical growth rate adjustment amount, the pulse frequency of the deposition energy field is calculated and dynamically adjusted in real time, thereby precisely controlling the vertical growth rate of the conductive metal material on the wafer to be processed.

[0040] S2.4 While adjusting the pulse frequency, based on the structural characteristics of the inverted truncated cone, the energy distribution density is increased simultaneously, and the spread of the metallic conductive material to the surrounding area is gradually increased to form an inverted truncated cone shape. Furthermore, while adjusting the pulse frequency of the deposition energy field, the required lateral spreading range of the current deposition layer is determined layer by layer based on the structural characteristics of the inverted frustum in the target morphology model of the growth column. Based on the required lateral spreading range of the current deposition layer, the energy distribution density of the deposition energy field in the electrode area is simultaneously increased, so that the spreading range of the metallic conductive material in each deposition layer increases layer by layer according to the inverted frustum outline requirement. The entire process ensures that the three-dimensional structure formed by the accumulation strictly conforms to the inverted frustum morphology through the coordinated control of pulse frequency and energy distribution density.

[0041] It should be noted that the structural features of the inverted frustum are obtained by acquiring the surface topology parameters of the wafer to be processed and the preset rheological properties of the solder paste, and by using the liquid bridge morphology evolution algorithm to calculate the target geometric parameters that can generate the maximum liquid bridge restoring force, thereby generating the target morphology model.

[0042] S2.5. Real-time monitoring of the diameter-to-height ratio. When the diameter-to-height ratio matches the target diameter-to-height ratio and the energy field of the top layer of the inverted frustum-shaped structure is released, a growth column is generated.

[0043] Furthermore, displacement sensors are used to capture real-time deposition height and visual monitoring is used to obtain instantaneous cross-sectional diameter. The dynamic diameter-to-height ratio is obtained through division. The dynamic diameter-to-height ratio is continuously compared with the target diameter-to-height ratio. When the dynamic diameter-to-height ratio and the target diameter-to-height ratio tend to be consistent and the deposition energy field completes the end release of the top layer of the inverted frustum shape, the deposition of the metallic conductive material is stopped and a growth column is generated.

[0044] It should be noted that the target diameter-to-height ratio is obtained by calculating the ratio of the column height parameter to the corresponding cross-sectional feature diameter parameter in the target morphology model of the growth column.

[0045] S3. Extract the three-dimensional contour information of the growth column from the growth column, compare the three-dimensional contour information of the growth column with the target morphological model of the growth column, and generate a morphological error matrix.

[0046] S3.1 Using the origin, axial direction and electrode region boundary of the growth column target morphology model as coordinate references, perform three-dimensional sampling on the growth column to generate three-dimensional contour information of the growth column; Furthermore, the central origin, central axis, and electrode region boundary of the growth column target morphology model are established as a unified coordinate reference; based on the coordinate reference, the growth column is subjected to high-precision physical surface scanning and three-dimensional sampling, and contour point cloud data is obtained; the contour point cloud data is subjected to structured integration and noise reduction processing to generate three-dimensional contour information of the growth column that can accurately characterize the physical entity.

[0047] S3.2 Using the coordinate datum as a unified reference, the three-dimensional contour information of the growth column is spatially aligned with the target morphology model of the growth column, and the registration parameters are obtained. Furthermore, using the coordinate reference as a unified reference, geometric feature point sets are extracted from the 3D contour information of the growth column and the target morphological model of the growth column, respectively. Through iterative nearest neighbor matching, spatial pose matching is performed on the two sets of geometric feature point sets, and the spatial transformation matrix is ​​solved. Rotation and translation transformation operations are performed on the 3D contour information of the growth column using the spatial transformation matrix to generate a point cloud to be registered. Iterative nearest neighbor matching is performed on the point cloud to be registered and the target morphological model of the growth column to eliminate residual pose offset. Finally, when the overlap between the point cloud to be registered and the target morphological model of the growth column is maximized, the registration parameters are obtained.

[0048] It should be noted that the registration parameters are a set of pose transformation parameters used to unify the three-dimensional contour information of the growth column with the target morphological model of the growth column under the same coordinate reference. They include translation and rotation, and are used to transform the coordinates of the contour points in the three-dimensional contour information of the growth column to a spatial position and orientation consistent with the target morphological model of the growth column. This ensures that the subsequent nearest neighbor mapping obtains a stable correspondence between the contour points and the target surface and supports the calculation of the morphological error matrix.

[0049] S3.3. Based on the correspondence between registration parameters and contour points-target surface, calculate the error vector field on the sampling profile sequence to generate the morphological error matrix.

[0050] Furthermore, the registration parameters are used to map the three-dimensional contour information of the growth column to the coordinate frame of the growth column target morphology model. Based on the principle of nearest neighbor in spatial position, the point-to-surface mapping relationship between the contour sampling points and the target surface is established. The coordinate difference of the corresponding points is extracted at each height level of the sampling profile sequence to construct an error vector field. By performing structured extraction and numerical encapsulation of the magnitude and direction of each vector in the error vector field, a morphological error matrix for correcting the processing trajectory is finally generated.

[0051] It should be noted that the correspondence between contour points and the target surface is obtained by performing nearest neighbor mapping on the contour points in the three-dimensional contour information of the growth column on the surface of the growth column target morphology model based on the registration parameters; the sampling profile sequence is formed by truncating the three-dimensional contour information of the growth column along the column height direction at a fixed step distance based on the discrete height index in the column height direction of the growth column target morphology model; in the field of geometric calculation and data processing, the spatial nearest neighbor principle is a logical criterion based on Euclidean spatial distance to find the point closest to the target point in a given set of points.

[0052] S4. The etching trajectory is corrected using the morphological error matrix, and the energy distribution is controlled to construct an increasing wetting energy level gradient from the center to the edge at the top of the growth column.

[0053] S4.1 Extract the deviation component of each coordinate point from the morphological error matrix, convert the deviation component into a compensation displacement vector, superimpose it into the initial etching trajectory, and calculate the corrected etching trajectory.

[0054] Furthermore, the deviation components corresponding to each coordinate point are extracted from the morphological error matrix point by point. The deviation components are then reverse-mapped and transformed into compensation displacement vectors with direction and magnitude. Through vector synthesis operation, the compensation displacement vectors are superimposed on the corresponding spatial nodes of the initial etching trajectory in real time. Finally, the trajectory coordinates are recalculated and aligned, and the corrected etching trajectory that can eliminate morphological deviations is output.

[0055] S4.2. The corrected etching trajectory is used as the sweeping guidance command of the energy beam. By adjusting the dwell time and duty cycle of the energy beam at different coordinate points, the energy distribution at the top of the growth column is controlled, and an infiltration energy level gradient that increases from the center to the edge is constructed.

[0056] Furthermore, the corrected etching trajectory is converted into specific sweep guidance commands to drive the energy beam to perform precise displacement. During the movement of the energy beam along the corrected etching trajectory, the dwell time of the energy beam at different coordinate points is changed in real time, and the duty cycle of the pulse signal is adjusted synchronously to differentiate the energy distribution density at the top of the growth column. The controlled energy distribution density is used to induce continuous changes in the surface physicochemical properties, and finally a wetting energy level gradient that increases from the center to the edge is constructed on the surface of the growth column.

[0057] S5. Based on the wetting energy level gradient, calculate the thermodynamic stability value of the growth column, and based on the thermodynamic stability value, select qualified growth columns and construct a growth column array.

[0058] S5.1 Collect gradient distribution data of the wetting energy level gradient at the top of the growth column, and calculate the Gibbs surface free energy of the growth column under high temperature environment based on the gradient distribution data. Furthermore, optical characterization techniques were used to detect the wetting energy level gradient at the top of the growth column, and the contact angle measurements corresponding to each spatial coordinate point were extracted and converted into gradient distribution data. The component energy parameters of different regions of the surface were calculated using the gradient distribution data, and the component energy parameters were nonlinearly accumulated using a temperature correction coefficient under high temperature conditions. Finally, the Gibbs surface free energy, which reflects the thermodynamic stability of the growth column interface, was calculated.

[0059] S5.2. Convert the Gibbs surface free energy into a functional minimizing the interfacial potential energy, solve the functional minimizing the interfacial potential energy, and output the thermodynamic stability value. Furthermore, substituting the Gibbs surface free energy density corresponding to the Gibbs surface free energy into the space surface integral equation, we construct a functional for minimizing the interface potential energy, expressed as: ; In the formula, It is a functional that minimizes the interface potential energy; It is by The enclosed volume region; It is the Gibbs surface free energy density; It is a spatial position vector on the curved surface; This is the local interface temperature at the free interface between the top of the growth column and the liquid solder during the solidification and melting stage. It is a surface area infinitesimal element; It is a volumetric infinitesimal element; It is the volume of molten solder that participates in the evolution of liquid bridge morphology during the solidification and melting stage; They are Lagrange multipliers; Using a variational iterative operator, the extremum of the functional minimizing the interface potential energy is optimized. Through multiple iterations, a convergent solution reflecting the minimum interface energy is locked. Finally, based on the degree of deviation between the convergent solution and the initial morphology, a standardized transformation is performed to output a value for measuring the thermodynamic stability of the growth column to measure its resistance to deformation.

[0060] S5.3 Based on thermodynamic stability values, growth columns with geometric deformation below the allowable error in the high-temperature reflow soldering environment are identified as qualified growth columns. Furthermore, for each growth column, the minimum solution of the interfacial potential energy corresponding to the thermodynamic stability value is used as the benchmark to determine whether it is a strict local minimum: on the one hand, the first variation satisfies the stationary point condition (the derivative of the potential energy with respect to deformation is zero); on the other hand, for all allowed small deformation perturbations, the operator corresponding to the second variation is positive definite, and the iteration from different initial morphologies will converge to the same minimum solution; only growth columns that simultaneously satisfy the above two conditions are judged as qualified growth columns.

[0061] S5.4 Extract the spatial coordinate information of each qualified growth column, and verify the spatial overlap with the preset point matrix. Remove unqualified sites, and perform physical point mapping on the electrode distribution map of the wafer to be processed to output the growth column array.

[0062] Furthermore, spatial coordinate information is extracted from qualified growth columns one by one to form a coordinate list, and the spatial overlap between the coordinate list and the preset point matrix is ​​calculated point by point to generate matching marks; after identifying and eliminating unqualified sites based on the matching marks, a valid coordinate list is generated; physical point mapping is performed on the electrode distribution map of the wafer to be processed using the valid coordinate list to generate a coordinate set of the corresponding electrode positions, and finally the coordinate set is encapsulated and output as a growth column array.

[0063] It should be noted that the dot matrix is ​​set based on the geometric position and spacing of the electrodes on the wafer to be processed, the density and array shape of the target growth pillars, and the alignment tolerance and allowable error requirements.

[0064] S6. Based on the growth column array, a self-aligned liquid bridge restoring force is generated during the die bonding and melting stage, and the chip self-alignment and orientation correction are induced to obtain a flip-chip LED.

[0065] S6.1 During the die bonding and melting stage, the wetting energy level gradient at the top of the growth column array is used to induce the liquid solder to spread asymmetrically. The asymmetric spreading causes the liquid bridge morphology to evolve, generating a surface tension vector pointing towards the center of the electrode region. Furthermore, during the solidification and melting stage, the liquid solder comes into contact with the top of the growth column array and forms an asymmetric spread under the action of the wetting energy level gradient; the asymmetric spread serves as the initial state to trigger the evolution of the liquid bridge morphology and continuously updates the spread boundary and curvature distribution; the change in curvature distribution converges into a surface tension vector pointing towards the center of the electrode region during the evolution of the liquid bridge morphology.

[0066] S6.2. The surface tension vector is synthesized into a self-aligning liquid bridge restoring force, and the spatial pose of the flip-chip to be calibrated is calibrated by acting on the center of gravity of the flip-chip to be calibrated, thereby obtaining the flip-chip.

[0067] Furthermore, the surface tension vector is vector synthesized to obtain the self-aligned liquid bridge restoring force, and the line of action of the self-aligned liquid bridge restoring force is projected onto the center of gravity of the flip-chip to be calibrated to form a calibration value; based on the calibration value, a reverse correction is applied to the spatial pose of the flip-chip to be calibrated to eliminate pose deviation and complete the spatial pose calibration; the flip-chip to be calibrated after spatial pose calibration is the flip-chip.

[0068] In summary, this invention constructs an inverted frustum growth pillar model by coupling wafer topology and solder paste rheological properties, and utilizes a dynamic pulse energy field to achieve precise deposition of microstructures. Subsequently, a wetting energy level gradient increasing from the center to the edge is constructed at the top of the growth pillar, combined with thermodynamic stability screening, thereby inducing asymmetric spreading and self-aligned liquid bridge recovery force of the liquid solder during the die bonding and melting stage, realizing active pose correction and high-precision anti-die bonding fabrication of flip-chip LEDs.

[0069] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A novel method for fabricating a solid bias-resistant chip, characterized in that: include, The surface topology parameters of the wafer to be processed are collected, and combined with the preset solder paste rheological properties, the target geometric parameters are calculated by the liquid bridge morphology evolution algorithm, and the growth column target morphology model is generated based on the target geometric parameters. The target morphology model of the growth column is converted into spatial coordinate instructions, and the deposition energy field is controlled to deposit metallic conductive materials in the electrode area of ​​the wafer to be processed. By dynamically adjusting the pulse frequency and energy distribution density, growth columns are prepared in the electrode area. The three-dimensional contour information of the growth column is extracted, and the three-dimensional contour information of the growth column is compared with the target morphological model of the growth column to generate a morphological error matrix. The etching trajectory is corrected by using the morphological error matrix and the energy distribution is controlled to create an increasing wetting energy gradient from the center to the edge at the top of the growth column. Based on the wetting energy level gradient, the thermodynamic stability values ​​of the growth columns are calculated, and qualified growth columns are selected based on the thermodynamic stability values, and a growth column array is constructed. Based on the growth column array, a self-aligned liquid bridge restoring force is generated during the die bonding and melting stage, which induces the chip to self-align and correct its orientation, thus obtaining a flip-chip LED.

2. The novel anti-fixed polarization chip fabrication method as described in claim 1, characterized in that: The process involves collecting the surface topology parameters of the wafer to be processed, combining them with preset solder paste rheological properties, calculating the target geometric parameters using a liquid bridge morphology evolution algorithm, and generating a growth pillar target morphology model based on the target geometric parameters. The specific steps are as follows: Scan the electrode region of the wafer to be processed to obtain surface topology parameters, which are then used as spatial boundary conditions. The spatial boundary conditions are coupled with the preset solder paste rheological properties and input into the liquid bridge morphology evolution algorithm for convergence iteration to calculate the target geometric parameters. Based on the topological logic of the inverted frustum, the target geometric parameters are subjected to surface fitting and spatial discretization to generate a growth column target morphology model.

3. The novel anti-polarization chip fabrication method as described in claim 2, characterized in that: The specific steps for converting the growth column target morphology model into spatial coordinate commands and controlling the deposition energy field to deposit metallic conductive material in the electrode region of the wafer to be processed are as follows. Using a slicing algorithm, the continuous geometric surface data in the growth column target morphology model is discretized into a lattice sequence to generate spatial coordinate instructions; The spatial coordinate command is transmitted to the control circuit, which controls the deposition energy field to align with the electrode area of ​​the wafer to be processed, determines the starting physical point of the accumulation of the metallic conductive material, and initiates the deposition.

4. The novel anti-fixed bias chip fabrication method as described in claim 3, characterized in that: The process of fabricating growth columns in the electrode region by dynamically adjusting the pulse frequency and energy distribution density is described in the following steps. Real-time monitoring of deposition height; based on the cross-sectional changes of the growth column target morphology model, the vertical growth rate of the metallic conductive material on the wafer to be processed is controlled by real-time calculation and adjustment of pulse frequency. While adjusting the pulse frequency, the energy distribution density is increased simultaneously according to the structural characteristics of the inverted frustum, and the spread of the metallic conductive material to the surrounding area is gradually increased to form the shape of the inverted frustum. The diameter-to-height ratio is monitored in real time. When the diameter-to-height ratio matches the target diameter-to-height ratio and the energy field of the top layer of the inverted frustum-shaped structure is released, a growth column is generated.

5. The novel anti-fixed polarization chip fabrication method as described in claim 4, characterized in that: The target diameter-to-height ratio is obtained by calculating the ratio of the column height parameter to the corresponding cross-sectional feature diameter parameter in the growth column target morphology model.

6. The novel anti-fixed bias chip fabrication method as described in claim 4, characterized in that: The process involves extracting the three-dimensional contour information of the growth column, comparing this contour information with the target morphological model of the growth column, and generating a morphological error matrix. The specific steps are as follows: Using the origin, axial direction, and electrode region boundary of the growth column target morphology model as coordinate references, three-dimensional sampling is performed on the growth column to generate three-dimensional contour information of the growth column; Using the coordinate datum as a unified reference, the three-dimensional contour information of the growth column is aligned with the target morphology model of the growth column in the execution space, and the registration parameters are obtained. Based on the correspondence between registration parameters and contour points and target surface, an error vector field is calculated on the sampled profile sequence to generate a morphological error matrix.

7. The novel anti-fixed polarization chip fabrication method as described in claim 6, characterized in that: The correspondence between the contour points and the target surface is obtained by performing nearest neighbor mapping on the contour points in the three-dimensional contour information of the growth column based on the registration parameters on the surface of the growth column target morphology model. The sampling profile sequence is formed by extracting the three-dimensional contour information of the growth column along the column height direction at a fixed step distance, based on the discrete height index in the target morphology model of the growth column.

8. The novel anti-fixed polarization chip fabrication method as described in claim 6, characterized in that: The method involves using a morphological error matrix to correct the etching trajectory and controlling the energy distribution to create a wetting energy level gradient that increases from the center to the edge at the top of the growth column. The specific steps are as follows: The deviation components of each coordinate point are extracted from the shape error matrix and converted into compensation displacement vectors, which are then superimposed on the initial etching trajectory to calculate the corrected etching trajectory. The corrected etching trajectory is used as the sweeping guidance command for the energy beam. By adjusting the dwell time and duty cycle of the energy beam at different coordinate points, the energy distribution at the top of the growth column is controlled, thus constructing an infiltration energy level gradient that increases from the center to the edge.

9. The novel anti-fixed polarization chip fabrication method as described in claim 8, characterized in that: The thermodynamic stability of the growth column is calculated based on the wetting energy level gradient. Based on these thermodynamic stability values, qualified growth columns are selected, and a growth column array is constructed. The specific steps are as follows: The gradient distribution data of the wetting energy level gradient at the top of the growth column were collected, and the Gibbs surface free energy of the growth column under high temperature was calculated based on the gradient distribution data. The Gibbs surface free energy is converted into a functional minimizing the interfacial potential energy, and the interfacial potential energy minimization functional is solved to output the thermodynamic stability value. Based on thermodynamic stability values, growth columns with geometric deformation below the tolerance in high-temperature reflow soldering environment are identified as qualified growth columns. Extract the spatial coordinate information of each qualified growth column, verify the spatial overlap with the preset point matrix, remove unqualified sites, and perform physical point mapping on the electrode distribution map of the wafer to be processed to output the growth column array.

10. The novel anti-fixed polarization chip fabrication method as described in claim 9, characterized in that: The method involves generating a self-aligned liquid bridge restoring force during the die bonding and melting stage based on a growth column array, inducing chip self-alignment and orientation correction, and obtaining a flip-chip LED. The specific steps are as follows. During the die bonding and melting stage, the wetting energy level gradient at the top of the growth column array is used to induce the liquid solder to spread asymmetrically. The asymmetric spreading triggers the evolution of the liquid bridge morphology and generates a surface tension vector pointing towards the center of the electrode region. The surface tension vector is used to synthesize a self-aligned liquid bridge restoring force, which is then applied to the center of gravity of the flip-chip to be calibrated to calibrate the spatial pose of the flip-chip and obtain the flip-chip.

Images