Hybrid Intermediate Layer and Its Formation Method

Abstract

This application discloses a hybrid interposer and a method for forming the same. The method includes: providing a glass interposer, the glass interposer including a plurality of discrete functional regions and a cut-out region located between adjacent functional regions, the glass interposer including opposing first and second surfaces; forming a first bonding layer on the first surface of the glass interposer; providing a plurality of silicon interposers, each silicon interposer including opposing third and fourth surfaces, the third surface having a second bonding layer; bonding at least one silicon interposer to each functional region of the glass interposer, such that the second bonding layer and the first bonding layer are mixed-bonded; and forming a molding compound covering the silicon interposers on the first surface of the glass interposer, the molding compound exposing the fourth surface of the silicon interposers. This method improves the size and interconnect density of the interposer and reduces the warpage of the interposer.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more particularly to a hybrid interposer and a method for forming the same. Background Technology

[0002] With the development of high-performance computing, artificial intelligence and other fields, chip packaging needs to integrate more and larger chips (such as CPU, GPU, HBM), which places extremely high demands on the size and performance of the interposer.

[0003] One approach is to use a silicon interposer, which offers extremely high interconnect density and excellent electrical and thermal properties. However, due to high cost and size limitations, it is difficult to provide ultra-large silicon interposers (several exposure fields) on a single substrate while ensuring high yield. Another approach is to use organic interposers, which can solve the problem of not being able to fabricate large sizes with a single silicon interposer and provide a large-size interposer solution. However, its interconnect density and electrical performance are lower. Furthermore, the mismatch in the coefficient of thermal expansion (CTE) between organic and silicon materials can easily cause warping, posing significant challenges to manufacturing and subsequent thermal cycling reliability. Summary of the Invention

[0004] The purpose of this application is to provide a hybrid interposer and a method for forming the same, which improves the size and interconnect density of the interposer and reduces the warpage of the interposer.

[0005] To achieve the above objectives, in a first aspect, embodiments of this application provide a method for forming a hybrid intermediary layer, comprising:

[0006] A glass interposer layer is provided, the glass interposer layer including a plurality of discrete functional regions and a cut-out region located between adjacent functional regions, the glass interposer layer including opposing first and second surfaces; A first bonding layer is formed on the first surface of the glass interlayer; A plurality of silicon interposers are provided, each of the silicon interposers including opposing third and fourth surfaces, the third surface having a second bonding layer; At least one silicon interposer is bonded to each functional region of the glass interposer, such that the second bonding layer and the first bonding layer are co-bonded; A molding compound covering the silicon interlayer is formed on the first surface of the glass interlayer, the molding compound exposing the fourth surface of the silicon interlayer.

[0007] In some embodiments of this application, bonding at least one of the silicon interposers to each functional region of the glass interposer includes: One silicon interposer is bonded to each functional region of the glass interposer, or multiple silicon interposers are bonded to each functional region of the glass interposer.

[0008] In some embodiments of this application, when multiple silicon interposers are bonded to each functional region of the glass interposer, the multiple silicon interposers are of the same size.

[0009] In some embodiments of this application, when multiple silicon interposers are bonded to each functional region of the glass interposer, the multiple silicon interposers have different sizes.

[0010] In some embodiments of this application, the first bonding layer includes a first bonding dielectric layer and a first bonding metal pad located in the first bonding dielectric layer, wherein the top surface of the first bonding dielectric layer exposes the surface of the first bonding metal pad.

[0011] In some embodiments of this application, the material of the first bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the first bonding metal pad includes copper, copper alloy or titanium.

[0012] In some embodiments of this application, a first redistribution layer is formed on a first surface of the glass interposer before the first bonding layer is formed; After the first redistribution layer is formed, the first bonding layer is formed on the first redistribution layer.

[0013] In some embodiments of this application, the first redistribution layer includes a first dielectric layer and a first metal line located in the first dielectric layer; The material of the first dielectric layer includes inorganic materials.

[0014] In some embodiments of this application, a portion of the first metal line is electrically connected to a portion of the first bonding metal pad.

[0015] In some embodiments of this application, the glass interposer has a glass via interconnect structure penetrating the first and second surfaces, and the glass via interconnect structure is electrically connected to the first metal line.

[0016] In some embodiments of this application, the second bonding layer includes a second bonding dielectric layer and a second bonding metal pad located in the second bonding dielectric layer, wherein the top surface of the second bonding dielectric layer exposes the surface of the second bonding metal pad.

[0017] In some embodiments of this application, the material of the second bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the second bonding metal pad includes one of copper, copper alloy or titanium.

[0018] In some embodiments of this application, the third or fourth surface of the silicon interposer has a second redistribution layer.

[0019] In some embodiments of this application, the second redistribution layer includes a second dielectric layer and a second metal line located in the second dielectric layer; The material of the second dielectric layer includes inorganic materials. In some embodiments of this application, the silicon interposer has a through-silicon via (TSV) interconnect structure. The through-silicon via (TSV) interconnect structure is electrically connected to the second metal line.

[0020] In some embodiments of this application, a plurality of silicon interposers are provided, including: A silicon wafer is provided, the silicon wafer including the opposing third and fourth surfaces, the silicon wafer including a plurality of grain regions and cleavages located between adjacent grain regions; The through-silicon via (TSV) interconnect structure is formed in each of the said grain regions of the silicon wafer, and the third surface exposes the top of the TSV interconnect structure; A second redistribution layer is formed on the third surface, and a second metal line in the second redistribution layer is electrically connected to the top of the through-silicon via interconnect structure. The second bonding layer is formed on the second redistribution layer; The silicon wafer is cut along the dicing path to form multiple discrete silicon interposers.

[0021] In some embodiments of this application, after the second bonding layer is formed on the second redistribution layer and before the fourth surface of the silicon wafer is thinned, the method further includes: thinning the fourth surface of the silicon wafer to expose the bottom end of the through-silicon via interconnect structure; Alternatively, after bonding the silicon interposer to the functional region of the glass interposer, the fourth surface of the silicon interposer is thinned to expose the bottom end of the through-silicon via interconnect structure.

[0022] In some embodiments of this application, a plurality of silicon interposers are provided, including: A silicon wafer is provided, the silicon wafer including the opposing third and fourth surfaces, the silicon wafer including a plurality of grain regions and cleavages located between adjacent grain regions; The through-silicon via (TSV) interconnect structure is formed in each of the said grain regions of the silicon wafer, and the fourth surface exposes the top of the TSV interconnect structure; A second redistribution layer is formed on the fourth surface, and a second metal line in the second redistribution layer is electrically connected to the top of the through-silicon via interconnect structure. The third surface of the silicon wafer is thinned to expose the bottom end of the through-silicon via interconnect structure; A second bonding layer is formed on the thinned third surface; The silicon wafer is cut along the dicing path to form multiple discrete silicon interposers.

[0023] In some embodiments of this application, the method further includes: mounting a semiconductor chip on the molding compound, wherein the semiconductor chip is electrically connected to the silicon interposer; The second surface of the glass interlayer is thinned; A third redistribution layer is formed on the thinned second surface; Solder protrusions are formed on the third redistribution layer.

[0024] Secondly, embodiments of this application also provide a hybrid intermediary layer, comprising: A glass interlayer, the glass interlayer comprising opposing first and second surfaces; A first bonding layer located on the first surface of the glass interlayer; At least one silicon interposer, each of the silicon interposers including opposing third and fourth surfaces, the third surface having a second bonding layer, at least one of the silicon interposers being bonded to the glass interposer, the second bonding layer and the first bonding layer being co-bonded; A molding compound covering the silicon interposer is located on the first surface of the glass interposer, and the molding compound exposes the fourth surface of the silicon interposer.

[0025] In some embodiments of this application, when multiple silicon interposers are bonded to the glass interposer, the dimensions of the multiple silicon interposers may be the same or different.

[0026] In some embodiments of this application, the first bonding layer includes a first bonding dielectric layer and a first bonding metal pad located in the first bonding dielectric layer, wherein the top surface of the first bonding dielectric layer exposes the surface of the first bonding metal pad; The material of the first bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the first bonding metal pad includes copper, copper alloy or titanium.

[0027] In some embodiments of this application, a first rewiring layer is also included, located on a first surface of the glass interposer layer; The first bonding layer is located on the first redistribution layer.

[0028] In some embodiments of this application, the first redistribution layer includes a first dielectric layer and a first metal line located in the first dielectric layer; The material of the first dielectric layer includes inorganic materials; A portion of the first metal circuit is electrically connected to a portion of the first bonding metal pad; The glass interposer has a glass via interconnect structure that extends through the first and second surfaces, and the glass via interconnect structure is electrically connected to the first metal line.

[0029] In some embodiments of this application, the second bonding layer includes a second bonding dielectric layer and a second bonding metal pad located in the second bonding dielectric layer, wherein the top surface of the second bonding dielectric layer exposes the surface of the second bonding metal pad; The material of the second bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the second bonding metal pad includes one of copper, copper alloy or titanium.

[0030] In some embodiments of this application, a second redistribution layer is also included, located on a third or fourth surface of the silicon interposer.

[0031] In some embodiments of this application, the second redistribution layer includes a second dielectric layer and a second metal line located in the second dielectric layer; The material of the second dielectric layer includes inorganic materials; The silicon interposer has a silicon via interconnect structure that extends through the third and fourth surfaces; The through-silicon via (TSV) interconnect structure is electrically connected to the second metal line.

[0032] In some embodiments of this application, it further includes: a semiconductor chip mounted on the molding compound, the semiconductor chip being electrically connected to the silicon interposer; A third redistribution layer located on the second surface of the glass interposer layer; The solder protrusion is located on the third redistribution layer.

[0033] The beneficial effects of this application are: This application discloses a hybrid interposer and a method for forming the same. The method includes: providing a glass interposer comprising a plurality of discrete functional regions and a cut-out region located between adjacent functional regions, the glass interposer comprising opposing first and second surfaces; forming a first bonding layer on the first surface of the glass interposer; providing a plurality of silicon interposers, each silicon interposer comprising opposing third and fourth surfaces, the third surface having a second bonding layer; bonding at least one silicon interposer to each functional region of the glass interposer, such that the second bonding layer and the first bonding layer are mixed-bonded; and forming a molding compound covering the silicon interposers on the first surface of the glass interposer, the molding compound exposing the fourth surface of the silicon interposers. In this application, at least one small-sized silicon interposer is bonded to a large-sized glass interposer, effectively realizing the construction of a larger-sized hybrid interposer and overcoming the size limitation of a single silicon interposer.

[0034] Furthermore, the hybrid interposer formed by the glass and silicon interposers utilizes an all-inorganic material (silicon and glass) system, fundamentally eliminating the enormous thermal stress caused by the mismatch in thermal expansion coefficients, achieving ultra-low warpage, and laying the foundation for large-size interposer packaging. Moreover, the glass interposer possesses the inherent advantages of low loss factor and high resistivity, making it ideal for high-speed, high-frequency signal transmission, reducing signal attenuation and crosstalk, and achieving excellent signal integrity. The silicon interposer material is silicon, which not only provides high-density metal wiring but is also an excellent thermal conductor, providing an efficient heat-carrying path for the semiconductor chip subsequently mounted on the fourth surface of the silicon interposer, avoiding the thermal bottlenecks caused by using organic materials.

[0035] Furthermore, when the silicon interposer and the glass interposer are bonded, a hybrid bonding process is performed through a first bonding layer and a second bonding layer. This hybrid bonding provides the resulting hybrid interposer with a micron-level interconnect spacing, which is far superior to microbump technology. This greatly increases the interconnect bandwidth between the glass interposer and the silicon interposer in the hybrid interposer, significantly reduces interconnect resistance and inductance, and improves the overall electrical performance of the hybrid interposer. In addition, the structure formed by hybrid bonding has high mechanical strength and good interface stability, which improves the overall reliability of the hybrid interposer.

[0036] Furthermore, since the glass interposer includes multiple discrete functional regions and cutting regions located between adjacent functional regions, at least one silicon interposer is bonded to each functional region of the glass interposer, and after forming a molding compound covering the silicon interposer on the first surface of the glass interposer, the molding compound and the glass interposer are divided along the cutting regions to form several discrete hybrid interposers, thereby realizing the mass production of hybrid interposers and improving the production efficiency of hybrid interposers. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0038] Figure 1 This is a schematic diagram of the process for forming a hybrid intermediary layer provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure after a glass intermediary layer is provided in the method for forming a hybrid intermediary layer provided in some embodiments of this application; Figure 3 This is a schematic diagram of the structure after a first bonding layer is formed on the first surface of a glass interposer in a method for forming a hybrid interposer provided in some embodiments of this application. Figure 4 This is a schematic diagram of the structure after a silicon wafer is provided in the method for forming a hybrid interposer layer provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure after forming a second bonding layer on the third surface of a silicon wafer in a method for forming a hybrid interposer layer provided in some embodiments of this application; Figure 6 This is a schematic diagram of the structure after forming a second redistribution layer and a second bonding layer on the third surface of a silicon wafer in a method for forming a hybrid interposer layer provided in some embodiments of this application. Figure 7 This is a schematic diagram of the structure after the silicon wafer is cut in the method for forming a hybrid interposer layer provided in some embodiments of this application; Figure 8 This is a schematic diagram of the structure after the dielectric layer in silicon is bonded to the glass interposer in some embodiments of the present application; Figure 9 This is a top view of the structure after multiple silicon dielectric layers of the same size are bonded to a glass interposer in the method for forming a hybrid interposer provided in some embodiments of this application. Figure 10 This is a top view of the structure after multiple silicon dielectric layers of different sizes are bonded to a glass interposer in the method for forming a hybrid interposer provided in some embodiments of this application. Figure 11This is a schematic diagram of the structure after forming the molding compound layer in the method for forming the hybrid interposer layer provided in some embodiments of this application; Figure 12 This is a schematic diagram of the structure after thinning the molding layer in the method for forming a hybrid interposer layer provided in some embodiments of this application. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0041] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0042] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0044] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0045] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0046] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0047] It is understood that in some of the accompanying drawings of this application, adjacent films with the same processing material are drawn as connected to make them resemble the actual structure.

[0048] This application first provides a method for forming a hybrid intermediary layer. Figure 1This is a flowchart illustrating the method for forming a hybrid intermediary layer provided in some embodiments of this application. (Refer to...) Figure 1 The method for forming the hybrid intermediary layer includes the following steps: Step S101: Provide a glass interposer layer, the glass interposer layer including a plurality of discrete functional regions and a cut area located between adjacent functional regions, the glass interposer layer including opposing first and second surfaces; Step S102: A first bonding layer is formed on the first surface of the glass interposer; Step S103: Provide a plurality of silicon interposers, each of the silicon interposers including opposing third and fourth surfaces, the third surface having a second bonding layer; Step S104: At least one silicon interposer is bonded to each functional region of the glass interposer, such that the second bonding layer and the first bonding layer are co-bonded. Step S105: A molding layer covering the silicon interlayer is formed on the first surface of the glass interlayer, the molding layer exposing the fourth surface of the silicon interlayer.

[0049] The method for forming the hybrid intermediary layer is described in detail below with reference to the accompanying drawings in some embodiments.

[0050] First, refer to Figure 1 In conjunction with references Figure 2 In step S101, a glass interposer layer 101 is provided, the glass interposer layer 101 including multiple discrete functional areas ( Figure 2 (Only one functional area is shown as an example) and a cut area located between adjacent functional areas (not shown in the figure), the glass interlayer 101 includes opposing first surface 11 and second surface 12.

[0051] The glass interposer 101 subsequently serves as part of a hybrid interposer, and the glass interposer 101 provides a large-scale process platform for subsequent processes.

[0052] The glass interposer 101 is made of glass, crystals, and the like. Compared to organic material interposers, the glass interposer 101 has ultra-low flatness (extremely flat), a lower coefficient of thermal expansion (CTE), better thermal and mechanical stability, and its CTE is more closely matched with that of the subsequently bonded silicon interposer. This allows the hybrid interposer formed based on the glass interposer 101 and the silicon interposer to use an all-inorganic material (silicon and glass) system, fundamentally eliminating the huge thermal stress caused by the mismatch in CTE, achieving ultra-low warpage, and laying the foundation for large-size interposer packaging. Furthermore, the glass interposer 101 has the inherent advantages of low loss factor and high resistivity, making it ideal for high-speed, high-frequency signal transmission, reducing signal attenuation and crosstalk, and achieving excellent signal integrity. In some embodiments, the CTE of the glass interposer 101 is less than or equal to 9 ppm / ℃, specifically 3 ppm / ℃-4 ppm / ℃ or 6 ppm / ℃-9 ppm / ℃.

[0053] The glass interposer layer 101 can have a relatively thin thickness and a large size. In one embodiment, the thickness of the glass interposer layer 101 is less than 800 micrometers, specifically 300-500 micrometers or 30-200 micrometers. In one example, the glass interposer layer 101 is cuboid in shape, and its size is greater than 30mm × 30mm. Specifically, the size of the glass interposer layer 101 can be 40mm × 40mm, 50mm × 50mm, 60mm × 60mm, 80mm × 80mm, 100mm × 100mm, 110mm × 110mm, 300mm × 300mm, 515mm × 510mm, 600mm × 600mm, or 620mm × 750mm.

[0054] In some embodiments, the glass interposer 101 has a glass via interconnect structure 102 penetrating the first surface 11 and the second surface 12. In some embodiments, the material of the glass via interconnect structure 102 is one or a combination of two or more of the following: copper, tungsten, aluminum, nickel, gold, gallium, silver, and titanium. In one example, the formation process of the glass via interconnect structure 102 includes: forming a glass via (TGV, Through Glass Via) in the glass interposer 101, which can be done using photosensitive glass method, focused power generation method, plasma etching method, laser ablation method, electrochemical discharge machining method, or laser-induced etching method; filling the glass via with a conductive metal material and planarizing the conductive metal material to form the glass via interconnect structure 102, where filling the conductive metal material can be done by electroplating or physical vapor deposition (e.g., sputtering), and planarizing the conductive metal material can be done by chemical mechanical polishing. It should be noted that the second surface 12 of the glass interposer 101 may or may not expose the bottom end of the glass via interconnect structure 102.

[0055] The glass interposer 101 includes multiple discrete functional regions and dicing regions located between adjacent functional regions. At least one silicon interposer is subsequently bonded to each functional region. After subsequent encapsulation, the dicing regions serve as channels for dividing the glass interposer 101 to form several discrete hybrid interposers, thereby enabling the mass production of hybrid interposers and improving the production efficiency of hybrid interposers.

[0056] Next, refer to Figure 1 In conjunction with references Figure 2 Step S102 is performed to form a first bonding layer 104 on the first surface 11 of the glass interposer layer 101.

[0057] The first bonding layer 104 is used to bond with the subsequent silicon interposer 201 (see reference). Figure 8 The second bonding layer 204 of the third surface 13 of the hybrid interposer is hybrid bonded, thereby providing micron-level interconnect spacing for the subsequently formed hybrid interposer, which is far superior to microbump technology. This greatly increases the interconnect bandwidth between the glass interposer 101 and the silicon interposer 201 in the hybrid interposer, significantly reduces interconnect resistance and inductance, and improves the overall electrical performance of the hybrid interposer. Furthermore, the structure formed by hybrid bonding has high mechanical strength and good interface stability, which improves the overall reliability of the hybrid interposer.

[0058] In some embodiments, the first bonding layer 104 includes a first bonding dielectric layer 104a and a first bonding metal pad 104b located in the first bonding dielectric layer 104a, wherein the top surface of the first bonding dielectric layer 104a exposes the surface of the first bonding metal pad 104b. In one example, the material of the first bonding dielectric layer 104a includes one of silicon oxide, titanium oxide, or silicon carbide; the material of the first bonding metal pad 104b includes one of copper, copper alloy, or titanium.

[0059] In some embodiments, the formation process of the first bonding layer 104 includes: forming a first bonding dielectric layer 104a on the first surface 11 of the glass interposer 101; forming a patterned first photoresist layer (not shown in the figure) on the first bonding dielectric layer 104a; etching the first bonding dielectric layer 104a using the patterned first photoresist layer as a mask to form a plurality of first trenches in the first bonding dielectric layer 104a; removing the patterned first photoresist layer; forming a first bonding metal layer in the first trenches and on the surface of the first bonding dielectric layer 104a; planarizing and removing part of the first bonding metal layer using a chemical mechanical masking process until the first bonding dielectric layer 104a is exposed, and forming a first bonding metal pad 104b in the first trenches.

[0060] In some embodiments, a first redistribution layer 103 is formed on the first surface 11 of the glass interposer 101 before the formation of the first bonding layer 104; after the formation of the first redistribution layer 103, the first bonding layer 104 is formed on the first redistribution layer 103. Due to the density of the glass via interconnect structure in the glass interposer 101 and the subsequent bonding of the silicon interposer 201 (reference 201), Figure 8 The density of the through-silicon via interconnect structure 202 in the two structures will be different, and the reconstruction of the interconnection between the two structures can be achieved through the first redistribution layer 103.

[0061] In some embodiments, the first redistribution layer 103 includes a first dielectric layer 103a and a first metal line 103b located in the first dielectric layer 103a. The first metal line 103b is electrically connected to the glass via interconnect structure 102. The material of the first dielectric layer 103a includes inorganic materials. Specifically, the material of the first dielectric layer 103a includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), and low dielectric constant materials (K less than 2.5). The material of the first metal line 103b includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The number of layers of the first dielectric layer 103a can be single or multiple, and correspondingly, the number of layers of the first metal line 103b can also be single or multiple.

[0062] In some embodiments, a portion of the first metal line 103b is electrically connected to a portion of the first bonding metal pad 104b, and subsequently a silicon interposer 201 (see reference) is applied. Figure 8 The second bonding layer 204 on the first bonding layer 104 is bonded to the first bonding layer 104, and the first metal line 103b can be electrically connected to the silicon interposer 201 through a portion of the first bonding metal pad 104b.

[0063] Next, refer to Figure 1 In conjunction with references Figure 7 In step S103, a plurality of silicon interposers 201 are provided, each of the silicon interposers 201 including opposing third surfaces 13 and fourth surfaces 14, wherein the third surface 13 has a second bonding layer 204.

[0064] The silicon interposer 201 is subsequently used for bonding to the glass interposer 101, and the silicon interposer 201 is part of the hybrid interposer. The silicon interposer 201 is made of silicon, which not only provides high-density metal wiring, but also is an excellent thermal conductor, providing an efficient heat dissipation path for the semiconductor chip subsequently mounted on the fourth surface of the silicon interposer 201, avoiding the thermal bottleneck caused by the use of organic materials.

[0065] The silicon interposer 201 is relatively small, much smaller than the glass interposer 101, and smaller than the size of a functional region within the glass interposer 101.

[0066] The second bonding layer 204 is subsequently mixed-bonded with the first bonding layer 104.

[0067] In some embodiments, the second bonding layer 204 includes a second bonding dielectric layer 204a and a second bonding metal pad 204b located in the second bonding dielectric layer 204a, wherein the top surface of the second bonding dielectric layer 204a exposes the surface of the second bonding metal pad 204b. In one example, the material of the second bonding dielectric layer 204a includes silicon oxide, titanium oxide, or silicon carbide; the material of the second bonding metal pad 204b includes copper, a copper alloy, or titanium.

[0068] In some embodiments, when the third surface 13 serves as the front side of the silicon interposer 201 and the corresponding fourth surface 14 serves as the back side of the silicon interposer 201, the third surface 13 of the silicon interposer 201 has a second redistribution layer 203 (see reference). Figure 6 The second redistribution layer 203 has a high density of metal lines, and the second bonding layer 204 is located on the second redistribution layer 203 on the third surface 13. In other embodiments, the second bonding layer 204 is located directly on the third surface 13.

[0069] In other embodiments, when the third surface 13 serves as the back side of the silicon interposer 201 and the corresponding fourth surface 14 serves as the front side of the silicon interposer 201, the fourth surface 14 of the silicon interposer 201 has a second redistribution layer (not shown in the figure), the second redistribution layer has high-density metal lines for connecting subsequent mounted semiconductor chips, and the second bonding layer 204 is located on the third surface 13.

[0070] In a specific example, refer to Figure 6 The second redistribution layer 203 includes a second dielectric layer 203a and a second metal line 203b located in the second dielectric layer 203a. The material of the second dielectric layer 203a includes inorganic materials. Specifically, the material of the second dielectric layer 203a includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), and low dielectric constant materials (K less than 2.5). The material of the second metal line 203b includes one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN. The second dielectric layer 203a can be a single layer or multiple layers, and correspondingly, the second metal line 203b can also be a single layer or multiple layers.

[0071] In some embodiments, the silicon interposer 201 has a through-silicon via (TSV) interconnect structure 202, the TSV interconnect structure 202 being made of one or more of Cu, Al, W, Ag, Au, Pt, Ni, Ti, Ta, TiN, TaN, TaC, and WN; the TSV interconnect structure 202 is electrically connected to the second metal circuit. In one example, the third surface 13 or the fourth surface 14 of the silicon interposer 201 exposes the top end of the TSV interconnect structure 202, and the bottom end of the TSV interconnect structure 202 is located within the silicon interposer 201, subsequently exposed by thinning the silicon interposer 201.

[0072] Different process steps can be used to form the silicon interposer 201.

[0073] In one specific embodiment, providing a plurality of silicon interposers 201 includes: refer to Figure 4 A silicon wafer 200 is provided, the silicon wafer 200 including the opposing third surface 13 and fourth surface 14, the silicon wafer 200 including a plurality of grain regions and dicing channels located between adjacent grain regions, each grain region may subsequently form a silicon interposer layer; Continue to refer to Figure 4 The through-silicon via (TSV) interconnect structure 202 is formed in each of the said grain regions of the silicon wafer 200, the third surface 13 exposes the top end of the TSV interconnect structure 202, and the bottom end of the TSV interconnect structure 202 is located in the silicon wafer 200; in some embodiments, reference is made to... Figure 6 It also includes: forming a second redistribution layer 203 on the third surface 13, wherein a second metal line 203b in the second redistribution layer 203 is electrically connected to the top end of the through-silicon via interconnect structure 202; refer to Figure 5 A second bonding dielectric layer 204 is formed on the third surface 13. In one specific embodiment, the formation process of the second bonding layer 204 includes: forming a second bonding dielectric layer 204a on the second redistribution layer; forming a patterned second photoresist layer on the second bonding dielectric layer 204a; etching the second bonding dielectric layer 204a using the patterned second photoresist layer as a mask to form a plurality of second trenches in the second bonding dielectric layer 204a; removing the patterned second photoresist layer; forming a second bonding metal layer in the second trenches and on the surface of the second bonding dielectric layer 204a; planarizing and removing part of the second bonding metal layer using a chemical mechanical masking process until the second bonding dielectric layer 204a is exposed, and forming a second bonding metal pad 204b in the second trenches; in some embodiments, refer to Figure 6The second bonding dielectric layer 204 is formed on the second redistribution layer 204 on the third surface 13; refer to Figure 7 The silicon wafer is diced along the dicing path to form multiple discrete silicon interposers 201. It should be noted that the bottom end of the through-silicon via (TSV) interconnect 202 can be exposed in different process steps; in one example, refer to... Figure 5 After the formation of the second bonding layer 204 and before dicing the silicon wafer along the dicing path, the method further includes: thinning the third surface 13 of the silicon wafer 200 to expose the bottom end of the through-silicon via interconnect 202. In another example, the bottom end of the through-silicon via interconnect 202 is not exposed before dicing (see reference). Figure 6 Subsequently, after bonding the silicon interposer 201 to the functional area of ​​the glass interposer 101, the fourth surface 14 of the silicon interposer 201 is thinned to expose the bottom end of the silicon through-hole interconnect structure 202.

[0074] In another specific embodiment, providing a plurality of silicon interposers 201 includes: A silicon wafer is provided, the silicon wafer including the opposing third and fourth surfaces, the silicon wafer including a plurality of grain regions and cleavages located between adjacent grain regions; The through-silicon via (TSV) interconnect structure is formed in each of the said grain regions of the silicon wafer, and the fourth surface exposes the top of the TSV interconnect structure; A second redistribution layer is formed on the fourth surface, and a second metal line in the second redistribution layer is electrically connected to the top of the through-silicon via interconnect structure. The third surface of the silicon wafer is thinned to expose the bottom end of the through-silicon via interconnect structure; A second bonding layer is formed on the thinned third surface; The silicon wafer is cut along the dicing path to form multiple discrete silicon interposers.

[0075] Next, refer to Figure 1 In conjunction with references Figure 8 In step S104, at least one silicon interposer 201 is bonded to each functional region 15 of the glass interposer 101, such that the second bonding layer 204 and the first bonding layer 104 are co-bonded.

[0076] At least one silicon interposer 201 is bonded to each functional region 15 of the glass interposer 101 using a hybrid bonding process. When the second bonding layer 204 and the first bonding layer 104 are hybrid bonded, the second bonding dielectric layer 204a in the second bonding layer 204 is bonded to the first bonding dielectric layer 104a in the first bonding layer 104, and the second bonding metal pad 204b in the second bonding layer 204 is bonded to the first bonding metal pad 104b in the first bonding layer 104.

[0077] In some embodiments, bonding at least one silicon interposer 201 to each functional region 15 of the glass interposer 101 includes: One silicon interposer 201 is bonded to each functional region 15 of the glass interposer 101, or multiple silicon interposers 201 are bonded to each functional region 15 of the glass interposer 101. In this application, at least one small-sized silicon interposer 201 obtained after dicing is bonded to a large-sized glass interposer 101, which effectively realizes the construction of a larger-sized hybrid interposer and breaks through the size limitation of a single silicon interposer.

[0078] In some embodiments, reference Figure 9 , Figure 9 for Figure 8 A top-view structural diagram. Figure 8 for Figure 9 A cross-sectional structural schematic diagram obtained along the cutting line AB shows that when multiple silicon interposers 201 are bonded to each functional region 15 of the glass interposer 101, the multiple silicon interposers 201 have the same size. In another embodiment, refer to... Figure 10 , Figure 10 for Figure 8 A top-view structural diagram. Figure 8 for Figure 10 The cross-sectional structural diagram obtained along the cutting line AB shows that when multiple silicon interposers 201 are bonded to each functional region 15 of the glass interposer 101, the dimensions of the multiple silicon interposers 201 are different. This allows for the achievement of the same or different wiring densities in different regions of the hybrid interposer, matching semiconductor chips with output ports of different sizes or densities, thereby improving the electrical performance of the hybrid interposer and expanding its application scenarios.

[0079] Finally, refer to Figure 1 In conjunction with references Figure 11 and Figure 12 In step S105, a molding compound 205 is formed on the first surface 11 of the glass interposer 101 to cover the silicon interposer 201, and the molding compound 205 exposes the fourth surface 14 of the silicon interposer 201.

[0080] The material of the molding layer 205 can be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, with or without fillers; or it can be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer, or polyvinyl alcohol, with fillers. The filler can be inorganic or organic. The process for forming the molding layer 205 includes compression molding or transfer molding.

[0081] The molding compound 205 is formed and then thinned so that the molding compound 205 exposes the fourth surface 14 of the silicon interposer 201, so as to facilitate the subsequent mounting of semiconductor chips on the fourth surface.

[0082] In some embodiments, after thinning the molding compound 205, the method further includes: mounting one or more semiconductor chips (not shown) on the fourth surface 14 of the molding compound 205 and the silicon interposer 201, the semiconductor chips being electrically connected to the silicon interposer 201; forming a third redistribution layer (not shown) on the thinned second surface 12 of the glass interposer 101, in one example, the third redistribution layer includes a third dielectric layer and a third metal line located in the third dielectric layer, the third metal line being electrically connected to the glass via interconnect structure 102; forming solder bumps (not shown) on the third redistribution layer, in one example, the solder bumps include solder balls, in another example, the solder bumps include metal pillars and solder balls located on top of the metal pillars; finally, dividing the molding compound 205 and the glass interposer 101 along the cutting region 16 to form a plurality of discrete hybrid interposers.

[0083] This application also provides a hybrid intermediary layer, as referenced in the embodiments. Figure 12 ,include: Glass interlayer 101, the glass interlayer 101 including opposing first surface 11 and second surface 12; The first bonding layer 104 is located on the first surface 11 of the glass interposer layer 101; At least one silicon interposer 201, each of the silicon interposers 201 including opposing third surfaces 13 and fourth surfaces 14, the third surface 13 having a second bonding layer 204, at least one of the silicon interposers 201 being bonded to the glass interposer 101, the second bonding layer 204 and the first bonding layer 104 being co-bonded; A molding layer 205 is placed on the first surface 11 of the glass interposer 101 to cover the silicon interposer 201, and the molding layer 205 exposes the fourth surface 14 of the silicon interposer 201.

[0084] In some embodiments, when a plurality of silicon interposers 201 are bonded to the glass interposer 101, the plurality of silicon interposers 201 may have the same or different dimensions.

[0085] In some embodiments, the first bonding layer 104 includes a first bonding medium layer 104a and a first bonding metal pad 104b located in the first bonding medium layer 104a, wherein the top surface of the first bonding medium layer 104a exposes the surface of the first bonding metal pad 104b. The material of the first bonding dielectric layer 104a includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the first bonding metal pad 104b includes one of copper, copper alloy or titanium.

[0086] In some embodiments, it further includes: a first redistribution layer 103 located on the first surface 11 of the glass interposer layer 101; The first bonding layer 104 is located on the first redistribution layer 103.

[0087] In some embodiments, the first redistribution layer includes a first dielectric layer 103a and a first metal line 103b located in the first dielectric layer 103a; The material of the first dielectric layer 103a includes inorganic materials; A portion of the first metal line 103b is electrically connected to a portion of the first bonding metal pad 104b; The glass interposer 101 has a glass via interconnect structure 102 that penetrates the first surface 11 and the second surface 12, and the glass via interconnect structure 102 is electrically connected to the first metal line 103b.

[0088] In some embodiments, the second bonding layer 204 includes a second bonding medium layer 204a and a second bonding metal pad 204b located in the second bonding medium layer 204a, wherein the top surface of the second bonding medium layer 204a exposes the surface of the second bonding metal pad 204b. The material of the second bonding dielectric layer 204a includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the second bonding metal pad 204b includes one of copper, copper alloy or titanium.

[0089] In some embodiments, it further includes a second redistribution layer (not shown) located on the third surface 13 or the fourth surface 14 of the silicon interposer 201.

[0090] In some embodiments, the second redistribution layer includes a second dielectric layer and a second metal line located in the second dielectric layer; The material of the second dielectric layer includes inorganic materials; The silicon interposer 201 has a silicon via interconnect structure 202 that penetrates the third surface 13 and the fourth surface 14; The through-silicon via interconnect structure 202 is electrically connected to the second metal line.

[0091] In some embodiments, the device further includes: a semiconductor chip mounted on the molding compound 205, the semiconductor chip being electrically connected to the silicon interposer 201; A third redistribution layer is located on the second surface 12 of the glass interposer layer 101; The solder protrusion is located on the third redistribution layer.

[0092] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0093] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0094] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming a hybrid interposer, the method comprising: include: A glass interposer layer is provided, the glass interposer layer including a plurality of discrete functional regions and a cut-out region located between adjacent functional regions, the glass interposer layer including opposing first and second surfaces; A first bonding layer is formed on the first surface of the glass interlayer; A plurality of silicon interposers are provided, each of the silicon interposers including opposing third and fourth surfaces, the third surface having a second bonding layer; At least one silicon interposer is bonded to each functional region of the glass interposer, such that the second bonding layer and the first bonding layer are co-bonded; A molding compound covering the silicon interlayer is formed on the first surface of the glass interlayer, the molding compound exposing the fourth surface of the silicon interlayer.

2. The forming method of a hybrid interposer according to claim 1, wherein Bonding at least one of the silicon interposers to each functional region of the glass interposer comprises: One silicon interposer is bonded to each functional region of the glass interposer, or multiple silicon interposers are bonded to each functional region of the glass interposer.

3. The forming method of a hybrid interposer according to claim 2, wherein When multiple silicon interposers are bonded to each functional region of the glass interposer, the multiple silicon interposers are of the same size.

4. The forming method of a hybrid interposer according to claim 2, wherein When multiple silicon interposers are bonded to each functional region of the glass interposer, the multiple silicon interposers have different sizes.

5. The forming method of a hybrid interposer according to claim 1, wherein The first bonding layer includes a first bonding dielectric layer and a first bonding metal pad located in the first bonding dielectric layer, with the top surface of the first bonding dielectric layer exposing the surface of the first bonding metal pad.

6. The forming method of a hybrid interposer according to claim 5, wherein The material of the first bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the first bonding metal pad includes copper, copper alloy or titanium.

7. The forming method of a hybrid interposer according to claim 5, wherein Before forming the first bonding layer, a first redistribution layer is formed on the first surface of the glass interposer layer; After the first redistribution layer is formed, the first bonding layer is formed on the first redistribution layer.

8. The forming method of a hybrid interposer according to claim 7, wherein The first redistribution layer includes a first dielectric layer and a first metal line located in the first dielectric layer; The material of the first dielectric layer includes inorganic materials; a portion of the first metal circuit is electrically connected to a portion of the first bonding metal pad.

9. The forming method of a hybrid interposer according to claim 8, wherein The glass interposer has a glass via interconnect structure that extends through the first and second surfaces, and the glass via interconnect structure is electrically connected to the first metal line.

10. The forming method of a hybrid interposer according to claim 1, wherein The second bonding layer includes a second bonding dielectric layer and a second bonding metal pad located in the second bonding dielectric layer, wherein the top surface of the second bonding dielectric layer exposes the surface of the second bonding metal pad.

11. The forming method of a hybrid interposer according to claim 10, wherein The material of the second bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the second bonding metal pad includes one of copper, copper alloy or titanium.

12. The forming method of a hybrid interposer according to claim 10, wherein The third or fourth surface of the silicon interposer has a second redistribution layer.

13. The forming method of a hybrid interposer according to claim 12, wherein The second redistribution layer includes a second dielectric layer and a second metal line located in the second dielectric layer; The material of the second dielectric layer includes inorganic materials.

14. The forming method of a hybrid interposer according to claim 13, wherein The silicon interposer has a through-silicon via interconnect structure; The through-silicon via (TSV) interconnect structure is electrically connected to the second metal line.

15. The method of forming a hybrid interposer of claim 14, wherein, Multiple silicon interposers are provided, including: A silicon wafer is provided, the silicon wafer including the opposing third and fourth surfaces, the silicon wafer including a plurality of grain regions and cleavages located between adjacent grain regions; A through-silicon via (TSV) interconnect structure is formed in each of the said grain regions of the silicon wafer, and the third surface exposes the top of the TSV interconnect structure; A second redistribution layer is formed on the third surface, and a second metal line in the second redistribution layer is electrically connected to the top of the through-silicon via interconnect structure. The second bonding layer is formed on the second redistribution layer; The silicon wafer is cut along the dicing path to form multiple discrete silicon interposers.

16. The method of forming a hybrid interposer of claim 14, wherein, After forming the second bonding layer on the second redistribution layer, and before thinning the fourth surface of the silicon wafer, the method further includes: thinning the fourth surface of the silicon wafer to expose the bottom end of the through-silicon via interconnect structure; Alternatively, after bonding the silicon interposer to the functional region of the glass interposer, the fourth surface of the silicon interposer is thinned to expose the bottom end of the through-silicon via interconnect structure.

17. The method of forming a hybrid interposer of claim 14, wherein, Multiple silicon interposers are provided, including: A silicon wafer is provided, the silicon wafer including the opposing third and fourth surfaces, the silicon wafer including a plurality of grain regions and cleavages located between adjacent grain regions; The through-silicon via (TSV) interconnect structure is formed in each of the said grain regions of the silicon wafer, and the fourth surface exposes the top of the TSV interconnect structure; A second redistribution layer is formed on the fourth surface, and a second metal line in the second redistribution layer is electrically connected to the top of the through-silicon via interconnect structure. The third surface of the silicon wafer is thinned to expose the bottom end of the through-silicon via interconnect structure; A second bonding layer is formed on the thinned third surface; The silicon wafer is cut along the dicing path to form multiple discrete silicon interposers.

18. The forming method of a hybrid interposer according to claim 1, wherein Also includes: A semiconductor chip is mounted on the molding compound layer, and the semiconductor chip is electrically connected to the silicon interposer layer. The second surface of the glass interlayer is thinned; A third redistribution layer is formed on the thinned second surface; Solder protrusions are formed on the third redistribution layer.

19. A hybrid interposer, comprising: include: A glass interlayer, the glass interlayer comprising opposing first and second surfaces; A first bonding layer located on the first surface of the glass interlayer; At least one silicon interposer, each of the silicon interposers including opposing third and fourth surfaces, the third surface having a second bonding layer, at least one of the silicon interposers being bonded to the glass interposer, the second bonding layer and the first bonding layer being co-bonded; A molding compound covering the silicon interposer is located on the first surface of the glass interposer, and the molding compound exposes the fourth surface of the silicon interposer.

20. The hybrid interposer of claim 19, wherein, When multiple silicon interposers are bonded to the glass interposer, the multiple silicon interposers may have the same or different dimensions.

21. The hybrid interposer of claim 19, wherein, The first bonding layer includes a first bonding dielectric layer and a first bonding metal pad located in the first bonding dielectric layer, wherein the top surface of the first bonding dielectric layer exposes the surface of the first bonding metal pad; The material of the first bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the first bonding metal pad includes copper, copper alloy or titanium.

22. The hybrid interposer of claim 19, wherein, Also includes: A first rewiring layer located on the first surface of the glass interposer layer; The first bonding layer is located on the first redistribution layer.

23. The hybrid interposer of claim 22, wherein, The first redistribution layer includes a first dielectric layer and a first metal line located in the first dielectric layer; The material of the first dielectric layer includes inorganic materials; A portion of the first metal line is electrically connected to a portion of the first bonding metal pad; The glass interposer has a glass via interconnect structure that extends through the first and second surfaces, and the glass via interconnect structure is electrically connected to the first metal line.

24. The hybrid interposer of claim 19, wherein, The second bonding layer includes a second bonding dielectric layer and a second bonding metal pad located in the second bonding dielectric layer, wherein the top surface of the second bonding dielectric layer exposes the surface of the second bonding metal pad; The material of the second bonding dielectric layer includes one of silicon oxide, titanium oxide, or silicon carbide nitride; The material of the second bonding metal pad includes one of copper, copper alloy or titanium.

25. The hybrid interposer of claim 24, wherein, Also includes: A second redistribution layer located on the third or fourth surface of the silicon interposer.

26. The hybrid interposer of claim 25, wherein, The second redistribution layer includes a second dielectric layer and a second metal line located in the second dielectric layer; The material of the second dielectric layer includes inorganic materials; The silicon interposer has a silicon via interconnect structure that extends through the third and fourth surfaces; The through-silicon via (TSV) interconnect structure is electrically connected to the second metal line.

27. The hybrid interposer layer according to claim 19, characterized in that, Also includes: A semiconductor chip is mounted on the molding compound, and the semiconductor chip is electrically connected to the silicon interposer. A third redistribution layer located on the second surface of the glass interposer layer; The solder protrusion is located on the third redistribution layer.

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