High precision addressable ring oscillator test chip, method, apparatus, and medium

Abstract

The application relates to a high-precision addressable ring oscillator test chip, method, device and medium, which comprises an addressing module, an output module and a plurality of ring oscillator test modules; the ring oscillator test module comprises a signal transmission module, a multifunctional test module and a plurality of ring oscillator test structures; the addressing module is used for selecting a ring oscillator test structure from the ring oscillator test structures of the plurality of ring oscillator test modules to perform a communication test; the multifunctional test module can switch the voltage compensation mode or the small-current test mode of the ring oscillator test structure based on a received control signal; when the characteristic parameters of the ring oscillator are measured, the voltage compensation mode can utilize voltage drop compensation to reduce the influence of the resistance voltage drop introduced in the test path, effectively improving the measurement precision, and the small-current test mode can effectively measure the static power supply current of the ring oscillator.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and manufacturing, and particularly relates to high-precision addressable ring oscillator test chips, methods, apparatus and media. Background Technology

[0002] Measurements from a Ring Oscillation (RO) device can be used to evaluate relevant process parameters and identify and locate yield issues, including the power supply current (IDDA, dynamic power supply current) under dynamic operating conditions, the power supply current (IDDQ, static power supply current) under static operating conditions, and the frequency (freq).

[0003] Current addressable ring oscillator test chips improve the area utilization of the test chip by sharing pads, and do not require probe movement during testing, thus saving test time. At the same time, they can measure the characteristic parameters of the ring oscillator, including IDDA and freq, but cannot support the measurement accuracy requirements of IDDQ.

[0004] Therefore, there is a great need for a solution that can effectively measure the IDDA, freq, and IDDQ parameters of a ring oscillator. Summary of the Invention

[0005] To address all or part of the problems of the prior art, this invention provides a high-precision addressable ring oscillator test chip, a high-precision addressable ring oscillator test method, a high-precision addressable ring oscillator test device, and a computer-readable storage medium.

[0006] Firstly, this embodiment provides a high-precision addressable ring oscillator test chip, including an addressing module (Decoder module), an output module (OUT module), and multiple ring oscillator test modules (BLK modules). The ring oscillator test module includes a signal transmission module, a multi-functional test module, and multiple ring oscillator test structures. The addressing module is used to select a ring oscillator test structure from the ring oscillator test structures (ROcells) of the plurality of ring oscillator test modules for connectivity testing; The multi-functional test module can switch between voltage compensation mode and low current test mode for testing the ring oscillator test structure based on the received control signal (mode control signal OFF). The voltage compensation mode is used to compensate for voltage drop when testing the characteristic parameters of the ring oscillator test structure. The low current test mode is used to test the static power supply current of the ring oscillator test structure.

[0007] In some embodiments, the ring oscillator test module includes multiple ring oscillator test structures (RO cells) and multiple peripheral circuits; The peripheral circuitry includes a signal transmission circuit, a multi-functional test module, a level conversion circuit, and a logic control signal generation circuit. The number of ring oscillator test structures and the number of peripheral circuits are the same, corresponding one-to-one; and the specific number of ring oscillator test structures is proportional to the addressing capability of the addressing module. The multiple ring oscillator test modules (BLK modules) are divided into at least two groups, and each group of ring oscillator modules is powered by an independent power supply; that is, the multiple ring oscillator test modules are at least divided into a first test module group and a second test module group, and are powered separately.

[0008] In some embodiments, the output module (OUT module) includes a 2-to-1 data selector; The 2-to-1 data selector is used to select either the first test module group or the second test module group for output based on the received MUX control signal.

[0009] In some embodiments, the level conversion circuit is used to convert the signal from the voltage of the core region (core voltage) to the voltage of the input / output region (I / O voltage), generating the logic control signal for the voltage required by the multi-functional test module.

[0010] In some embodiments, the logic control signal generation circuit includes a first inverter, a second inverter, a third inverter, and a first NAND gate; The logic control signal generation circuit is connected to the addressing module (Decoder module) and receives the row signal (ROW) and column signal (COL) output by the addressing module. The row and column signals are passed through a NAND gate and then through the first inverter to output the address strobe signal (SEL). The row and column signals are passed through NAND gates, then through the level conversion circuit to be converted into voltages in the input / output region, thus generating the NSELIO signal; The NSELIO signal is passed through the second inverter and then input together with the received mode control signal (OFF) into the first NAND gate to generate the PCONIO signal. The PCONIO signal is passed through the third inverter to output the NCONIO signal.

[0011] In some embodiments, the ring oscillator test structure (RO cell) includes a VDDE pin, a VDDES pin, an OUT pin, and an EBL pin; The VDDE and VDDES pins are connected to the power supply after passing through the multi-functional test module; the OUT pin is transmitted to the output module for output through the signal transmission module; the EBL pin is connected to the output terminal of the AND gate, and the input terminal of the AND gate receives the oscillation signal (EBL) and the address strobe signal (SEL).

[0012] In some embodiments, the ring oscillator test module includes at least one signal transmission module and at least one local frequency divider; Furthermore, the number of signal transmission modules and the number of local frequency dividers are the same, and they correspond one-to-one; The signal transmission module includes multiple signal transmission circuits connected in sequence, and at most only the output result of one signal transmission circuit in the signal transmission module is transmitted as the final output of the signal transmission module.

[0013] In some embodiments, the signal transmission circuit includes a second NAND gate, a fourth inverter, and a first AND gate; The output signal (RO_OUT) of the OUT pin of the ring oscillator test structure (RO cell) is input to the second NAND gate together with the address strobe signal (SEL). After passing through the fourth inverter, it is input to the output result (RO_bit_OUT) of the first AND gate together with the output result (RO_pre_OUT) of the previous signal transmission circuit or the ground voltage signal (VSSC). The output of the last signal transmission circuit in the series of interconnected signal transmission circuits is the final output of the signal transmission module. The ground voltage signal (VSSC) is provided by the first power supply.

[0014] In some embodiments, the multi-functional test module includes a transmission gate and a PMOS; The input terminal of the transmission gate is connected to the power supply, the output terminal is connected to the VDDE pin of the ring oscillator test structure (ROcell), the control terminal is connected to the NCONIO signal, and the complementary control terminal is connected to the PCONIO signal. The source of the PMOS is connected to the power supply, the drain is connected to the VDDES pin of the ring oscillator test structure (RO cell), and the gate is connected to the NSELIO signal.

[0015] Secondly, this embodiment provides a high-precision addressable ring oscillator testing method, which utilizes the high-precision addressable ring oscillator test chip described in the first aspect for testing; The high-precision addressable ring oscillator testing method includes the following steps: Obtain test requirements, including the test structure of the ring oscillator to be tested, the characteristic parameters to be tested, and the accuracy requirements; Based on the aforementioned test requirements, generate the control signals; Based on the received control signals (start-up signal EBL, mode control signal OFF, MUX control signal, address signal, and address selection signal), the ring oscillator test structure to be connected is selected, and the multi-functional test module is switched to test the characteristic parameters to be tested in voltage compensation mode or low current test mode.

[0016] In some embodiments, the plurality of ring oscillator test modules (BLK modules) are divided into at least two groups, each group of ring oscillator modules being powered by an independent power supply; that is, the plurality of ring oscillator test modules are at least divided into a first test module group and a second test module group, and are powered separately. Based on the aforementioned test requirements, the generation of various control signals includes: Using the generated address signal and address selection signal, parallel testing of ring oscillator test structures belonging to different test module groups is supported. Test data is obtained by testing the VDDE pin and VDDES pin of the ring oscillator test structure respectively, or the ring oscillator test structure is selected based on the MUX control signal and the test data is output through the output module.

[0017] In some embodiments, the step of selecting the connected ring oscillator test structure based on the received control signal and switching the multi-functional test module to test the characteristic parameters under test in voltage compensation mode or low current test mode includes: The multi-functional test module performs dynamic power supply current (IDDA) testing on the ring oscillator test structure in voltage compensation mode. The multi-functional test module performs static power supply current (IDDQ) testing on the ring oscillator test structure in voltage compensation mode. The multi-functional test module performs frequency (freq) testing on the ring oscillator test structure in voltage-compensated mode; and / or The multi-functional test module performs static power supply current (IDDQ) testing on the ring oscillator test structure in a low-current test mode. The multi-functional test module operates in voltage compensation mode, including: when the received mode control signal (OFF) is high, the NCONIO signal is high, the PCONIO signal and NSELIO signal are low, the transmission gate and PMOS are both turned on, a working voltage is input to the VDDE pin through the transmission gate, the current is measured on the VDDE pin, and the voltage of the VDDES pin is measured. The multi-functional test module operates in a low-current test mode: when the received mode control signal (OFF) is low, the PCONIO signal is high, the NCONIO signal and NSELIO signal are low, the transmission gate is turned off, the PMOS is turned on, a working voltage is input to the VDDES pin through the PMOS, and the current is measured on the VDDES pin.

[0018] Thirdly, this embodiment provides a high-precision addressable ring oscillator testing device, the device comprising: The acquisition module is used to acquire test requirements, including the test structure of the ring oscillator under test, the characteristic parameters to be tested, and the accuracy requirements. The generation module is used to generate various control signals based on the test requirements. The test module is used to select the ring oscillator test structure to be connected based on the received control signal, and switch the multi-functional test module to test the characteristic parameters to be tested in voltage compensation mode or low current test mode.

[0019] Fourthly, this embodiment provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the high-precision addressable ring oscillator testing method described in the second aspect above.

[0020] The aforementioned high-precision addressable ring oscillator test chip features a multi-functional test module capable of switching between voltage compensation mode and low-current test mode. During routine measurements of characteristic parameters such as IDDA, freq, and IDDQ of the ring oscillator, the voltage compensation mode utilizes voltage drop compensation to reduce the influence of resistive voltage drop introduced into the test path, effectively improving measurement accuracy. The low-current test mode enables effective measurement of the low-current IDDQ parameter of the ring oscillator. Furthermore, a high-precision addressable ring oscillator test method, a high-precision addressable ring oscillator test device, and a computer-readable storage medium are also disclosed, all possessing the performance and beneficial effects of the aforementioned high-precision addressable ring oscillator test chip. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a ring oscillator in one embodiment; Figure 2 This is a schematic diagram of the structure of a high-precision addressable ring oscillator test chip in one embodiment; Figure 3 This is a schematic diagram of the layout of a ring oscillator test module in one embodiment; Figure 4 This is a circuit diagram of the signal transmission module in one embodiment; Figure 5 This is a circuit diagram of a logic control signal generation circuit in one embodiment; Figure 6 This is a schematic diagram of the pinout of a ring oscillator test structure in one embodiment. Detailed Implementation

[0023] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0025] It should also be understood that the terms "comprising / including" or "having," etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term "and / or" includes any and all combinations of the associated listed items.

[0026] A ring oscillator can be constructed by connecting an odd number of logic gates or circuit modules with NOT functions, with their outputs and inputs connected end to end, forming a ring. Figure 1 This is the simplest three-stage ring oscillator, composed of three NOT gates (A, B, C). At any given moment, applying an initial level (high or low) to any input will cause the ring oscillator to start oscillating. By measuring parameters such as the power supply current (IDDA, dynamic power supply current) under dynamic operating conditions, the power supply current (IDDQ, static power supply current) under static operating conditions, and the frequency (freq = 1 / T), the resistance and capacitance (R, C) characteristics of a single circuit can be evaluated. Specially designed test structures based on ring oscillators can also be extended to evaluate the characteristics of devices or interconnects that make up a single circuit.

[0027] In some embodiments of the present invention, the ring oscillator test structure (RO cell) used is a ring oscillator, which can be composed of an odd number of identical gate circuits or circuit modules with logic "NOT" function, or it can be composed of an even number of identical gate circuits or circuit modules with logic "NOT" function plus a different gate circuit or circuit module with logic "NOT" function.

[0028] To achieve effective measurement of the IDDA, freq, and IDDQ parameters of a ring oscillator, this embodiment provides a method such as... Figure 2 The high-precision addressable ring oscillator test chip shown includes an addressing module (Decoder module), an output module (OUT module), and multiple ring oscillator test modules (BLK modules): ring oscillator test structure 1, ring oscillator test structure 2, ..., ring oscillator test structure (N-1), and ring oscillator test structure N; The ring oscillator test module includes a signal transmission module, a multi-functional test module, and multiple ring oscillator test structures. The addressing module is used to select a ring oscillator test structure from the ring oscillator test structures (ROcells) of the plurality of ring oscillator test modules for connectivity testing; The multi-functional test module can switch between voltage compensation mode and low current test mode to test the ring oscillator test structure based on the received control signal; the voltage compensation mode is used to compensate for voltage drop when testing the characteristic parameters of the ring oscillator test structure; the low current test mode is used to test the static power supply current of the ring oscillator test structure.

[0029] The aforementioned high-precision addressable ring oscillator test chip is equipped with a multi-functional test module that can switch between voltage compensation mode and low-current test mode. When performing routine measurements on characteristic parameters such as IDDA, freq, and IDDQ of the ring oscillator, the voltage compensation mode can reduce the influence of the resistance voltage drop introduced in the test path by utilizing voltage drop compensation, effectively improving the measurement accuracy. The low-current test mode enables effective measurement of the low-current IDDQ parameter of the ring oscillator.

[0030] In this embodiment, as Figure 3 As shown, the ring oscillator test module includes multiple ring oscillator test structures (RO cells) and multiple peripheral circuits; The peripheral circuitry includes a signal transmission circuit, a multi-functional test module, a level conversion circuit, and a logic control signal generation circuit. The number of ring oscillator test structures and the number of peripheral circuits are the same, corresponding one-to-one; and the specific number of ring oscillator test structures is proportional to the addressing capability of the addressing module. The multiple ring oscillator test modules (BLK modules) are divided into at least two groups, and each group of ring oscillator modules is powered by an independent power supply; that is, the multiple ring oscillator test modules are at least divided into a first test module group and a second test module group, and are powered separately.

[0031] Specifically, the first test module group is powered by the third set of power pads VDDEL / VDDEL; the second test module group is powered by the fourth set of power pads VDDER / VDDERS.

[0032] It should be noted that in this embodiment, 16 RO cells are placed in the ring oscillator test module. However, in other embodiments, fewer than 16 RO cells or more than 16 RO cells may be placed depending on the specific application scenario requirements. This application does not impose any specific limitations.

[0033] In this embodiment, the ring oscillator test module includes at least one signal transmission module and at least one local frequency divider; such as Figure 3 As shown, the ring oscillator test module includes two signal transmission modules: a signal transmission module formed by connecting the signal transmission circuits corresponding to the eight RO cells on the left, and a signal transmission module formed by connecting the signal transmission circuits corresponding to the eight RO cells on the right.

[0034] The number of signal transmission modules and the number of local frequency dividers are the same, corresponding one-to-one. One function of the local frequency divider is to facilitate stable signal transmission through the signal transmission path at the RO cell OUT pin. Another function is to reduce the frequency at the RO cell OUT terminal to 1 / N of its original value for subsequent measurements. In this embodiment, multiple D flip-flops are combined to form an N-stage frequency divider, which is used as the local frequency divider. In other embodiments, other circuits or modules can be used to implement the local frequency divider, such as frequency dividers based on JK flip-flops or frequency dividers based on shift registers. This application does not impose specific limitations on these.

[0035] A partial frequency divider can be configured based on the frequency range that the peripheral circuit can transmit and the final output frequency range. On one hand, if the output frequency of the ring oscillator under test is higher than the frequency range that the peripheral circuit can transmit, a partial frequency divider needs to be configured on the ring oscillator under test to reduce the frequency. On the other hand, since all ring oscillators are not necessarily the same type and have the same output frequency, one or more global frequency dividers are selected during the overall peripheral circuit design, taking into account the final output frequency range. All test structures share one or more global frequency dividers. However, if the output frequency of a certain ring oscillator is still higher than the final output frequency range, a partial frequency divider needs to be configured on that ring oscillator to reduce the frequency. Therefore, in the design of this test chip, both the partial and global frequency dividers can be configured with different division stages according to the actual situation, which not only achieves flexible frequency division configuration but also reduces the area occupied by the frequency divider.

[0036] like Figure 4 As shown, the signal transmission module includes multiple signal transmission circuits connected in sequence, and at most only the output result of one signal transmission circuit in the signal transmission module is transmitted as the final output of the signal transmission module.

[0037] In this embodiment, as Figure 4 and Figure 6 As shown, the signal transmission circuit includes a second NAND gate, a fourth inverter, and a first AND gate; The output signals (RO_OUT: RO_OUT0, ..., RO_OUT6, RO_OUT7) of the OUT pin of the ring oscillator test structure (RO cell) are input together with the address strobe signals (SEL: SEL0, ..., SEL6, SEL7) to the second NAND gate. After passing through the fourth inverter, they are input together with the output result of the previous signal transmission circuit (RO_pre_OUT: RO_bit_OUT0, ..., RO_bit_OUT6, RO_bit_OUT7) or the ground voltage signal (VSSC) to the output result (RO_bit_OUT: RO_bit_OUT0, ..., RO_bit_OUT6, RO_bit_OUT7) of the first AND gate. The output of the last signal transmission circuit in the series of interconnected signal transmission circuits is the final output of the signal transmission module. The ground voltage signal (VSSC) is the common ground voltage of the circuit system, which is provided by the first power supply. VSSC is always 0. It is connected to one input of the first stage OR gate of the signal transmission circuit. The output of this OR gate is determined by the other input, and the output level is consistent with the other input.

[0038] In this embodiment, as Figure 5 As shown, the level shifting circuit is used to convert the signal from the voltage of the core area (core voltage, 0.9V) to the voltage of the input / output area (I / O voltage, 2.5V), generating the logic control signals (NCONIO signal, PCONIO signal, and NSELIO signal, etc.) required by the multi-functional test module.

[0039] In this embodiment, as Figure 5 As shown, the logic control signal generation circuit includes a first inverter, a second inverter, a third inverter, and a first NAND gate; The logic control signal generation circuit is connected to the addressing module (Decoder module) and receives the row signal (ROW) and column signal (COL) output by the addressing module. The row and column signals are passed through a NAND gate and then through the first inverter to output the address strobe signal (SEL). The row and column signals are passed through NAND gates, then through the level conversion circuit to be converted into voltages in the input / output region, thus generating the NSELIO signal; The NSELIO signal is passed through the second inverter and then input together with the mode control signal (OFF) into the first NAND gate to generate the PCONIO signal; The PCONIO signal is passed through the third inverter to output the NCONIO signal.

[0040] Figure 5 In the example, with ROW, COL, and OFF signals all set to 1, the resulting SEL and NCONIO signals are all set to 1, while the resulting NSELIO and PCONIO signals are all set to 0. Furthermore, due to the intermediate level shifting circuit, a change in the power domain is achieved before and after the level shifting circuit: the SEL signal belongs to the 0.9V power domain of the core voltage (Core0.9 powerdomain), while the NCONIO, NSELIO, and PCONIO signals belong to the 2.5V power domain of the I / O voltage (IO2.5 powerdomain).

[0041] In this embodiment, as Figure 6 As shown, the ring oscillator test structure (RO cell) includes the VDDE pin, VDDES pin, OUT pin, and EBL pin.

[0042] Internally: both pins VDDE and VDDES are connected to the VDD power supply terminal of the ring oscillator test structure; the OUT pin is connected to the output terminal of the ring oscillator test structure; the EBL pin is connected to the start / stop control port of the ring oscillator test structure. Specifically, for an RO cell that can be composed of inverters or logic gates that can generate NOT, it generally includes ports: power supply (VDD) and ground (VSS / GND) for supplying power to these inverters / logic gates; output terminal (OUT) for leading out the oscillation signal; and start / stop control port for controlling the oscillator to start or stop generating waveforms.

[0043] Externally: The VDDE and VDDES pins are connected to the power supply after passing through the multi-functional test module; the OUT pin is transmitted to the output module (OUT module) for output (connected to the OUTPUT pad) through the signal transmission module; the EBL pin is connected to the output of the AND gate, and the input of the AND gate is the oscillation signal (EBL) and the address strobe signal (SEL).

[0044] Specifically, the VDDE pin and VDDES pin are connected to the power supply after passing through the multi-functional test module, including: when the BLK module belongs to the first test module group, it is connected to the third group of power pads VDDEL / VDDELS; when the BLK module belongs to the second test module group, it is connected to the fourth group of power pads VDDER / VDDERS.

[0045] In this embodiment, as Figure 6 As shown, the multifunctional test module includes a transmission gate and a PMOS; both the transmission gate and the PMOS adopt an I / O device design.

[0046] The input of the transmission gate is connected to the power supply (VDDEL / VDDER), and the output is connected to the VDDE pin of the ring oscillator test structure (RO cell). The control terminal is connected to the NCONIO signal, and the complementary control terminal is connected to the PCONIO signal. The transmission gate is typically composed of multiple sets of N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and P-channel metal-oxide-semiconductor field-effect transistors (P-channel MOSFETs). The PCONIO signal controls the gate of the P-channel MOSFET in the transmission gate, and the NCONIO signal controls the gate of the N-channel MOSFET in the transmission gate; both can be turned on or off simultaneously.

[0047] The source of the PMOS is connected to the power supply (VDDELS / VDDERS), the drain is connected to the VDDES pin of the ring oscillator test structure (RO cell), and the gate is connected to the NSELIO signal.

[0048] Specifically, the input terminal of the transmission gate is connected to the power supply, including: when the BLK module it belongs to is in the first test module group, it is connected to the third power pad VDDEL; when the BLK module it belongs to is in the second test module group, it is connected to the fourth power pad VDDER. The source of the PMOS is connected to the power supply, including: when the BLK module it belongs to is in the first test module group, it is connected to the third power pad VDDELS; when the BLK module it belongs to is in the second test module group, it is connected to the fourth power pad VDDERS.

[0049] When the received mode control signal (OFF) is high, the row signal ROW and column signal COL are both high because the current ring oscillator test structure RO cell is selected for testing. The NCONIO signal is high, and the PCONIO and NSELIO signals are low. The transmission gate and PMOS are both turned on. The multi-functional test module operates in voltage compensation mode, inputting a working voltage to the VDDE pin through the transmission gate, measuring the current on the VDDE pin, and measuring the voltage on the VDDES pin.

[0050] The introduction of peripheral circuitry and long wires significantly increases the resistance R in the current testing path. When the measured current is large, this introduces IR drop. This embodiment minimizes the impact of IR drop by performing multiple voltage compensations (VDDE-VDDES) on the VDDE pin. VDDE in the (VDDE-VDDES) difference is the operating voltage required by the RO CELL, and VDDES is the voltage measured on the VDDES pin (RO CELL's VDD). The voltage compensation process is described below with a specific example: Assuming the DUT (RO CELL) belongs to the first test module group, this voltage compensation process will be implemented at VDDEL and VDDELS. Assuming the required operating voltage of the DUT (RO CELL) is 0.9V, the first voltage applied to VDDEL is 0.9V, and the current measured at VDDELS is assumed to be 0.8V. The second voltage applied to VDDEL is 0.9 + (0.9 - 0.8) = 1.0V, and the current measured at VDDELS is assumed to be 0.88V. The third voltage applied to VDDEL is 1.0 + (0.9 - 0.88) = 1.02V. This process continues until the voltage measured at VDDELS is approximately 0.9V (the preset measured voltage is 0.899~0.901V, within a 1mV error range). At this point, the compensation is considered complete.

[0051] When the received mode control signal (OFF) is low, the row signal ROW and column signal COL are both high because the current ring oscillator test structure RO cell is selected for testing. The PCONIO signal is high, and the NCONIO and NSELIO signals are low. The transmission gate is turned off, the PMOS is turned on, and the multi-functional test module operates in low-current test mode. It inputs a working voltage to the VDDES pin through the PMOS and measures the current on the VDDES pin.

[0052] Since some ROs have relatively small IDDQ (possibly on the order of -8 / -9), if the voltage compensation mode is used for direct measurement, the background current of the voltage compensation mode will have a significant impact on it. However, if the low current test mode is used for measurement, the background current is smaller than that of the voltage compensation mode, which will result in a more accurate measurement of the RO's IDDQ.

[0053] In this embodiment, the high-precision addressable ring oscillator test chip also includes multiple pads; The multiple pads include multiple address pads (ADDR1~4, ADDREN), control signal pads (MUX, EBL, OFF), output pads (OUTPUT), and four sets of power pads (VDDC / VSSC, VDDIO / VSSIO, VDDEL / VDDELS and GNDE1 / GNDE2, VDDER / VDDERS and GNDE3 / GNDE4 / GNDE5 / GNDE6). The multiple address pads (ADDR1~4, ADDREN) are used to output multiple address signals (ADDR1~4) and address selection signals (ADDREN). The OUTPUT pad is connected to the output module (OUT module) and is used to receive data from the output module and output it. The four power pads provide four power supplies. The first power supply (VDDC / VSSC) supplies power to the logic control signal generation circuit, output module, signal transmission module, and level conversion circuit, providing the core voltage. The second power supply (VDDIO / VSSIO) supplies power to the level conversion circuit and multi-functional test module, providing the input / output voltage. The remaining two power supplies supply power to the ring oscillator test structures in the first and second test module groups, respectively: the third power supply (VDDEL / VDDELS and GNDE1 / GNDE2) supplies power to the ring oscillator test structures in the first test module group, and the fourth power supply (VDDER / VDDERS and GNDE3 / GNDE4 / GNDE5 / GNDE6) supplies power to the ring oscillator test structures in the second test module group. The control signal pads include pad MUX, pad EBL, and pad OFF; wherein, pad MUX is used to output a MUX control signal to select data from the first test module group or the second test module group for output; pad EBL is used to output an oscillation signal (EBL); and pad OFF is used to output a mode control signal to control the selection of the working mode of the multi-functional test module.

[0054] It should be noted that in this embodiment, "ADDR1, ADDR3..." etc. are identified as the names of the pads, which also correspond to the names of the signals they transmit. In this embodiment, four groups of power pads are provided. The third group of power pads supplies power to the ring oscillator test structure of the first test module group, and the fourth group of power pads supplies power to the ring oscillator test structure of the second test module group. However, in other embodiments, more groups of power pads can be provided based on specific application scenario requirements to support power supply to more test module groups. This application does not impose specific limitations on this.

[0055] In this embodiment, the addressing module (Decoder module) is connected to the multiple address pads (ADDR1~4, ADDREN) and is used to receive multiple address signals (ADDR1~4) and address selection signals (ADDREN) to generate row signals (ROW) and / or column signals (COL). Using the latch principle, when the address selection signal is low, multiple address signals and row signals are selected, and the row signal is generated based on the multiple address signals; when the address selection signal is high, multiple address signals and column signals are selected, and the column signal is generated based on the multiple address signals; wherein, the row signal is used to select the ring oscillator test module (BLK), and the column signal is used to select the ring oscillator test structure (RO cell) inside the ring oscillator test module.

[0056] By using the above addressing method, more pads are saved, and the number of test addresses in a single scribe line can be increased from the usual 100+ to more than 300.

[0057] In this embodiment, the output module (OUT module) includes a 2-to-1 data selector; the 2-to-1 data selector is used to select data from the first test module group (the RO cell on the left) or the second test module group (the RO cell on the right) for output according to the received MUX control signal.

[0058] Specifically, the high-precision addressable ring oscillator test chip supports parallel testing of ring oscillator test structures belonging to different groups. That is, the RO cells of the first test module group and the second test module group can be connected and tested simultaneously. During addressing, the corresponding BLKs in the two groups can be set to the same address, so when a certain address is selected, data from both addresses can be measured simultaneously. A 2-to-1 data selector can be used to select the currently output test data.

[0059] In this embodiment, the output module (OUT module) further includes a global frequency divider and an I / O driver. The data selected by the 2-to-1 data selector is then transmitted to the OUTPUT pad sequentially through the global frequency divider and the I / O driver. The global frequency divider, like the local frequency divider, consists of multiple D flip-flops. However, it can also be implemented using other circuits / modules depending on the specific application requirements.

[0060] Based on the same inventive concept, this application also provides a testing method using the high-precision addressable ring oscillator test chip described above. The solution provided by this testing method is similar to the implementation described in the high-precision addressable ring oscillator test chip. Therefore, the specific limitations in one or more embodiments of the high-precision addressable ring oscillator testing method provided below can be found in the limitations of the high-precision addressable ring oscillator test chip described above, and will not be repeated here.

[0061] In one embodiment, a high-precision addressable ring oscillator testing method is provided, including the following steps: Obtain test requirements, including the test structure of the ring oscillator to be tested, the characteristic parameters to be tested, and the accuracy requirements; Based on the aforementioned test requirements, generate the control signals; Based on the received control signal, the test structure of the ring oscillator to be tested is selected, and the multi-functional test module is switched to test the characteristic parameters to be tested in voltage compensation mode or low current test mode.

[0062] Specifically, the received control signals include the oscillation start signal EBL, the mode control signal OFF, the MUX control signal, the address signal, and the address selection signal.

[0063] The aforementioned high-precision addressable ring oscillator testing method is based on a high-precision addressable ring oscillator test chip. Through the design method of the addressable test chip, a set of pads (usually 22-25 PADs) is shared on a limited wafer area to achieve efficient and high-precision testing of three test items: dynamic current, static current, and frequency of the ring oscillator.

[0064] In this embodiment, the plurality of ring oscillator test modules (BLK modules) are divided into at least two groups, and each group of ring oscillator modules is powered by an independent power supply; that is, the plurality of ring oscillator test modules are at least divided into a first test module group and a second test module group, and are powered separately. Based on the aforementioned test requirements, the generation of various control signals includes: Using the generated address signal and address selection signal, parallel testing of ring oscillator test structures belonging to different groups is supported. Test data is obtained by testing the VDDE pin and VDDES pin of the ring oscillator test structure respectively, or the ring oscillator test structure is selected based on the MUX control signal and the test data is output through the output module.

[0065] In this embodiment, the step of selecting the connected ring oscillator test structure based on the received control signal and switching the multi-functional test module to test the characteristic parameters to be tested in voltage compensation mode or low current test mode includes: The multi-functional test module performs dynamic power supply current (IDDA) testing on the ring oscillator test structure in voltage compensation mode. The multi-functional test module performs static power supply current (IDDQ) testing on the ring oscillator test structure in voltage compensation mode. The multi-functional test module performs frequency (freq) testing on the ring oscillator test structure in voltage-compensated mode; and / or The multi-functional test module performs static power supply current (IDDQ) testing on the ring oscillator test structure in a low-current test mode.

[0066] The above four testing methods will be illustrated below through specific application examples.

[0067] Pad settings: 1) ADDR1~4 and ADDREN signal inputs are used for addressing and sequentially traversing the chip address; VDDIO / VSSIO provides power to the IO device circuit; VDDC / VSSC provides power to the core device circuit; GNDE1~6 provides the common ground voltage of the DUT, which is usually 0.

[0068] I. Voltage compensation mode test, including: 1) Dynamic power supply current (IDDA) test; Control signal settings: At this time, the OFF input is high to enter the voltage compensation mode, the EBL input is high, the voltage is applied to VDDEL / VDDER and the current is measured respectively, and the voltage is measured from the VDDELS / VDDERS terminals.

[0069] Turning on and off of related components: At this time, the transmission gate and PMOS in the multi-function test module of the selected address are both turned on; the RO CELL of the selected address enters the oscillation mode due to the rise of EBL.

[0070] Test method: The corresponding BLK addresses in the two groups can be the same. Therefore, when a certain address is selected, the IDDA data of the two actual addresses can be measured at the same time. The test needs to be carried out through a compensation process, that is, the difference between (VDDE-VDDES) is compensated multiple times at the VDDEL and VDDER terminals to reduce IR drop. When the compensation is in place, the two IDDA data are read from the VDDEL and VDDER terminals respectively, which are the measured dynamic power supply currents (IDDA).

[0071] The aforementioned dynamic power current (IDDA) test method can simultaneously measure the data of two DUTs, improving the test time for a single DUT; and by setting up a compensation path, the true IR drop level and the true operating voltage of the DUT can be determined, significantly improving the accuracy of the dynamic power current (IDDA) test.

[0072] 2) Static power supply current (IDDQ) test; Control signal settings: At this time, the OFF input is high to enter the voltage compensation mode, the EBL input is low to apply voltage to VDDEL / VDDER respectively, and the voltage is measured from the VDDELS / VDDERS terminals.

[0073] The on / off state of related components: At this time, the transmission gate and PMOS module in the multi-function test module of the selected address are both turned on; the RO CELL of the selected address is powered on but does not enter the oscillation mode because EBL is in a low level state.

[0074] Test method (basically the same as IDDA test): The corresponding BLK addresses in the two groups can be the same, so when a certain address is selected, the IDDQ data of the two actual addresses can be measured simultaneously. The test needs to be performed through a compensation process, that is, the difference between (VDDE-VDDES) is compensated multiple times at the VDDEL and VDDER terminals to reduce IR drop. When the compensation is in place, the two IDDQ data are read from the VDDEL and VDDER terminals respectively, which are the measured static power supply currents (IDDQ). Generally, since the magnitude of IDDQ is smaller than that of IDDA, the number of compensation operations is usually less than that of IDDA.

[0075] The aforementioned static power current (IDDQ) testing method can simultaneously measure data from two DUTs, improving the testing time for a single DUT. Furthermore, by incorporating a compensation path, the true IR drop magnitude and the actual operating voltage of the DUT can be determined, significantly improving the accuracy of the IDDQ test. Additionally, existing addressable ring oscillator test chips cannot effectively measure IDDQ under normal conditions.

[0076] 3) Frequency (freq) test: Control signal settings: At this time, the OFF input is high to enter the voltage compensation mode, the EBL input is high to apply voltage to VDDEL / VDDER respectively, and the voltage is measured from the VDDELS / VDDERS terminals.

[0077] The conduction and shutdown of related components (consistent with IDDA testing): At this time, the transmission gate and PMOS module in the multi-function test module of the selected address are both turned on; the RO CELL of the selected address enters the oscillation mode due to the rise of EBL.

[0078] Test method: The corresponding BLK addresses in the two groups can be the same. However, since the data for frequency measurement is transmitted from the signal transmission circuit and output module (OUT module) connected to the OUT pin of the DUT, and then output through the OUTPUT pad, but there is only one OUTPUT pad, after selecting one address and after VDDE compensation is in place (the same method as IDDA), the MUX signal needs to be set to low level (to measure the frequency of the DUT in the first test module group) or high level (to measure the frequency of the DUT in the second test module group). Select one of the DUTs and output the data from the OUTPUT pad, which is the measured frequency (freq).

[0079] The frequency (freq) test method described above, by setting up a compensation path, can determine the true IR drop level and the true operating voltage of the DUT, thus significantly improving the accuracy of frequency testing.

[0080] II. Low current test mode, including: Control signal settings: At this time, the OFF input is low to enter the low-level measurement mode, the EBL input is low, and voltage is applied to VDDELS / VDDERS and current is measured respectively.

[0081] Turning on and off of related components: At this time, the transmission gate of the selected address is turned off, and the PMOS of the selected address is turned on; the RO CELL of the selected address is powered on but does not enter the oscillation mode because EBL is set to a low level.

[0082] Test method: The corresponding BLK addresses in the two groups can be the same. Therefore, when a certain address is selected, the IDDQ data of the two actual addresses can be measured at the same time. No compensation is required for the test. After applying voltage to the VDDELS / VDDERS terminals, the corresponding current at these two terminals is the IDDQ data.

[0083] The aforementioned low-current test mode for measuring static power supply current (IDDQ) allows for simultaneous parallel measurement of IDDQ data for two device under test (DUTs), improving the testing time for a single DUT and offering higher accuracy than the low-current IDDQ measured using voltage compensation mode. Furthermore, currently available addressable ring oscillator test chips cannot effectively measure IDDQ under normal conditions.

[0084] It should be noted that in this embodiment, there are two ways to measure IDDQ. Based on the requirements of industrial applications for measurement accuracy, when the current is large, the voltage compensation mode is used to measure the static power supply current (IDDQ); when the current is small, the small current test mode is used to measure the static power supply current (IDDQ).

[0085] Based on the same inventive concept, this application also provides an apparatus for implementing the high-precision addressable ring oscillator testing method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the high-precision addressable ring oscillator testing apparatus provided below can be found in the limitations of the high-precision addressable ring oscillator testing method described above, and will not be repeated here.

[0086] In one embodiment, a high-precision addressable ring oscillator testing apparatus is provided, the apparatus comprising: The acquisition module is used to acquire test requirements, including the test structure of the ring oscillator under test, the characteristic parameters to be tested, and the accuracy requirements. The generation module is used to generate various control signals based on the test requirements. The test module is used to select the ring oscillator test structure to be connected based on the received control signal, and switch the multi-functional test module to test the characteristic parameters to be tested in voltage compensation mode or low current test mode.

[0087] Each functional module of the high-precision addressable ring oscillator testing device implements the steps in the above-described embodiments of the high-precision addressable ring oscillator testing methods.

[0088] Each module in the aforementioned high-precision addressable ring oscillator testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of a computer device, so that the processor can call and execute the corresponding operations of each module.

[0089] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the embodiments of the high-precision addressable ring oscillator test methods described above.

[0090] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0091] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0092] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A high-precision addressable ring oscillator test chip, characterized in that, Includes an addressing module, an output module, and multiple ring oscillator test modules; The ring oscillator test module includes a signal transmission module, a multi-functional test module, and multiple ring oscillator test structures. The addressing module is used to select a ring oscillator test structure from the ring oscillator test structures of the plurality of ring oscillator test modules for connectivity testing; The multi-functional test module can switch between voltage compensation mode and low current test mode to test the ring oscillator test structure based on the received control signal; the voltage compensation mode is used to compensate for voltage drop when testing the characteristic parameters of the ring oscillator test structure; the low current test mode is used to test the static power supply current of the ring oscillator test structure.

2. The high-precision addressable ring oscillator test chip according to claim 1, characterized in that, The ring oscillator test module includes multiple ring oscillator test structures and multiple peripheral circuits; The peripheral circuitry includes a signal transmission circuit, a multi-functional test module, a level conversion circuit, and a logic control signal generation circuit. The number of ring oscillator test structures and the number of peripheral circuits are the same, corresponding one-to-one; and the specific number of ring oscillator test structures is proportional to the addressing capability of the addressing module. The multiple ring oscillator test modules are divided into at least two groups, and each group of ring oscillator modules is powered by an independent power supply; that is, the multiple ring oscillator test modules are at least divided into a first test module group and a second test module group, and are powered separately.

3. The high-precision addressable ring oscillator test chip according to claim 2, characterized in that, The output module includes a 2-to-1 data selector; The 2-to-1 data selector is used to select either the first test module group or the second test module group for output based on the received MUX control signal.

4. The high-precision addressable ring oscillator test chip according to claim 2, characterized in that, The level conversion circuit is used to convert the signal from the voltage in the core area to the voltage in the input / output area, thereby generating the logic control signal for the voltage required by the multi-functional test module.

5. The high-precision addressable ring oscillator test chip according to claim 4, characterized in that, The logic control signal generation circuit includes a first inverter, a second inverter, a third inverter, and a first NAND gate; The logic control signal generation circuit is connected to the addressing module and receives the row and column signals output by the addressing module. The row and column signals are passed through a NAND gate, and then through the first inverter to output an address strobe signal; The row and column signals are passed through NAND gates, then through the level conversion circuit to be converted into voltages in the input / output region, thus generating the NSELIO signal; The NSELIO signal is passed through the second inverter and then input together with the received mode control signal into the first NAND gate to generate the PCONIO signal. The PCONIO signal is passed through the third inverter to output the NCONIO signal.

6. The high-precision addressable ring oscillator test chip according to claim 5, characterized in that, The ring oscillator test structure includes the VDDE pin, VDDES pin, OUT pin, and EBL pin; The VDDE and VDDES pins are connected to the power supply after passing through the multi-functional test module; the OUT pin is transmitted to the output module for output through the signal transmission module; the EBL pin is connected to the output terminal of the AND gate, and the input terminal of the AND gate receives the oscillation signal and the address strobe signal.

7. The high-precision addressable ring oscillator test chip according to claim 6, characterized in that, The ring oscillator test module includes at least one signal transmission module and at least one local frequency divider; Furthermore, the number of signal transmission modules and the number of local frequency dividers are the same, and they correspond one-to-one; The signal transmission module includes multiple signal transmission circuits connected in sequence, and at most only the output result of one signal transmission circuit in the signal transmission module is transmitted as the final output of the signal transmission module.

8. The high-precision addressable ring oscillator test chip according to claim 7, characterized in that, The signal transmission circuit includes a second NAND gate, a fourth inverter, and a first AND gate; The output signal of the OUT pin of the ring oscillator test structure, together with the address strobe signal, is input to the second NAND gate. After passing through the fourth inverter, it is input to the first AND gate along with the output result of the previous signal transmission circuit or the ground voltage signal, and then output as a result. The output of the last signal transmission circuit in the series of interconnected signal transmission circuits is the final output of the signal transmission module. The ground voltage signal is provided by the first power supply.

9. The high-precision addressable ring oscillator test chip according to claim 6, characterized in that, The multi-functional test module includes a transmission gate and a PMOS; The input terminal of the transmission gate is connected to the power supply, the output terminal is connected to the VDDE pin of the ring oscillator test structure, the control terminal is connected to the NCONIO signal, and the complementary control terminal is connected to the PCONIO signal. The source of the PMOS is connected to the power supply, the drain is connected to the VDDES pin of the ring oscillator test structure (RO cell), and the gate is connected to the NSELIO signal.

10. A high-precision addressable ring oscillator testing method, characterized in that, The test was performed using the high-precision addressable ring oscillator test chip according to any one of claims 1 to 9; The high-precision addressable ring oscillator testing method includes the following steps: Obtain test requirements, including the test structure of the ring oscillator to be tested, the characteristic parameters to be tested, and the accuracy requirements; Based on the aforementioned test requirements, generate the control signals; Based on the received control signal, the test structure of the ring oscillator to be tested is selected, and the multi-functional test module is switched to test the characteristic parameters to be tested in voltage compensation mode or low current test mode.

11. The high-precision addressable ring oscillator test method according to claim 10, characterized in that, The multiple ring oscillator test modules are divided into at least two groups, and each group of ring oscillator modules is powered by an independent power supply; that is, the multiple ring oscillator test modules are at least divided into a first test module group and a second test module group, and are powered separately. Based on the aforementioned test requirements, the generation of various control signals includes: Using the generated address signal and address selection signal, parallel testing of ring oscillator test structures belonging to different test module groups is supported. Test data is obtained by testing the VDDE pin and VDDES pin of the ring oscillator test structure respectively, or the ring oscillator test structure is selected based on the MUX control signal and the test data is output through the output module.

12. The high-precision addressable ring oscillator test method according to claim 10, characterized in that, The process of selecting the connected ring oscillator test structure based on the received control signal and switching the multi-functional test module to test the characteristic parameters under test in voltage compensation mode or low current test mode includes: The multi-functional test module performs dynamic power current testing on the ring oscillator test structure in voltage compensation mode. The multi-functional test module performs static power current testing on the ring oscillator test structure in voltage compensation mode. The multi-functional test module performs frequency testing on the ring oscillator test structure in voltage compensation mode; and / or The multi-functional test module performs static power current testing on the ring oscillator test structure in a low-current test mode. The multi-functional test module operates in voltage compensation mode, including: when the received mode control signal is high, the NCONIO signal is high, the PCONIO signal and NSELIO signal are low, the transmission gate and PMOS are both turned on, a working voltage is input to the VDDE pin through the transmission gate, the current is measured on the VDDE pin, and the voltage of the VDDES pin is measured. The multi-functional test module operates in a low-current test mode: when the received mode control signal is low, the PCONIO signal is high, the NCONIO signal and NSELIO signal are low, the transmission gate is turned off, the PMOS is turned on, a working voltage is input to the VDDES pin through the PMOS, and the current is measured on the VDDES pin.

13. A high-precision addressable ring oscillator testing device, characterized in that, The device includes: The acquisition module is used to acquire test requirements, including the test structure of the ring oscillator under test, the characteristic parameters to be tested, and the accuracy requirements. The generation module is used to generate various control signals based on the test requirements. The test module is used to select the ring oscillator test structure to be connected based on the received control signal, and switch the multi-functional test module to test the characteristic parameters to be tested in voltage compensation mode or low current test mode.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the high-precision addressable ring oscillator test method according to any one of claims 10 to 12.

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