Cross-process simulation integrated circuit behavior modeling method based on transfer learning and self-enhancement optimization

Abstract

The cross-process simulation integrated circuit behavior modeling method based on transfer learning and self-enhancement optimization belongs to the technical field of electronic design automation and artificial intelligence, and first, the circuit simulation data of a source process and a target process are subjected to feature engineering processing and alignment based on physical characteristics; a forward performance prediction model is constructed, a transfer learning strategy of source domain pre-training combined with target domain partial layer fine-tuning is adopted, and a mapping from circuit parameters to performance indicators is established; secondly, a reverse parameter backstepping model is constructed, and self-enhancement closed-loop optimization is performed, the forward model is used as a verifier to perform performance evaluation on the samples generated by the reverse model, high-confidence samples are selected to iteratively update the reverse model, and process rule hard constraints are introduced in the output layer to perform parameter boundary clipping; finally, the circuit design parameters meeting the requirements of the target process are output. The present application significantly improves the design efficiency and physical reliability of the simulation IP cross-process migration, and effectively solves the model generalization problem in the small sample scene.

Description

Technical Field

[0001] This invention belongs to the fields of electronic design automation (EDA) and artificial intelligence, specifically relating to a method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-enhancing optimization. Background Technology

[0002] With the rapid development of the integrated circuit industry and the continuous iteration of process nodes, achieving rapid migration of analog circuit IP between different process nodes has become crucial for shortening product launch cycles. Traditional analog circuit migration methods mainly rely on manual experience to adjust device dimensions and perform repeated SPICE simulation verification. This method is inefficient and requires a high level of experience from designers.

[0003] In recent years, AI-based design-aided methods have gradually become a research hotspot. However, existing AI modeling methods typically require a large amount of data for training to ensure model accuracy. In practical cross-process migration scenarios, the source process (such as a mature legacy process) usually has massive amounts of historical simulation data, while data for the target process (such as a newly introduced advanced process) is often very scarce. Directly using scarce target process data to train the model can easily lead to overfitting and poor generalization ability; while directly reusing the source process model can lead to inaccurate predictions due to differences in process parameter distribution.

[0004] Furthermore, existing reverse engineering methods (i.e., inferring circuit parameters from performance indicators) often lack a verification mechanism for the physical rationality of the generated samples. This leads to situations where the generated circuit parameters, while mathematically satisfying the model mapping, are infeasible or violate design rules in actual physical circuits. Therefore, how to fully utilize source process knowledge to achieve high-precision, physically reliable cross-process behavior modeling and parameter inversion under conditions of scarce target process data is a pressing technical challenge that needs to be addressed. Summary of the Invention

[0005] The purpose of this invention is to provide a cross-process analog integrated circuit behavior modeling method based on transfer learning and self-enhancing optimization, which solves the technical problems of low model accuracy, poor generalization ability and lack of physical constraints in reverse design when target process data is scarce.

[0006] A method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-enhancing optimization includes the following steps:

[0007] S1: Obtain source process circuit simulation data and target process circuit simulation data, and perform feature engineering processing based on physical characteristics. Construct an input vector containing device-level geometric features and system-level matching features based on the design parameters and performance indicators of transistors, differential pairs, and current mirrors.

[0008] S2, based on the aligned integrated calibration architecture and the dual-path prediction mechanism of multilayer perceptron (MLP) + residual correction, constructs a positive prediction model from circuit design parameters to performance indicators. It adopts a transfer learning strategy, first pre-training the model using source process circuit simulation data, then freezing some shallow parameters of the model, and fine-tuning the deep parameters of the model using target process circuit simulation data. The number of frozen layers is dynamically adjusted through a layer freezing search mechanism to achieve the optimal balance between preserving source domain knowledge and adapting to the target domain distribution, thereby constructing a high-precision positive performance prediction model.

[0009] S3, Construct a reverse parameter back-reasoning model from performance indicators to circuit design parameters; The reverse parameter back-reasoning model adopts a deep neural network architecture including a heterogeneous input transformation layer, a fully connected nonlinear hidden layer and a normalized output layer. The input circuit performance indicators are processed sequentially through heterogeneous data preprocessing, standardization processing, nonlinear feature transformation, normalized output and denormalized mapping, and the output circuit design parameters are then obtained.

[0010] S4. A self-enhancing closed-loop optimization mechanism is introduced; the inverse parameter back-calculation model is trained, and a randomly generated target performance vector is input to obtain the predicted circuit design parameters; the trained forward prediction model is used as a validator to evaluate the performance consistency of the predicted circuit design parameters generated by the inverse parameter back-calculation model; high-confidence samples are selected and expanded into the target process circuit simulation data, and the inverse parameter back-calculation model is iteratively retrained.

[0011] S5 introduces hard constraint control at the output of the inverse parameter back-reasoning model. Based on the design rules of the target process, the output circuit design parameters are boundary-trimmed to constrain the size of individual devices and the proportional relationship between devices. The optimized circuit design information is output, including the final target process circuit design parameters, the corresponding performance prediction report and model evaluation index.

[0012] Compared with existing technologies, the advantages of this invention are as follows: Based on a deep transfer learning architecture and a self-enhancing closed-loop optimization mechanism, this invention can efficiently utilize source process knowledge to fill gaps in target process data, prioritize the screening of high-confidence samples, and gradually improve the model's prediction accuracy and physical consistency. This significantly reduces the design cycle and trial-and-error costs of cross-process transfer, thereby significantly improving the reliability and automation efficiency of analog integrated circuit design. Specific beneficial effects include:

[0013] (1) The present invention adopts the transfer learning strategy of “source domain pre-training + target domain freezing fine-tuning”, combined with the layer freezing search mechanism, which can effectively overcome the overfitting problem caused by the scarcity of target process data and achieve high-precision performance prediction with very few samples.

[0014] (2) This invention innovatively constructs a "reverse boosting" self-enhancing closed loop, uses the forward model to generate pseudo-label data to assist training, solves the ill-posed problem of "one-to-many" mapping in reverse design, and greatly improves the accuracy of reverse derivation parameters;

[0015] (3) The present invention incorporates physical prior knowledge such as W / L ratio and matching degree in feature engineering, and introduces hard constraint trimming based on process rules at the output end to ensure that the generated circuit parameters are not only mathematically optimal, but also physically feasible and meet the actual chip fabrication requirements.

[0016] (4) The positive prediction model of this invention adopts a two-layer architecture of Ridge regression and HGB residual correction, which effectively combines the robustness of the linear model and the fitting ability of the nonlinear model. The output results include detailed performance reports and parameter configurations, which directly serve subsequent circuit simulation and layout design. Attached Figure Description

[0017] Figure 1 This is a flowchart of the modeling method based on transfer learning and self-reinforcement optimization in a specific embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the 5T operational amplifier circuit structure in a specific embodiment of the present invention.

[0019] Figure 3 The circuit design parameters and circuit performance indicators of the 5T operational amplifier in a specific embodiment of the present invention are as follows.

[0020] Figure 4 This is a schematic diagram of the two-layer architecture of the positive performance prediction model in a specific embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the specific network architecture of the inverse parameter back-calculation model in this embodiment of the invention.

[0022] Figure 6 This is a schematic diagram of the self-reinforcing closed-loop optimization process in a specific embodiment of the present invention.

[0023] Figure 7 This is a table showing the results of the cross-process behavior modeling method in a specific embodiment of the present invention running on a 5T operational amplifier.

[0024] Figure 8 This is a fitting diagram of the back-inferred parameters in a specific embodiment of the present invention. Detailed Implementation

[0025] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0026] like Figure 1As shown, the method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-enhancing optimization includes the following steps.

[0027] S1: Data Acquisition and Physically Based Feature Engineering. Large-scale circuit simulation data from the source process (e.g., 180nm process) is acquired as source domain data, and small-scale circuit simulation data from the target process (e.g., 65nm process) is acquired as target domain data. The circuit's netlist file is read, and design parameters (e.g., transistor width W, length L, bias current Ibias, etc.) and performance metrics (e.g., gain, phase margin PM, unity-gain bandwidth UGF, etc.) are extracted. To improve the model's understanding of the circuit's physical characteristics, feature engineering is performed on the extracted parameters. The constructed input vector includes not only the original geometric dimensions but also physical features: the width-to-length ratio (W / L) of transistors is calculated to characterize current driving capability; the size ratio of differential pairs (e.g., M1 and M2 in a 5T op-amp) is calculated to characterize matching degree; and the transconductance-to-current ratio (gm / Id) is calculated to characterize the operating region. All feature data are standardized based on the statistics of the training set to eliminate dimensional differences and provide high-quality foundational data for subsequent modeling. Taking a 5T operational amplifier as an example, its circuit structure is as follows: Figure 2 As shown, the circuit design parameters and performance indicators are as follows: Figure 3 As shown, the input features cover the size parameters and bias current of each transistor from M1 to M5.

[0028] S2: Construct a positive performance prediction model and perform transfer learning. Based on the data processed in step S1, construct the following model: Figure 4 The illustrated "Alignment Integration Calibration" two-layer architecture forward mapping model first processes the input circuit design parameters (W, L, Ibias) through a feature engineering layer, then proceeds to dual-path prediction: a base prediction layer fits the main trend of the performance index. Although the illustrated architecture includes the Ridge regression option, this embodiment specifically uses a Multilayer Perceptron (MLP) as the base model to achieve cross-process transfer; the residual correction layer uses a histogram gradient boosting tree to fit the nonlinear residuals. After the two outputs are superimposed, they are calibrated using order-preserving regression through a probability calibration layer to obtain the final performance index. To address the scarcity of target process data, a transfer learning strategy is implemented based on the MLP in the base prediction layer: first, the MLP is pre-trained using large-scale source domain data to learn general physical laws; then, when transferring to the target domain, a layer freezing strategy is used, keeping the parameters of the preceding network layers near the feature engineering layer in the MLP unchanged, and only using a small amount of target domain data to fine-tune the unfrozen subsequent regression prediction layer. By dynamically adjusting the number of frozen layers through a layer-freezing search mechanism, an optimal balance is achieved between preserving source domain knowledge and adapting to the target domain distribution, thereby constructing a high-precision positive performance prediction model.

[0029] S3, constructing a reverse parameter derivation model from performance indicators to circuit design parameters. For example... Figure 5 As shown, to overcome the "one-to-many" mapping problem and the large differences in data distribution in analog circuit reverse engineering, this embodiment constructs a deep neural network architecture including a heterogeneous input transformation layer, a fully connected nonlinear hidden layer, and a normalized output layer. First, the model introduces a heterogeneous input transformation layer to preprocess the input circuit performance indicators differently. For the unity-gain bandwidth (UGF), which has a very large span of physical dimensions, the Yeo-Johnson transform is used to improve the normality of the data distribution, making it more suitable for neural network learning. For the common-mode rejection ratio (CMRR) and slew rate (SR), which have high dynamic ranges, the Log1p (natural logarithm plus one) transform is used to effectively compress the numerical range and prevent gradient explosion. Other conventional indicators are not transformed, and then all indicators are standardized. All processed features are concatenated in this layer to form a high-dimensional input feature vector. Subsequently, the data enters the fully connected nonlinear hidden layer. To accurately capture the highly nonlinear mapping relationship from the performance space to the parameter space, this layer is designed as a cascaded deep fully connected network structure, containing three fully connected sub-layers with the number of neurons set to 384, 256, and 128 respectively. For the activation function selection, this layer uniformly adopts GELU (Gaussian Error Linear Unit), utilizing its smoothness near zero to better preserve the subtle gradient information of circuit parameters and improve the model's fitting accuracy. Finally, the normalized output layer outputs the circuit design parameters to be inferred (such as transistor width / length W / L, bias current Ibias, etc.). To ensure the physical validity of the output values, this layer uses the Sigmoid activation function to strictly limit all predicted values ​​to the normalized interval [0,1]. Then, combined with the physical parameter boundaries defined by the process library, the normalized values ​​are mapped back to the true physical design parameter space through an inverse normalization operation, thus completing the final inverse inference from performance indicators to physical parameters.

[0030] S4: Introducing a self-reinforcing closed-loop optimization mechanism. To address the aforementioned ill-posed problem and significantly improve the model's generalization ability, this embodiment introduces the following mechanism: Figure 6The self-enhancing closed-loop strategy is illustrated. In practice, the initial inverse parameter backpropagation model is first trained using limited target domain data. Then, a closed-loop iterative process is initiated: random sampling is performed within the performance index space to generate batch target performance vectors, which are then input into the current inverse model to obtain predicted circuit design parameters. Next, these predicted parameters are input into the high-precision forward model trained in step S2, using the forward model as a "virtual simulator" to calculate its reconstructed performance index. Based on this, the error (e.g., mean square error, MSE) between the reconstructed performance index and the original sampled performance index is calculated. If this error is less than a preset threshold, the corresponding predicted design parameters are determined to be "high-confidence samples" with high physical consistency. The system then uses the selected high-confidence samples and their corresponding design parameters as "pseudo-label" data to expand the target domain training set, and uses the expanded dataset to iteratively retrain the inverse model. This "generation-validation-selection-enhancing" process is continuously repeated until the model's error on the validation set converges, thereby significantly improving the prediction accuracy and physical consistency of the inverse model under the target process.

[0031] S5: Hard Constraint Control and Output Based on Process Rules. While the circuit parameters output by the reverse model mathematically satisfy the mapping relationship, they may exceed the physical limits allowed by the process. Therefore, a hard constraint control module is introduced at the output. Based on the design rules of the target process, physical boundaries for each transistor size are set (e.g., width W limited to 0.5µm to 50µm, length L limited to 0.5µm to 2µm, bias current limited to 5µA to 20µA). If the parameters output by the reverse model exceed these ranges, they are forcibly truncated to the boundary values. Figure 2 The 5T operational amplifier shown not only restricts the size of individual components, but also constrains the proportional relationship between components (such as M1 and M2 must remain symmetrical) to ensure that the generated netlist meets the matching requirements of analog circuit layout design.

[0032] Output optimized circuit design information. After optimization, output the final target process circuit design parameters, corresponding performance prediction report, and model evaluation metrics. The output information can be directly used for subsequent EDA simulation verification or automated layout generation.

[0033] To verify the method described in this invention, a test was conducted using a 5T operational amplifier migrated from a 180nm process to a 65nm process. The test set used a strictly isolated hidden dataset, and the evaluation metrics included the coefficient of determination (R²), root mean square error (RMSE), and mean absolute percentage error (MAPE).

[0034] like Figure 7As shown, this embodiment quantitatively evaluates the prediction accuracy of the forward performance prediction model under the target process. The evaluation covers five key circuit performance indicators: common-mode rejection ratio (CMRR), which measures the ability of the differential amplifier circuit to suppress common-mode signals; DC gain (dc_gain), which reflects the low-frequency open-loop voltage gain of the amplifier; phase margin, which is a key criterion for system stability; forward slew rate (slewrate_pos), which reflects the rate of forward change of the output voltage in response to the input step signal; and unity-gain bandwidth (ugf) when the gain drops to 1. Experimental statistical results show that, thanks to the application of the transfer learning strategy, the model performs excellently in all indicators. Specifically, the prediction determination coefficients R² for all indicators are stable above 0.92, with the R² for unity-gain bandwidth (ugf) reaching as high as 0.999, indicating that the model can fit the frequency domain characteristics very well. In terms of error control, the geometric mean absolute percentage error (GMAPE) for each indicator remains at a low level; for example, the GMAPE for common-mode rejection ratio is only 0.78%, and the phase margin is 0.57%. These data strongly demonstrate that the "forward pre-training-domain fine-tuning" modeling method proposed in this embodiment can accurately learn the complex nonlinear mapping relationship between circuit design parameters and performance space, and can guarantee extremely high prediction confidence even when the target process samples are scarce, providing a reliable evaluation benchmark for subsequent reverse self-enhancing optimization.

[0035] To verify the effectiveness of the self-enhancing closed-loop optimization mechanism in cross-process reverse engineering, this embodiment quantitatively evaluates the design parameters (w1-w3, l1-l3, Ibias) of the 5T op-amp generated by the reverse model. The evaluation dimensions include the design error between the generated parameters and the actual values. Specific indicators uniformly adopt MSE, MAE, R², and MAPE to provide multi-dimensional performance metrics. Visualization includes dimensional scatter plots and indicator comparison charts for easy intuitive analysis. Because there are too many parameters to predict, the parameter fitting effect of the key design parameter w2 (load transistor width) is shown as follows: Figure 8As shown in the figure, this graph visually illustrates the scatter plot comparison between the parameter values ​​predicted by the inverse parameter estimation model (vertical axis Pred w2) and the actual design parameter values ​​(horizontal axis True w2). As can be seen from the graph, the vast majority of blue scatter points converge closely near the ideal diagonal of y=x, exhibiting a very high linear correlation, indicating that the prediction results are highly consistent with the actual values. Quantitative evaluation metrics show that the mean absolute error (MAE) of this parameter prediction is 2.6769, the coefficient of determination (R²) is as high as 0.9198, and the mean absolute percentage error (MAPE) is only about 2.68%. This result strongly demonstrates that the "forward pre-training-reverse self-enhancement" closed-loop framework proposed in this invention can accurately capture the complex nonlinear mapping from the performance space to the design parameter space, and can still achieve high-precision circuit parameter estimation and physical consistency verification even when target process samples are scarce.

[0036] The above description is only a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or changes made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-reinforcing optimization, characterized by: The method includes the following steps: S1: Obtain source process circuit simulation data and target process circuit simulation data, and perform feature engineering processing based on physical characteristics. Construct an input vector containing device-level geometric features and system-level matching features based on the design parameters and performance indicators of transistors, differential pairs, and current mirror transistors. Calculate the width-to-length ratio (W / L) of the transistor as the device-level geometric feature based on the circuit netlist information. Calculate the parameter ratios between differential pair transistors or current mirror transistors, as well as the transconductance-to-current ratio gm / Id, as system-level matching characteristics; All feature data are standardized to eliminate dimensional differences, providing basic data for subsequent forward prediction and backward parameter inference models. The statistics of the standardization process are calculated only based on the training set to prevent data leakage. S2, based on an aligned integrated calibration architecture and a dual-path prediction mechanism of multilayer perceptron (MLP) + residual correction, constructs a forward prediction model from circuit design parameters to performance indicators. It employs a two-layer architecture of Ridge regression and HGB residual correction, and utilizes a transfer learning strategy. First, the model is pre-trained using source process circuit simulation data. Then, some shallow parameters of the model are frozen, and deep parameters are fine-tuned using target process circuit simulation data. A layer-freezing search mechanism dynamically adjusts the number of frozen layers, achieving an optimal balance between preserving source domain knowledge and adapting to the target domain distribution, thus constructing a high-precision forward performance prediction model. The forward prediction model uses an aligned integrated calibration architecture, specifically including: using a linear regression model as the base layer to extract the main linear relationship between circuit parameters and performance indicators; divided into dual-path prediction, including a base prediction layer based on multilayer perceptron (MLP) to fit the main trend of performance indicators, and a residual correction layer using a gradient boosting tree model to capture higher-order nonlinear effects of the circuit; after the two outputs are superimposed, an order-preserving regression model is used as a probability calibration layer to superimpose and calibrate the outputs of the base layer and the residual correction layer to obtain the final performance prediction value. S3, Construct a reverse parameter back-reasoning model from performance indicators to circuit design parameters; The reverse parameter back-reasoning model adopts a deep neural network architecture including a heterogeneous input transformation layer, a fully connected nonlinear hidden layer and a normalized output layer. The input circuit performance indicators are processed sequentially through heterogeneous data preprocessing, standardization processing, nonlinear feature transformation, normalized output and denormalized mapping, and the output circuit design parameters are then obtained. S4. A self-enhancing closed-loop optimization mechanism is introduced; the inverse parameter back-calculation model is trained, and a randomly generated target performance vector is input to obtain the predicted circuit design parameters; the trained forward prediction model is used as a validator to evaluate the performance consistency of the predicted circuit design parameters generated by the inverse parameter back-calculation model; high-confidence samples are selected and expanded into the target process circuit simulation data, and the inverse parameter back-calculation model is iteratively retrained. S5 introduces hard constraint control at the output of the inverse parameter back-reasoning model. Based on the design rules of the target process, the output circuit design parameters are boundary-trimmed to constrain the size of individual devices and the proportional relationship between devices. The optimized circuit design information is output, including the final target process circuit design parameters, the corresponding performance prediction report and model evaluation index.

2. The method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-enhancing optimization according to claim 1, characterized in that: In S2, the shallow parameters of the frozen model part in the transfer learning strategy are implemented through a layer-freezing search mechanism; The layer freezing search mechanism is as follows: During the fine-tuning stage of the target process data, different numbers of pre-process network layers are frozen sequentially to keep them in the pre-trained state of the source process unchanged, and only the parameters of the unfrozen post-process layers in the network are trained; the number of frozen layers is dynamically adjusted, and the prediction accuracy of the model on the validation set is evaluated through cross-validation. The number of frozen layers with the highest prediction accuracy is selected as the optimal configuration; wherein, the pre-process network layers refer to several consecutive hidden layers located at the input end and the middle part of the network, which are used to extract the general physical features of the circuit design.

3. The method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-reinforcement optimization according to claim 1, characterized in that: The specific construction process of the inverse parameter back-calculation model described in S3 is as follows: A heterogeneous input transformation layer is constructed to perform differentiated preprocessing on the input circuit performance indicators. Specifically, the Yeo-Johnson power transform is used for the unity-gain bandwidth with a large distribution span, and the natural logarithm Log1p logarithmic transform is used for the common-mode rejection ratio and slew rate with high dynamic range. Other conventional indicators are not transformed. Then, standardization is performed. A fully connected nonlinear hidden layer is constructed, containing several cascaded fully connected network layers with progressively decreasing neuron nodes. A Gaussian error linear unit (GELU) is uniformly used as the activation function to capture the highly nonlinear mapping relationship between performance indicators and design parameters. A normalized output layer is constructed, corresponding to the circuit design parameters. The Sigmoid activation function is used to limit the output to a normalized value range, and the normalized value is mapped back to the actual physical design parameter space through an inverse normalization operation, thus completing the back-calculation from performance indicators to physical parameters.

4. The method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-reinforcement optimization according to claim 1, characterized in that: The self-reinforcing closed-loop optimization mechanism introduced in S4 includes the following steps: S41: Train the reverse parameter back-calculation model using the initial target process circuit simulation data; S42: Use inverse parameters to back-engineer the model and generate batch predictive design parameters based on randomly sampled performance indicators; S43: Input the predicted design parameters into the trained positive prediction model to obtain the reconstruction performance index; S44: Calculate the error between the reconstruction performance index and the sampling performance index, and select the predicted design parameters with an error less than the preset threshold as high-confidence samples. S45: Add high-confidence samples to the target process circuit simulation data, use them as the target domain training set to retrain the inverse parameter backpropagation model, and repeat steps S42 to S45 until the iteration termination condition is met.

5. The method for modeling the behavior of cross-process analog integrated circuits based on transfer learning and self-reinforcing optimization according to claim 1, characterized in that: In S5, the boundary trimming of the output circuit design parameters according to the design rules of the target process refers to setting the physical upper and lower limits of transistor size, resistance, capacitance and bias current. If the parameters output by the reverse parameter back-engineering model exceed the range, they are forcibly truncated to the boundary value.

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