A method and system for optimizing a press-pack IGBT device package structure

Abstract

The application relates to the technical field of power electronics, and discloses a press-contact type IGBT device packaging structure optimization method and system. The method comprises the following steps: constructing an equivalent model of a press-contact type IGBT device; constructing a differential algebraic equation for uniformly describing the equivalent model of the press-contact type IGBT device and circuit port variables; converting the differential algebraic equation into a nonlinear algebraic equation group through time domain discretization, and constructing an iteration matrix with a global state vector as a derivation object according to a solving mode of the nonlinear algebraic equation group; performing low-dimensional subspace projection on the iteration matrix based on a Krylov subspace, and combining residual minimization to solve a linear subproblem of the iteration matrix, so that current uniformity characteristic results of the press-contact type IGBT device are obtained; and the packaging structure of the press-contact type IGBT device is optimized based on current density distribution reflected by the current uniformity characteristic results. The application can improve the current uniformity and operation reliability of the system.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a method and system for optimizing the packaging structure of a press-fit IGBT device. Background Technology

[0002] With the continuous increase in the scale and voltage and current levels of power systems, press-fit IGBTs are widely used in power electronic equipment such as DC circuit breakers, ultra-high voltage converters, and high-power inverters due to their reliable structure, strong heat dissipation capabilities, and high current carrying capacity. To meet the demands of tens of thousands of amperes of high-current transmission and high-frequency breaking, the current carrying capacity and withstand voltage of a single IGBT chip are insufficient for extreme operating conditions. In engineering, modular designs using hundreds or even thousands of IGBT chips connected in parallel are commonly adopted. However, when large-scale chips are connected in parallel, factors such as parasitic inductance / resistance differences caused by the packaging structure, uneven heat dissipation paths, and chip parameter dispersion can directly lead to an imbalance in current distribution between chips. This not only accelerates chip lifespan degradation but can also trigger thermal runaway in severe cases, even causing the entire module to fail. Therefore, accurately analyzing the current sharing characteristics of large-scale parallel IGBTs and optimizing the packaging structure accordingly has become a crucial step in improving the reliability and operational safety of power electronic equipment.

[0003] Currently, calculation methods for the current sharing characteristics of parallel IGBTs are mainly divided into three categories, but all have certain limitations: First, direct solution methods based on circuit models, which establish an electro-thermal coupling model through the nodal voltage method or state-space method, can achieve high accuracy when the number of chips is small. However, as the number of parallel chips increases to hundreds, the degree of freedom of the model increases geometrically, and the matrix dimension expands sharply, resulting in a sharp drop in computational efficiency, making it difficult to adapt to the needs of rapid engineering design; Second, numerical iterative methods such as Jacobi are efficient in small to medium-scale problems, but they are less effective when dealing with electrical parameters, thermal parameters, and other complex electrical and thermal parameters. When there is a strong coupling effect of physical parameters of conductors, the difference in magnitude of parameters in different physical domains will lead to the deterioration of the condition number of the equation system, which is prone to numerical oscillation. Not only is the convergence speed slow, but the convergence accuracy may also be insufficient. Third, although the finite element simulation method can finely characterize the electric field, temperature field and carrier distribution inside the chip, it has high requirements for modeling the details of the packaging structure (such as chip layout, bonding wire layout and substrate material), and the simulation process is time-consuming and cannot meet the timeliness requirements of comparing and optimizing multiple packaging structures. At the same time, it is difficult to fully take into account the comprehensive influence of parasitic parameters and heat dissipation paths on current sharing characteristics.

[0004] Therefore, there is an urgent need for an innovative method that takes into account both the coupling effect of multiple physical domains and the influence of packaging structure, so as to achieve rapid and accurate evaluation of the current sharing characteristics of large-scale parallel IGBTs, thereby providing a scientific basis for packaging structure optimization. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method and system for optimizing the packaging structure of press-fit IGBT devices.

[0006] In a first aspect, embodiments of the present invention provide a method for optimizing the packaging structure of a press-fit IGBT device, comprising: Based on the electrical-thermal-carrier coupling relationship of press-fit IGBT devices operating in parallel, an equivalent model of press-fit IGBT devices is constructed. By combining the circuit system parameters surrounding the press-fit IGBT device, a differential algebraic equation is constructed to uniformly describe the equivalent model of the press-fit IGBT device and the circuit port variables. The differential algebraic equations are discretized in the time domain and transformed into a system of nonlinear algebraic equations. Based on the solution method of the nonlinear algebraic equation system, an iterative matrix is ​​constructed with the global state vector as the object of differentiation. Based on the Krylov subspace, the iteration matrix is ​​projected into a low-dimensional subspace and the linear subproblem of the iteration matrix is ​​solved by combining residual minimization to obtain the current sharing characteristics of the press-fit IGBT device. Based on the current density distribution reflected by the current sharing characteristics, the packaging structure of the press-fit IGBT device is optimized.

[0007] Preferably, the construction of an equivalent model of the press-fit IGBT device based on the electro-thermal-carrier coupling relationship of the press-fit IGBT devices operating in parallel includes: Based on the correspondence between internal space charge and potential when the press-fit IGBT device is in parallel operation, an electric field equation is established. Based on the carrier transport law and current distribution requirements of the press-fit IGBT devices during parallel operation, a carrier equation is established. Based on the relationship between the internal heat generation, transfer and temperature distribution of the press-fit IGBT devices during parallel operation, a thermal field equation is established; The electric field equation, the carrier equation, and the thermal field equation are coupled and correlated to form an equivalent model of the press-fit IGBT device.

[0008] Preferably, the carrier equation includes a carrier continuity equation and a current density equation. The carrier continuity equation is used to characterize the time evolution of electrons and holes under the coupling effect of electric field, concentration gradient and temperature. The current density equation is used to quantify the electric field drift component and concentration diffusion component of the current.

[0009] Preferably, the step of constructing a differential-algebraic equation that uniformly describes the equivalent model of the press-fit IGBT device and the circuit port variables by combining the circuit system parameters surrounding the press-fit IGBT device includes: The circuit system parameters surrounding the press-fit IGBT device are determined, and the circuit system parameters are mathematically modeled to obtain the circuit parameter equations; Extract the device dynamic equations corresponding to the equivalent model of the press-fit IGBT device, and associate the device dynamic equations and the circuit parameter equations through circuit port variables to form globally coupled differential algebraic equations.

[0010] Preferably, the circuit system parameters include IGBT chip physical characteristic parameters, circuit parasitic parameters, and environmental condition parameters.

[0011] Preferably, the step of converting the differential algebraic equation into a system of nonlinear algebraic equations through time-domain discretization, and constructing an iterative matrix with the global state vector as the object of differentiation according to the solution method of the nonlinear algebraic equation system, includes: The differential algebraic equation is discretized in the time domain using difference discretization to obtain the discrete residual equation, and the discrete residual equation is characterized as a system of nonlinear algebraic equations; The global state vector is determined based on the iterative solution method of the nonlinear algebraic equation system, and an iterative matrix is ​​constructed based on the partial derivatives of the nonlinear algebraic equation system with respect to the global state vector.

[0012] Preferably, the global state vector includes node voltage vector, inductor current vector, and internal state variables of the IGBT chip.

[0013] Preferably, the step of projecting the iteration matrix into a low-dimensional subspace based on the Krylov subspace and solving the linear subproblem of the iteration matrix by minimizing the residuals to obtain the current sharing characteristics of the press-fit IGBT device includes: Based on the initial residual and the iteration matrix in the iterative solution process, a Krylov subspace is constructed, wherein the initial residual is the residual value of the discrete residual equation in the current iteration step during the iterative solution process; The Krylov subspace is subjected to Arnoldi orthogonalization to generate an orthogonal basis matrix and an upper Hessenberg matrix; Based on the orthogonal basis matrix and the upper Hessenberg matrix, the linear subproblem corresponding to the iteration matrix is ​​solved by residual minimization to obtain an approximate solution to the linear subproblem; The global state vector is updated based on the approximate solution, and the collector current of the press-fit IGBT device in each parallel branch is calculated according to the updated global state vector and the definition of port integral. Based on the collector current of the press-fit IGBT device in each of the parallel branches, the current sharing characteristics of the press-fit IGBT device are calculated, wherein the current sharing characteristics include the branch average current, the relative deviation of the single branch current, and the worst-case chip current factor.

[0014] Preferably, optimizing the packaging structure of the press-fit IGBT device based on the current density distribution reflected by the current sharing characteristics includes: Based on the current density distribution reflected by the current sharing characteristics, the number, position and geometry of the bosses in the packaging structure of the press-fit IGBT device are designed in a hierarchical manner. The hierarchical design includes increasing the number of bosses and expanding the geometry of the bosses in areas where the current density is higher than a first threshold, and reducing the number of bosses and shrinking the geometry of the bosses in areas where the current density is lower than a second threshold.

[0015] Secondly, embodiments of the present invention provide a system for optimizing the packaging structure of a press-fit IGBT device, comprising: The equivalent model construction module is used to construct an equivalent model of the press-fit IGBT device based on the electrical-thermal-carrier coupling relationship of the press-fit IGBT device operating in parallel. The algebraic equation construction module is used to construct differential algebraic equations that uniformly describe the equivalent model of the press-fit IGBT device and the circuit port variables by combining the circuit system parameters surrounding the press-fit IGBT device. The iterative matrix construction module is used to transform the differential algebraic equation into a system of nonlinear algebraic equations through time-domain discretization, and to construct an iterative matrix with the global state vector as the object of differentiation according to the solution method of the nonlinear algebraic equation system. The current sharing result determination module is used to perform low-dimensional subspace projection on the iteration matrix based on the Krylov subspace and solve the linear subproblem of the iteration matrix by combining residual minimization, so as to obtain the current sharing characteristic result of the press-fit IGBT device; The packaging structure optimization module is used to optimize the packaging structure of the press-fit IGBT device based on the current density distribution reflected by the current sharing characteristic results.

[0016] Compared with existing technologies, the optimization method and system for the packaging structure of a press-fit IGBT device disclosed in this invention have the following advantages: By constructing an equivalent model of electro-thermal-carrier coupling, the interaction law of multiple physical domains during parallel operation is fully captured, ensuring the accuracy of current sharing characteristic calculation; by leveraging the Krylov subspace low-dimensional projection and residual minimization strategy, the numerical ill-conditioning caused by the difference in the magnitude of parameters in multiple physical domains is effectively alleviated, significantly improving the iteration convergence stability and computational efficiency, and adapting to large-scale chip parallel scenarios; based on the accurate current sharing characteristic results, the packaging structure is optimized in stages, and by differentiating the number, position, and geometric dimensions of the bosses, the coordinated matching of current conduction paths and thermal equilibrium is achieved, greatly improving the current distribution uniformity of the parallel system, enhancing the heat dissipation capacity and structural stress balance of the device, and adapting to the engineering application needs of power electronic equipment such as DC circuit breakers, ultra-high voltage converters, and high-power inverters. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for optimizing the packaging structure of a press-fit IGBT device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the process for obtaining the flow sharing characteristics based on the Krylov subspace in an embodiment of the present invention; Figure 3 This is a schematic diagram of the hierarchical design of the boss in the packaging structure of the press-fit IGBT device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a pressure-fit IGBT device packaging structure optimization system according to an embodiment of the present invention; Figure label: 1-13, Boss; 01, Equivalent Model Construction Module; 02, Algebraic Equation Construction Module; 03, Iterative Matrix Construction Module; 04, Flow Equalization Result Determination Module; 05, Encapsulation Structure Optimization Module. Detailed Implementation

[0018] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0019] In the description of this invention, it should be understood that the terms "first" and "second," etc., are used to distinguish different objects, rather than to describe a specific order.

[0020] In the description of this invention, it should be noted that, unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by those skilled in the art. The terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the invention. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0021] Press-fit IGBT parallel systems are a key component in high-power power electronic equipment for achieving high current transmission and power conversion. The core design concept involves integrating multiple press-fit IGBT chips in parallel according to a specific topology to overcome the current carrying capacity limit of a single chip and meet the equipment's operational requirements for thousands of amperes or even higher current levels. The stable operation of this system relies on two key technologies: first, uniform current distribution among the chips to avoid localized overcurrent due to parameter dispersion and parasitic effects; and second, adaptation of the packaging structure to the electrothermal characteristics of the parallel system to ensure heat dissipation efficiency and structural reliability. Understanding the characteristics of this system is fundamental to subsequent packaging structure optimization and ensuring the long-term reliable operation of the equipment.

[0022] like Figure 1 The diagram shown is a flowchart illustrating a method for optimizing the packaging structure of a press-fit IGBT device according to an embodiment of the present invention. (Refer to...) Figure 1 An embodiment of the present invention provides a method for optimizing the packaging structure of a press-fit IGBT device, comprising the following steps: S1. Based on the electrical-thermal-carrier coupling relationship of the press-fit IGBT devices in parallel operation, construct an equivalent model of the press-fit IGBT devices; To accurately describe the conduction and voltage drop characteristics of press-fit IGBT devices during parallel operation, an equivalent model of the press-fit IGBT device needs to be established. The essence of this equivalent model is an electrical-thermal-carrier coupling model.

[0023] The electric-thermal-carrier coupling relationship in parallel operation of press-fit IGBT devices refers to the synergistic relationship of interaction and mutual influence between the internal electric field, carrier transport field, and thermal field of the device. Specifically, the electric field distribution determines the drift and diffusion direction and velocity of carriers. The current generated by the carrier movement produces Joule heating and other heat, which is input into the thermal field. The temperature change of the thermal field, in turn, changes key parameters such as carrier mobility, recombination rate, and device dielectric constant, thereby affecting the electric field distribution and carrier transport characteristics, forming a closed-loop coupling effect of "electric field-carrier-thermal field".

[0024] Based on the mechanism of this coupling relationship, this step establishes equations that characterize the essential laws of each physical field, and then integrates these equations to achieve a precise equivalent characterization of the parallel operation characteristics of the press-fit IGBT device.

[0025] Specifically, step S1 includes: 11) Based on the correspondence between internal space charge and potential when the press-fit IGBT device is connected in parallel, establish the electric field equation; The electric field equation, also known as the Poisson equation, describes the relationship between internal space charge and potential in press-fit IGBT devices operating in parallel. In parallel scenarios, due to differences in parasitic resistance / inductance of each branch, the port potentials of different IGBT chips will exhibit uneven distribution. The electric field equation calculates the potential field inside each chip, providing underlying electrical parameters for subsequent analysis of how potential differences lead to uneven carrier movement and thus current bias.

[0026] Specifically, the electric field equations are as follows: in, Represents the vector differential operator. Represents electric potential, Indicates electron concentration. Indicates hole concentration. Indicates the donor ion concentration. Indicates the concentration of acceptor ions. Represents the dielectric constant. It represents the elementary charge.

[0027] 12) Based on the carrier transport law and current distribution requirements of press-fit IGBT devices in parallel operation, establish the carrier equation; In parallel operation, the carrier concentration and mobility of each chip will vary due to differences in parasitic parameters and temperature. For example, a chip with higher carrier mobility will generate a larger current density under the same potential difference, ultimately leading to excessive current in that branch. The carrier equation, by calculating the carrier evolution and current density of each chip, directly outputs the branch current and is the core basis for evaluating current sharing deviation and worst-case chip current factor.

[0028] Specifically, the carrier equations include the carrier continuity equation and the current density equation. The carrier continuity equation is used to characterize the time evolution of electrons and holes under the coupling of electric field, concentration gradient and temperature, while the current density equation is used to quantify the electric field drift component and concentration diffusion component of the current.

[0029] The carrier continuity equation is shown below: in, Represents electron current density, Represents hole current density. Indicates the carrier generation rate. Indicates the composite rate. This represents the rate of change of electron concentration over time. This represents the rate of change of hole concentration over time.

[0030] The current density equation consists of two parts: electric field drift and concentration diffusion, as shown below: in, , Indicates electric field strength. Indicates the electron diffusion coefficient. Represents the hole diffusion coefficient. Indicates electron mobility. This represents the hole mobility rate.

[0031] 13) Establish the thermal field equation by combining the relationship between the internal heat generation, transfer and temperature distribution of the press-fit IGBT devices during parallel operation; The thermal field equation, also known as the thermal balance equation, describes the relationship between heat generation, transfer, and temperature distribution within a device. In parallel scenarios, current imbalance directly leads to some chips generating more Joule heat due to overcurrent, causing localized temperature increases. These temperature increases, in turn, reduce carrier mobility, further exacerbating the uneven current distribution. Therefore, by calculating the temperature field of each parallel chip, the thermal field equation can identify overheating risk areas and provide a basis for correcting temperature-sensitive parameters in the carrier equation. This enables a fully coupled analysis of the "electricity-heat-carrier" relationship, providing crucial support for reliability assessment and package heat dissipation optimization in parallel systems.

[0032] Specifically, the thermal field equations are as follows: in, Indicates density, Indicates specific heat capacity. Indicates thermal conductivity. Indicates Joule heating. Indicates temperature. Represents the quasi-Fermi level of electrons. This represents the quasi-Fermi level of a hole.

[0033] 14) Couple the electric field equation, carrier equation and thermal field equation to form an equivalent model of the press-fit IGBT device.

[0034] In the process of constructing the equivalent model of the press-fit IGBT device, the electric field equation, the carrier equation, and the thermal field equation are not independently superimposed, but are coupled by establishing the parameter interaction and physical mechanism relationship between the equations.

[0035] Specifically, the potential distribution in the electric field equation directly determines the drift electric field strength of the charge carriers in the carrier equation, thus affecting the transport rate and current density of the charge carriers. The Joule heat generated by the current density in the carrier equation and the thermal effect generated by carrier recombination serve as heat source terms input into the thermal field equation, driving the distribution and evolution of the temperature field. The temperature results of the thermal field equation, in turn, correct temperature-sensitive parameters such as the dielectric constant of the electric field equation and the mobility and recombination rate of the charge carrier equation. Finally, the electric field equation, the carrier equation, and the thermal field equation are combined into a set of interdependent coupled equations, which fully characterize the closed-loop interaction law of electric-thermal-charge carriers when the press-fit IGBT device is in parallel, thereby forming an accurate equivalent model of the press-fit IGBT device.

[0036] S2. Combining the circuit system parameters surrounding the press-fit IGBT device, construct a differential algebraic equation that uniformly describes the equivalent model of the press-fit IGBT device and the circuit port variables. After completing the equivalent model of the press-fit IGBT device, in order to achieve a coordinated characterization of the device characteristics and the circuit system, it is necessary to first perform modeling and integration at the circuit system level.

[0037] Specifically, step S2 includes: 21) Determine the circuit system parameters surrounding the press-fit IGBT device, and perform mathematical modeling of the circuit system parameters to obtain the circuit parameter equations; The circuit system parameters include IGBT chip physical characteristic parameters, circuit parasitic parameters, and environmental condition parameters. Specifically, for IGBT chip physical characteristic parameters, core parameters such as threshold voltage, carrier lifetime, and electron / hole mobility are obtained through chip technical manuals or experimental testing to clarify the electrical and semiconductor physical characteristics of the device itself. For circuit parasitic parameters, parameters such as bus inductance, bus resistance, branch inductance, branch resistance, and bus capacitance are extracted or determined through circuit simulation or actual measurement, based on the parallel system topology, to quantify the impact of non-ideal characteristics in the circuit on the system. Regarding environmental condition parameters, environmental influencing factors such as the casing reference temperature, cooling medium flow rate, and heat dissipation coefficient are determined according to the actual application scenarios of press-fit IGBTs (such as DC circuit breakers and ultra-high voltage converters), clarifying the impact of external conditions on the device and circuit.

[0038] Furthermore, mathematical modeling is performed based on circuit theory and component characteristics: Focusing on circuit parasitic parameters, we establish voltage-current dynamic relationship equations for bus inductance and resistance. For example, the voltage balance equation for bus inductance is shown below: in, Indicates bus inductance. This represents the rate of change of the bus inductor current over time. Indicates the voltage of the external voltage source. This indicates the series resistance of the busbar. Indicates the bus inductance current. This indicates the bus voltage.

[0039] The current balance equation for the bus capacitance is established as follows: in, Indicates bus capacitance. This represents the rate of change of the bus voltage over time. This represents the sum of the inductor currents in all parallel branches. This indicates the external load current.

[0040] The branch-level voltage-current evolution equations are established for the inductance and resistance of each parallel branch, as shown below: in, Indicates the first The inductance of the branch circuit, Indicates the first The inductor and resistor of the branch circuit are connected in series. Indicates the first The inductor current of the branch, Indicates the first The time rate of change of the inductor current in each branch is Indicates the first Collector-emitter voltage of the IGBT in the branch circuit.

[0041] Meanwhile, the physical characteristic parameters of the IGBT chip are used as inputs to the nonlinear characteristics of the device, and environmental condition parameters are used as boundary constraints of the model (such as the correction of the heat loss calculation by cooling conditions). Finally, the above parameters and component characteristics are integrated through mathematical expressions to form circuit parameter equations that can characterize the dynamic operation law of the circuit.

[0042] It should be noted that, in addition to the voltage balance equation, current balance equation, and branch-level voltage-current evolution equation for the bus inductance mentioned above, the circuit parameter equations also include the KCL equation for the gate node, which is used to characterize the current conservation at the IGBT gate node, as shown below: in, Indicates the first The driving voltage of each branch Indicates the gate voltage. Indicates gate resistance. This represents the gate current. This equation describes the electrical characteristics of the IGBT gate node through the conservation relationship between the inflow and outflow currents in the gate branch, and is the core of the gate control section in the circuit parameter equations.

[0043] 22) Extract the device dynamic equations corresponding to the equivalent model of the press-fit IGBT device, and associate the device dynamic equations and circuit parameter equations through circuit port variables to form a globally coupled differential algebraic equation.

[0044] The device dynamic equations are extracted from the equivalent model of the press-fit IGBT device. These equations are mathematical expressions of the electric-thermal-carrier coupling characteristics. They include the electric field equation (electric field equation) which describes the relationship between potential and space charge, the carrier equation (carrier continuity equation and current density equation) which describes carrier transport and current formation, the thermal field equation (thermal field equation) which reflects heat generation and temperature distribution, and the device collector current equation obtained based on port surface integration. Together, these equations constitute the dynamic constraints at the device level.

[0045] The collector current equation for the device is as follows: in, Indicates the first The collector current of the branch, Indicates the first Collector surface area of ​​an IGBT Represents the unit normal vector of the collector surface. A small element representing the surface area of ​​the collector electrode.

[0046] Selecting the gate-emitter voltage Collector-emitter voltage Branch inductor current and bus voltage Key variables, such as port-related parameters in the device dynamic equations (e.g.) Determines the internal electric field strength of the device The variables (reflecting the device current output) and the corresponding variables in the circuit parameter equations (such as the circuit branch equations) are... Bus capacitor current balance Establish a one-to-one correspondence to achieve parameter exchange between device characteristics and circuit states.

[0047] The associated device dynamic equations are combined with the circuit parameter equations, including time derivative terms (such as the rate of change of electron concentration). Inductor current change rate Bus voltage change rate The part containing differential equations (such as KCL, KVL and the relationship between internal parameters of the device) constitutes algebraic equations, and finally forms a globally coupled differential-algebraic equation, realizing a unified mathematical description of the internal physical processes of the device and the dynamics of the external circuit.

[0048] S3. The differential algebraic equations are discretized in the time domain and transformed into a system of nonlinear algebraic equations. Based on the solution method of the nonlinear algebraic equation system, an iterative matrix is ​​constructed with the global state vector as the object of differentiation. Specifically, step S3 includes: 31) The time-domain discretization of the differential algebraic equation is performed by difference discretization to obtain the discrete residual equation, and the discrete residual equation is characterized as a system of nonlinear algebraic equations; To facilitate numerical computation, the differential algebraic equations are discretized in the time domain using difference discretization to obtain discrete residual equations, i.e., a system of nonlinear algebraic equations, whose expression is: in, Represents the discrete residual vector. Represents the current global state vector. This represents the next global state vector. Represents the system quality matrix. Represents a vector of nonlinear functions. Represents the external source vector. This represents the discrete time step.

[0049] 32) Determine the global state vector based on the iterative solution of the nonlinear algebraic equation system, and construct the iteration matrix based on the partial derivatives of the nonlinear algebraic equation system with respect to the global state vector.

[0050] Since the nonlinear algebraic equation system contains nonlinear square roots and logarithmic terms, an iterative method is used to solve it. Therefore, it is necessary to determine the composition of the global state vector, which includes the node voltage vector, the inductor current vector, and the internal state variables of the IGBT chip.

[0051] The iteration matrix is ​​constructed based on the partial derivative of the discrete residual equation with respect to the global state vector. The expression of the iteration matrix is ​​as follows: in, Represents the iteration matrix, This represents the partial derivative of the discrete residual equation with respect to the global state vector. Represents the system quality matrix. This represents the partial derivative of the nonlinear function vector with respect to the global state vector. This represents the global state vector.

[0052] Finally, based on the characteristics of multiple parallel branches, the iteration matrix is ​​made to exhibit a block-sparse structure. This block-sparse structure includes derivative blocks for the circuit portion, derivative blocks within each IGBT chip, and derivative blocks for the coupling between the device and the circuit, adapting to the solution requirements of large-scale parallel systems. Specifically, the iteration matrix exhibits a block-sparse structure, as shown below: in, Represents the block form of the iteration matrix. This represents the derivative block of the circuit section. Indicates the first The internal derivative block of each IGBT chip Indicates the first The coupling derivative block between the IGBT chip and the circuit. Indicates the first The transpose of the coupling derivative block of an IGBT chip and circuit. , , , This represents a zero matrix or structural placeholder used to maintain the structural consistency of matrix blocks. Through this structured iterative matrix, the global state vector can be updated at each iteration step, achieving unified and convergent computation of circuit and device dynamics.

[0053] S4. Based on the Krylov subspace, the iteration matrix is ​​projected into a low-dimensional subspace and the linear subproblem of the iteration matrix is ​​solved by minimizing the residual to obtain the current sharing characteristics of the press-fit IGBT device. In solving the linear subproblem of the iterative matrix in a parallel system of press-fit IGBT devices, the large magnitude range of physical parameters involved in the electro-thermal-carrier coupling characteristics makes it easy to induce numerical ill-conditioning when using conventional iterative methods. This leads to slow convergence or even stagnation in the solution process, making it difficult to obtain accurate results efficiently. To overcome this technical bottleneck, this step introduces the Krylov subspace method to project the iterative matrix into a low-dimensional subspace. Simultaneously, a residual minimization strategy is used to balance the coupling relationships between multiple physical domains, laying the foundation for a stable and efficient solution to the linear subproblem.

[0054] like Figure 2 As shown, this is a flowchart illustrating step S4. (Refer to...) Figure 2 Step S4 includes: S401. Construct the Krylov subspace based on the initial residual and iteration matrix in the iterative solution process; The initial residual is the residual value of the discrete residual equation in the current iteration step during the iterative solution process. The Krylov subspace is generated by the repeated interaction of the initial residual and the iteration matrix, and its expression is: in, Indicated by the iteration matrix Compared with the initial residual generated dimensional Krylov subspace, The spanning space operator represents the linear space generated by the set of vectors enclosed in curly braces.

[0055] S402. Perform Arnoldi orthogonalization on the Krylov subspace to generate orthogonal basis matrices and upper Hessenberg matrices; Perform Arnoldi orthogonalization on the Krylov subspace to generate 3D orthogonal basis matrix and the step-like upper Hessenberg matrix ,satisfy This enables the projection of the iterative matrix onto a low-dimensional subspace.

[0056] S403. Solve the linear subproblem corresponding to the iteration matrix by minimizing the residuals based on the orthogonal basis matrix and the upper Hessenberg matrix to obtain an approximate solution to the linear subproblem. For the linear subproblems corresponding to the iteration matrix, the GMRES method is used to achieve residual minimization. By minimizing the residual norm, the optimization variables in the subspace are determined, thus obtaining an approximate solution to the linear subproblem. The GMRES method (Generalized Minimal Residual Method) is an iterative solution technique suitable for solving large, sparse, and potentially asymmetric linear equation systems. Compared to traditional iterative methods, the GMRES method effectively alleviates the numerical ill-conditioning caused by the difference in the magnitude of parameters in the electro-thermal-carrier multi-physics domains, improving the convergence stability of the linear subproblem solution while ensuring controllable computational complexity.

[0057] Specifically, for the linear subproblem corresponding to the iteration matrix The GMRES method is used to solve the residual minimization problem. ( Represents the initial residual coefficient. Represents the standard basis vectors. (Representing the optimization variables within the subspace) Then by Obtain approximate solutions to linear subproblems.

[0058] S404. Update the global state vector based on the approximate solution, and calculate the collector current of the press-fit IGBT device in each parallel branch according to the updated global state vector and the definition of port integral. The global state vector is updated using an approximate solution. The global state vector covers the potential distribution, carrier distribution, and voltage and current variables of each press-fit IGBT device. Based on the definition of port integral, the collector current of the press-fit IGBT devices in each parallel branch is calculated.

[0059] Specifically, the global state vector is updated based on the approximate solution. The global state vector includes the potential distribution, carrier distribution, and circuit voltage and current variables of each IGBT chip; the collector current of each parallel branch is calculated according to the port integral definition. in, Indicates the first Collector current of a press-fit IGBT branch Indicates the first Collector surface area of ​​an IGBT This indicates the number of crimped IGBT branches.

[0060] S405. Calculate the current sharing characteristics of the press-fit IGBT device based on the collector current of the press-fit IGBT device in each parallel branch.

[0061] Based on the obtained collector currents of each branch, the current sharing characteristics are calculated. These results include the average branch current, the relative deviation of the current in a single branch, and the worst-case chip current factor.

[0062] The following is a detailed explanation of the flow sharing characteristics results: 1) Average current of the branch: The average current of a branch refers to the arithmetic mean of the collector currents of all parallel press-fit IGBT branches at the same moment. It is used to reflect the average current carrying capacity of the entire parallel system and provides a benchmark for subsequent measurement of the deviation of the current in each branch. It is calculated using the following formula: in, This represents the average current of the branch.

[0063] 2) Relative deviation of current in a single branch: The relative deviation of a single branch current refers to the difference between the collector current of a parallel branch and the average current of that branch, and its ratio to the average current of the branch. It is used to quantify the magnitude and direction of the deviation of the current of a single branch from the average level of the system (a positive deviation indicates that the current of that branch is higher than the average current, and a negative deviation indicates that the current is lower than the average current). It is calculated using the following formula: in, Indicates the first The relative deviation of the current in each branch.

[0064] 3) Worst-case slice flow factor: The worst-case current factor is the ratio of the largest collector current to the average current of all parallel branches. It reflects the severity of current concentration in a parallel system. The closer the value is to 1, the more uniform the current distribution. A larger value indicates that the current in a certain branch is much higher than the average level, posing a risk of overcurrent / overheating. It is calculated using the following formula: in, This represents the worst-case flow factor.

[0065] Furthermore, to more comprehensively quantify the current distribution uniformity of the entire press-fit IGBT parallel system and avoid the limitation that a single indicator cannot reflect the overall current sharing effect of the system, the current sharing characteristic results also include an overall system current sharing performance index, which is calculated using the following formula: in, This represents the overall current sharing characteristics of the system; the smaller the value, the better the overall current sharing effect of the system.

[0066] By using the current sharing characteristics results, the parallel current sharing characteristics under different operating conditions can be directly compared, thereby evaluating the uniformity of current distribution and device safety, providing data support for subsequent packaging structure optimization design, and thus ensuring the reliability and stability of the device under high load operating conditions.

[0067] S5. Based on the current density distribution reflected by the current sharing characteristics, the packaging structure of the press-fit IGBT device is optimized.

[0068] Based on the current density distribution reflected by the current sharing characteristics, a hierarchical design is implemented for the number, location, and geometry of the bosses in the package structure of press-fit IGBT devices to optimize the current conduction path and thermal balance of the package structure. The hierarchical design involves increasing the number and size of the bosses in regions where the current density is above a first threshold, and decreasing the number and size of the bosses in regions where the current density is below a second threshold. It should be noted that the first and second thresholds must be determined in conjunction with the device's rated current density.

[0069] like Figure 3 As shown, this is a schematic diagram of the hierarchical design of the boss in the packaging structure of a press-fit IGBT device according to an embodiment of the present invention. (Refer to...) Figure 3 Taking a crimped IGBT module with 13 protrusions as an example, it intuitively presents the hierarchical layout of protrusions and the size differentiation design based on current density distribution.

[0070] Specifically, based on the current flow characteristics reflected in the current sharing characteristics (the current density is highest in the central area, followed by the periphery, and lowest in the outermost layer), the module packaging area is divided into three current flow levels, corresponding to different numbers, arrangements, and geometric dimensions of protrusions: the central current flow level area bears the highest current density, with 5 protrusions arranged in a cross shape (numbered 1-5) to ensure the current carrying capacity and heat dissipation efficiency of the core area; the periphery current flow level area has the second highest current density, with 4 protrusions (numbered 6-9) arranged around the central area to achieve current transition; the outermost current flow level area has the lowest current density, with 4 protrusions (numbered 10-13) arranged at the edge of the module to avoid structural redundancy.

[0071] Furthermore, Figure 3 It also reflects the differentiated design of the dimensions of the bosses at each level. Specifically, the five bosses in the central area (numbered 1-5) have larger diameters and heights to reduce local current density and improve heat conduction by increasing the conductive cross-sectional area; the four outer bosses (numbered 6-9) are designed with medium dimensions to balance the overall heat dissipation of the module while meeting current requirements; and the four outermost bosses (numbered 10-13) have smaller dimensions to adapt to low current loads while optimizing the stress distribution of the module.

[0072] Furthermore, if the module size is larger or the current density distribution is more complex in practical applications, it can be based on... Figure 3 The intermediate-level logic adds current levels (such as level four and level five), adjusts the spacing and number of bosses, and achieves precise matching between the boss structure and the current distribution.

[0073] This invention discloses a method for optimizing the packaging structure of a press-fit IGBT device. By constructing an equivalent model of electro-thermal-carrier coupling, it comprehensively captures the interaction laws of multiple physical domains during parallel operation, ensuring the accuracy of current sharing characteristic calculation. Utilizing Krylov subspace low-dimensional projection and residual minimization strategies, it effectively alleviates numerical ill-conditioning caused by differences in the magnitude of parameters across multiple physical domains, significantly improving iterative convergence stability and computational efficiency, and adapting to large-scale chip parallel scenarios. Based on accurate current sharing characteristic results, it performs hierarchical optimization of the packaging structure, achieving coordinated matching of current conduction paths and thermal equilibrium through differentiated design of the number, position, and geometric dimensions of protrusions. This significantly improves the uniformity of current distribution in the parallel system, enhances device heat dissipation capacity and structural stress balance, and adapts to the engineering application requirements of power electronic equipment such as DC circuit breakers, ultra-high voltage converters, and high-power inverters.

[0074] like Figure 4 The diagram shown is a structural schematic of a pressure-fit IGBT device packaging structure optimization system according to an embodiment of the present invention. (Refer to...) Figure 4 An embodiment of the present invention provides a packaging structure optimization system for a press-fit IGBT device, comprising: Equivalent model construction module 01 is used to construct an equivalent model of the press-fit IGBT device based on the electrical-thermal-carrier coupling relationship of the press-fit IGBT device in parallel operation; Algebraic equation construction module 02 is used to combine the circuit system parameters surrounding the press-fit IGBT device to construct differential algebraic equations that uniformly describe the equivalent model of the press-fit IGBT device and the circuit port variables. The iterative matrix construction module 03 is used to transform differential algebraic equations into a system of nonlinear algebraic equations through time-domain discretization, and to construct an iterative matrix with the global state vector as the object of differentiation according to the solution method of the nonlinear algebraic equation system. The current sharing result determination module 04 is used to perform low-dimensional subspace projection on the iteration matrix based on the Krylov subspace and combine residual minimization to solve the linear subproblem of the iteration matrix, so as to obtain the current sharing characteristic results of the press-fit IGBT device. The packaging structure optimization module 05 is used to optimize the packaging structure of the press-fit IGBT device based on the current density distribution reflected by the current sharing characteristics.

[0075] It should be noted that each module in the aforementioned pressure-fit IGBT device packaging structure optimization system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independently of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module. For specific limitations regarding the pressure-fit IGBT device packaging structure optimization system, please refer to the limitations of the pressure-fit IGBT device packaging structure optimization method described above; both have the same function and role, and will not be repeated here.

[0076] In summary, the present invention provides a method and system for optimizing the packaging structure of a press-fit IGBT device. By constructing an equivalent model of the electro-thermal-carrier coupling, it comprehensively captures the interaction laws of multiple physical domains during parallel operation, ensuring the accuracy of current sharing characteristic calculation. Utilizing the Krylov subspace low-dimensional projection and residual minimization strategy, it effectively alleviates the numerical ill-conditioning caused by the difference in the magnitude of parameters in multiple physical domains, significantly improving iterative convergence stability and computational efficiency, and adapting to large-scale chip parallel scenarios. Based on the accurate current sharing characteristic results, it performs hierarchical optimization of the packaging structure, achieving coordinated matching of current conduction paths and thermal equilibrium through differentiated design of the number, position, and geometric dimensions of the bosses. This significantly improves the uniformity of current distribution in the parallel system, enhances the device's heat dissipation capacity and structural stress balance, and adapts to the engineering application needs of power electronic equipment such as DC circuit breakers, ultra-high voltage converters, and high-power inverters.

[0077] The various embodiments in this specification are described in a progressive manner. For directly identical or similar parts of the embodiments, refer to each other. Each embodiment focuses on its differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0078] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A method for optimizing the packaging structure of a press-fit IGBT device, characterized in that, include: Based on the electrical-thermal-carrier coupling relationship of press-fit IGBT devices operating in parallel, an equivalent model of press-fit IGBT devices is constructed. By combining the circuit system parameters surrounding the press-fit IGBT device, a differential algebraic equation is constructed to uniformly describe the equivalent model of the press-fit IGBT device and the circuit port variables. The differential algebraic equations are discretized in the time domain and transformed into a system of nonlinear algebraic equations. Based on the solution method of the nonlinear algebraic equation system, an iterative matrix is ​​constructed with the global state vector as the object of differentiation. Based on the Krylov subspace, the iteration matrix is ​​projected into a low-dimensional subspace and the linear subproblem of the iteration matrix is ​​solved by combining residual minimization to obtain the current sharing characteristics of the press-fit IGBT device. Based on the current density distribution reflected by the current sharing characteristics, the packaging structure of the press-fit IGBT device is optimized.

2. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 1, characterized in that, The equivalent model of the press-fit IGBT device is constructed based on the electro-thermal-carrier coupling relationship of the parallel operation of the press-fit IGBT device, including: Based on the correspondence between internal space charge and potential when the press-fit IGBT device is in parallel operation, an electric field equation is established. Based on the carrier transport law and current distribution requirements of the press-fit IGBT devices during parallel operation, a carrier equation is established. Based on the relationship between the internal heat generation, transfer and temperature distribution of the press-fit IGBT devices during parallel operation, a thermal field equation is established; The electric field equation, the carrier equation, and the thermal field equation are coupled and correlated to form an equivalent model of the press-fit IGBT device.

3. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 2, characterized in that, The carrier equations include a carrier continuity equation and a current density equation. The carrier continuity equation is used to characterize the time evolution of electrons and holes under the coupling of electric field, concentration gradient and temperature. The current density equation is used to quantify the electric field drift component and concentration diffusion component of the current.

4. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 1, characterized in that, The construction of a differential-algebraic equation that combines the circuit system parameters surrounding the press-fit IGBT device with the equivalent model of the press-fit IGBT device and the circuit port variables to uniformly describe them includes: The circuit system parameters surrounding the press-fit IGBT device are determined, and the circuit system parameters are mathematically modeled to obtain the circuit parameter equations; Extract the device dynamic equations corresponding to the equivalent model of the press-fit IGBT device, and associate the device dynamic equations and the circuit parameter equations through circuit port variables to form globally coupled differential algebraic equations.

5. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 4, characterized in that, The circuit system parameters include IGBT chip physical characteristic parameters, circuit parasitic parameters, and environmental condition parameters.

6. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 1, characterized in that, The step of discretizing the differential-algebraic equations into a system of nonlinear algebraic equations in the time domain, and constructing an iterative matrix with the global state vector as the object of differentiation according to the solution method of the nonlinear algebraic equation system, includes: The differential algebraic equation is discretized in the time domain using difference discretization to obtain the discrete residual equation, and the discrete residual equation is characterized as a system of nonlinear algebraic equations; The global state vector is determined based on the iterative solution method of the nonlinear algebraic equation system, and an iterative matrix is ​​constructed based on the partial derivatives of the nonlinear algebraic equation system with respect to the global state vector.

7. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 6, characterized in that, The global state vector includes node voltage vector, inductor current vector, and internal state variables of the IGBT chip.

8. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 1, characterized in that, The process of projecting the iteration matrix into a low-dimensional subspace based on the Krylov subspace and solving the linear subproblem of the iteration matrix by minimizing the residual yields the current sharing characteristics of the press-fit IGBT device, including: Based on the initial residual and the iteration matrix in the iterative solution process, a Krylov subspace is constructed, wherein the initial residual is the residual value of the discrete residual equation in the current iteration step during the iterative solution process; The Krylov subspace is subjected to Arnoldi orthogonalization to generate an orthogonal basis matrix and an upper Hessenberg matrix; Based on the orthogonal basis matrix and the upper Hessenberg matrix, the linear subproblem corresponding to the iteration matrix is ​​solved by residual minimization to obtain an approximate solution to the linear subproblem; The global state vector is updated based on the approximate solution, and the collector current of the press-fit IGBT device in each parallel branch is calculated according to the updated global state vector and the definition of port integral. Based on the collector current of the press-fit IGBT device in each of the parallel branches, the current sharing characteristics of the press-fit IGBT device are calculated, wherein the current sharing characteristics include the branch average current, the relative deviation of the single branch current, and the worst-case chip current factor.

9. The method for optimizing the packaging structure of a press-fit IGBT device according to claim 1, characterized in that, The optimization of the packaging structure of the press-fit IGBT device based on the current density distribution reflected by the current sharing characteristics includes: Based on the current density distribution reflected by the current sharing characteristics, the number, position and geometry of the bosses in the packaging structure of the press-fit IGBT device are designed in a hierarchical manner. The hierarchical design includes increasing the number of bosses and expanding the geometry of the bosses in areas where the current density is higher than a first threshold, and reducing the number of bosses and shrinking the geometry of the bosses in areas where the current density is lower than a second threshold.

10. A system for optimizing the packaging structure of a press-fit IGBT device, characterized in that, include: The equivalent model construction module is used to construct an equivalent model of the press-fit IGBT device based on the electrical-thermal-carrier coupling relationship of the press-fit IGBT device operating in parallel. The algebraic equation construction module is used to construct differential algebraic equations that uniformly describe the equivalent model of the press-fit IGBT device and the circuit port variables by combining the circuit system parameters surrounding the press-fit IGBT device. The iterative matrix construction module is used to transform the differential algebraic equation into a system of nonlinear algebraic equations through time-domain discretization, and to construct an iterative matrix with the global state vector as the object of differentiation according to the solution method of the nonlinear algebraic equation system. The current sharing result determination module is used to perform low-dimensional subspace projection on the iteration matrix based on the Krylov subspace and solve the linear subproblem of the iteration matrix by combining residual minimization, so as to obtain the current sharing characteristic result of the press-fit IGBT device; The packaging structure optimization module is used to optimize the packaging structure of the press-fit IGBT device based on the current density distribution reflected by the current sharing characteristic results.

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