A front-end neuromorphic processing circuit for display panel gate pulse modulation and a working method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUZHOU UNIV
- Filing Date
- 2026-04-24
- Publication Date
- 2026-05-29
Smart Images
Figure CN122116787A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display driver integrated circuits and neuromorphic device application technology, and in particular to a front-end neuromorphic processing circuit for gate pulse modulation of display panels and its working method. Background Technology
[0002] In modern large-size display panels, gate line RC delay can cause severe distortion of the drive pulse waveform as it travels to the far end. The industry commonly uses gate pulse modulation (GPM) circuits to perform slope-trimmed discharge on the falling edge of the pulse to compensate for the turn-off difference between near and far pixels.
[0003] To achieve high-quality display, the discharge parameters of the GPM (such as discharge slope and cutoff voltage) need to be adaptively adjusted according to the real-time temperature of the panel, different row numbers, and aging levels. However, if existing display driver ICs use traditional CMOS digital architectures (such as ADC+DSP+SRAM lookup table method) to calculate these adaptive parameters, they will face serious problems such as large chip area, limited data throughput bandwidth, and excessive static power consumption.
[0004] Neuromorphic cross arrays based on resistive synaptic devices exhibit extremely high energy efficiency in analog computing. However, their application in GPM front-end information processing faces two major technical bottlenecks: First, purely passive cross arrays suffer from severe sneak path current during parallel computing, leading to a sharp decline in readout accuracy; second, large output currents from the array cause bit line potential drift, rendering Ohm's law ineffective (i.e., the input voltage is no longer equal to the actual voltage applied across the device), thus disrupting the linearity of analog matrix multiplication. Summary of the Invention
[0005] In view of this, the purpose of the present invention is to provide a front-end neuromorphic processing circuit for gate pulse modulation of a display panel and its working method. As an intelligent information processor of the GPM driver front end, the circuit can realize low power consumption and high linearity multidimensional parameter calculation, and provide accurate analog control signals for the subsequent GPM module, thereby realizing adaptive modulation of the gate pulse waveform of the display panel without significantly increasing the chip area and power consumption.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: a front-end neuromorphic processing circuit for gate pulse modulation of a display panel, comprising a feature mapping input module, a 1T1R neuromorphic cross array module, and a bit line clamping and differential readout module; The output of the feature mapping input module is connected to the word line of the 1T1R neuromorphic cross array module; the bit line of the 1T1R neuromorphic cross array module is connected to the input of the bit line clamping and differential readout module. The feature mapping input module is used to acquire the physical characteristics of the display panel in real time and convert them into multi-dimensional analog input voltage; The 1T1R neuromorphic cross array module is used to store preset waveform modulation weights, receive the multidimensional analog input voltage and perform analog matrix multiplication operations, and output analog converged current in parallel through multiple bit lines. The bit line clamping and differential readout module is used to clamp the potential of the bit line to a fixed reference voltage, extract the analog convergence current and perform differential subtraction, and output an analog control signal characterizing the modulation parameters to the subsequent gate pulse modulation module.
[0007] In a preferred embodiment, the 1T1R neuromorphic cross array module is composed of an array of multiple 1T1R units, and each 1T1R unit includes a selection transistor and a two-terminal non-volatile synaptic device. The gate of the select transistor is connected to the control line of the array and is normally open during simulation to eliminate array creeping current; the source or drain of the select transistor is connected in series with one end of the two-terminal non-volatile synaptic device, the other end of the two-terminal non-volatile synaptic device is connected to the word line, and the end of the select transistor not connected to the two-terminal non-volatile synaptic device is connected to the bit line.
[0008] In a preferred embodiment, the bit lines of the 1T1R neuromorphic cross array module adopt a differential pair structure, and each differential pair consists of a positive weight bit line and a negative weight bit line. In a preferred embodiment, the bit line clamping and differential readout module includes a regulated common gate clamping submodule and a current subtraction submodule; The voltage-regulating common-gate clamping submodule includes an operational amplifier and a clamping transistor. The inverting input terminal of the operational amplifier is connected to the bit line, the non-inverting input terminal of the operational amplifier is connected to the fixed reference voltage, and the output terminal is connected to the gate of the clamping transistor. The bit line potential is clamped to the fixed reference voltage through negative feedback. The current subtraction submodule uses a current mirroring circuit to algebraically subtract the current extracted from the positive weight bit line from the current extracted from the negative weight bit line at the physical node, and outputs the net current as the analog control signal.
[0009] In a preferred embodiment, the physical features of the display panel collected by the feature mapping input module include at least one of the following: the row number feature of the current scan, the ambient temperature feature of the panel, and the cumulative aging time feature of the panel.
[0010] In a preferred embodiment, the analog control signals output by the bit line clamping and differential readout module are multiple independent signals, which respectively provide the discharge slope control parameters, cutoff threshold parameters and trigger delay time parameters required by the subsequent gate pulse modulation module.
[0011] The present invention also provides a method for operating a front-end neuromorphic processing circuit for gate pulse modulation of a display panel, characterized by comprising the following steps: Step S1, Feature Acquisition and Mapping: Extract the real-time physical features of the display panel, map them linearly or non-linearly to an analog voltage vector Vin, and apply them to the word lines of the 1T1R neuromorphic cross array module; Step S2, High linearity simulation calculation: Turn on the selection transistor in the 1T1R unit, and use the conductance values of the non-volatile synaptic devices at both ends as weights to perform parallel simulation matrix multiplication; Step S3, Virtual Ground Clamping and Anti-Drift Readout: The operational amplifier controls the clamping transistor through negative feedback to force the bit line to remain at a fixed reference voltage, eliminate potential drift during the calculation process, and extract the analog convergence current on the positive and negative weighted bit lines. Step S4, Differential Subtraction and Parameter Output: The extracted current is differentially subtracted to obtain the net current, which is then output directly to the subsequent GPM module as a waveform control parameter in the form of current or converted voltage to complete the front-end data processing.
[0012] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention employs a 1T1R architecture to construct a neuromorphic array. By utilizing a selection transistor, it effectively cuts off the creeping current path of unselected cells, ensuring readout accuracy for large-scale arrays. Simultaneously, it innovatively introduces a voltage-regulated common-gate clamp circuit at the readout end, utilizing the "virtual short" characteristic of a high-gain operational amplifier to forcibly clamp the bit line to a fixed reference potential. Regardless of the magnitude of the array's output current, the actual voltage drop across the device is always strictly equal to the input voltage minus the fixed reference voltage, ensuring the absolute validity of Ohm's law and thus guaranteeing extremely high linearity in analog matrix multiplication.
[0013] 2. This invention abandons the cumbersome "ADC sampling - DSP digital processing - SRAM lookup table - DAC output" architecture found in traditional digital driver chips. Through a differential bit-pair design combined with a current mirror circuit, this invention directly performs algebraic subtraction of positive and negative weights in the analog (current) domain, and provides the net output current directly as a control signal to the GPM module. This process eliminates the need for complex analog-to-digital conversion, significantly reducing the power consumption of the display driver IC's front-end information processing and saving valuable chip area.
[0014] 3. The circuit of this invention acts as an independent intelligent "front-end brain," capable of fusing multi-dimensional physical characteristics of the display panel, such as row number, temperature, and aging time, and instantaneously and in parallel outputting multiple control parameters required for GPM (such as discharge slope, cutoff threshold, and delay time) through different columns of the array. This design not only reduces the bandwidth pressure on the digital bus inside the display driver IC but also achieves adaptive and precise modulation of the gate pulse waveform for each row, significantly improving the optical uniformity of large-size display panels. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the overall architecture of the front-end neuromorphic processing circuit of the present invention. Figure 2 This is a schematic diagram of the core circuit of the clamping differential readout module of the 1T1R neuromorphic cross array bit line of the present invention. Figure 3 This is a schematic diagram illustrating the working principle of the GPM module after the circuit outputs multiple parameters to control the output in the embodiment. Detailed Implementation
[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0017] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0018] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof. Example
[0019] This embodiment provides a front-end processing circuit for calculating the GPM discharge slope, referencing... Figure 1-3 It includes a feature mapping input module, a 1T1R neuromorphic cross array module, and a bit-line clamping and differential readout module; The output of the feature mapping input module is connected to the word line of the 1T1R neuromorphic cross array module; the bit line of the 1T1R neuromorphic cross array module is connected to the input of the bit line clamping and differential readout module. The feature mapping input module is used to acquire the physical characteristics of the display panel in real time and convert them into multi-dimensional analog input voltage; The 1T1R neuromorphic cross array module is used to store preset waveform modulation weights, receive the multidimensional analog input voltage and perform analog matrix multiplication operations, and output analog converged current in parallel through multiple bit lines. The bit line clamping and differential readout module is used to clamp the potential of the bit line to a fixed reference voltage, extract the analog convergence current and perform differential subtraction, and output an analog control signal characterizing the modulation parameters to the subsequent gate pulse modulation module.
[0020] 1. Device and array construction: Pt / TaO x / TiN is used as a non-volatile synaptic device at both ends. It is connected in series with an NMOS transistor to form a 1T1R cell. A 32×2 1T1R cross array is constructed.
[0021] 2. Feature Input: The feature mapping input module converts the current scan row number into an analog voltage V. in The input word line is then used. Simultaneously, a turn-on voltage is applied to the gate of the select transistor, completely isolating the creeping current of adjacent cells.
[0022] 3. Clamping and Readout: The two bit lines of the array (BL) ﹢ and BL ﹣ These are connected to the common-gate regulated submodule. The non-inverting input of the operational amplifier is connected to a 0.5V reference voltage, and the inverting input is connected to the bit line. Through negative feedback, the bit line potential is strictly clamped at 0.5V, eliminating potential drift.
[0023] 4. Difference Subtraction and Output: BL ﹢ Current I ﹢ Pulled into the compute node via a PMOS current mirror; BL ﹣ Current I ﹣ The current is drawn from the compute node after passing through a combination of PMOS and NMOS current mirrors. The net current I output from the node is... net = I ﹢ - I ﹣ As the final analog control signal, it is directly handed over to the subsequent GPM circuit to control the drain current of its discharge tube. Example
[0024] This example demonstrates how to provide three parameters simultaneously for the GPM module: "slope", "cutoff threshold", and "delay time".
[0025] 1. Array configuration: Based on HfO x The dielectric layer consists of 1T1R cells, forming a 64×6 array. The 6 bit lines form 3 sets of differential pairs.
[0026] 2. Multidimensional mapping: The row number, the output voltage of the ambient temperature sensor, and the voltage recording the aging time are all used as vector inputs to the word line.
[0027] 3. Parallel Output: After processing by the clamping and differential readout modules, the first set of differential pairs outputs I. slope The discharge slope is adjusted by the GPM; the second differential pair outputs I. vth The current flowing through the resistor is converted into voltage, which is then fed to the GPM comparator to set the cutoff threshold; the third differential pair outputs I. delay The delay time is set by the GPM timer.
[0028] This embodiment successfully completes massive data fusion and computation at the front end. The GPM module only needs to receive these three analog signals to perform adaptive chamfering, which greatly reduces the bandwidth pressure on the digital bus inside the display driver IC.
[0029] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.
Claims
1. A front-end neuromorphic processing circuit for gate pulse modulation of a display panel, characterized in that, It includes a feature mapping input module, a 1T1R neuromorphic cross array module, and a bit-line clamping and differential readout module; The output of the feature mapping input module is connected to the word line of the 1T1R neuromorphic cross array module; the bit line of the 1T1R neuromorphic cross array module is connected to the input of the bit line clamping and differential readout module. The feature mapping input module is used to acquire the physical characteristics of the display panel in real time and convert them into multi-dimensional analog input voltage; The 1T1R neuromorphic cross array module is used to store preset waveform modulation weights, receive the multidimensional analog input voltage and perform analog matrix multiplication operations, and output analog converged current in parallel through multiple bit lines. The bit line clamping and differential readout module is used to clamp the potential of the bit line to a fixed reference voltage, extract the analog convergence current and perform differential subtraction, and output an analog control signal characterizing the modulation parameters to the subsequent gate pulse modulation module.
2. The front-end neuromorphic processing circuit for gate pulse modulation of a display panel according to claim 1, characterized in that, The 1T1R neuromorphic cross array module is composed of multiple 1T1R unit arrays, and each 1T1R unit includes a selection transistor and a two-terminal non-volatile synaptic device. The gate of the select transistor is connected to the control line of the array and is normally open during simulation to eliminate array creeping current; the source or drain of the select transistor is connected in series with one end of the two-terminal non-volatile synaptic device, the other end of the two-terminal non-volatile synaptic device is connected to the word line, and the end of the select transistor not connected to the two-terminal non-volatile synaptic device is connected to the bit line.
3. The front-end neuromorphic processing circuit for gate pulse modulation of a display panel according to claim 1, characterized in that, The bit lines of the 1T1R neuromorphic cross array module adopt a differential pair structure, and each differential pair consists of a positive weight bit line and a negative weight bit line.
4. The front-end neuromorphic processing circuit for gate pulse modulation of a display panel according to claim 1, characterized in that, The bit line clamping and differential readout module includes a regulated common gate clamping submodule and a current subtraction submodule; The voltage-regulating common-gate clamping submodule includes an operational amplifier and a clamping transistor. The inverting input terminal of the operational amplifier is connected to the bit line, the non-inverting input terminal of the operational amplifier is connected to the fixed reference voltage, and the output terminal is connected to the gate of the clamping transistor. The bit line potential is clamped to the fixed reference voltage through negative feedback. The current subtraction submodule uses a current mirroring circuit to algebraically subtract the current extracted from the positive weight bit line from the current extracted from the negative weight bit line at the physical node, and outputs the net current as the analog control signal.
5. The front-end neuromorphic processing circuit for gate pulse modulation of a display panel according to claim 1, characterized in that, The physical features of the display panel collected by the feature mapping input module include at least one of the following: the row number feature of the current scan, the ambient temperature feature of the panel, and the cumulative aging time feature of the panel.
6. The front-end neuromorphic processing circuit for gate pulse modulation of a display panel according to claim 1, characterized in that, The analog control signals output by the bit line clamping and differential readout module are multiple independent signals, which respectively provide the discharge slope control parameters, cutoff threshold parameters and trigger delay time parameters required by the subsequent gate pulse modulation module.
7. A method of operating a front-end neuromorphic processing circuit for gate pulse modulation of a display panel according to any one of claims 1-6, characterized in that, Includes the following steps: Step S1, Feature Acquisition and Mapping: Extract the real-time physical features of the display panel, map them linearly or non-linearly to an analog voltage vector Vin, and apply them to the word lines of the 1T1R neuromorphic cross array module; Step S2, High linearity simulation calculation: Turn on the selection transistor in the 1T1R unit, and use the conductance values of the non-volatile synaptic devices at both ends as weights to perform parallel simulation matrix multiplication; Step S3, Virtual Ground Clamping and Anti-Drift Readout: The operational amplifier controls the clamping transistor through negative feedback to force the bit line to remain at a fixed reference voltage, eliminate potential drift during the calculation process, and extract the analog convergence current on the positive and negative weighted bit lines. Step S4, Differential Subtraction and Parameter Output: The extracted current is differentially subtracted to obtain the net current, which is then output directly to the subsequent GPM module as a waveform control parameter in the form of current or converted voltage to complete the front-end data processing.