Low-voltage low-leakage organic field effect transistor array and preparation method and application thereof

Abstract

The application discloses a low-voltage and low-leakage organic field effect transistor array and a preparation method and application thereof, and belongs to the technical field of organic electronics. The low-voltage and low-leakage organic field effect transistor array cooperatively suppresses leakage current in two directions of vertical and horizontal directions. A high-k-low-k double-layer composite dielectric layer is constructed, wherein the high-k dielectric layer realizes low-voltage gate control, and the low-k dielectric layer serves as a tunneling barrier to suppress vertical gate leakage; meanwhile, a patterned photoetching semiconductor layer is constructed, so that a semiconductor region is located inside a channel, and a horizontal parasitic leakage path is cut off.

Description

Technical Field

[0001] This invention relates to the field of organic electronics technology, and in particular to a low-voltage, low-leakage organic field-effect transistor array, its fabrication method, and its application. Background Technology

[0002] Organic field-effect transistors (OFETs) possess superior flexibility, low cost, large-area fabrication capabilities, and designable molecular structures, making them crucial building blocks for next-generation flexible electronics, skin electronics, bio-integrated systems, and large-area sensor arrays. However, the intrinsic physical properties of polymer dielectric materials and limitations in large-area thin-film fabrication processes lead to a significant increase in gate leakage current, increased power consumption, and poor stability, becoming major factors restricting the commercial application of these devices.

[0003] On the one hand, most existing polymer dielectric materials exhibit non-ideal leakage behavior. Low-k polymers, such as polydimethylsiloxane (PDMS) and polyvinyl alcohol (PVA), have low capacitance per unit area (Ci). To obtain sufficient charge carriers to drive the transistor, extremely high operating voltages (>40V) are typically required. In the pursuit of device miniaturization, this leads to an increase in the electric field strength within the insulating layer, resulting in severe insulation breakdown or gate leakage. High-k polymers, while capable of achieving effective channel control at lower voltages (<12V), often contain a large number of polar groups or residual hydroxyl groups. Under the influence of an electric field, these polar groups not only readily adsorb moisture, resulting in slow polarization (hysteresis in the transfer curve and threshold voltage drift), but also undergo minute intrinsic dissociation. The leakage paths formed by these ion migrations significantly increase the power consumption of the device, severely reducing the transistor's energy efficiency and long-term operational stability. On the other hand, in actual large-area production, continuous, unpatterned semiconductor thin films are commonly used. Since the deposition area of ​​the semiconductor thin film far exceeds the actual channel area of ​​the transistor, numerous conductive paths exist outside the source and drain electrodes, resulting in large-scale parasitic leakage current. These two types of non-ideal leakage behaviors significantly increase the power consumption of the transistor, affecting the device's energy efficiency and operational stability. Therefore, how to synergistically address the intrinsic electrical characteristic defects of the dielectric layer and the parasitic effects brought about by large-area processes to achieve a general-purpose OTFT device with low operating voltage, low leakage current, and high stability is a crucial challenge that urgently needs to be addressed in the field of flexible electronics. Summary of the Invention

[0004] The purpose of this invention is to address the technical deficiencies in the prior art by providing a method for fabricating a low-voltage, low-leakage organic field-effect transistor array.

[0005] Another object of the present invention is to provide a low-voltage, low-leakage organic field-effect transistor array obtained by the above-described preparation method.

[0006] Another object of the present invention is to provide an application of the above-described low-voltage, low-leakage organic field-effect transistor array.

[0007] The technical solution adopted to achieve the purpose of this invention is: A method for fabricating a low-voltage, low-leakage organic field-effect transistor array includes the following steps: Step 1: Spin-coat a high-k dielectric layer solution onto a temporary substrate to obtain a high-k dielectric layer; Step 2: Spin-coat a low-k dielectric solution onto the high-k dielectric layer to obtain a bilayer composite dielectric layer; Step 3: Vapor-phase octadecyltrichlorosilane modification is performed on the double-layer composite dielectric layer to form a stretchable composite dielectric layer on a temporary substrate; Step 4: Use semiconductor solution photolithography to form a patterned semiconductor array semiconductor layer; Step 5: Press the source electrode and drain electrode into the channel formed by the patterned semiconductor array to complete the stacking of the source electrode, drain electrode and semiconductor layer, and then press them onto the stretchable composite dielectric layer of step 3. Step 6: Remove the temporary substrate and attach the gate electrode to the high-k dielectric layer to obtain a low-voltage, low-leakage organic field-effect transistor array.

[0008] In the above technical solution, in step 1, the high-k dielectric layer solution includes polyurethane urea (PUU) solution, nitrile rubber (NBR) solution, or poly(vinylidene fluoride-co-hexafluoropropylene) (P(VDF-HFP)) solution.

[0009] In the above technical solution, the polyurethane urea (PUU) solution preparation process is as follows: 4-aminophenyl disulfide (APDS) is mixed with poly(propylene glycol), toluene-2,4 diisocyanate-terminated (PPG-TDI), a solvent is added, and a polymerization reaction is carried out to obtain a polyurethane urea (PUU) solution.

[0010] In the above technical solution, the nitrile rubber solution is a mixture of nitrile rubber and cyclohexanone.

[0011] In the above technical solution, in step 2, the low-k dielectric layer solution is a styrene-polyethylene-polybutene-styrene block polymer (SEBS) solution; the poly(vinylidene fluoride-co-hexafluoropropylene) solution is a mixture of poly(vinylidene fluoride-co-hexafluoropropylene) and acetone.

[0012] In the above technical solution, the styrene-polyethylene-polybutene-styrene block polymer solution is a mixture of styrene-polyethylene-polybutene-styrene block polymer and toluene.

[0013] In the above technical solution, in step 1, the temporary substrate needs to be cleaned sequentially with water, acetone, and isopropanol, and then dried with nitrogen.

[0014] In the above technical solution, in step 1, the temporary substrate needs to be modified with an octadecyltrichlorosilane solution, wherein the octadecyltrichlorosilane (OTS) solution is a mixture of octadecyltrichlorosilane and n-heptane.

[0015] In the above technical solution, the specific process of using semiconductor solution photolithography in step 4 is as follows: Indobisthiophene cobenzothiadiazole (IDTBT) is dissolved in the solvent chloroform to obtain a semiconductor solution. The semiconductor solution is spin-coated onto another temporary substrate. After annealing, an IDTBT film is obtained. Photoresist is spin-coated onto the IDTBT film, and patterning photolithography is performed. The process includes development, rinsing, drying, oxygen plasma etching, vapor-phase octadecyltrichlorosilane modification, and removal of the photoresist to obtain the semiconductor layer of the patterned semiconductor array.

[0016] In the above technical solution, in step 5, a vacuum mask evaporation method is used to deposit metallic gold as the source and drain.

[0017] In the above technical solution, in step 5, the gate electrode, source electrode, and drain electrode are prepared by the following method: Step 5.1: The conductive polymer dispersion Clevios PH1000 and the ethylene glycol surfactant FS-30 are mixed and heated to obtain a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid (PEDOT:PSS) solution; Step 5.2: Drop poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid solution onto a temporary substrate, heat, spin-coat, anneal, acid-treat, clean, and dry to obtain a PEDOT:PSS film. Under heating conditions, spray an aqueous dispersion of single-walled carbon nanotubes (SWCNTs) onto the PEDOT:PSS film, acid-treat, clean, and dry to obtain a thin film electrode. Step 5.3: Spin-coat photoresist onto the thin film electrode, cure, perform photolithography, development, rinsing, drying, oxygen plasma etching, vapor-phase octadecyltrichlorosilane modification, remove photoresist, and obtain the source electrode, drain electrode and gate electrode respectively; Step 5.4: SEBS solution is dropped onto the source electrode and drain electrode respectively, and then spin-coated and cured to obtain an adhesive layer. PDMS is then cast onto the adhesive layer and spin-coated and cured to obtain an upper substrate containing the source electrode and drain electrode. Step 5.5: Peel off the temporary substrate containing the source electrode and drain electrode from the upper substrate, press the source electrode and drain electrode into the channel formed by the patterned semiconductor array to complete the stacking of the source electrode and drain electrode, and then press them onto the stretchable composite dielectric layer of step 3.

[0018] Another aspect of the present invention includes a low-voltage, low-leakage organic field-effect transistor array obtained by the fabrication method, comprising a plurality of low-voltage, low-leakage organic field-effect transistors. Each low-voltage, low-leakage organic field-effect transistor comprises, from bottom to top, a lower substrate, a gate electrode, a double-layer composite dielectric layer, a semiconductor layer of a patterned semiconductor array, a source and a drain, and an upper substrate. The double-layer composite dielectric layer comprises, from bottom to top, a high-k dielectric layer and a low-k dielectric layer. The source and drain are located within a channel formed by the patterned semiconductor array.

[0019] Another aspect of the present invention includes the application of the low-voltage, low-leakage organic field-effect transistor array in the field of flexible electronics.

[0020] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention discloses a low-voltage, low-leakage organic field-effect transistor array, which synergistically suppresses leakage current in both vertical and lateral directions: a high-k-low-k bilayer composite dielectric layer is constructed, wherein the high-k dielectric layer realizes low-voltage gate control, while the low-k dielectric layer acts as a tunneling barrier to suppress vertical gate leakage; at the same time, the patterned semiconductor layer makes the semiconductor region located inside the channel, cutting off the lateral parasitic leakage path; 2. The method provided by this invention is simple, requires a low preparation temperature, and can be used for large-area fabrication via mechanical exfoliation. This invention effectively suppresses gate leakage in organic thin-film field-effect transistors at its source, thereby solving the problems of increased power consumption and poor stability caused by gate leakage. The method of this invention is applicable to different high-dielectric layer systems and has universality. 3. This invention establishes a material and process foundation for the design and manufacturing process development of low-power, high-performance stretchable electronic devices for different applications. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the organic field-effect transistor array of the present invention.

[0022] Wherein, 1: lower substrate, 2: gate electrode, 3: high-k dielectric layer, 4: low-k dielectric layer, 5: stretchable composite dielectric layer, 6: semiconductor layer, 7: source and drain, 8: upper substrate.

[0023] Figure 2 This is a schematic diagram of an organic field-effect transistor array according to Embodiment 2 or Embodiment 3 of the present invention.

[0024] Figure 3 These are optical microscope images and physical images of the organic field-effect transistor array of Embodiment 1 of the present invention.

[0025] Figure 4 The transfer curves are for the organic field-effect transistor array of Embodiment 1 of the present invention.

[0026] Figure 5 This is a thermal diagram of the gate leakage current of the organic field-effect transistor array in Embodiment 1 of the present invention.

[0027] Figure 6 The figures show the performance variation curves of the organic field-effect transistor array under different stretching conditions in Embodiment 1 of the present invention, wherein (a) is the stretching parallel to the conductive channel; and (b) is the stretching perpendicular to the conductive channel.

[0028] Figure 7 The graph shows the performance change of the organic field-effect transistor array of Embodiment 1 of the present invention after 1000 cycles of 30% stretching.

[0029] Figure 8 The transfer curves are for an organic field-effect transistor, where (a) is the organic field-effect transistor of Comparative Example 1 and (b) is the organic field-effect transistor of Example 2.

[0030] Figure 9 The transition curves are for an array of field-effect transistors, where (a) is the field-effect transistor of Comparative Example 2 and (b) is the field-effect transistor of Example 3. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0032] Example 1 like Figure 1 As shown, a method for fabricating a low-voltage, low-leakage organic field-effect transistor array includes the following steps: Step 1: Spin-coat a high-k dielectric solution onto a temporary substrate (silicon) to obtain a high-k dielectric layer; specifically including the following steps: Step 1.1: The first temporary substrate is sequentially cleaned with deionized water, acetone, and isopropanol, then bleed with nitrogen, and treated with oxygen plasma for 3 min. Subsequently, it is immersed in a hydrophobic octadecyltrichlorosilane solution (a mixture of octadecyltrichlorosilane and n-heptane in a volume ratio of 1:1000) for octadecyltrichlorosilane solution modification for 2 h to obtain the first temporary substrate modified with OTS.

[0033] Step 1.2: 4-Aminophenyl disulfide (APDS) and poly(propylene glycol), toluene-2,4-diisocyanate-terminated (PPG-TDI) were mixed at a mass ratio of 12:100 and dissolved in tetrahydrofuran at a concentration of 170 mg / ml. The mixture was placed on a heating table at 40°C and 200 rpm for 24 h to carry out the dissolution and polymerization reaction, thereby obtaining a polyurethane urea (PUU) solution.

[0034] Step 1.3: A 170 mg / ml polyurethane urea (PUU) solution was drop-cast onto the first temporary substrate modified with OTS, spin-coated at 5000 rpm for 40 s, and cured at 100 °C for 4 h to obtain a high-k dielectric layer.

[0035] Step 2 involves spin-coating a low-k dielectric solution onto the high-k dielectric layer to obtain a composite dielectric layer; specifically, this includes the following steps: Step 2.1: Add ethylene-polyethylene-polybutene-styrene block polymer (SEBS) particles to the solvent toluene and place them on a heating table at 40°C and 300 rpm for 12 hours to dissolve them, forming a styrene-polyethylene-polybutene-styrene block polymer (SEBS) solution with a concentration of 10 mg / ml.

[0036] Step 2.2: The SEBS solution is drop-cast onto the high-k dielectric layer obtained in step 1, spin-coated at 5000 rpm for 40 s, and then dried at 80°C for 30 min to obtain the composite dielectric layer.

[0037] Step 3: Place the composite dielectric layer in an oven at 60°C and modify it with 1.5 μL of vapor-phase OTS for 30 min to form a stretchable composite dielectric layer on the first temporary substrate.

[0038] Step 4 specifically includes the following steps: Step 4.1: The second temporary substrate (silicon) is sequentially cleaned with deionized water, acetone, and isopropanol, then bleed with nitrogen, and then treated with oxygen plasma for 3 min. After that, it is placed in an oven at 60°C and modified with 1.5 μL of gas phase OTS for 30 min to obtain the second temporary substrate modified with gas phase OTS.

[0039] Step 4.2: Add indene dithiophene cobenzothiadiazole (IDTBT) to the solvent chloroform and place it on a heating table at 40°C and 300 rpm for 4 hours to dissolve it, forming an IDTBT solution with a concentration of 5 mg / ml. Step 4.3: Drop casting of IDTBT solution onto the second temporary substrate modified with vapor phase OTS, spin coating at 1500 rpm for 40 s, followed by annealing at 100 °C for 30 min under nitrogen atmosphere to obtain IDTBT film.

[0040] Step 4.4: Spin-coat photoresist (AZ 5200) onto the IDTBT film at 6000 rpm for 30 s, dry at 100℃ for 4 min for curing, place in a photolithography machine, and perform photolithography according to the pattern to form a patterned semiconductor array (including 5×5 semiconductor array sites). After removal, place in diluted developer (developer:water = 1:4) for 1 min for development, remove, rinse with deionized water twice and dry with nitrogen, etch with 0.36 mbar oxygen plasma for 7 min, modify with 1.5 μL gas phase OTS at 60℃ for 30 min, place in acetone solvent for photoresist removal for 1 min, rinse with acetone and dry with nitrogen to form a semiconductor layer of a crisscrossed rectangular semiconductor array.

[0041] Step 5 specifically includes the following steps: Step 5.1: Mix 20 mL of conductive polymer dispersion Clevios PH1000, 1.3 mL of ethylene glycol and 42.57 μL of fluorosurfactant FS-30, and place on a heating stage at 40 °C and 200 rpm for 12 h to dissolve, thus obtaining a PEDOT:PSS solution.

[0042] 1.3636 g of aqueous dispersion of single-walled carbon nanotubes (SWCNTs) was diluted in 20 ml of water, sonicated for 10 min, and centrifuged at 2000 rpm for 30 min to obtain the SWCNTs solution.

[0043] Step 5.2: Drop-cast the PEDOT:PSS solution onto the OTS-modified third temporary substrate (silicon wafer), place it on a heating stage at 80°C for 1 min, spin-coat at 6000 rpm for 30 s, anneal in an oven at 100°C for 1 h, immerse in concentrated nitric acid for 3 min of acid treatment, rinse thoroughly with deionized water, and dry with nitrogen to obtain a PEDOT:PSS film. Place the PEDOT:PSS film on a heating stage at 150°C, and then spray SWCNTs solution 20-25 times at a distance of 25 cm above the PEDOT:PSS film. Immerse in concentrated nitric acid for 3 min of acid treatment, rinse thoroughly with deionized water, and dry with nitrogen to obtain a thin film electrode.

[0044] Step 5.3: Spin-coat photoresist (AZ 5200) onto the thin-film electrode at 6000 rpm for 30 s, and cure at 100℃ for 4 min. Perform photolithography according to the source electrode, drain electrode, and gate electrode patterns respectively. Develop in diluted developer (developer:water = 1:4) for 1 min, remove, rinse with deionized water, and dry with nitrogen. Etch with 0.36 mbar oxygen plasma for 7 min, remove, modify with 1.5 μL of vapor-phase OTS at 60℃ for 30 min, remove in acetone solvent for 1 min to remove the photoresist, rinse with acetone, and dry with nitrogen to obtain the source electrode, drain electrode, and gate electrode respectively.

[0045] Step 5.4: Add SEBS particles to the solvent toluene and dissolve them on a heating stage at 40°C and 300 rpm for 12 hours to obtain a SEBS solution with a concentration of 60 mg / ml. Drop the SEBS solution onto the source and drain electrodes, spin coat at 1000 rpm for 60 seconds, and cure at 80°C for 30 minutes to obtain an adhesive layer. Then, cast PDMS (PDMS prepolymer and crosslinking agent mixed at a volume ratio of 10:1) onto the adhesive layer, spin coat at 400 rpm for 30 seconds, and cure at 100°C for 30 minutes to obtain an upper substrate containing source and drain electrodes.

[0046] Step 5.5: After heating the third temporary substrate containing the source electrode and drain electrode for three minutes, peel it off. Press the source electrode and drain electrode into the channel formed by the patterned semiconductor array in step 4.4 to complete the stacking of the source electrode, drain electrode and semiconductor layer. Peel off the second temporary substrate and press it onto the stretchable composite dielectric layer in step 3. After heating for three minutes, peel off the first temporary substrate. Step 6: Drop-cast the SEBS solution from Step 5.4 onto the gate electrode, spin-coat at 1000 rpm for 60 s, and cure at 80°C for 30 min to obtain an adhesive layer. Then, cast PDMS (PDMS prepolymer and crosslinking agent mixed at a volume ratio of 10:1) onto the adhesive layer, spin-coat at 400 rpm for 30 s, and cure at 100°C for 30 min to obtain a lower substrate containing the gate electrode. Then, attach the gate electrode to the high-k dielectric layer, align the upper and lower substrates, and obtain a low-voltage, low-leakage organic field-effect transistor array (stretchable) with a total of 25 transistors.

[0047] Depend on Figure 3 As can be seen from the optical microscope, the semiconductor and electrode patterning edges are sharp, achieving high-precision patterning. The physical image shows that the device exhibits no delamination or breakage under stretching, demonstrating its excellent mechanical properties.

[0048] Id is the drain current and IG is the gate drain current.

[0049] Example 2 like Figure 2 As shown, this embodiment provides a method for fabricating a low-voltage, low-leakage organic field-effect transistor array, which differs from the fabrication method in Embodiment 1 in the following ways: Step 1.3: P(VDF-HFP) solution (polyvinylidene fluoride-hexafluoropropylene) is drop-cast onto the first temporary substrate, spin-coated at 4500 rpm for 40 s, and dried at 100°C for 30 min to obtain a high-k dielectric layer. The P(VDF-HFP) solution is obtained by mixing P(VDF-HFP) with acetone solvent at a mass ratio of 1:9 and dissolving on a heating stage at 40°C and 200 rpm for 12 h.

[0050] The patterned semiconductor array from step 4.4 needs to be transferred onto the stretchable composite dielectric layer using 3M tape.

[0051] Step 5.4: Using a vacuum mask evaporation method, gold is deposited into the channels formed by the patterned semiconductor array in step 4.4 to obtain source and drain electrodes with a thickness of 30 nm each, at a vacuum level of 5 × 10⁻⁶. -6 The torr deposition rate is 0.01 nm / s.

[0052] Step 6: Fabricate gate electrodes (silicon wafers) on the high-k dielectric layer to finally obtain a low-voltage, low-leakage organic field-effect transistor array.

[0053] The remaining steps are the same as in Example 1.

[0054] Example 3 This embodiment provides a method for fabricating a low-voltage, low-leakage organic field-effect transistor array, which differs from the fabrication method in Embodiment 2 in the following ways: Step 1.3: The NBR solution is drop-cast onto the first temporary substrate, spin-coated at 1000 rpm for 80 s, and dried at 100°C for 10 min to obtain a high-k dielectric layer. The NBR solution is obtained by adding NBR to the solvent cyclohexanone and placing it on a heating stage at 100°C and 300 rpm for 12 h to dissolve and form an NBR solution with a concentration of 25 mg / ml.

[0055] The remaining steps are the same as in Example 2.

[0056] Example 4 like Figure 1As shown, this embodiment provides an organic field-effect transistor array obtained by the fabrication method of Embodiment 1, including multiple low-voltage, low-leakage organic field-effect transistors. Each low-voltage, low-leakage organic field-effect transistor includes, from bottom to top, a lower substrate 1, a gate electrode 2, a stretchable composite dielectric layer 5, a semiconductor layer 6 of a patterned semiconductor array, a source and a drain 7, and an upper substrate 8. The stretchable composite dielectric layer includes, from bottom to top, a high-k dielectric layer 3 and a low-k dielectric layer 4. The source and drain 7 are located within the channel formed by the patterned semiconductor array.

[0057] Comparative Example 1 This comparative example provides a method for fabricating an organic field-effect transistor array, which differs from the method in Example 2 in the following ways: the dielectric layer is only a high-k dielectric layer, and no low-k dielectric layer is composited on it; the rest of the fabrication is the same as in Example 2.

[0058] Comparative Example 2 This comparative example provides a method for fabricating an organic field-effect transistor array, which differs from the method in Example 3 in the following ways: the dielectric layer is a single-layer NBR, and the rest of the fabrication is the same as in Example 3.

[0059] Application Example 1 The electrical performance of the transistor array in Example 1 was tested as follows: Probes were placed on the source, drain, and gate of each transistor, respectively. The source was grounded, a voltage of -10 V was applied to the drain, and the gate voltage ranged from -10 V to 2 V. The transfer curve of each transistor was then measured. Transfer curves for 25 transistors were obtained, and the results are as follows. Figure 4 As shown. Figure 4 The gate leakage current in the transfer curve at a gate voltage of -10 V, and the sum of the gate leakage currents of the 25 transistors, are shown below. Figure 5 As shown. By Figure 4 and Figure 5 It can be seen that each transistor exhibits good uniformity, can operate normally at -10V, and the gate leakage current is less than 10V. -8 A.

[0060] Application Example 2 The useless power consumption and mobility of any transistor prepared in Example 1 were tested. The experimental procedure was as follows: The left and right ends of the transistor were fixed to vernier calipers and secured with tape, and its initial length was measured. The transistor was then stretched along the direction parallel to the channel and perpendicular to the channel, respectively, to strains of 25%, 50%, 75%, and 100%. Its transfer curve was measured, and its useless power consumption and mobility were calculated. The strain was defined as: (stretched length - initial length) / initial length. The results are as follows. Figure 6 As shown. By Figure 6 The average mobility is 0.335 ± 0.06 cm.2 V -1 s -1 The useless power consumption at 0% is 5.88 × 10⁻⁶. -8 When W is stretched to 100% parallel to the channel, the useless power consumption is 6.04 × 10⁻⁶. -8 When W is stretched to 100% perpendicular to the channel, the useless power consumption is 6.47 × 10⁻⁶. -8 The change in useless power consumption before and after stretching is slight, indicating that stretching has no effect on the electrical performance of the device.

[0061] One transistor from Example 1 was stretched to 30% length parallel to and perpendicular to the channel, and then restored to its original length as one cycle. This was repeated 500 times and 1000 times, and its transfer curve was tested. Figure 7 As shown, the wasted power and mobility were calculated. In the 0-100% tensile test and the 30% tensile test with 1000 cycles, the performance degradation of the low-voltage, low-leakage organic field-effect transistor was negligible, demonstrating good tensile properties and mechanical stability. The wasted power at 0% was 5.53 × 10⁻⁶. -8 After being stretched parallel to the channel to 30% and subjected to 1000 cyclic stretching cycles, the useless power consumption is 6.36 × 10⁻⁶. -8 After being stretched perpendicular to the channel to 30% and subjected to 1000 cyclic stretching cycles, the useless power consumption is 8.17 × 10⁻⁶. -8 This indicates that the transistor has good mechanical stability.

[0062] Application Example 3 like Figure 8 As shown in (a) of Comparative Example 1, an organic field-effect transistor can operate at -10 V and has a mobility of 0.109 cm⁻¹. 2 V -1 s -1 The leakage current is 2×10 -8 A. Compared with the results of Comparative Example 1, Example 2 ( Figure 8 In transistor (b) of the above, the mobility increased from 0.109 to 0.956 cm⁻¹. 2 V -1 s -1 The on / off ratio is 10. 4 Leakage current from 2×10 -8 A decreased to 2×10 -9 A. In Example 2, by adding a layer of SEBS and semiconductor patterning on the PVDF-HFP, the vertical leakage current and lateral parasitic current of the transistor are reduced, respectively. The leakage current and power consumption are reduced by nearly an order of magnitude, while the mobility is increased by nearly an order of magnitude.

[0063] Application Example 4 like Figure 9As shown in (a) of Comparative Example 2, an organic field-effect transistor can operate at -10 V and has a mobility of 0.077 cm⁻¹. 2 V -1 s -1 The leakage current is 1.3 × 10⁻⁶. -7 A. Compared with Comparative Example 2, Example 3 ( Figure 9 In (b) of the above, the mobility ranges from 0.077 cm⁻¹. 2 V -1 s -1 Increased to 0.71 cm 2 V -1 s -1 The on / off ratio is 10. 5 The leakage current is 1.3 × 10 -7 A decreased to 2×10 -8 A. By adding a layer of SEBS and semiconductor patterning on the NBR, leakage current and power consumption are reduced by nearly an order of magnitude, while mobility is increased by an order of magnitude.

[0064] The above description is only a preferred embodiment of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a low-voltage, low-leakage organic field-effect transistor array, characterized in that, Includes the following steps: Step 1: Spin-coat a high-k dielectric layer solution onto a temporary substrate to obtain a high-k dielectric layer; Step 2: Spin-coat a low-k dielectric solution onto the high-k dielectric layer to obtain a bilayer composite dielectric layer; Step 3: Vapor-phase octadecyltrichlorosilane modification is performed on the double-layer composite dielectric layer to form a stretchable composite dielectric layer on a temporary substrate; Step 4: Use semiconductor solution photolithography to form a patterned semiconductor array semiconductor layer; Step 5: Press the source electrode and drain electrode into the channel formed by the patterned semiconductor array to complete the stacking of the source electrode, drain electrode and semiconductor layer, and then press them onto the stretchable composite dielectric layer of step 3. Step 6: Remove the temporary substrate and attach the gate electrode to the high-k dielectric layer to obtain a low-voltage, low-leakage organic field-effect transistor array.

2. The preparation method according to claim 1, characterized in that, In step 1, the high-k dielectric layer solution includes a polyurethane urea solution, a nitrile rubber solution, or a poly(vinylidene fluoride-co-hexafluoropropylene) solution.

3. The preparation method according to claim 1, characterized in that, In step 1, the temporary substrate needs to be modified with an octadecyltrichlorosilane solution, which is a mixture of octadecyltrichlorosilane and n-heptane.

4. The preparation method according to claim 2, characterized in that, The preparation process of the polyurethane urea solution is as follows: 4-aminophenyl disulfide is mixed with poly(propylene glycol) and toluene-2,4-diisocyanate for end capping, and then a solvent is added to carry out a polymerization reaction to obtain the polyurethane urea solution; the nitrile rubber solution is a mixture of nitrile rubber and cyclohexanone. The poly(vinylidene fluoride-co-hexafluoropropylene) solution is a mixture of poly(vinylidene fluoride-co-hexafluoropropylene) and acetone.

5. The preparation method according to claim 1, characterized in that, In step 2, the low-k dielectric layer solution is a styrene-polyethylene-polybutene-styrene block polymer solution; the styrene-polyethylene-polybutene-styrene block polymer solution is a mixture of styrene-polyethylene-polybutene-styrene block polymer and toluene.

6. The preparation method according to claim 1, characterized in that, In step 4, the specific process of using semiconductor solution photolithography for patterning is as follows: Indobisthiophene cobenzothiadiazole is dissolved in chloroform to obtain a semiconductor solution. The semiconductor solution is spin-coated onto another temporary substrate, annealed, and an IDTBT film is obtained. Photoresist is spin-coated onto the IDTBT film, and patterning photolithography is performed, followed by development, rinsing, drying, oxygen plasma etching, vapor-phase octadecyltrichlorosilane modification, and removal of the photoresist to obtain the semiconductor layer of the patterned semiconductor array.

7. The preparation method according to claim 1, characterized in that, In step 5, a vacuum mask evaporation method is used to deposit metallic gold as the source and drain.

8. The preparation method according to claim 1, characterized in that, In step 5, the gate electrode, source electrode, and drain electrode are prepared by the following method: Step 5.1: The conductive polymer dispersion Clevios PH1000 and the ethylene glycol surfactant FS-30 are mixed and heated to obtain a poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid solution. Step 5.2: Drop poly(3,4-ethylenedioxythiophene)-polystyrene sulfonic acid solution onto a temporary substrate, heat, spin-coat, anneal, acid-treat, clean, and dry to obtain a PEDOT:PSS film. Under heating conditions, spray an aqueous dispersion of single-walled carbon nanotubes onto the PEDOT:PSS film, acid-treat, clean, and dry to obtain a thin film electrode. Step 5.3: Spin-coat photoresist onto the thin film electrode, cure, perform photolithography, development, rinsing, drying, oxygen plasma etching, vapor-phase octadecyltrichlorosilane modification, remove photoresist, and obtain the source electrode, drain electrode and gate electrode respectively; Step 5.4: SEBS solution is dropped onto the source electrode and drain electrode respectively, and then spin-coated and cured to obtain an adhesive layer. PDMS is then cast onto the adhesive layer and spin-coated and cured to obtain an upper substrate containing the source electrode and drain electrode. Step 5.5: Peel off the temporary substrate containing the source electrode and drain electrode from the upper substrate, press the source electrode and drain electrode into the channel formed by the patterned semiconductor array to complete the stacking of the source electrode and drain electrode, and then press them onto the stretchable composite dielectric layer of step 3.

9. The low-voltage, low-leakage organic field-effect transistor array obtained by the fabrication method according to any one of claims 1 to 8, characterized in that, It includes multiple low-voltage, low-leakage organic field-effect transistors. Each low-voltage, low-leakage organic field-effect transistor includes, from bottom to top, a lower substrate, a gate electrode, a double-layer composite dielectric layer, a semiconductor layer of a patterned semiconductor array, a source and a drain, and an upper substrate. The double-layer composite dielectric layer includes, from bottom to top, a high-k dielectric layer and a low-k dielectric layer. The source and drain are located within a channel formed by the patterned semiconductor array.

10. The application of the low-voltage, low-leakage organic field-effect transistor array as described in claim 9 in the field of flexible electronics.

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