Hall sensor chip and method of manufacturing

Abstract

The application relates to the technical field of sensors, and provides a Hall sensor chip and a manufacturing method. The Hall sensor chip comprises a first type substrate, a first type well region formed in the first type substrate, a first ultrathin tunneling oxide layer and a contact electrode formed on the surface of the first type well region, and a second type heavily doped polysilicon layer formed on the surface of the first ultrathin tunneling oxide layer; the first type substrate, the first ultrathin tunneling oxide layer and the second type heavily doped polysilicon layer constitute a tunneling oxide layer passivation contact structure; the doping type of the first type well region is different from the doping type of the second type heavily doped polysilicon layer, and under the action of the first ultrathin tunneling oxide layer, the surface of the first type well region can form a depletion region. The application utilizes the tunneling oxide layer passivation contact structure to reduce the influence of surface effects on the performance of the Hall sensor and reduce noise caused by interface states.

Description

Technical Field

[0001] This invention relates to the field of sensor technology, and more specifically to a Hall sensor chip and its manufacturing method. Background Technology

[0002] A Hall sensor is a magnetic sensor used for measuring magnetic fields. It utilizes the Hall effect in semiconductors to measure the Hall voltage generated in a Hall device by an external magnetic field. Because Hall sensors have a simple structure, especially silicon-based Hall sensors which can be monolithically integrated with backend conditioning circuit ICs, their cost is very low. This makes Hall sensors widely used in magnetic field measurement, position measurement, and current measurement.

[0003] Existing Hall element structures typically consist of a P-substrate, an N-well formed on the P-substrate, an N+ contact electrode formed on the N-well, and a P+ capping layer formed on the surface of the N-well. The surface of the Hall element generally contains a significant amount of residual charge and interface states. These charges and interface states affect the transport of charge carriers within the N-well region, thus significantly impacting the noise and offset of the Hall element; this is known as the surface effect. To reduce the surface effect, a P+ capping layer can be applied to the N-well surface. Firstly, the P+ capping layer separates the N-well doped region from the surface, preventing surface defects and charges from affecting the current in the N-well, effectively reducing the 1 / f noise of the Hall element. Secondly, the P+ capping layer can reduce the effective thickness of the N-well, which can improve the current-dependent sensitivity of the Hall element to some extent.

[0004] The common method for forming a P+ capping layer on the N-well surface is to create a P+ doped region using ion implantation or diffusion. This method can reduce surface effects to some extent, but it also has some unavoidable drawbacks. First, ion implantation typically produces a long tail, making it difficult to precisely control the implantation depth and consequently the thickness of the Hall effective region, leading to poor sensitivity consistency of the Hall element. Second, ion implantation generates numerous defects in the implanted region. While these defects can be partially eliminated through post-annealing, the remaining defects still increase carrier recombination, thus affecting the performance of the Hall element. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a Hall sensor chip and its manufacturing method, which uses a tunnel oxide passivating contact (TOPCon) structure to replace the P+ doped layer in traditional Hall elements, thereby reducing the impact of surface effects on the performance of the Hall sensor.

[0006] The first aspect of the present invention provides a Hall sensor chip, comprising: a first type substrate, a first type well region formed in the first type substrate, a first ultrathin tunneling oxide layer and a contact electrode formed on the surface of the first type well region, and a second type heavily doped polycrystalline silicon layer formed on the surface of the first ultrathin tunneling oxide layer; The first type of substrate, the first ultrathin tunneling oxide layer, and the second type of heavily doped polycrystalline silicon layer constitute a tunneling oxide layer passivation contact structure. The doping type of the first type of well region is different from that of the second type of heavily doped polycrystalline silicon layer. Under the action of the first ultrathin tunneling oxide layer, a depletion region can be formed on the surface of the first type of well region.

[0007] In this embodiment of the invention, the thickness of the first ultrathin tunneling oxide layer is 1~1.6 nm; The thickness of the second type of heavily doped polysilicon layer is 20~200 nm, and the doping concentration of the second type of heavily doped polysilicon layer is greater than 1×10⁻⁶. 20 cm -3 .

[0008] In this embodiment of the invention, the doping type of the first type of well region is N-type, and the doping type of the second type of heavily doped polysilicon layer is P-type. Alternatively, the first type of well region is doped with P-type, and the second type of heavily doped polysilicon layer is doped with N-type.

[0009] In this embodiment of the invention, the contact electrode includes: a second ultrathin tunneling oxide layer and a first type of heavily doped polycrystalline silicon layer. The doping type of the first type of heavily doped polycrystalline silicon layer is different from that of the second type of heavily doped polycrystalline silicon layer, and the doping type of the first type of heavily doped polycrystalline silicon layer is the same as that of the first type of substrate.

[0010] In this embodiment of the invention, the doping type of the second type of heavily doped polysilicon layer is P-type, the doping type of the first type of heavily doped polysilicon layer is N-type, and the doping type of the first type of substrate is N-type. Alternatively, the second type of heavily doped polysilicon layer is N-type, the first type of heavily doped polysilicon layer is P-type, and the first type of substrate is P-type.

[0011] In this embodiment of the invention, the Hall sensor chip further includes: a ground electrode; The second type of heavily doped polycrystalline silicon layer is directly connected to the ground electrode.

[0012] A second aspect of the present invention provides a method for manufacturing a Hall sensor chip, comprising: A first-type well region is formed in a first-type substrate; An ultrathin tunneling oxide layer is formed on the surface of the first type of well region; A second type of heavily doped polycrystalline silicon layer is formed on the surface of an ultrathin tunneling oxide layer; Contact electrodes are formed on the first type of well region; The first type of substrate, the ultrathin tunneling oxide layer, and the second type of heavily doped polysilicon layer constitute a tunneling oxide passivation contact structure. The doping type of the second type of heavily doped polysilicon layer is different from the doping type of the first type of well region. Under the action of the ultrathin tunneling oxide layer, a depletion region can be formed on the surface of the first type of well region.

[0013] In this embodiment of the invention, forming a first-type well region in a first-type substrate includes: An N-type silicon substrate was used as the first type of substrate, and an oxide layer with a thickness of 200 nm was grown on the surface of the N-type silicon substrate. An ion implantation window is formed on the oxide layer by photolithography. N-type ion implantation is performed in the ion implantation window to form an N-type well region, which serves as the first type of well region.

[0014] In this embodiment of the invention, forming an ultrathin tunneling oxide layer on the surface of the first type of well region includes: A dense oxide layer is grown on the surface of the first type of well region by dry oxygen oxidation or wet chemical oxidation, and the thickness of the oxide layer is controlled to be 1~1.6 nm. This oxide layer serves as an ultrathin tunneling oxide layer.

[0015] In this embodiment of the invention, forming a second type of heavily doped polycrystalline silicon layer on the surface of the ultrathin tunneling oxide layer includes: A layer of polycrystalline silicon is deposited on the surface of an ultrathin tunneling oxide layer using chemical vapor deposition. At the same time, P-type ion doping is performed in situ to form a heavily doped P-type polycrystalline silicon layer, which serves as a second type of heavily doped polycrystalline silicon layer.

[0016] In this embodiment of the invention, forming a contact electrode on the first type of well region includes: A contact electrode region window is formed on the surface of the first type of well region using photolithography. An ultrathin oxide layer is grown within the window of the contact electrode region, and N-type heavily doped polycrystalline silicon is deposited on the ultrathin oxide layer to form an N-type heavily doped polycrystalline silicon layer. The ultrathin oxide layer and the N-type heavily doped polycrystalline silicon layer constitute the contact electrode.

[0017] In this embodiment of the invention, forming a contact electrode on the first type of well region includes: The surface of the first type of well region surrounding the tunnel oxide passivation contact structure is heavily N-type doped to form an N+ region, which serves as the contact electrode.

[0018] This invention uses a tunneling oxide passivated contact (TOPCon) structure to replace the P+ doped layer in traditional Hall elements. The tunneling oxide passivated contact (TOPCon) structure provides excellent passivation for the well region surface and can generate a depletion region on the well region surface, preventing the current in the well region from passing through the device surface, thereby reducing the impact of surface effects on the performance of the Hall sensor. At the same time, the tunneling oxide passivated contact (TOPCon) structure provides excellent passivation for the well region surface, reducing the influence of interface charge and interface dangling bonds on the Hall current, and can effectively reduce the 1 / f noise caused by interface states.

[0019] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a cross-sectional structural diagram of the Hall sensor chip provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the planar structure of the Hall sensor chip provided in Embodiment 1 of the present invention; Figure 3 This is a cross-sectional structural diagram of the Hall sensor chip provided in Embodiment 2 of the present invention; Figure 4 This is a flowchart of a method for manufacturing a Hall sensor chip according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the well region formed in the manufacturing method provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the ultrathin tunneling oxide layer formed in the manufacturing method provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the structure of the heavily doped polycrystalline silicon layer formed in the manufacturing method provided in the embodiments of the present invention; Figure 8 This is a schematic diagram of the structure of the contact electrode formed in the manufacturing method provided in the embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of the contact electrode formed in the manufacturing method provided in another embodiment of the present invention; Figure 10This is a schematic diagram of the structure of the metal electrode formed in the manufacturing method provided in the embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures 10-Substrate, 11-Trap region, 12-First ultrathin tunneling oxide layer, 13-Second type heavily doped polycrystalline silicon layer, 14-Contact electrode, 15-Second ultrathin tunneling oxide layer, 16-First type heavily doped polycrystalline silicon layer, 17-Metal electrode. Detailed Implementation

[0022] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0023] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0024] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "interlocked" should be interpreted broadly, referring to mechanical connections, electrical connections, or connections that allow for mutual communication; direct connections or indirect connections via an intermediate medium; and connections within two components or interactions between two components. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0025] Existing Hall sensor chips typically consist of a P-substrate, an N-well formed on the P-substrate, an N+ contact electrode formed on the N-well, and a P+ capping layer formed on the surface of the N-well. A P+ doped region is usually formed as the P+ capping layer using methods such as ion implantation or diffusion. This method can reduce surface effects to some extent, but it also has drawbacks: First, ion implantation generally produces a relatively long tail, making it difficult to precisely control the ion implantation depth, which in turn makes it difficult to precisely control the thickness of the Hall effective region, resulting in poor sensitivity consistency of the Hall element; second, ion implantation generates many defects in the implanted region. Although these defects can be partially eliminated by post-annealing, the remaining defects still cause increased carrier recombination, thus affecting the performance of the Hall element.

[0026] To address the problems of existing technologies, embodiments of the present invention provide a Hall sensor chip and a manufacturing method thereof. The Hall sensor chip includes: a first type substrate, a first type well region formed in the first type substrate, a first ultrathin tunneling oxide layer and a contact electrode formed on the surface of the first type well region, and a second type heavily doped polysilicon layer formed on the surface of the first ultrathin tunneling oxide layer. The first type substrate, the first ultrathin tunneling oxide layer, and the second type heavily doped polysilicon layer constitute a tunneling oxide passivation contact (TOPCon) structure. The doping type of the first type well region is different from that of the second type heavily doped polysilicon layer. Under the action of the first ultrathin tunneling oxide layer, a depletion region can be formed on the surface of the first type well region. This invention employs a tunneling oxide passivated contact (TOPCon) structure to replace the P+ doped layer in traditional Hall elements. The TOPCon structure provides excellent passivation for the well region surface and generates a depletion region on the well region surface, preventing current in the well region from passing through the device surface, thereby reducing the impact of surface effects on the performance of the Hall sensor. At the same time, the TOPCon structure provides excellent passivation for the well region surface, reducing the influence of interface charge and interface dangling bonds on the Hall current, and can effectively reduce 1 / f noise caused by interface states.

[0027] In the above description, the first type and the second type refer to two types of charge carriers: P-type (holes) and N-type (electrons). If the first type is P-type, then the second type is N-type; if the first type is N-type, then the second type is P-type. In this embodiment of the invention, the doping type of the first type well region is opposite to the doping type of the second type heavily doped polysilicon layer. If the doping type of the first type well region is N-type, then the doping type of the second type heavily doped polysilicon layer is P-type; if the doping type of the first type well region is P-type, then the doping type of the second type heavily doped polysilicon layer is N-type. The technical solution of the present invention will be described in detail below through specific embodiments.

[0028] Example 1 Figure 1 This is a cross-sectional structural diagram of the Hall sensor chip provided in Embodiment 1 of the present invention. Figure 1 As shown, the Hall sensor chip provided in this embodiment includes: an N-type substrate 10, an N-type well region 11, a first ultrathin tunneling oxide layer 12, a second type heavily doped polysilicon layer 13, and a contact electrode 14. The N-type well region 11 is formed in the N-type substrate 10, the first ultrathin tunneling oxide layer 12 is formed on the surface of the N-type well region 11, and the second type heavily doped polysilicon layer 13 is formed on the surface of the first ultrathin tunneling oxide layer 12. The N-type substrate 10, the first ultrathin tunneling oxide layer 12, and the second type heavily doped polysilicon layer 13 constitute a tunneling oxide passivated contact (TOPCon) structure. The second type heavily doped polysilicon layer 13 is a P-type heavily doped polysilicon layer. In the TOPCon structure, the heavily doped polysilicon and the ultrathin tunneling oxide layer work together to effectively passivate the surface of the N-type well region. Moreover, since the doping type of the N-type well region is different from (opposite to) that of the heavily doped polysilicon layer of the P-type well, and the thickness of the first ultrathin tunneling oxide layer is very small, a depletion region can be formed on the surface of the N-type well region under the action of the first ultrathin tunneling oxide layer. This prevents the current in the N-type well region from passing through the surface of the N-type well region, thereby reducing the impact of surface effects on the performance of the Hall element.

[0029] In this embodiment, an ultrathin tunneling oxide layer and a heavily doped polysilicon layer are stacked to form a tunneling oxide passivation contact (TOPCon) structure, which provides interface passivation and majority carrier tunneling transport. A TOPCon structure is formed on the well region of the Hall element. The heavily doped polysilicon and oxide layer in the TOPCon structure work together to effectively passivate the surface of the N-type well region. Since the doping type of the P-type heavily doped polysilicon is opposite to that of the N-type well region, and the oxide layer thickness between them is very small, a depletion region is generated on the surface of the N-type well region. This prevents the current in the N-type well region from passing through the surface, thereby reducing the impact of surface effects on the performance of the Hall element. This embodiment of the invention applies a TOPCon structure to the Hall element, which can optimize interface carrier transport and improve the response speed and sensitivity of the Hall element.

[0030] The ultrathin tunneling oxide layer, as the core of the TOPCon structure, allows majority carriers (electrons) to tunnel through while minority carriers (holes) are blocked. If the thickness of the ultrathin tunneling oxide layer is too thick, it will hinder tunneling; if the thickness is too thin, it will passivate and fail.

[0031] In a preferred embodiment, the thickness of the first ultrathin tunneling oxide layer 12 is 1~1.6 nm. The thickness of the second type heavily doped polycrystalline silicon layer 13 is 20~200 nm, and the doping type of the second type heavily doped polycrystalline silicon layer 13 is P-type with a doping concentration greater than 1×10⁻⁶.20 cm -3 .

[0032] like Figure 1 and Figure 2 As shown, the N-type well region 11 in the N-type substrate 10 serves as the Hall disk of the Hall element, and the TOPCon structure is formed on the surface of the Hall disk as a capping layer. Contact electrodes 14 are formed on the surface of the N-type well region 11, located around the Hall disk, and separated from the TOPCon structure. Preferably, the TOPCon structure is located at the center of the Hall disk, and four contact electrodes are symmetrically distributed around the TOPCon structure.

[0033] In a preferred embodiment, the Hall sensor chip is provided with a ground electrode (not shown in the figure). The second type (P-type) heavily doped polysilicon layer in the TOPCon structure can also serve as an electrode. The second type (P-type) heavily doped polysilicon layer is directly connected to the ground electrode, thereby keeping this region in a low potential region. This not only improves the stability of the device but also provides shielding, enhancing the device's anti-interference capability.

[0034] Example 2 Figure 3 This is a cross-sectional structural diagram of the Hall sensor chip provided in Embodiment 2 of the present invention. Figure 3 As shown, the Hall sensor chip provided in this embodiment includes: an N-type substrate 10, an N-type well region 11, a first ultrathin tunneling oxide layer 12, a second type heavily doped polysilicon layer 13, and contact electrodes. The contact electrodes include a second ultrathin tunneling oxide layer 15 and a first type heavily doped polysilicon layer 16. The N-type well region 11 is formed in the N-type substrate 10, the first ultrathin tunneling oxide layer 12 is formed on the surface of the N-type well region 11, and the second type heavily doped polysilicon layer 13 is formed on the surface of the first ultrathin tunneling oxide layer 12. The N-type substrate 10, the first ultrathin tunneling oxide layer 12, and the second type heavily doped polysilicon layer 13 constitute a tunneling oxide passivated contact (TOPCon) structure. The second type heavily doped polysilicon layer 13 is a P-type heavily doped polysilicon layer. In the TOPCon structure, the heavily doped polysilicon and the ultrathin tunneling oxide layer work together to effectively passivate the surface of the N-type well region. Moreover, since the doping type of the N-type well region is different from (opposite to) that of the heavily doped polysilicon layer of the P-type well, and the thickness of the first ultrathin tunneling oxide layer is very small, a depletion region can be formed on the surface of the N-type well region under the action of the first ultrathin tunneling oxide layer. This prevents the current in the N-type well region from passing through the surface of the N-type well region, thereby reducing the impact of surface effects on the performance of the Hall element.

[0035] In this embodiment, an ultrathin tunneling oxide layer and a heavily doped polysilicon layer are stacked to form a TOPCon structure, which provides interface passivation and majority carrier tunneling transport. The TOPCon structure is formed on the well region of the Hall element. The heavily doped polysilicon and oxide layer in the TOPCon structure work together to effectively passivate the surface of the N-type well region. Since the doping type of the P-type heavily doped polysilicon is opposite to that of the N-type well region, and the oxide layer between them is very thin, a depletion region is generated on the surface of the N-type well region. This prevents the current in the N-type well region from passing through the surface, thereby reducing the impact of surface effects on the performance of the Hall element. This embodiment of the invention applies a TOPCon structure to the Hall element, which can optimize interface carrier transport and improve the response speed and sensitivity of the Hall element.

[0036] In this embodiment, the thickness of the first ultrathin tunneling oxide layer 12 is 1~1.6 nm. The thickness of the second type heavily doped polycrystalline silicon layer 13 is 20~200 nm, and the doping type of the second type heavily doped polycrystalline silicon layer 13 is P-type with a doping concentration greater than 1×10⁻⁶. 20 cm -3 .

[0037] In this embodiment, a TOPCon structure is used for passivation of the substrate surface in the Hall element, and also as a contact electrode. That is, both the power excitation electrode (the well region and its surface capping layer) and the Hall detection electrode (contact electrode) in the Hall element employ a TOPCon structure. The contact electrode includes a second ultrathin tunneling oxide layer 15 and a first-type heavily doped polysilicon layer 16. The first-type heavily doped polysilicon layer 16 constituting the Hall detection electrode (contact electrode) is N-type doped, and the second-type heavily doped polysilicon layer 13 constituting the power excitation electrode (the TOPCon structure serving as the well region surface capping layer) is P-type doped. That is, the doping type (N-type) of the first-type heavily doped polysilicon layer is different from the doping type (P-type) of the second-type heavily doped polysilicon layer, but the doping type (N-type) of the first-type heavily doped polysilicon layer is the same as the doping type of the N-type substrate.

[0038] Optionally, the second type of heavily doped polysilicon layer 13 is p-type, the first type of heavily doped polysilicon layer 16 is n-type, and the first type of substrate 10 is n-type. Alternatively, the second type of heavily doped polysilicon layer 13 is n-type, the first type of heavily doped polysilicon layer 16 is p-type, and the first type of substrate 10 is p-type.

[0039] Optionally, the Hall sensor chip may be equipped with a ground electrode (not shown in the attached diagram). The second type (P-type) heavily doped polysilicon layer in the TOPCon structure can also function as an electrode. The second type (P-type) heavily doped polysilicon layer is directly connected to the ground electrode, thereby keeping this region in a low potential region. This not only improves the stability of the device but also provides shielding, enhancing the device's anti-interference capability.

[0040] The Hall sensor chip provided in this embodiment of the invention has the following characteristics: 1. In Hall elements, the TOPCon structure is used to cover the N-well region, replacing the P+ covering region in traditional Hall elements. This avoids direct ion implantation into the silicon substrate, effectively reducing damage inside the substrate and avoiding the problem of increased carrier recombination rate caused by Auger recombination in the P+ region, thus reducing the carrier recombination rate on the substrate surface. The doping type of the polysilicon in the TOPCon structure is opposite to that of the substrate, which can form a depletion layer on the substrate surface, achieving the same function as the traditional P+ capping layer, that is, pushing the effective Hall region into the substrate, and avoiding the problem of poor depth control of the traditional P+ capping layer.

[0041] 2. The TOPCon structure consists of a silicon substrate, an ultrathin oxide layer, and heavily doped polysilicon. This structure is similar to the polysilicon gate structure in CMOS technology and can be fabricated using the polysilicon gate process in CMOS technology, making it compatible with CMOS technology.

[0042] 3. The ultrathin oxide layer in the TOPCon structure is very dense, which can effectively passivate the surface states, further reduce the recombination of charge carriers on the surface, and effectively reduce the interface states on the silicon surface.

[0043] 4. The doping type of the heavily doped polysilicon in the TOPCon structure is opposite to that of the N-well in the Hall element. It can form a depletion region on the surface of the N-well, which limits the current to a certain depth below the surface of the N-well and avoids the influence of the interface state of the silicon surface.

[0044] 5. The ultrathin oxide layer and the heavily doped polycrystalline silicon layer in the TOPCon structure work together to passivate the N-well silicon surface, reduce the influence of interface charge and interface dangling bonds on the Hall current, and effectively reduce the 1 / f noise caused by interface states.

[0045] 6. The TOPCon structure can be selectively used to fabricate the contact electrode in the Hall element. When the TOPCon structure is used as the contact electrode, the doping type of the polycrystalline silicon in it is the same as the doping type of the substrate. When the TOPCon structure is used as the contact electrode, the surface of the contact area can be passivated. Compared with the traditional method where the metal directly contacts the silicon substrate, the carrier recombination rate in the contact area can be effectively reduced, thereby reducing the noise of the device.

[0046] 7. The TOPCon structure, which replaces the traditional P+ cover layer, can be directly grounded, providing shielding for the Hall area and effectively improving the anti-interference capability of the Hall element.

[0047] This invention provides a method for manufacturing the Hall sensor chip described above. For example... Figure 4 As shown, the manufacturing method of the Hall sensor chip provided in this embodiment includes the following steps: S410, forming a first-type well region in a first-type substrate; S420, an ultrathin tunneling oxide layer is formed on the surface of the first type of well region; S430, a second type of heavily doped polycrystalline silicon layer is formed on the surface of an ultrathin tunneling oxide layer; S440, a contact electrode is formed on the first type of well region.

[0048] The first type of substrate, the ultrathin tunneling oxide layer, and the second type of heavily doped polysilicon layer constitute the tunneling oxide passivation contact (TOPCon) structure. The doping type of the second type of heavily doped polysilicon layer is different from that of the first type of well region. Under the action of the ultrathin tunneling oxide layer, a depletion region can be formed on the surface of the first type of well region.

[0049] In this embodiment of the invention, if the first type is P-type, then the second type is N-type; if the first type is N-type, then the second type is P-type. The doping type of the first type well region is opposite to the doping type of the second type heavily doped polysilicon layer. If the doping type of the first type well region is N-type, then the doping type of the second type heavily doped polysilicon layer is P-type; if the doping type of the first type well region is P-type, then the doping type of the second type heavily doped polysilicon layer is N-type.

[0050] In step S410 above, forming a first-type well region in a first-type substrate specifically includes: using an N-type silicon substrate as the first-type substrate 10, growing an oxide layer with a thickness of 200 nm on the surface of the N-type silicon substrate using thermal oxidation or chemical vapor deposition (CVD); forming an ion implantation window on the oxide layer using photolithography, and performing N-type ion implantation in the ion implantation window to form a well region as described above. Figure 5 The N-type well region 11 shown is a first type of well region.

[0051] In step S420 above, forming an ultrathin tunneling oxide layer on the surface of the first type of well region specifically includes: growing a dense oxide layer on the surface of the N-type well region 11 using dry oxygen oxidation or wet chemical oxidation, and controlling the thickness of the oxide layer to be 1~1.6 nm. This oxide layer serves as the first ultrathin tunneling oxide layer 12, and the structure of the first ultrathin tunneling oxide layer 12 is as follows: Figure 6 As shown.

[0052] In step S430 above, forming a second type of heavily doped polycrystalline silicon layer on the surface of the ultrathin tunneling oxide layer specifically includes: depositing a layer of polycrystalline silicon on the surface of the first ultrathin tunneling oxide layer 12 using chemical vapor deposition (CVD), and simultaneously performing in-situ doping with P-type ions (such as boron (B), gallium (Ga), or indium (In)) to form a P-type heavily doped polycrystalline silicon layer. This P-type heavily doped polycrystalline silicon layer serves as the second type of heavily doped polycrystalline silicon layer 13, and the structure of the second type of heavily doped polycrystalline silicon layer 13 is as follows: Figure 7 As shown, the heavily doped polysilicon in the TOPCon structure is formed by in-situ doping, which avoids the lateral diffusion of impurities in the ion implantation process. The size of the covered area is easy to control, which can effectively reduce the zero bias of the Hall element.

[0053] In an optional embodiment, the contact electrode adopts a TOPCon structure. In step S440 above, the contact electrode with the TOPCon structure is formed as follows: a contact electrode region window is formed on the surface of the N-type well region 11 using a photolithography process; a second ultrathin tunneling oxide layer 15 is grown and formed within the contact electrode region window; and N-type (such as phosphorus or arsenic) heavily doped polycrystalline silicon is deposited on the second ultrathin tunneling oxide layer 15 to form a first type heavily doped polycrystalline silicon layer 16 (N-type heavily doped polycrystalline silicon layer). The second ultrathin tunneling oxide layer 15 and the first type heavily doped polycrystalline silicon layer 16 constitute a structure as follows: Figure 8 The contact electrode is shown.

[0054] In an optional embodiment, refer to Figure 2 In the N-type substrate 10, the N-type well region 11 serves as the Hall disk of the Hall element, and the TOPCon structure composed of the first ultrathin tunneling oxide layer 12 and the second type heavily doped polycrystalline silicon layer 13 is located on the surface of the Hall disk as a capping layer. Figure 9 As shown, contact electrodes 14 are formed on the surface of the N-type well region 11, located around the Hall disk, and separated from the TOPCon structure. The TOPCon structure is located at the center of the Hall disk, and four contact electrodes are symmetrically distributed around the TOPCon structure.

[0055] In another embodiment, the contact electrode can be formed in step S440 by heavily doping the surface of the N-type well region around the TOPCon structure with N-type (such as phosphorus or arsenic) to form an N+ region, which serves as the contact electrode 14.

[0056] After step S440, a second type of heavily doped polysilicon layer 13 and a contact electrode 14 are formed on their surfaces. Figure 10 The metal electrodes shown complete the fabrication of the Hall sensor chip. Specifically, the metal electrodes are formed by depositing metal material on the surface of a second-type (P-type) heavily doped polysilicon layer, the surface of the contact electrode, and / or the surface of a first-type (N-type) heavily doped polysilicon layer, followed by planarization to form metal electrode 17.

[0057] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. A Hall sensor chip, characterized in that, include: A first type of substrate, a first type of well region formed in the first type of substrate, a first ultrathin tunneling oxide layer and a contact electrode formed on the surface of the first type of well region, and a second type of heavily doped polycrystalline silicon layer formed on the surface of the first ultrathin tunneling oxide layer. The first type of substrate, the first ultrathin tunneling oxide layer, and the second type of heavily doped polycrystalline silicon layer constitute a tunneling oxide layer passivation contact structure. The doping type of the first type of well region is different from that of the second type of heavily doped polycrystalline silicon layer. Under the action of the first ultrathin tunneling oxide layer, a depletion region can be formed on the surface of the first type of well region.

2. The Hall sensor chip according to claim 1, characterized in that, The thickness of the first ultrathin tunneling oxide layer is 1~1.6 nm; The thickness of the second type of heavily doped polysilicon layer is 20~200 nm, and the doping concentration of the second type of heavily doped polysilicon layer is greater than 1×10⁻⁶. 20 cm -3 .

3. The Hall sensor chip according to claim 1, characterized in that, The first type of well region is doped with N-type, and the second type of heavily doped polysilicon layer is doped with P-type. Alternatively, the first type of well region is doped with P-type, and the second type of heavily doped polysilicon layer is doped with N-type.

4. The Hall sensor chip according to claim 1, characterized in that, The contact electrode includes: a second ultrathin tunneling oxide layer and a first type of heavily doped polycrystalline silicon layer. The doping type of the first type of heavily doped polycrystalline silicon layer is different from that of the second type of heavily doped polycrystalline silicon layer. The doping type of the first type of heavily doped polycrystalline silicon layer is the same as that of the first type of substrate.

5. The Hall sensor chip according to claim 4, characterized in that, The second type of heavily doped polysilicon layer is P-type, the first type of heavily doped polysilicon layer is N-type, and the first type of substrate is N-type. Alternatively, the second type of heavily doped polysilicon layer is N-type, the first type of heavily doped polysilicon layer is P-type, and the first type of substrate is P-type.

6. The Hall sensor chip according to claim 1, characterized in that, Also includes: Grounding electrode; The second type of heavily doped polycrystalline silicon layer is directly connected to the ground electrode.

7. A method for manufacturing a Hall sensor chip, characterized in that, include: A first-type well region is formed in a first-type substrate; An ultrathin tunneling oxide layer is formed on the surface of the first type of well region; A second type of heavily doped polycrystalline silicon layer is formed on the surface of an ultrathin tunneling oxide layer; Contact electrodes are formed on the first type of well region; The first type of substrate, the ultrathin tunneling oxide layer, and the second type of heavily doped polysilicon layer constitute a tunneling oxide passivation contact structure. The doping type of the second type of heavily doped polysilicon layer is different from the doping type of the first type of well region. Under the action of the ultrathin tunneling oxide layer, a depletion region can be formed on the surface of the first type of well region.

8. The method for manufacturing a Hall sensor chip according to claim 7, characterized in that, The formation of a first-type well region in a first-type substrate includes: An N-type silicon substrate was used as the first type of substrate, and an oxide layer with a thickness of 200 nm was grown on the surface of the N-type silicon substrate. An ion implantation window is formed on the oxide layer by photolithography. N-type ion implantation is performed in the ion implantation window to form an N-type well region, which serves as the first type of well region.

9. The method for manufacturing a Hall sensor chip according to claim 7, characterized in that, The formation of an ultrathin tunneling oxide layer on the surface of the first type of well region includes: A dense oxide layer is grown on the surface of the first type of well region by dry oxygen oxidation or wet chemical oxidation, and the thickness of the oxide layer is controlled to be 1~1.6 nm. This oxide layer serves as an ultrathin tunneling oxide layer.

10. The method for manufacturing a Hall sensor chip according to claim 7, characterized in that, The formation of a second type of heavily doped polycrystalline silicon layer on the surface of the ultrathin tunneling oxide layer includes: A layer of polycrystalline silicon is deposited on the surface of an ultrathin tunneling oxide layer using chemical vapor deposition. At the same time, P-type ion doping is performed in situ to form a heavily doped P-type polycrystalline silicon layer, which serves as a second type of heavily doped polycrystalline silicon layer.

11. The method for manufacturing a Hall sensor chip according to claim 7, characterized in that, The formation of contact electrodes on the first type of well region includes: A contact electrode region window is formed on the surface of the first type of well region using photolithography. An ultrathin oxide layer is grown within the window of the contact electrode region, and N-type heavily doped polycrystalline silicon is deposited on the ultrathin oxide layer to form an N-type heavily doped polycrystalline silicon layer. The ultrathin oxide layer and the N-type heavily doped polycrystalline silicon layer constitute the contact electrode.

12. The method for manufacturing a Hall sensor chip according to claim 7, characterized in that, The formation of contact electrodes on the first type of well region includes: The surface of the first type of well region surrounding the tunnel oxide passivation contact structure is heavily N-type doped to form an N+ region, which serves as the contact electrode.

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