Test structure and test method

Abstract

A test structure and a test method, the test structure comprising: a metal plate; a to-be-tested interconnection via electrically connected with the metal plate; a first interconnection via located at a side of the to-be-tested interconnection via and electrically connected with the metal plate; a first current signal loading end electrically connected with a top of the to-be-tested interconnection via; a first voltage signal loading end electrically connected with the top of the to-be-tested interconnection via and separated from the first current signal loading end; a second current signal loading end electrically connected with the first interconnection via; and a second voltage signal loading end electrically connected with the first interconnection via and separated from the second current signal loading end. The precision of obtaining the resistance value of the to-be-tested interconnection via to the metal plate is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a test structure and test method. Background Technology

[0002] In semiconductor technology, MiM (Metal-Insulator-Metal) plate resistor technology involves the use of multilayer metal structures. MiMs are widely used in radio frequency (RF) and microwave circuits, semiconductor packaging, and high-performance integrated circuits to achieve precise resistance matching, signal transmission, and power management. By utilizing the conductivity properties of different metal materials and the dielectric properties of the insulating layer, MiMs can achieve the required resistance value within a limited space, while reducing parasitic effects and signal interference, thus improving circuit performance and reliability.

[0003] By selecting appropriate metal materials and insulating dielectrics, the resistance of metal plates can provide a consistent value over a wide frequency range and is insensitive to temperature and process variations. Furthermore, MiM structures are easily integrated with existing semiconductor manufacturing processes, supporting smaller feature sizes and higher circuit densities, which is crucial for modern electronic devices that prioritize miniaturization and cost-effectiveness.

[0004] Currently, the accuracy of obtaining the resistance value from the through-hole (RDV) to the metal plate still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a test structure and test method to improve the accuracy of obtaining the resistance value from the interconnect to the metal plate.

[0006] To address the aforementioned problems, embodiments of the present invention provide a test structure, comprising: a metal electrode plate; an interconnecting via to be tested, electrically connected to the metal electrode plate; a first interconnecting via located on the side of the interconnecting via to be tested, and electrically connected to the metal electrode plate; a first current signal loading terminal electrically connected to the top of the interconnecting via to be tested; a first voltage signal loading terminal electrically connected to the top of the interconnecting via to be tested, and the first voltage signal loading terminal is separate from the first current signal loading terminal; a second current signal loading terminal electrically connected to the first interconnecting via; and a second voltage signal loading terminal electrically connected to the first interconnecting via, and the second voltage signal loading terminal is separate from the second current signal loading terminal.

[0007] Optionally, the interconnect via to be tested includes one or more sub-interconnect vias to be tested; when the interconnect via to be tested is a plurality of sub-interconnect vias to be tested, the plurality of sub-interconnect vias to be tested are arranged in parallel at intervals along a first direction and a second direction, and the first direction and the second direction are perpendicular to each other.

[0008] Optionally, the second current signal loading terminal and the second voltage signal loading terminal are both located on top of the first interconnect via; the test structure further includes: a first interconnect layer located on top of the first interconnect via, and the bottom of the first interconnect layer is electrically connected to the first interconnect via, and the top of the first interconnect layer is electrically connected to the second current signal loading terminal and the second voltage signal loading terminal.

[0009] Optionally, the first interconnect via includes a plurality of first sub-interconnect vias, and the plurality of first sub-interconnect vias are arranged in parallel at intervals along the same direction and located at the edge portion of the metal electrode plate.

[0010] Optionally, the first current signal loading terminal includes a first main body and a first protrusion in contact with the first main body; the first voltage signal loading terminal includes a first main body and a second protrusion in contact with the first main body, the first protrusion and the second protrusion are separate, the first current signal loading terminal and the first voltage signal loading terminal share the first main body, and the first main body is electrically connected to the interconnecting via to be tested.

[0011] Optionally, the second current signal loading terminal includes a second main body and a third protrusion in contact with the second main body; the second voltage signal loading terminal includes a second main body and a fourth protrusion in contact with the second main body, the third protrusion and the fourth protrusion are separate, the second current signal recording terminal and the second voltage signal loading terminal share the second main body, and the second main body is electrically connected to the first interconnecting via.

[0012] Optionally, the second main body surrounds the edge portion of the metal electrode plate, and the first end and the last end of the second main body are spaced apart.

[0013] Optionally, the first main body portion penetrates the area between the beginning and end ends of the second main body portion.

[0014] Optionally, the first current signal loading terminal, the first voltage signal loading terminal, the second current signal loading terminal, and the second voltage signal loading terminal are located on the same layer.

[0015] Optionally, the materials of the first current signal loading terminal, the second current signal loading terminal, the first voltage signal loading terminal, and the second voltage signal loading terminal all include aluminum.

[0016] Optionally, the metal plate includes a capacitor metal plate.

[0017] Accordingly, this embodiment of the invention also provides a testing method, comprising: providing the test structure provided in this embodiment of the invention; applying a constant current between the first current signal loading terminal and the second current signal loading terminal; after applying a constant current between the first current signal loading terminal and the second current signal loading terminal, obtaining the voltage between the first voltage signal loading terminal and the second voltage signal loading terminal; and obtaining the resistance value from the interconnect to the metal plate based on the voltage and the constant current.

[0018] Optionally, the resistance value R = V / I from the interconnect to the metal plate is obtained, where V refers to the voltage between the first voltage signal loading terminal and the second voltage signal loading terminal, and I refers to the constant current applied between the first current signal loading terminal and the second current signal loading terminal.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0020] In the test structure provided in this embodiment of the invention, the interconnect via under test is electrically connected to the metal electrode plate. A first interconnect via is located on the side of the interconnect via under test and is electrically connected to the metal electrode plate. A first current signal loading terminal is electrically connected to the top of the interconnect via under test, and a first voltage signal loading terminal is electrically connected to the top of the interconnect via under test, but the first voltage signal loading terminal is separate from the first current signal loading terminal. A second current signal loading terminal is electrically connected to the first interconnect via, and a second voltage signal loading terminal is electrically connected to the first interconnect via, but the second voltage signal loading terminal is separate from the second current signal loading terminal. During the subsequent measurement of the resistance value from the interconnect via under test to the metal electrode plate, a constant current is applied to the first current signal loading terminal and the second current signal loading terminal to make the interconnect via under test... A first test path is formed between the metal plate and the first interconnect via. The current flowing through the interconnect to be tested to the metal plate is the applied constant current. In the subsequent process of obtaining the voltage between the first voltage signal loading terminal and the second voltage signal loading terminal, a second test path is also formed between the interconnect to be tested, the metal plate, and the first interconnect via. The input impedance in the second test path is much greater than the resistance value from the interconnect to be tested to the metal plate, so that the voltage value of the first interconnect via and the metal plate itself can be ignored. Thus, the voltage obtained in the second test path is the voltage from the interconnect to be tested to the metal plate. Since the voltage obtained in the second test path is the voltage from the interconnect to be tested to the metal plate, the current flowing through the interconnect to be tested to the metal plate is the applied constant current, thereby improving the accuracy of obtaining the resistance value from the interconnect to the metal plate. Attached Figure Description

[0021] Figure 1This is a schematic diagram of an embodiment of the test structure of the present invention;

[0022] Figure 2 This is a flowchart corresponding to one embodiment of the testing method of the present invention. Detailed Implementation

[0023] As is known from the background art, the accuracy of obtaining the resistance value from the interconnect via to the metal plate still needs to be improved.

[0024] To address the aforementioned technical problems, embodiments of the present invention provide a test structure, comprising: a metal electrode plate; an interconnecting via to be tested, electrically connected to the metal electrode plate; a first interconnecting via located on the side of the interconnecting via to be tested, and electrically connected to the metal electrode plate; a first current signal loading terminal electrically connected to the top of the interconnecting via to be tested; a first voltage signal loading terminal electrically connected to the top of the interconnecting via to be tested, and the first voltage signal loading terminal is separate from the first current signal loading terminal; a second current signal loading terminal electrically connected to the first interconnecting via; and a second voltage signal loading terminal electrically connected to the first interconnecting via, and the second voltage signal loading terminal is separate from the second current signal loading terminal.

[0025] In the test structure provided in this embodiment of the invention, the interconnect via under test is electrically connected to the metal electrode plate. A first interconnect via is located on the side of the interconnect via under test and is electrically connected to the metal electrode plate. A first current signal loading terminal is electrically connected to the top of the interconnect via under test, and a first voltage signal loading terminal is electrically connected to the top of the interconnect via under test, but the first voltage signal loading terminal is separate from the first current signal loading terminal. A second current signal loading terminal is electrically connected to the first interconnect via, and a second voltage signal loading terminal is electrically connected to the first interconnect via, but the second voltage signal loading terminal is separate from the second current signal loading terminal. During the subsequent measurement of the resistance value from the interconnect via under test to the metal electrode plate, a constant current is applied to the first current signal loading terminal and the second current signal loading terminal to make the interconnect via under test... A first test path is formed between the metal plate and the first interconnect via. The current flowing through the interconnect to be tested to the metal plate is the applied constant current. In the subsequent process of obtaining the voltage between the first voltage signal loading terminal and the second voltage signal loading terminal, a second test path is also formed between the interconnect to be tested, the metal plate, and the first interconnect via. The input impedance in the second test path is much greater than the resistance value from the interconnect to be tested to the metal plate, so that the voltage value of the first interconnect via and the metal plate itself can be ignored. Thus, the voltage obtained in the second test path is the voltage from the interconnect to be tested to the metal plate. Since the voltage obtained in the second test path is the voltage from the interconnect to be tested to the metal plate, the current flowing through the interconnect to be tested to the metal plate is the applied constant current, thereby improving the accuracy of obtaining the resistance value from the interconnect to the metal plate.

[0026] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic diagram of an embodiment of the test structure of the present invention.

[0028] refer to Figure 1The test structure includes: a metal electrode plate 106; an interconnect via 136 to be tested, electrically connected to the metal electrode plate 106; a first interconnect via 102 located on the side of the interconnect via 136 to be tested, and the first interconnect via 102 is electrically connected to the metal electrode plate 106; a first current signal loading terminal 122 electrically connected to the top of the interconnect via 136 to be tested; a first voltage signal loading terminal 132 electrically connected to the top of the interconnect via 136 to be tested, and the first voltage signal loading terminal 132 is separate from the first current signal loading terminal 122; a second current signal loading terminal 112 electrically connected to the first interconnect via 102; and a second voltage signal loading terminal 109 electrically connected to the first interconnect via 102, and the second voltage signal loading terminal 109 is separate from the second current signal loading terminal 112.

[0029] It should be noted that the interconnect via 136 under test is electrically connected to the metal electrode plate 106, the first interconnect via 102 is located on the side of the interconnect via 136 under test, and the first interconnect via 102 is electrically connected to the metal electrode plate 106. The first current signal loading terminal 122 is electrically connected to the top of the interconnect via 136 under test, and the first voltage signal loading terminal 132 is electrically connected to the top of the interconnect via 136 under test, and the first voltage signal loading terminal 132 is electrically connected to the first current signal loading terminal 106. The circuit is divided into two phases: the second current signal loading terminal 112 is electrically connected to the first interconnect via 102, and the second voltage signal loading terminal 109 is electrically connected to the first interconnect via 102, but the second voltage signal loading terminal 109 is separated from the second current signal loading terminal 112. During the subsequent measurement of the resistance value from the interconnect via 136 to the metal plate 106, a constant current is applied to the first current signal loading terminal 122 and the second current signal loading terminal 112, forming a first test path between the interconnect via 136, the metal plate 106, and the first interconnect via 102. The current flowing through the interconnect via 136 to the metal plate 106 is the applied constant current. During the subsequent acquisition of the voltage between the first voltage signal loading terminal 132 and the second voltage signal loading terminal 109, a second test path is also formed between the interconnect via 136, the metal plate 106, and the first interconnect via 102. The input impedance in this second test path is much greater than that between the interconnect via 136 and the metal plate 106. The resistance value is such that the voltage value between the first interconnect via 102 and the metal plate 106 is negligible, thus the voltage obtained in the second test path is the voltage between the interconnect via 136 and the metal plate 106. Since the voltage obtained in the second test path is the voltage between the interconnect via 136 and the metal plate 106, the current passing through the interconnect via 136 and the metal plate 106 is the applied constant current, thereby improving the accuracy of obtaining the resistance value between the interconnect via 136 and the metal plate 106.

[0030] Specifically, the metal electrode 106 is used to electrically connect to the interconnect via 136 under test and the first interconnect via 102, so that the interconnect via 136 under test, the metal electrode 106 and the first interconnect via 102 can form a test path.

[0031] As an example, the metal plate 106 includes a capacitor (MiM) metal plate 106.

[0032] It should be noted that, with the metal plate 106 as the structure under test, in the subsequent test method, the resistance value from the interconnect 136 to the metal plate 106 is obtained, thereby determining whether the interconnect 136 to the capacitor metal plate 106 can meet the electrical performance requirements.

[0033] Specifically, the interconnect via 136 is used as the structure under test for testing, which facilitates the subsequent acquisition of the resistance value from the interconnect via 136 to the metal plate 106.

[0034] In this embodiment, the interconnect via 136 to be tested includes one or more sub-interconnect vias 100 to be tested.

[0035] It should be noted that the interconnect via 136 under test is used to electrically connect to the metal plate 106. In the subsequent test method, a constant current is applied between the first current signal loading terminal 122 and the second current signal loading terminal 112, and the voltage between the first voltage signal loading terminal 132 and the second voltage signal loading terminal 109 is obtained to obtain the resistance value from the interconnect via 136 under test to the metal plate 106. By making the interconnect via 136 under test include multiple sub-interconnect vias 100 under test, after obtaining the resistance value from the interconnect via 136 under test to the metal plate 106, it is convenient to quickly obtain the resistance value from each sub-interconnect via 100 under test to the metal plate 106.

[0036] In this embodiment, when the interconnect via 136 to be tested is a plurality of sub-interconnect vias 100 to be tested, the plurality of sub-interconnect vias 100 to be tested are along a first direction (e.g., Figure 1 (as shown in the X direction) and the second direction (as shown in the X direction) Figure 1 The first and second directions are arranged in parallel at intervals (as shown in the Y direction), and the first and second directions are perpendicular to each other.

[0037] Specifically, the multiple interconnect vias 100 under test are arranged in parallel at intervals along the first and second directions. This means that the multiple interconnect vias 100 under test are arranged in a matrix along the first and second directions, making the spacing between adjacent interconnect vias 100 under test the same. This reduces the process difficulty of forming the multiple interconnect vias 100 under test. At the same time, the parallel arrangement of the multiple interconnect vias 100 under test along the first and second directions also makes the contact area between the interconnect vias 100 under test and the metal electrode plate 106 the same. This means that the resistance between the interconnect vias 100 under test and the metal electrode plate 106 is the same. Accordingly, after obtaining the resistance value between the interconnect vias 136 under test and the metal electrode plate 106, the resistance between each interconnect via 100 under test and the metal electrode plate 106 can be quickly determined by the number of interconnect vias 100 under test.

[0038] It should be noted that the first interconnect via 102 is electrically connected to the metal electrode 106, thereby enabling the metal electrode 106 to be electrically connected to the second current signal loading terminal 112 and the second voltage signal loading terminal 109 through the first interconnect via 102. This allows the interconnect via 136 under test to form a test path to the metal electrode, which is beneficial for subsequently obtaining the current and voltage of the interconnect via 136 under test to the metal electrode.

[0039] In this embodiment, the first interconnect via 102 includes a plurality of first sub-interconnect vias 101, and the plurality of first sub-interconnect vias 101 are arranged in parallel at intervals along the same direction and located at the edge portion of the metal electrode plate 106.

[0040] Specifically, the first interconnect via 102 includes a plurality of first sub-interconnect vias 101, thereby making the contact area between each first sub-interconnect via 101 and the second current signal loading terminal 112 and the second voltage signal loading terminal 109 moderate. This reduces the contact resistance between the first sub-interconnect via 101 and the second current signal loading terminal 112 and the second voltage signal loading terminal 109 during the subsequent formation of the test path, thereby reducing the impact of the contact resistance on the accuracy of obtaining the resistance value from the interconnect via 136 to the metal plate electrode.

[0041] It should be noted that the plurality of first sub-interconnect vias 101 are located at the edge portion of the metal electrode plate 106, which can increase the distance between the first sub-interconnect vias 101 and the interconnect vias 136 to be tested. During the formation of the first sub-interconnect vias 101, the formation process window can be increased, and the process difficulty of forming the first sub-interconnect vias 101 can be reduced.

[0042] It should be noted that the first current signal loading terminal 122 is used as a constant loading current.

[0043] In this embodiment, the first current signal loading terminal 122 is located above the interconnect via 136 to be tested.

[0044] Specifically, the first current signal loading terminal 122 is located above the interconnect via 136 to be tested, which can reduce the area occupied by the test structure and facilitate further reduction in the volume of the test structure.

[0045] In this embodiment, the first current signal loading terminal 122 includes a first main body portion 120 and a first protrusion portion 121 that contacts the first main body portion 120.

[0046] It should be noted that the first main body 120 is used to electrically connect with the interconnect via 136 to be tested, and the first protrusion 121 is used to electrically connect with the external circuit structure, so that the interconnect via 136 to be tested can be electrically connected with the external circuit structure through the first main body 120 and the first protrusion 121.

[0047] As an example, the material of the first current signal loading terminal 122 includes aluminum.

[0048] Specifically, aluminum has good electrical conductivity, low resistivity, and low material cost, making it suitable for large-scale use.

[0049] It should be noted that the first voltage signal loading terminal 132 is used as a port for measuring voltage.

[0050] In this embodiment, the first voltage signal loading terminal 132 includes a first main body portion 120 and a second protrusion portion 131 that contacts the first main body portion 120. The first protrusion portion 121 and the second protrusion portion 131 are separate. The first current signal loading terminal 122 and the first voltage signal loading terminal 132 share the first main body portion 120, and the first main body portion 120 is electrically connected to the interconnect via 136 to be tested.

[0051] It should be noted that the first main body 120 is used to electrically connect with the interconnect via 136 under test, and the second protrusion 131 is used to electrically connect with the external circuit structure. This allows the interconnect via 136 under test to be electrically connected to the external circuit structure through the first main body 120 and the second protrusion 131. At the same time, the first protrusion 121 and the second protrusion 131 are separated, which reduces the probability of the first protrusion 121 and the second protrusion 131 being short-circuited. This allows the first protrusion 121 to be used to apply a constant current, and the second protrusion 131 to be used to measure voltage.

[0052] It should also be noted that the first current signal loading terminal 122 and the first voltage signal loading terminal 132 share the first main body 120, which eliminates the need for both the first current signal loading terminal 122 and the first voltage signal loading terminal 132 to have a main body, thereby reducing the number of process steps and lowering the process cost.

[0053] As an example, the material of the first voltage signal loading terminal 132 includes aluminum.

[0054] It should be noted that the second current signal loading terminal 112 is used as a constant current loading terminal.

[0055] In this embodiment, the second current signal loading terminal 112 and the second voltage signal loading terminal 109 are both located on top of the first interconnect via 102.

[0056] Specifically, the second current signal loading terminal 112 and the second voltage signal loading terminal 109 are both located on top of the first interconnect via 102, which can reduce the area occupied by the test structure and facilitate further reduction in the volume of the test structure.

[0057] In this embodiment, the second current signal loading terminal 112 includes a second main body 108 and a third protrusion 110 that contacts the second main body 108.

[0058] It should be noted that the second main body 108 is used to electrically connect with the first interconnecting via 102, and the third protrusion 110 is used to electrically connect with the external circuit structure, so that the first interconnecting via 102 can be electrically connected to the external circuit structure through the second main body 108 and the third protrusion 110.

[0059] In this embodiment, the second main body 108 surrounds the edge portion of the metal electrode plate 106, and the first end and the last end of the second main body 108 are spaced apart.

[0060] Specifically, the second main body 108 surrounds the edge portion of the metal electrode plate 106, enabling the second main body 108 to be electrically connected to each of the first sub-interconnection through holes 101.

[0061] It should be noted that the first and last ends of the second main body 108 are spaced apart, providing space for the first main body 120 to pass through the area between the first and last ends of the second main body 108.

[0062] In this embodiment, the first main body 120 passes through the area between the first end and the last end of the second main body 108.

[0063] Specifically, the first main body 120 penetrates the area between the beginning and end of the second main body 108, so that the first main body 120 and the second main body 108 are on the same layer, thereby reducing the overall thickness of the test structure.

[0064] As an example, the material of the second current signal loading terminal 112 includes aluminum.

[0065] It should be noted that the second voltage signal loading terminal 109 is used as a port for measuring voltage.

[0066] In this embodiment, the second voltage signal loading terminal 109 includes a second main body 108 and a fourth protrusion 107 that contacts the second main body 108. The third protrusion 110 is separate from the fourth protrusion 107. The second current signal recording terminal and the second voltage signal loading terminal 109 share the second main body 108, and the second main body 108 is electrically connected to the first interconnecting through hole 102.

[0067] Specifically, the second main body 108 is used to electrically connect with the first interconnect via 102, and the third protrusion 110 is used to electrically connect with the external circuit structure. This allows the first interconnect via 102 to be electrically connected to the external circuit structure through the second main body 108 and the third protrusion 110, thereby enabling a test path to be formed between the interconnect via 136 under test and the metal plate. This facilitates the subsequent acquisition of the current and voltage of the interconnect via 136 under test and the metal plate. At the same time, the third protrusion 110 is separated from the fourth protrusion 107, reducing the probability of the third protrusion 110 and the fourth protrusion 107 being short-circuited. This allows the third protrusion 110 to be used to apply a constant current, and the fourth protrusion 107 to be used to measure voltage.

[0068] As an example, the material of the second voltage signal loading terminal 109 includes aluminum.

[0069] In this embodiment, the first current signal loading terminal 122, the first voltage signal loading terminal 132, the second current signal loading terminal 112, and the second voltage signal loading terminal 109 are located on the same layer.

[0070] Specifically, compared to the first current signal loading terminal 122, the first voltage signal loading terminal 132, the second current signal loading terminal 112, and the second voltage signal loading terminal 109 being in different schemes, the first current signal loading terminal 122, the first voltage signal loading terminal 132, the second current signal loading terminal 112, and the second voltage signal loading terminal 109 being in the same layer can reduce the overall thickness of the test structure.

[0071] In this embodiment, the test structure further includes: a first interconnect layer located on top of the first interconnect via 102, with the bottom of the first interconnect layer electrically connected to the first interconnect via 102, and the top of the first interconnect layer electrically connected to the second current signal loading terminal 112 and the second voltage signal loading terminal 109.

[0072] Specifically, the first interconnect layer provides a high degree of flatness for setting the second current signal loading terminal 112 and the second voltage signal loading terminal 109.

[0073] In this embodiment, the material of the first interconnect layer includes one or both of aluminum and copper.

[0074] Accordingly, the present invention also provides a testing method. Figure 2 This is a schematic flowchart corresponding to one embodiment of the testing method of the present invention. The following is in conjunction with the appendix... Figure 2 The testing methods of this implementation will be described in detail.

[0075] Reference Figure 2 Step S1: Provide the test structure provided in the aforementioned embodiments.

[0076] For a detailed description of the test structure, please refer to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0077] Reference Figure 2 Step S2: Apply a constant current between the first current signal loading terminal 122 and the second current signal loading terminal 112.

[0078] It should be noted that applying a constant current between the first current signal loading terminal 122 and the second current signal loading terminal 112 ensures that the current through the interconnect 136 to the metal plate 106 is known and stable, reducing measurement errors caused by current fluctuations and improving the accuracy of obtaining the resistance value from the interconnect 136 to the metal plate 106.

[0079] It should also be noted that by applying a constant current to the first current signal loading terminal 122 and the second current signal loading terminal 112, a first test path is formed between the interconnect via 136 under test, the metal electrode 106, and the first interconnect via 102. The current flowing through the interconnect via 136 under test to the metal electrode 106 is the applied constant current. In the subsequent process of acquiring the voltage between the first voltage signal loading terminal 132 and the second voltage signal loading terminal 109, a second test path is also formed between the interconnect via 136 under test, the metal electrode 106, and the first interconnect via 102. The input impedance in the test path is much greater than the resistance value from the interconnect 136 to the metal plate 106, making the voltage value of the first interconnect 102 and the metal plate 106 negligible. Thus, the voltage obtained in the second test path is the voltage from the interconnect 136 to the metal plate 106. Since the voltage obtained in the second test path is the voltage from the interconnect 136 to the metal plate 106, the current passing through the interconnect 136 to the metal plate 106 is the applied constant current, thereby improving the accuracy of obtaining the resistance value from the interconnect 136 to the metal plate 106.

[0080] In this embodiment, the step of applying a constant current between the first current signal loading terminal 122 and the second current signal loading terminal 112 includes: electrically connecting the positive terminal of the constant current device to the first current signal loading terminal 122, electrically connecting the negative terminal of the constant current device to the first current signal loading terminal 122, and applying a constant current between the first current signal loading terminal 122 and the second current signal loading terminal 112.

[0081] Reference Figure 2 Step S3: After applying a constant current between the first current signal loading terminal 122 and the second current signal loading terminal 112, the voltage between the first voltage signal loading terminal 132 and the second voltage signal loading terminal 109 is obtained.

[0082] It should be noted that during the process of obtaining the voltage between the first voltage signal loading terminal 132 and the second voltage signal loading terminal 109, the interconnect via 136 under test, the metal plate 106, and the first interconnect via 102 also form a second test path. The input impedance in this second test path is much greater than the resistance value from the interconnect via 136 under test to the metal plate 106, making the voltage value of the first interconnect via 102 and the metal plate 106 itself negligible. Thus, the voltage obtained in the second test path is the voltage from the interconnect via 136 under test to the metal plate 106. Since the voltage obtained in the second test path is the voltage from the interconnect via 136 under test to the metal plate 106, the current passing through the interconnect via 136 under test to the metal plate 106 is the applied constant current, thereby improving the accuracy of obtaining the resistance value from the interconnect via 136 under test to the metal plate 106.

[0083] In this embodiment, the voltage between the first voltage signal loading terminal 132 and the second voltage signal loading terminal 109 is obtained by a voltmeter.

[0084] Reference Figure 2 Step S4: Based on the voltage and constant current, obtain the resistance value from the interconnect 136 to the metal plate 106.

[0085] It should be noted that since the voltage obtained in the second test path is the voltage from the interconnect 136 to the metal plate 106, the current passing through the interconnect 136 to the metal plate 106 is the applied constant current, thereby improving the accuracy of obtaining the resistance value of the interconnect 136 to the metal plate 106.

[0086] In this embodiment, the resistance value R = V / I from the interconnect 136 to the metal plate 106 is obtained, where V refers to the voltage between the first voltage signal loading terminal 132 and the second voltage signal loading terminal 109, and I refers to the constant current applied between the first current signal loading terminal 122 and the second current signal loading terminal 112.

[0087] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: Metal electrode plates; The interconnecting via to be tested is electrically connected to the metal electrode plate; The first interconnecting via is located on the side of the interconnecting via to be tested, and the first interconnecting via is electrically connected to the metal electrode plate; The first current signal loading terminal is electrically connected to the top of the interconnecting via to be tested; The first voltage signal loading terminal is electrically connected to the top of the interconnecting via to be tested, and the first voltage signal loading terminal is separate from the first current signal loading terminal; The second current signal loading terminal is electrically connected to the first interconnecting via. The second voltage signal loading terminal is electrically connected to the first interconnecting via, and the second voltage signal loading terminal is separate from the second current signal loading terminal.

2. The test structure as described in claim 1, characterized in that, The interconnect via to be tested includes one or more sub-interconnect vias to be tested; When the interconnect to be tested consists of multiple sub-interconnects to be tested, the multiple sub-interconnects to be tested are arranged in parallel at intervals along a first direction and a second direction, and the first direction and the second direction are perpendicular to each other.

3. The test structure as described in claim 1, characterized in that, The second current signal loading terminal and the second voltage signal loading terminal are both located at the top of the first interconnect via; The test structure further includes: a first interconnect layer located on top of the first interconnect via, with the bottom of the first interconnect layer electrically connected to the first interconnect via, and the top of the first interconnect layer electrically connected to the second current signal loading terminal and the second voltage signal loading terminal.

4. The test structure as described in claim 1, characterized in that, The first interconnect via includes a plurality of first sub-interconnect vias, and the plurality of first sub-interconnect vias are arranged in parallel at intervals along the same direction and located at the edge portion of the metal electrode plate.

5. The test structure as described in claim 1, characterized in that, The first current signal loading terminal includes a first main body and a first protrusion that contacts the first main body; The first voltage signal loading terminal includes a first main body and a second protrusion that contacts the first main body. The first protrusion and the second protrusion are separate. The first current signal loading terminal and the first voltage signal loading terminal share the first main body, and the first main body is electrically connected to the interconnecting via to be tested.

6. The test structure as described in claim 5, characterized in that, The second current signal loading terminal includes a second main body and a third protrusion that contacts the second main body; The second voltage signal loading terminal includes a second main body and a fourth protrusion that contacts the second main body. The third protrusion is separate from the fourth protrusion. The second current signal recording terminal and the second voltage signal loading terminal share the second main body, and the second main body is electrically connected to the first interconnecting via.

7. The test structure as described in claim 6, characterized in that, The second main body surrounds the edge portion of the metal electrode plate, and the first end and the last end of the second main body are spaced apart.

8. The test structure as described in claim 7, characterized in that, The first main body portion penetrates the area between the beginning and end of the second main body portion.

9. The test structure as described in claim 1, characterized in that, The first current signal loading terminal, the first voltage signal loading terminal, the second current signal loading terminal, and the second voltage signal loading terminal are located on the same layer.

10. The test structure as described in claim 1, characterized in that, The materials of the first current signal loading terminal, the second current signal loading terminal, the first voltage signal loading terminal, and the second voltage signal loading terminal all include aluminum.

11. The test structure as described in claim 1, characterized in that, The metal plates include capacitor metal plates.

12. A testing method, characterized in that, include: Provide a test structure as described in any one of claims 1 to 11; A constant current is applied between the first current signal loading terminal and the second current signal loading terminal; After applying a constant current between the first current signal loading terminal and the second current signal loading terminal, the voltage between the first voltage signal loading terminal and the second voltage signal loading terminal is obtained. Based on the voltage and constant current, the resistance value from the interconnect to the metal plate is obtained.

13. The test method as described in claim 12, characterized in that, Obtain the resistance value R = V / I from the interconnect to the metal plate, where V refers to the voltage between the first voltage signal loading terminal and the second voltage signal loading terminal, and I refers to the constant current applied between the first current signal loading terminal and the second current signal loading terminal.

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