An in-memory computing method of monte carlo bayesian neural network
By controlling the activation of neural network connections within the in-memory computing architecture, the acceleration problem of Monte Carlo Bayesian neural networks is solved, enabling efficient DropConnect operations and improving computational energy efficiency and speed.
Patent Information
- Application Number
- CN202610110262.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-27
- Publication Date
- 2026-06-02
Smart Images
Figure CN122132351A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of memory and in-memory computing technology, specifically relating to an in-memory computing method for Monte Carlo Bayesian neural network inference. Background Technology
[0002] Neural networks have important applications in many fields such as computer graphics, biomedicine, and natural language processing. However, traditional neural network models often require a large amount of high-quality training data, and the weights remain fixed after training, which may lead to overfitting or poor robustness on untrained datasets. In contrast, Bayesian neural networks, by introducing Bayesian theory, introduce a prior distribution into the weights, enabling the model to adapt to different data and exhibiting high robustness and data generalization ability.
[0003] Standard Bayesian neural networks are complex to train and may suffer from efficiency issues when handling large-scale data. Monte Carlo Bayesian neural networks, as a type of Bayesian neural network, introduce uncertainty during inference by using a "dropconnect" operation. The final result is obtained by averaging multiple predictions. This method has advantages such as not requiring changes to the model training process, simple implementation, and controllable computational cost.
[0004] In-memory computing, as a novel computing paradigm, can accelerate neural network inference. Currently, most in-memory computing architectures primarily use a single storage medium, making it difficult to implement DropConnect operations and accelerate Monte Carlo Bayesian neural networks. Summary of the Invention
[0005] To address the aforementioned issues and further improve the performance of Bayesian neural network hardware inference and provide stronger computing power, this application proposes an in-memory computation method for Monte Carlo Bayesian neural networks.
[0006] The technical solution of this application is as follows:
[0007] An in-memory computation method for Monte Carlo Bayesian neural networks, the specific steps of which include:
[0008] 1) Construct an in-memory computing architecture, including a memory array, a write selection module, a write driver module, an input driver module, and a read module. The memory array has M rows and N columns, including M×N memory cells. Each memory cell includes a write transistor, a read transistor, and non-volatile memory. The source of the write transistor and the gate of the read transistor are connected to form a volatile memory node. The drain of the read transistor is connected to the first terminal of the non-volatile memory. In the memory array, the gates of all write transistors in the same row are connected to the same write word line, and the second terminals of all non-volatile memory in the same row are connected to the same read bit line. The drains of all write transistors in the same column are connected to the same write bit line, and the sources of all read transistors in the same column are connected to the same read word line. All write word lines of the memory array are connected to the write selection module, all write bit lines of the memory array are connected to the write driver module, all read bit lines of the memory array are connected to the input driver module, and all read word lines of the memory array are connected to the read module.
[0009] 2) The elements of the weight parameter matrix of the Bayesian neural network are mapped and stored in the non-volatile memory of each storage unit of the storage array, wherein the non-volatile memory represents the corresponding weight parameters by the conductance state.
[0010] 3) Randomly generate a mask matrix. The write selection module and the write drive module use the write word line and the write bit line, respectively, to write each element of the mask matrix as a voltage signal to the volatile storage node of the corresponding storage unit. The mask element stored in each volatile storage node is configured to control whether the connection in the neural network corresponding to the weight stored in the non-volatile memory in the same unit is activated, thereby realizing the random connection deactivation (DropConnect) operation.
[0011] 4) The input vector is applied in parallel to multiple read bit lines of the memory array through the input driving module; the output current of the multiple read word lines of the memory array is obtained, and the readout module obtains the output current vector;
[0012] 5) Quantize the output current vector into a digital signal to obtain the single inference calculation result of the neural network;
[0013] 6) Repeat steps 3) to 5) multiple times for the same input vector to obtain a set of calculation results. Average the calculation results to obtain the final Monte Carlo Bayesian neural network inference output.
[0014] Furthermore, the results of a single inference calculation of the neural network are stored in an output buffer module.
[0015] Furthermore, the write transistor is one of an oxide semiconductor transistor, a two-dimensional material transistor, a carbon nanotube, or a silicon-based transistor.
[0016] Furthermore, the read transistor is one of an oxide semiconductor transistor, a two-dimensional material transistor, a carbon nanotube, or a silicon-based transistor.
[0017] Furthermore, the non-volatile memory is one of resistive random access memory (RRAM), phase change memory (PCM), ferroelectric memory (FeRAM), or magnetic tunnel junction random access memory (MRAM).
[0018] The beneficial effects of this invention are as follows:
[0019] This invention controls whether the neural network connection corresponding to the non-volatile memory is activated by storing mask information in volatile SN nodes, and efficiently implements the DropConnect operation in hardware. When repeatedly erasing and writing the mask, volatile memory has advantages such as high durability, high erase and write speed and low power consumption. During inference, parallel simulation calculation is used. Combining the above advantages, the computing energy efficiency and speed are greatly improved. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the in-memory computing architecture in a specific embodiment of the present invention;
[0021] Figure 2 This is a circuit diagram of the storage array in a specific embodiment of the present invention;
[0022] Figure 3 This is a circuit diagram of the storage unit in a specific embodiment of the present invention;
[0023] Figure 4 This is a flowchart of the in-memory calculation method in a specific embodiment of the present invention. Detailed Implementation
[0024] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0025] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.
[0026] This invention first constructs a Monte Carlo Bayesian neural network in-memory computation architecture, such as... Figure 1 As shown, it includes a storage array, a write selection module, a write driver module, an input driver module, a read module, and an output buffer module.
[0027] Among them, the storage array is as follows Figure 2 As shown, there are M rows and N columns, comprising M*N storage units; as Figure 3 As shown, the memory cell includes a write transistor (WT), a read transistor (RT), and the non-volatile memory (R); the source of the write transistor is connected to the gate of the read transistor, together forming the volatile memory node (SN); the drain of the read transistor is connected to the first terminal of the non-volatile memory, and the second terminal of the non-volatile memory is connected to the read bit line;
[0028] In some embodiments, the write transistor WT can be one of an oxide semiconductor transistor, a two-dimensional material transistor, a carbon nanotube, or a silicon-based transistor.
[0029] In some embodiments, the read transistor RT can be one of an oxide semiconductor transistor, a two-dimensional material transistor, a carbon nanotube, or a silicon-based transistor.
[0030] In some embodiments, the non-volatile memory R can be one of resistive random access memory (RRAM), phase change memory (PCM), ferroelectric memory (FeRAM), or magnetic tunnel junction random access memory (MRAM).
[0031] In the memory array, for multiple memory cells located in the same row, the gate of the write transistor is connected to the same write word line (WWL), and the second terminal of the non-volatile memory is connected to the same read bit line (RBL); for multiple memory cells located in the same column, the drain of the write transistor is connected to the same write bit line (WBL), and the source of the read transistor is connected to the same read word line (RWL).
[0032] All write word lines of the array are connected to the write selection module, write bit lines are connected to the write driver module, read bit lines are connected to the input driver module, and read word lines are connected to the read module.
[0033] like Figure 4As shown, the Monte Carlo Bayesian neural network in-memory computation method of this embodiment is performed on the in-memory computation architecture constructed above, and includes the following steps:
[0034] Step 1: Map and store each element of the weight parameter matrix W of the Bayesian neural network in the non-volatile memory of each storage unit of the storage array. The non-volatile memory represents the corresponding weight parameters with electrical conductance state.
[0035] In this embodiment, the weight parameter matrix W of the Bayesian neural network is an M-row N-column matrix, where M is the number of rows in the storage array and N is the number of columns in the storage array.
[0036] In this example, the weight parameter matrix of the Bayesian neural network is: The parameter elements W of the weight parameter matrix W ij The non-volatile memory R corresponding to the memory cell in the i-th row and j-th column of the memory array is written to. ij middle.
[0037] The non-volatile memory R has multiple levels of resistors, each corresponding to a different conductance state, which enables the non-volatile memory R to store multiple bits.
[0038] Step 2: Randomly generate a mask matrix. Using the write selection module and the write driver module, respectively, through the write word line WWL and the write bit line WBL, the mask matrix M is generated. t Each element of the mask matrix is written as a voltage signal into the volatile storage node SN of the corresponding storage unit. In this embodiment, each element of the mask matrix is written into the volatile storage node SN of the corresponding storage unit in the storage array; the mask element stored in each volatile storage node is configured to control whether the connection in the neural network corresponding to the weight stored in the non-volatile memory in the same unit is activated, thereby realizing the DropConnect operation;
[0039] In this embodiment, the mask matrix M t It is a matrix of the same size as the weight parameter matrix W, and the mask matrix is also an M-row N-column matrix.
[0040] In this embodiment, the mask matrix The elements M of the mask matrix Mt tij The volatile memory SN corresponding to the memory cell written to the i-th row and j-th column of the memory array ij In the middle. Where t is the t-th calculation.
[0041] Step 3: The input vector x is applied in parallel to multiple read lines of the memory array through the input driving module; the output current of the multiple read word lines of the memory array is obtained, and the readout module obtains the output current vector I.yt ;
[0042] In this embodiment, the input vector is applied in parallel to multiple read lines RBL of the array, including: after the input vector is converted into a corresponding voltage signal, the voltage signal is applied to the corresponding read line RBL.
[0043] In this embodiment, the length of the input vector x is M, meaning that the input vector x includes M components. Each component of the input vector x is quantized and converted into a corresponding analog voltage signal. Subsequently, the input vector x is applied in parallel as a voltage signal to the M read lines RBL1-RBL1 of the memory array. M superior.
[0044] In this embodiment, the input vector x = (x1, x2, ..., x...) M After quantization, the input voltages are V1, V2, ... V. M Input voltages V1, V2, ... V M These correspond to the M read lines RBL1, RBL2, ... RBL applied to the memory array, respectively. M .
[0045] In this embodiment, the output current I of each column is read by the readout module connected to each readout line RWL, thus obtaining N readout lines RWL1, RWL2, ..., RWL1. N The corresponding N output currents I yt1 I yt2 , ..., I ytN .
[0046] Step 4: Quantize the output current vector into a digital signal to obtain the single-step inference calculation result y of the neural network. t The data is stored in the output buffer module.
[0047] Step 5: Repeat steps 2 through 4 T times for the same input vector x to obtain a set of calculation results Y = (y1, y2, ..., y T The result Y is averaged to obtain the final Monte Carlo Bayesian neural network inference output. The variance of the results represents the uncertainty of this inference.
[0048] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. An in-memory computation method for a Monte Carlo Bayesian neural network, the specific steps of which include: 1) Construct an in-memory computing architecture, including a memory array, a write selection module, a write driver module, an input driver module, and a read module. The memory array has M rows and N columns, including M×N memory cells. Each memory cell includes a write transistor, a read transistor, and non-volatile memory. The source of the write transistor and the gate of the read transistor are connected to form a volatile memory node. The drain of the read transistor is connected to the first terminal of the non-volatile memory. In the memory array, the gates of all write transistors in the same row are connected to the same write word line, and the second terminals of all non-volatile memory cells in the same row are connected to the same read bit line. The drains of all write transistors in the same column are connected to the same write bit line, the sources of all read transistors in the same column are connected to the same read word line, all write word lines of the memory array are connected to the write selection module, all write bit lines of the memory array are connected to the write drive module, all read bit lines of the memory array are connected to the input drive module, and all read word lines of the memory array are connected to the read module. 2) The elements of the weight parameter matrix of the Bayesian neural network are mapped and stored in the non-volatile memory of each storage unit of the storage array, wherein the non-volatile memory represents the corresponding weight parameters by the conductance state. 3) Randomly generate a mask matrix. The write selection module and the write drive module write each element of the mask matrix as a voltage signal to the volatile storage node of the corresponding storage unit through the write word line and the write bit line, respectively. The mask element stored in each volatile storage node is configured to control whether the connection in the neural network corresponding to the weight stored in the non-volatile memory in the same unit is activated. 4) The input vector is applied in parallel to multiple read lines of the memory array through the input driver module; The readout module obtains the output current vector by acquiring the output current of multiple read word lines of the storage array. 5) Quantize the output current vector into a digital signal to obtain the result of a single inference calculation of the neural network; 6) Repeat steps 3) to 5) multiple times for the same input vector to obtain a set of calculation results. Average the calculation results to obtain the final Monte Carlo Bayesian neural network inference output.
2. The in-memory computation method of the Monte Carlo Bayesian neural network as described in claim 1, characterized in that, The results of a single inference calculation by the neural network are stored in an output buffer module.
3. The in-memory computation method of the Monte Carlo Bayesian neural network as described in claim 1, characterized in that, The write transistor is selected from one of oxide semiconductor transistors, two-dimensional material transistors, carbon nanotubes, and silicon-based transistors.
4. The in-memory computation method of the Monte Carlo Bayesian neural network as described in claim 1, characterized in that, The read transistor is selected from one of oxide semiconductor transistors, two-dimensional material transistors, carbon nanotubes, and silicon-based transistors.
5. The in-memory computation method of the Monte Carlo Bayesian neural network as described in claim 1, characterized in that, The non-volatile memory is a resistive switching memory, a phase-change memory, a ferroelectric memory, or a magnetic tunnel junction memory.