A time domain storage-computation integrated unit and array structure based on RRAM
By embedding RRAM cells into an inverter delay chain, a time-domain in-memory computing unit and array structure are realized, solving the high power consumption problem caused by the static current path of the in-memory computing array, improving system energy efficiency, and making it suitable for artificial intelligence and edge computing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING UNIV OF SCI & TECH
- Filing Date
- 2026-01-16
- Publication Date
- 2026-06-05
AI Technical Summary
Existing in-memory computing arrays based on current/voltage domains have static current paths, resulting in high power consumption during readouts, making it difficult to meet the energy efficiency requirements of resource-constrained scenarios such as edge computing.
By embedding RRAM cells into an inverter delay chain and changing the delay through the high and low impedance states of the RRAM device, a time-domain in-memory computing unit and array structure can be realized. The delayed signal is used to perform multiplication and accumulation calculations in the time domain, avoiding continuous current paths.
It reduces the readout power consumption of the in-memory computing array, improves the computing energy efficiency of the system, and is suitable for artificial intelligence and edge computing scenarios.
Smart Images
Figure CN122152760A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a time-domain in-memory computing unit and array structure based on RRAM. Background Technology
[0002] With the rapid development of large-scale models and edge computing, artificial intelligence inference tasks are placing higher demands on computing power and energy efficiency. The separation of computation and storage in the traditional von Neumann architecture leads to frequent data movement; the "memory wall" problem caused by data movement is particularly prominent in high-throughput, low-power scenarios. Computing in Memory (CIM) technology can effectively alleviate this problem by performing computation directly within memory. Resistive Random Access Memory (RRAM), due to its non-volatility, high-density integration, and analog conductivity characteristics, has become one of the core components of CIM. However, existing CIM arrays based on current / voltage domains have static current paths, resulting in high array power consumption during readouts. For resource-constrained scenarios such as edge inference, a new architecture for cell and array design is urgently needed to further reduce the power consumption of CIM cells and readout circuits, thereby improving the overall energy efficiency of the system.
[0003] like Figure 1 The diagram shows a typical existing in-memory computing unit structure, consisting of a transistor and an RRAM device connected in series. The word line (WL) is connected to the gate of the transistor, while the bit line (BL) and source line (SL) are connected to the two ends of the transistor and the RRAM device, respectively. This in-memory computing unit structure achieves writing to the RRAM device by applying a voltage difference across BL and SL, and controlling whether the cell is selected via WL; similarly, reading from the cell is achieved by applying a small voltage between BL and SL. Further, a cross array composed of BL, WL, and SL can be constructed. During computation, the result is represented by the current output by each cell. Clearly, the aforementioned cells and array exhibit a considerable static current during computation, resulting in high power consumption for the in-memory computing unit and array. Summary of the Invention
[0004] To address the aforementioned issues, this invention proposes a time-domain in-memory computing unit and array structure based on RRAM. By embedding RRAM into an inverter-based delay chain, the problem of excessive static power consumption during readout of the in-memory computing unit and array structure is solved, thereby further improving the computing efficiency of the in-memory computing circuit.
[0005] The first aspect of the present invention provides a time-domain in-memory computing unit structure based on RRAM, including a front inverter, wherein the front inverter includes a P-type MOS transistor P1 and an N-type MOS transistor N1, wherein the P-type MOS transistor P1 and the N-type MOS transistor N1 are connected to the input port DI and the top electrode of the RRAM device. P-type MOSFET P1 is connected to power supply VDD, and N-type MOSFET N1 is connected to ground GND; The RRAM device includes two ports: a top electrode and a bottom electrode, wherein the top electrode is connected to the front inverter, and the bottom electrode is connected to the rear inverter; A transmission gate switch includes P-type MOSFET P2 and N-type MOSFET N2, wherein N-type MOSFET N2 is connected to word line port WL, and P-type MOSFET P2 is connected to port WLB. Both P-type MOSFET P2 and N-type MOSFET N2 are connected to the bottom electrode of the RRAM device and port SL, used to control whether different setting voltages are applied to the RRAM device; The rear inverter includes P-type MOSFET P3 and N-type MOSFET N3, wherein P-type MOSFET P3 and N-type MOSFET N3 are connected to output port DO and the bottom electrode of the RRAM device. P-type MOSFET P3 is connected to power supply VDD, and N-type MOSFET N3 is connected to ground GND. The data switch transistor is an N-type MOSFET N4, which is connected to the data port DATA, the top electrode of the RRAM device, and the bottom electrode of the RRAM device. The N-type MOSFET N4 controls whether to short-circuit the RRAM device according to the high or low level of the port DATA, thereby realizing multiplication and accumulation calculation.
[0006] Optionally, the P-type MOS transistor P1 includes a P1 gate, a P1 drain, and a P1 source, wherein the P1 gate is connected to the input port DI, the P1 drain is connected to the top electrode of the RRAM device, and the P1 source is connected to the power supply VDD.
[0007] Optionally, the N-type MOS transistor N1 includes an N1 gate, an N1 drain, and an N1 source, wherein the N1 gate is connected to the input port DI, the N1 drain is connected to the top electrode of the RRAM device, and the N1 source is connected to the ground terminal GND.
[0008] Optionally, the P-type MOS transistor P2 includes a P2 gate, a P2 drain, and a P2 source, wherein the P2 gate is connected to the port WLB, the P2 source or P2 drain is connected to the bottom electrode of the RRAM device, and the P2 drain or P2 source is connected to the port SL.
[0009] Optionally, the N-type MOS transistor N2 includes an N2 gate, an N2 drain, and an N2 source, wherein the N2 gate is connected to the port WL, the N2 source or N2 drain is connected to the bottom electrode of the RRAM device, and the N2 drain or N2 source is connected to the port SL.
[0010] Optionally, the P-type MOS transistor P3 includes a P3 gate, a P3 drain, and a P3 source, wherein the P3 gate is connected to the bottom electrode of the RRAM device, the P3 drain is connected to the output port DO, and the P3 source is connected to the power supply VDD.
[0011] Optionally, the N-type MOS transistor N3 includes an N3 gate, an N3 drain, and an N3 source, wherein the N3 gate is connected to the bottom electrode of the RRAM device, the N3 drain is connected to the output port DO, and the N3 source is connected to the ground terminal GND.
[0012] Optionally, the N-type MOS transistor N4 includes an N4 gate, an N4 drain, and an N4 source, wherein the N4 gate is connected to the DATA port, the N4 drain is connected to the bottom electrode of the RRAM device, and the N4 source is connected to the top electrode of the RRAM device.
[0013] A second aspect of this invention provides a time-domain in-memory computing array structure based on RRAM, comprising: multiple in-memory computing unit structures arranged in rows and columns to form an in-memory computing array, wherein the ports WL of each in-memory computing unit structure located in the same row are connected to the same array WL port, and the ports WLB of each in-memory computing unit structure located in the same row are connected to the same array WLB port. Except for the first and last in-memory computing unit structures, the input port DI of each in-memory computing unit structure is connected to the output port DO of the previous unit, and the output port DO of each in-memory computing unit structure is connected to the input port DI of the next unit. The input port of the first in-memory computing unit structure in each row is connected to the input port DI of that row, and the output port DO is connected to the input port DI of the second unit in that row; the input port DI of the last in-memory computing unit structure in each row is connected to the output port DO of the previous unit, and the output port DO is connected to the output port DO of that row. Further, the ports SL of each in-memory computing unit structure located in the same column are connected to the same array port SL; the ports DATA of each in-memory computing unit structure located in the same column are connected to the same array port DATA.
[0014] Furthermore, in the rewrite mode, the i-th row is first selected through port WL, while the ports WL of other rows are all low and not selected; if a low-impedance state needs to be written, the port SL of the j-th column is set to low, and the port SL corresponding to the (j-1)-th column cell is input to high. After passing through the inverter 203 of the (j-1)-th column, the input port DI of the j-th column is low. Cell writing is achieved by multiplexing the port SL in the delay chain. In readout mode, an input pulse is generated by an external circuit at the beginning of each working cycle. This input pulse is input to the input port DI of each row of the array. The total delay of the row is finally generated by multiplying and accumulating the RRAM device resistance state and the port DATA input of each row. The output total delay signal is further converted into a digital signal by a time domain readout circuit outside the cell.
[0015] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0016] This invention proposes a time-domain in-memory computing unit and array structure based on RRAM. RRAM cells are embedded in an inverter delay chain. The high and low impedance states of the RRAM devices alter the delay of the RRAM-based time-domain in-memory computing unit structure. The delayed signal is further serially accumulated within a row of the RRAM-based time-domain in-memory computing array structure. By measuring the total delay time from the beginning to the end of the row, the multiplication and accumulation result determined by the RRAM impedance states of each cell and the input data can be obtained. This unit and array structure have no continuous current path, enabling in-memory computing functionality with no quiescent current in the time domain. Its low readout power consumption has practical application potential, solving the problem of excessive readout power consumption in current in-memory computing architectures and further improving the overall energy efficiency of in-memory computing systems. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 A schematic diagram of an existing in-memory computing unit structure;
[0019] Figure 2 This is a schematic diagram of the time-domain in-memory computing unit structure based on RRAM according to an embodiment of the present invention;
[0020] Figure 3 This is a schematic diagram of a time-domain in-memory array structure based on RRAM according to an embodiment of the present invention.
[0021] Explanation of reference numerals in the attached figures: 20- Time-domain in-memory computing unit structure based on RRAM, 201- Front inverter, 202- Transmission gate, 203- Back inverter, 204- Data switch transistor, and 30- Time-domain in-memory computing array structure based on RRAM. Detailed Implementation
[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.
[0023] To facilitate the description of the technical solution of this invention, the following naming rules are adopted for each transistor in the circuit: the P-type MOS transistor in the front inverter is designated as P1, and the N-type MOS transistor as N1; the P-type MOS transistor in the transmission gate is designated as P2, and the N-type MOS transistor as N2; the P-type MOS transistor in the rear inverter is designated as P3, and the N-type MOS transistor as N3; the data switch transistor is designated as N4. The above naming is only used for the description of this application and does not constitute a limitation on the scope of protection of this invention.
[0024] like Figure 2 As shown, a first aspect of the present invention discloses a time-domain in-memory computing unit structure 20 based on RRAM, the time-domain in-memory computing unit structure based on RRAM includes: a front inverter 201, a transmission gate 202, an RRAM device, a rear inverter 203, and a data switch 204.
[0025] The front inverter 201 includes a P-type MOSFET P1 and an N-type MOSFET N1, which are connected to the input port DI and the top electrode of the RRAM device. The P-type MOSFET P1 is connected to the power supply VDD, and the N-type MOSFET N1 is connected to the ground terminal GND. The RRAM device has two ports, a top electrode and a bottom electrode, with the top electrode connected to the front inverter and the bottom electrode connected to the rear inverter. The transmission gate switch 202 includes a P-type MOSFET P2 and an N-type MOSFET N2, with the N-type MOSFET N2 connected to the word line port WL and the P-type MOSFET P2 connected to port WLB. Both the P-type MOSFET P2 and the N-type MOSFET N2 are connected to the bottom electrode of the RRAM device and port SL, used to control whether different setting voltages are applied to the RRAM device. The rear inverter 203 includes a P-type MOSFET P3 and an N-type MOSFET N3, which are connected to the output port DO and the bottom electrode of the RRAM device. P-type MOSFET P3 is connected to power supply VDD, and N-type MOSFET N3 is connected to ground GND; data switch MOSFET 204 is N-type MOSFET N4, which is connected to data port DATA, the top electrode of RRAM device and the bottom electrode of RRAM device. N-type MOSFET N4 controls whether to short-circuit RRAM device according to the high or low level of port DATA, thereby realizing multiplication and accumulation calculation.
[0026] Specifically, the P-type MOSFET P1 includes a P1 gate, a P1 drain, and a P1 source. The P1 gate is connected to the input port DI, the P1 drain is connected to the top electrode of the RRAM device, and the P1 source is connected to the power supply VDD. The N-type MOSFET N1 includes an N1 gate, an N1 drain, and an N1 source. The N1 gate is connected to the input port DI, the N1 drain is connected to the top electrode of the RRAM device, and the N1 source is connected to the ground terminal GND. The P-type MOSFET P2 includes a P2 gate, a P2 drain, and a P2 source. The P2 gate is connected to the port WLB, the P2 source or P2 drain is connected to the bottom electrode of the RRAM device, and the P2 drain or P2 source is connected to the port SL. N-type MOSFET N2 includes an N2 gate, an N2 drain, and an N2 source. The N2 gate is connected to port WL, and either the N2 source or drain is connected to the bottom electrode of the RRAM device. The N2 drain or source is also connected to port SL. P-type MOSFET P3 includes a P3 gate, a P3 drain, and a P3 source. The P3 gate is connected to the bottom electrode of the RRAM device, the P3 drain is connected to the output port DO, and the P3 source is connected to the power supply VDD. N-type MOSFET N3 includes an N3 gate, an N3 drain, and an N3 source. The N3 gate is connected to the bottom electrode of the RRAM device, the N3 drain is connected to the output port DO, and the N3 source is connected to ground GND. The N-type MOS transistor N4 includes an N4 gate, an N4 drain, and an N4 source. The N4 gate is connected to the DATA port, the N4 drain is connected to the bottom electrode of the RRAM device, and the N4 source is connected to the top electrode of the RRAM device.
[0027] In write mode, a transmission gate 202 composed of two switching transistors P2 and N2, and a front inverter 201 composed of P1 and N1, are used to jointly realize the low-resistance and high-resistance states of the RRAM device for writing. The power supply voltage is V during write mode. set First, connect port WL to a high level and WLB to a low level, turning on transmission gate 202 and selecting the desired cell. Next, apply a low level to DI and ground SL. At this point, the voltage at the top electrode of the RRAM is V. set At this point, the voltage difference across the RRAM device will exceed the positive threshold voltage, and it will be written into a low-impedance state; conversely, port DI will be high, and a voltage V will be applied to port SL. set At this time, the voltage of the top electrode of the RRAM is low, and the voltage difference across the RRAM cell will exceed the reverse threshold voltage, and it will be written as a high-impedance state.
[0028] In readout mode, the delay of the DI input pulse edge is generated by the aforementioned front inverter 201 and rear inverter 203, and the input data is simultaneously connected through the data switch transistor 204. The power supply voltage is set to a lower read voltage V. read At this time, port WL is low, and transmission gate 202 is closed to isolate the influence of port SL on the read circuit. Therefore, there is no continuous quiescent current on the RRAM device. By applying a signal edge to input port DI, the level in the delay cell is flipped. The delay time of the cell is determined by the product of the input data DATA and the RRAM device's impedance state set in the write mode. When the input DATA is 1, the RRAM device is short-circuited, so the output delay is approximately zero; conversely, when the input is 0, if the written RRAM is in a high impedance state, the output delay is t. delay If the RRAM being written to is in a low-impedance state, the output delay can also be approximated as zero. The output delay signal is further converted into a digital signal by a time-domain readout circuit outside the cell.
[0029] like Figure 3 As shown in the second aspect of the present invention, a time-domain in-memory computing array structure 30 based on RRAM is disclosed, comprising: multiple in-memory computing unit structures 20. The structure described in this invention has no continuous current path, enabling in-memory computing operations without static current in the time domain, reducing the power consumption of the in-memory computing array, improving computing energy efficiency, and is suitable for hardware acceleration in artificial intelligence and edge computing scenarios.
[0030] Multiple in-memory computing unit structures 20 are arranged in rows and columns to form an in-memory computing array. The array consists of m rows and n columns, with an actual size of m rows and n+2 columns after considering delay chain redundancy. Each in-memory computing unit structure in the same row has its port WL connected to the same array WL port, and its port WLB connected to the same array WLB port. Except for the first and last in-memory computing unit structures, each in-memory computing unit structure's input port DI is connected to the output port DO of the previous unit, and each in-memory computing unit structure's output port DO is connected to the input port DI of the next unit. The first in-memory computing unit structure in each row has its input port connected to the input port DI of that row, and its output port DO is connected to the input port DI of the second unit in that row. The last in-memory computing unit structure in each row has its input port DI connected to the output port DO of the previous unit, and its output port DO is connected to the output port DO of that row. Furthermore, each in-memory computing unit structure in the same column has its port SL connected to the same array port SL; and each in-memory computing unit structure in the same column has its port DATA connected to the same array port DATA.
[0031] The high-resistance and low-resistance states of the RRAM device represent the stored weight values, respectively. During the write phase, the resistance state configuration is achieved through the cooperation of the transmission gate switch and the inverter. During the read phase, the RRAM is embedded in the inverter delay chain, and the RRAM is selectively short-circuited according to the input value through the data switch transistor, so that the cell delay time is jointly determined by the product of the RRAM resistance state and the input data. The time-domain in-memory array structure based on RRAM is composed of multiple of the above-mentioned cell structures connected in the row and column directions. Multiple of the above-mentioned cell structures are cascaded in the row direction to achieve delay accumulation. The multiplication and accumulation result is obtained by measuring the total propagation time of the signal from the beginning to the end of the row.
[0032] Specifically, to write to a cell in the i-th row and j-th column of the array, the i-th row is first selected via port WL, while ports WL for other rows are low and not selected. To write to a low-impedance state, port SL in the j-th column is set low. To make the input port DI of this cell low, the port SL corresponding to the (j-1)-th column cell is set high. After passing through the inverter 203 in the (j-1)-th column, the input port DI of the j-th column becomes low, thus achieving cell writing using port SL multiplexing within the delay chain. Further analysis shows that to prevent the voltage settings from interfering with the impedance state of other cells in the i-th row, a protective voltage needs to be applied to the other ports SL in the same row. Taking the low-impedance state as an example, ports SL for cells before column (j-1) need to be set high, while ports SL for cells after column j need to be set low. This ensures that the voltage difference across all cells except the selected cell is zero.
[0033] In readout mode, an input pulse is generated by an external circuit at the beginning of each working cycle. This input pulse is input to the input port DI of each row of the array. The total delay of that row is finally calculated by multiplying and accumulating the RRAM device resistance state and the port DATA input of each row. If the equivalent resistance of the RRAM resistance state and the data switch transistor in parallel in each cell is R... p The total delay of the output of this line can be expressed by the following formula.
[0034]
[0035] Where n is the number of cells in a single row of the array, α is a correction factor related to factors such as process deviation and cell layout, and C L The load capacitor is used for charging and discharging within the cell. The output line delay signal is further converted into a digital signal by a time-domain readout circuit outside the cell.
[0036] It should be noted that the foregoing explanation of the embodiment of the RRAM-based time-domain in-memory computing unit structure also applies to the RRAM-based time-domain in-memory computing array structure of this embodiment, and will not be repeated here.
[0037] The present invention proposes a time-domain in-memory computing unit and array structure based on RRAM. RRAM cells are embedded in an inverter delay chain. The delay of the time-domain in-memory computing unit structure is altered by the high and low impedance states of the RRAM devices. The delayed signal is further serially accumulated within a row of the RRAM-based time-domain in-memory computing array structure. By measuring the total delay time from the beginning to the end of the row, the multiplication and accumulation result determined by the RRAM impedance states of each cell and the input data can be obtained. This unit and array structure have no continuous current path, enabling in-memory computing functionality without quiescent current in the time domain. Its low readout power consumption has practical application potential, solving the problem of excessive readout power consumption in current in-memory computing architectures and further improving the overall energy efficiency of in-memory computing systems.
[0038] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.
Claims
1. A time-domain in-memory computing unit structure based on RRAM, characterized in that, include A front inverter, comprising a P-type MOSFET P1 and an N-type MOSFET N1, wherein the P-type MOSFET P1 and the N-type MOSFET N1 are connected to the top electrode of the input port DI and the RRAM device, the P-type MOSFET P1 is connected to the power supply VDD, and the N-type MOSFET N1 is connected to the ground terminal GND. The RRAM device includes two ports: a top electrode and a bottom electrode, wherein the top electrode is connected to the front inverter and the bottom electrode is connected to the rear inverter. A transmission gate switch, comprising a P-type MOS transistor P2 and an N-type MOS transistor N2, wherein the N-type MOS transistor N2 is connected to the word line port WL, the P-type MOS transistor P2 is connected to the port WLB, and both the P-type MOS transistor P2 and the N-type MOS transistor N2 are connected to the bottom electrode of the RRAM device and the port SL, for controlling whether different setting voltages are applied to the RRAM device; The rear inverter includes a P-type MOSFET P3 and an N-type MOSFET N3, wherein the P-type MOSFET P3 and the N-type MOSFET N3 are connected to the output port DO and the bottom electrode of the RRAM device, the P-type MOSFET P3 is connected to the power supply VDD, and the N-type MOSFET N3 is connected to the ground terminal GND. The data switch transistor is an N-type MOS transistor N4, which is connected to the data port DATA, the top electrode of the RRAM device, and the bottom electrode of the RRAM device. The N-type MOS transistor N4 controls whether to short-circuit the RRAM device according to the high or low level of the port DATA to realize multiplication and accumulation calculation.
2. The time-domain in-memory computing unit structure based on RRAM according to claim 1, characterized in that, The P-type MOS transistor P1 includes a P1 gate, a P1 drain, and a P1 source. The P1 gate is connected to the input port DI, the P1 drain is connected to the top electrode of the RRAM device, and the P1 source is connected to the power supply VDD.
3. The time-domain in-memory computing unit structure based on RRAM according to claim 1, characterized in that, The N-type MOS transistor N1 includes an N1 gate, an N1 drain, and an N1 source. The N1 gate is connected to the input port DI, the N1 drain is connected to the top electrode of the RRAM device, and the N1 source is connected to the ground terminal GND.
4. The time-domain in-memory computing unit structure based on RRAM according to claim 1, characterized in that, The P-type MOS transistor P2 includes a P2 gate, a P2 drain, and a P2 source. The P2 gate is connected to the port WLB, the P2 source or P2 drain is connected to the bottom electrode of the RRAM device, and the P2 drain or P2 source is connected to the port SL.
5. The time-domain in-memory computing unit structure based on RRAM according to claim 1, characterized in that, The N-type MOS transistor N2 includes an N2 gate, an N2 drain, and an N2 source. The N2 gate is connected to the port WL, the N2 source or the N2 drain is connected to the bottom electrode of the RRAM device, and the N2 drain or the N2 source is connected to the port SL.
6. The time-domain in-memory computing unit structure based on RRAM according to claim 1, characterized in that, The P-type MOS transistor P3 includes a P3 gate, a P3 drain, and a P3 source. The P3 gate is connected to the bottom electrode of the RRAM device, the P3 drain is connected to the output port DO, and the P3 source is connected to the power supply VDD.
7. The time-domain in-memory computing unit structure based on RRAM according to claim 1, characterized in that, The N-type MOS transistor N3 includes an N3 gate, an N3 drain, and an N3 source. The N3 gate is connected to the bottom electrode of the RRAM device, the N3 drain is connected to the output port DO, and the N3 source is connected to the ground terminal GND.
8. The time-domain in-memory computing unit structure based on RRAM according to claim 1, characterized in that, The N-type MOS transistor N4 includes an N4 gate, an N4 drain, and an N4 source. The N4 gate is connected to the DATA port, the N4 drain is connected to the bottom electrode of the RRAM device, and the N4 source is connected to the top electrode of the RRAM device.
9. A time-domain in-memory computing array structure based on RRAM, characterized in that, The system employs multiple RRAM-based time-domain in-memory computing unit (IMU) structures as described in any one of claims 1-8. These IMU structures are arranged in rows and columns to form an IMU array. In each IMU structure located in the same row, port WL is connected to the same array WL port, and port WLB is connected to the same array WLB port. Except for the first and last IMU structures, the input port DI of each IMU structure is connected to the output port DO of the previous unit, and the output port DO of each IMU structure is connected to the input port DI of the next unit. The input port of the first IMU structure in each row is connected to the input port DI of that row, and the output port DO is connected to the input port DI of the second unit in that row. The input port DI of the last IMU structure in each row is connected to the output port DO of the previous unit, and the output port DO is connected to the output port DO of that row. Port SL of each IMU structure located in the same column is connected to the same array port SL. Port DATA of each IMU structure located in the same column is connected to the same array port DATA.
10. A time-domain in-memory computing array structure based on RRAM according to claim 9, characterized in that, In rewrite mode, the i-th row is first selected through port WL, while the ports WL of other rows are low and not selected. If a low-impedance state needs to be written, the port SL of the j-th column is set to low, and the port SL corresponding to the (j-1)-th column cell is input to high. After passing through the inverter 203 of the (j-1)-th column, the input port DI of the j-th column is low. Cell writing is achieved by multiplexing the port SL in the delay chain. In readout mode, an input pulse is generated by an external circuit at the beginning of each working cycle. This input pulse is input to the input port DI of each row of the array. The total delay of the row is finally generated by multiplying and accumulating the RRAM device resistance state and the port DATA input of each row. The output total delay signal is further converted into a digital signal by a time domain readout circuit outside the cell.