A 100G line side signal FEC demodulation decoding method based on FPGA implementation

Abstract

The application relates to a 100G line side signal FEC demodulation decoding method based on FPGA, aiming to improve the signal transmission reliability and transmission distance of a high-speed optical fiber communication system, and simultaneously reduce the system cost. The method comprises key steps of signal preprocessing, synchronization, extraction, windowing, FFT operation, anti-aliasing filtering, signal demodulation, FEC decoding, signal recovery and error correction processing and the like. Through accurate signal processing technology and efficient FEC algorithm, the application can significantly improve the anti-interference ability and transmission quality of signals while maintaining high data throughput. In addition, the method also optimizes the hardware resource configuration and algorithm implementation of the FPGA, thereby reducing the power consumption and cost of the system. The application is suitable for 100G and higher rate optical fiber communication systems, and has important practical application value for improving the stability, reliability and economy of a communication network.

Description

Technical Field

[0001] This invention relates to the field of high-speed optical communication technology, and in particular to a 100G line-side signal FEC demodulation and decoding method based on FPGA implementation. Background Technology

[0002] In the field of high-speed optical communication technology, data transmission reliability and system performance are two core indicators for evaluating the quality of a communication system. With the continuous increase in data transmission rates, especially high-speed transmissions of 100Gbps and above, ensuring the integrity and accuracy of signals during transmission becomes particularly important. Forward Error Correction (FEC), as a key technology for improving data transmission reliability, adds redundant information at the transmitting end, enabling the receiving end to detect and correct errors, thereby improving communication quality.

[0003] FPGAs (Field-Programmable Gate Arrays) have become an ideal platform for implementing FEC demodulation and decoding in high-speed optical communication systems due to their parallel processing capabilities, reconfigurability, and I / O flexibility. The parallel processing capabilities of FPGAs can significantly accelerate algorithm execution, which is particularly important for processing high-speed signals. Furthermore, the reconfigurability of FPGAs allows for changes to their functionality through software updates without altering the hardware, greatly facilitating algorithm optimization and upgrades.

[0004] In 100G optical communication systems, signal demodulation and decoding is a complex process involving multiple steps such as symbol synchronization, carrier recovery, and sampling. These steps are crucial for ensuring high data transmission efficiency and low error rates. Traditional demodulation and decoding methods suffer from low efficiency and high error rates when processing high-speed signals, especially in complex modulation formats such as high-order QAM (quadrature amplitude modulation), including 8QAM, 16QAM, and 64QAM probabilistic shaping (PS). To address these issues, researchers have proposed various low-complexity soft-information demodulation techniques, such as using constellation region partitioning to simplify soft-information calculations and using region merging to approximate the ownership problem of boundary regions, thereby reducing computational complexity and improving demodulation and decoding efficiency.

[0005] Furthermore, hard-decision iterative demodulation and decoding methods for multi-level coded modulation have been proposed to address the error propagation problem in the combination of pulse position modulation (PPM) and multi-level coding. These methods effectively reduce the bit error rate (BER) and improve system reliability through iterative approaches.

[0006] In summary, with the development of optical communication technology, the demand for high-speed optical communication systems is increasing, and there is an urgent need for a method that can significantly improve the reliability and performance of the system while ensuring high data transmission efficiency. Summary of the Invention

[0007] To address the aforementioned problems, this invention provides a 100G line-side signal FEC demodulation and decoding method based on FPGA implementation, aiming to solve the problems of low efficiency and high error rate in existing technologies when processing high-speed signals. This method optimizes the hardware implementation of the FEC algorithm and utilizes the high-speed parallel processing capabilities of the FPGA to achieve efficient, low-latency FEC demodulation and decoding of 100Gbps signals, thereby significantly improving the reliability of signal transmission and the overall performance of the system.

[0008] The present invention includes signal preprocessing, signal synchronization, signal extraction and windowing, FFT operation, dealiasing filtering, signal demodulation, FEC decoding, signal recovery and error correction processing modules.

[0009] The signal preprocessing module first converts the input 100G OTN line-side signal into an optical-to-electrical signal. The electrical signal is then filtered to remove high-frequency noise and amplified by an amplifier. This process ensures signal quality.

[0010] The signal synchronization module uses clock recovery technology to extract clock information from the signal to achieve symbol synchronization, and uses carrier phase estimation technology to achieve carrier synchronization to eliminate the influence of carrier frequency deviation.

[0011] The signal decimation and windowing module employs multi-tap decimation technology. The input signal is decimated according to a specific decimation factor K, forming K signals. The selection of the decimation factor K is based on the characteristics of the signal and the processing capability of the FPGA. The decimated K signals are then windowed using Hamming windowing technology to reduce spectral leakage and edge effects.

[0012] The FFT operation module integrates K M-point FFT IP cores in the FPGA to perform Fast Fourier Transform (FFT) on the K-channel windowed signal, converting the time-domain signal into a frequency-domain signal. The number of FFT points M is determined based on the signal bandwidth and sampling rate to ensure sufficient spectral resolution.

[0013] The dealiasing filter module eliminates the aliasing effect caused by insufficient sampling rate in the signal after FFT transformation by using word filters.

[0014] The signal demodulation module uses coherent demodulation technology to demodulate the signal after dealiasing filtering and extract symbol information. During the demodulation process, soft decision technology is used to quantize the phase and amplitude of each symbol to obtain a soft decision value.

[0015] After the demodulated soft decision value is input into the FEC decoder, the FEC decoding uses a dual error correction algorithm of high-performance low-density parity check (LDPC) and Turbo code to achieve efficient error correction.

[0016] After receiving a near-original transmitted signal after FEC decoding, the signal recovery and error correction processing mode needs to further improve signal quality by employing signal equalization, symbol mapping, and cyclic redundancy check techniques, as there may be a small number of errors.

[0017] The performance optimization module monitors FPGA resources in real time and adjusts key parameters in the signal processing process to optimize system performance, improve processing speed, and reduce power consumption.

[0018] The beneficial effects of this invention are as follows: 1. Improved Signal Transmission Reliability: By employing an FPGA-based 100G line-side signal FEC demodulation and decoding method, this invention significantly improves the transmission reliability of signals in high-speed optical fiber communication systems. FEC technology adds redundant information at the transmitting end, enabling the receiving end to detect and correct a certain number of errors, thereby reducing the bit error rate. Soft-decision FEC decoding provides higher gain compared to hard-decision methods because it utilizes more signal information (such as phase and amplitude) for error correction, allowing the system to maintain high performance under more complex channel conditions.

[0019] 2. Extending Transmission Distance: In high-speed fiber optic communication systems, signals are affected by various adverse factors during long-distance transmission, such as chromatic dispersion and nonlinear effects. This invention, through an efficient FEC demodulation and decoding method, can effectively combat these effects, thereby extending the signal transmission distance. By reducing the bit error rate, the system can achieve signal transmission over longer distances without increasing additional hardware costs, which has significant economic implications for the construction and maintenance of long-distance fiber optic communication networks.

[0020] 3. Reduced System Cost and Power Consumption: This invention leverages the parallel processing capabilities and programmability of FPGAs to achieve high-performance, low-latency signal processing. This not only improves processing speed but also reduces system power consumption. The programmability of FPGAs allows for flexible system configuration according to different application requirements, reducing the need for dedicated hardware and thus lowering the overall system cost. Furthermore, optimizing the FPGA's HDL programming can further reduce power consumption, which is significant for the energy efficiency ratio of data centers and large-scale communication networks. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of the 100G line-side signal FEC demodulation and decoding method based on FPGA implementation according to the present invention.

[0023] Figure 2 This is a schematic diagram of the coherent receiving DSP of a 100G line-side signal FEC demodulation and decoding method based on FPGA implementation according to the present invention. Detailed Implementation

[0024] The technical solution of the invention will be described in detail below with reference to the accompanying drawings: like Figure 1 , Figure 2 As shown, this invention discloses a 100G line-side signal FEC demodulation and decoding method and system based on FPGA implementation. By optimizing the hardware implementation of the FEC algorithm and utilizing the high-speed parallel processing capability of FPGA, it achieves efficient and low-latency FEC demodulation and decoding of 100Gbps signals, thereby significantly improving the reliability of signal transmission and the overall performance of the system.

[0025] This invention includes modules for signal preprocessing, signal synchronization, signal decimation and windowing, FFT operation, dealiasing filtering, signal demodulation, FEC decoding, and signal recovery and error correction. The specific steps are as follows: Step 1: In the signal preprocessing stage, the optical signal on the 100G line side is first converted from an optical signal to an electrical signal via photoelectric conversion. Next, a low-pass filter is used to filter out high-frequency noise exceeding the signal bandwidth to reduce signal distortion. Then, an adjustable gain amplifier is used to amplify the filtered signal to compensate for losses during fiber optic transmission and ensure the signal strength meets the requirements of subsequent processing stages. Finally, an automatic gain control (AGC) module dynamically adjusts the amplifier gain to adapt to input signals of varying strengths, ensuring the signal remains optimal in subsequent processing. This preprocessing step provides high-quality input signals for subsequent critical steps such as signal synchronization, decimation, and FFT operations.

[0026] Step Two: In the signal synchronization step, accurate signal recovery is ensured through both carrier synchronization and symbol synchronization. For carrier synchronization, an internal synchronization method is used to directly extract synchronization information from the received signal. For signals without carrier frequency components, such as DSB, SSB, and 2PSK, pilot signals can be added to the transmitted signal. The receiver uses a narrowband filter to filter out the pilot signals, assisting in generating a coherent carrier frequency. For carrier extraction without auxiliary pilots, a nonlinear transformation method is used to obtain the carrier frequency from the signal. Harmonic components of the carrier frequency are extracted from the signal using square loop and Costas loop techniques, and then frequency division is used to obtain the carrier synchronization signal. Symbol synchronization employs a self-synchronization method, without relying on auxiliary synchronization information. An open-loop synchronization method is used, employing a nonlinear transformation processing circuit and a narrowband filter to extract the discrete frequency components of the symbol rate.

[0027] Step 3: During signal decimation, the received 100G line-side signal undergoes photoelectric conversion and pre-amplification before entering a digital downconverter (DDC) to convert the high-frequency signal into a lower intermediate frequency or baseband signal. In this step, we employ multi-tap decimation technology. Based on the signal's sampling rate and bandwidth, we select a suitable decimation factor K and downsample the signal using a digital decimation filter to reduce the computational complexity of subsequent processing while retaining sufficient signal information. The decimated signal is divided into K paths, each with a reduced sampling rate but still containing enough information for subsequent processing. The decimated K-path signals then undergo windowing to reduce spectral leakage and edge effects. We select suitable window functions—Hamming windows—which effectively reduce spectral leakage during Fast Fourier Transform (FFT). Windowing involves multiplying each point of the signal sample by the corresponding value of the window function. This process is implemented in the FPGA using a lookup table (LUT) to improve processing speed. The windowed signal will have a smoother spectral envelope in the frequency domain, which helps to improve the accuracy of spectral analysis after FFT transformation and provides high-quality signal samples for subsequent signal demodulation and FEC decoding.

[0028] Step 4: The FFT (Fast Fourier Transform) operation is a crucial step in converting a time-domain signal into a frequency-domain signal. K M-point FFT IP cores are integrated into the FPGA, with each core processing one windowed signal. The selection of M points is based on the signal bandwidth and sampling rate to ensure sufficient spectral resolution and processing efficiency. The configuration of the FFT IP core includes setting parameters such as the FFT size, input data type, and output data type to adapt to different signal processing needs.

[0029] Step 5: For the K-channel windowed signals, transmission is achieved through the FPGA's internal high-speed data bus to ensure data flow continuity and real-time performance. Input data buffering and scheduling are managed to adapt to the FFT IP core's processing speed, preventing data overflow or processing delays. Each signal undergoes an M-point FFT operation within the FFT IP core, converting the time-domain signal to a frequency-domain signal. The FFT algorithm employs a recursive butterfly operation structure, using a divide-and-conquer approach to decompose the large-scale FFT into multiple smaller-scale FFTs, thereby reducing computational complexity.

[0030] Step Six: The result of the FFT operation is stored in the FPGA's internal cache for subsequent signal processing modules to access. By using pipelined technology to reduce computational latency and parallel processing technology to improve processing speed, the output frequency domain signal contains the frequency component information of the original time domain signal, providing basic data for dealiasing filtering and signal demodulation.

[0031] Step 7: The dealiasing filtering step is crucial for ensuring signal processing quality. Based on the Nyquist sampling theorem, a digital low-pass filter is designed with a cutoff frequency slightly lower than half the sampling frequency to effectively filter out aliasing components above the Nyquist frequency. The frequency response of the filter is converted into the time-domain impulse response, i.e., the filter coefficients, through the inverse Discrete Fourier Transform (DFT). These coefficients are stored in the FPGA's read-only memory (ROM) for fast access during signal processing. After the FFT transform, these filter coefficients are applied to each frequency point of the signal, achieving the filtering effect in the frequency domain through convolution operations, thereby removing aliasing components. By accumulating the filtered signals, the final dealiased signal is obtained.

[0032] Step 8: Perform necessary spectral correction on the frequency domain signal after FFT transformation to compensate for distortions in the filter and signal transmission process. Coherent demodulation technology is employed, utilizing the known carrier frequency and phase information to demodulate the signal. During demodulation, considering potential multipath effects and time delay spread, the minimum mean square error (MMSE) and maximum likelihood (ML) algorithms are used for time alignment and phase correction. Symbol detection is performed on the demodulated signal, determining the corresponding symbol value based on the signal's amplitude and phase information. Soft decision processing is applied to the detected symbol sequence to generate soft decision values, which include not only the hard decision results for the symbols but also the symbol reliability information.

[0033] Step Nine: The receiving end receives the FEC frames processed by soft decision and decomposes each FEC frame into multiple subframes, each containing a certain number of symbols. These subframes are sent sequentially to the decoder group according to the decoding cycle. The decoder group consists of multiple decoders connected in a cascaded manner, each decoder having the same decoding control logic. During the decoding cycle, if the first FEC decoder in the decoder group receives enough subframes, it assembles these subframes into an FEC frame to be decoded and performs soft decision FEC decoding. If the number of received subframes exceeds the required number, the first arriving subframe is sent to the next level decoder, while the remaining subframes are assembled into an FEC frame to be decoded. By using multiple interconnected FEC decoders to perform multiple iterative decodings on each subframe, the error correction capability of the FEC decoder is improved. Furthermore, by decomposing the FEC frame into subframes, the time-division scheduling cycle of the operational circuits in the FEC decoder can be flexibly designed according to the frame length of the subframes, reducing the size of the operational circuits in the FEC decoder, making it easy to implement and cost-effective. Ultimately, the decoder group is able to recover the source data based on the forward error correction decoding algorithm corresponding to the transmitter.

[0034] Step 10: Although the signal from Step 9 has corrected most of the errors, a small number of residual errors may still exist. This step uses adaptive equalizer technology to equalize the signal to compensate for channel-induced distortion. Cyclic Redundancy Check (CRC) is used for error detection. If an error is detected, different error correction strategies are employed based on the nature and location of the error, such as error concealment, error interpolation, or requesting retransmission. For errors that cannot be corrected, they are isolated through error location and marking to prevent error propagation and ensure data integrity.

[0035] Through the above embodiments, the 100G line-side signal FEC demodulation and decoding method based on FPGA implementation of the present invention can significantly improve the signal transmission reliability of high-speed optical fiber communication systems, extend the transmission distance, and reduce system costs, which is of great practical significance for improving the stability and economy of communication networks. Each component of the system has been carefully designed and optimized to ensure maximum overall performance. Furthermore, the system's flexibility and scalability provide possibilities for future technology upgrades and application expansion. Various aspects of the invention are described in this disclosure with reference to the accompanying drawings, which illustrate numerous illustrative embodiments. The embodiments of this disclosure are not necessarily defined to include all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed in this invention are not limited to any particular implementation. Additionally, some aspects of the invention disclosed can be used alone or in any suitable combination with other aspects of the invention disclosed.

[0036] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. The first claim of this invention relates to a 100G line-side signal FEC demodulation and decoding method implemented based on FPGA, characterized in that... This method integrates a series of technical steps, including signal preprocessing, synchronization, decimation, windowing, FFT operation, dealiasing filtering, signal demodulation, FEC decoding, and signal recovery and error correction. Specifically, the method first converts the optical signal into an electrical signal through photoelectric conversion, and then performs signal amplification and automatic gain control to ensure that the signal quality meets the requirements of subsequent processing. Subsequently, precise carrier synchronization and symbol synchronization steps are used to achieve accurate signal synchronization, providing an accurate timing reference for subsequent processing. Next, multi-tap decimation technology and window functions are used to process the signal to reduce spectral leakage. In the FFT operation step, the FFT IP core in the FPGA is used to perform a fast Fourier transform on the signal, converting the time-domain signal into a frequency-domain signal. In the dealiasing filtering step, a digital low-pass filter is designed and applied to eliminate the aliasing effect caused by insufficient sampling rate. The signal demodulation step employs coherent demodulation technology to extract symbol information. In the FEC decoding step, the demodulated soft decision value is input into the FEC decoder for error correction. Finally, in the signal recovery and error correction processing step, strategies such as adaptive equalization, error detection, and error concealment or retransmission requests are used to ensure the integrity and accuracy of the data.

2. The signal synchronization according to claim 1, characterized in that, The specific steps include carrier synchronization and symbol synchronization. The internal synchronization method is used to achieve accurate signal synchronization. Carrier synchronization is achieved by extracting synchronization information from the signal or adding pilot signals to help generate coherent carrier frequencies. Symbol synchronization is achieved by inserting synchronization signals into the transmitted signal or by using technologies such as digital phase-locked loops to ensure accurate signal recovery and provide accurate timing references for subsequent signal processing.

3. The FFT operation according to claim 1, characterized in that, The specific steps include configuring FFT IP cores, data flow management, FFT operation execution, result caching and output, and performance optimization; integrating multiple FFT IP cores in the FPGA to perform fast Fourier transform on the windowed signal, converting the time-domain signal into a frequency-domain signal, reducing computational latency through pipeline technology, or improving processing speed through parallel processing technology, optimizing FPGA HDL programming, reducing resource consumption, and improving the energy efficiency ratio of FFT operations.

4. The dealiasing filter according to claim 1, characterized in that, The specific steps include designing a digital low-pass filter with a cutoff frequency slightly lower than half the sampling frequency to effectively filter out aliasing components above the Nyquist frequency; windowing the frequency response of the ideal low-pass filter using the window function method; and converting the frequency response of the filter into the impulse response in the time domain, i.e., the filter coefficients, through the inverse of the Discrete Fourier Transform (DFT). These coefficients are stored in the read-only memory (ROM) of the FPGA for fast access during signal processing.

5. The signal demodulation according to claim 1, characterized in that, The specific steps include using coherent demodulation technology to demodulate the signal using known carrier frequency and phase information; during demodulation, considering the multipath effect and time delay spread that the signal may be subject to, using minimum mean square error (MMSE) and maximum likelihood (ML) algorithms to perform time alignment and phase correction on the signal; performing symbol detection on the demodulated signal; and determining the corresponding symbol value based on the amplitude and phase information of the signal.

6. The FEC decoding according to claim 1, characterized in that, The specific steps include inputting the demodulated soft decision value into the FEC decoder for error correction; the FEC decoder employs a high-performance low-density parity check (LDPC) and Turbo code dual error correction algorithm to achieve efficient error correction; signal quality is further improved through signal recovery techniques, such as signal equalization and symbol mapping; cyclic redundancy check (CRC) is used for error detection; if an error is detected, appropriate processing measures are taken according to the error type, such as requesting retransmission or using error concealment techniques.

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