Drive holding circuit and electronic device

Abstract

This application relates to the field of power electronics technology and discloses a drive holding circuit, electronic device, and vehicle. The drive holding circuit includes a first circuit and a second circuit. The first circuit is adapted to receive a power supply signal and a control signal, and to conduct when the control signal switches from invalid to valid, thereby generating a drive signal based on the power supply signal and latching the drive signal to keep it valid. The second circuit is adapted to receive the drive signal and a safety logic signal, and to release the latch of the drive signal when the control signal and the safety logic signal meet preset conditions, causing the drive signal to fail. This application can maintain a valid drive state even when a drive signal source failure occurs, thereby effectively avoiding the impact of a single fault on the function of the electronic device and significantly improving system reliability.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a drive holding circuit, electronic equipment, and vehicle. Background Technology

[0002] In electronic devices, the realization of their functions generally requires a drive signal generator to emit a drive signal, which is then sent to the load through a drive signal path to drive the load. In this process, the drive signal generator must continuously generate drive signals to ensure the continuous operation of the load unit.

[0003] In related technologies, microcontroller units (MCUs) are typically used as the source of drive signals. However, MCUs account for a high proportion of system failures. Once an MCU fails, it will cause a single point fault (SPF) in the electronic device, which will then cause the electronic device to malfunction and seriously affect the system's single point fault tolerance capability. Summary of the Invention

[0004] This application provides a drive holding circuit, electronic device, and vehicle, which solves the technical problem that the output of the drive signal in the electronic device is highly dependent on the normal operation of the drive signal source, resulting in extremely low fault tolerance of the system at a single point of failure. It can still maintain an effective drive state when the drive signal source fails, thereby effectively avoiding the impact of a single fault on the function of the electronic device and significantly improving the system reliability.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, this application provides a drive-holding circuit, the drive-holding circuit comprising: A first circuit is adapted to receive a power supply signal and a control signal, and to be turned on when the control signal switches from invalid to valid, so as to generate a drive signal according to the power supply signal and to self-lock the drive signal so that the drive signal remains valid. The second circuit is adapted to receive the drive signal and the safety logic signal, and to release the self-locking of the drive signal when the control signal and the safety logic signal meet preset conditions, thereby causing the drive signal to fail.

[0006] The drive holding circuit proposed in this application utilizes a first loop to generate and latch the drive signal at the control signal transition edge, thus ensuring a continuous output of a valid drive level even if the control signal source subsequently fails. Furthermore, a second loop introduces a collaborative judgment mechanism between the control signal and safety logic signal. The control signal indicates whether the drive function is enabled, while the safety logic signal indicates whether the system is operating normally. The drive signal's latch release operation is only executed when both the control signal and the safety logic signal simultaneously meet preset conditions, preventing erroneous shutdown caused by a single signal anomaly. Compared to related technologies, this application's embodiment ensures a continuous and effective output of the drive signal even in the event of a control signal failure, enabling the system to continue driving the backend load normally under single-point-of-failure conditions. This effectively avoids the impact of a single fault on the functionality of electronic equipment and significantly improves system reliability.

[0007] Optionally, the first circuit includes a first switch and a second switch; The first switch is configured to be turned on when the control signal is valid and / or the drive signal is valid; The second switch is configured to turn on when the first switch is on, so as to output the valid drive signal.

[0008] Optionally, the first circuit further includes a first diode; Wherein, the anode of the first diode is adapted to receive the control signal, and the cathode of the first diode is connected to the control terminal of the first switching transistor; The control terminal of the first switch is adapted to receive the control signal, the first terminal of the first switch is adapted to receive the power supply signal, and the second terminal of the first switch is grounded. The control terminal of the second switch is connected to the first terminal of the first switch, the first terminal of the second switch is adapted to receive the power supply signal, and the second terminal of the second switch is connected to the control terminal of the first switch and is adapted to output the drive signal.

[0009] Optionally, the first switching transistor is an NPN transistor, and the second switching transistor is a PNP transistor.

[0010] The first circuit, through a first and second switching transistor, forms a positive feedback self-locking circuit structure. When the control signal changes from invalid to valid, the first switching transistor turns on first, pulling down the control terminal potential of the second switching transistor, causing it to turn on and output a drive signal. Subsequently, this drive signal feeds back to the control terminal of the first switching transistor, causing the first circuit to tend towards dynamic equilibrium, thereby achieving level self-locking of the drive signal. In this way, the first circuit, with its simple circuit structure composed of discrete components, can maintain the drive signal without the need for complex and redundant integrated chips, significantly reducing circuit costs. Furthermore, this application utilizes a first diode to prevent reverse connection interference from the drive signal, thus improving the reliability of the self-locking structure.

[0011] Optionally, the second circuit includes a third switch and a fourth switch; The third switch is configured to turn on when the control signal is invalid, and the fourth switch is configured to turn on when the safety logic signal is valid. The second circuit is configured to release the self-locking of the drive signal when the third switch and the fourth switch are simultaneously turned on.

[0012] Optionally, the control terminal of the third switch is adapted to receive the control signal, and the first terminal of the third switch is adapted to receive the drive signal; The control terminal of the fourth switch is adapted to receive the safety logic signal, the first terminal of the fourth switch is connected to the second terminal of the third switch, and the second terminal of the fourth switch is grounded.

[0013] Optionally, the third switching transistor is a PNP transistor, and the fourth switching transistor is an NPN transistor.

[0014] The second circuit implements precise self-locking release logic for the drive signal through the third and fourth switches. Only when both conditions are met simultaneously—the control signal has been confirmed invalid and the safety logic signal is valid—is the system in a normal operating state where the drive signal can be turned off. The third and fourth switches are turned on together, forcibly pulling the drive signal output node low, thereby releasing the self-lock. This ensures that the drive signal output can be effectively turned off and also effectively prevents the drive signal from being mistakenly turned off, greatly improving the system reliability.

[0015] Optionally, the drive holding circuit further includes a second diode configured to regulate the drive signal so that the effective level of the drive signal output by the drive holding circuit matches the drive load.

[0016] By leveraging the voltage regulation function of the second diode, the drive holding circuit can flexibly adapt to drive loads with different rated operating voltages, eliminating the need to design dedicated drive circuits for loads with specific voltage requirements, thus significantly improving the circuit's versatility and adaptability. Simultaneously, the stabilized drive signal prevents abnormal load operation due to voltage fluctuations, further ensuring the stability and reliability of load operation.

[0017] Secondly, embodiments of this application provide an electronic device, which includes the aforementioned drive and hold circuit.

[0018] Thirdly, embodiments of this application provide a vehicle that includes the aforementioned electronic equipment. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 A schematic diagram of a drive-hold circuit provided in an embodiment of this application; Figure 2 A schematic diagram of the circuit structure of the first loop provided in an embodiment of this application; Figure 3 A schematic diagram of the circuit structure of the second loop provided in an embodiment of this application; Figure 4 A schematic diagram of the circuit structure of the third circuit provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the operation flow of the drive-hold circuit provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the description, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy.

[0023] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0024] In the functional implementation of electronic devices, the MCU acts as the source of drive signals. Its output drive signals are transmitted to the load through the drive signal path to ensure that the load stably executes the preset functions. This process is highly dependent on the continuous and uninterrupted operation of the drive signal source. According to industry reliability data and functional safety analysis, MCU failures typically account for 10% to 40% of overall system failures.

[0025] As the requirements for functional safety in fields such as automotive electronics and industrial control become increasingly stringent, some industry standards stipulate that a single fault must not lead to the failure of safety functions, that is, the system must have single point of failure tolerance (SPF-tolerant) capability.

[0026] In addition, some related technologies achieve drive signal protection by adding a second MCU and supporting components to build a redundant control architecture. Although this can address the MCU failure problem to some extent, the use of redundant MCUs and complex dedicated components directly leads to a significant increase in hardware costs and also causes the system complexity to increase exponentially.

[0027] Therefore, there is an urgent need for a low-cost and highly reliable drive signal holding solution.

[0028] This application provides a drive-hold circuit 10, such as Figure 1As shown, this circuit can be used in electronic devices such as industrial control devices, consumer electronics terminals, and automotive application equipment, as well as vehicles. The drive holding circuit 10 includes a first circuit 11 and a second circuit 12. The first circuit 11 is adapted to receive power supply signals and control signals, and is turned on when the control signal switches from invalid to valid, so as to generate a drive signal according to the power supply signal and self-lock the drive signal to keep the drive signal valid.

[0029] The second circuit 12 is adapted to receive drive signals and safety logic signals, and release the self-locking of the drive signal when the control signal and safety logic signal meet preset conditions, thereby causing the drive signal to fail.

[0030] Specifically, the drive-holding circuit 10 is connected to the processor module 20, the power supply module 30, and the safety logic output module 40, respectively. In this embodiment, taking the new energy vehicle field as an example, the power supply module 30 can be an on-board battery. The power supply module 30 outputs a power supply signal to provide the operating voltage for the entire drive-holding circuit. The processor module 20 can be an MCU, and the aforementioned control signal can be a digital output signal of the MCU. Its invalid state is low (e.g., 0 V), and its valid state is high (e.g., 3.3 V, 5 V, etc.). The control signal switches from invalid to valid, corresponding to the rising edge of the MCU output, thus serving as the trigger condition for starting the drive-holding circuit. The safety logic output module 40 generates a safety logic signal. During normal system operation, the safety logic signal is high; during system malfunction, the safety logic signal is low. It is understood that the safety logic signal is a high-level valid signal.

[0031] The first circuit 11 is a positive feedback latch structure composed of discrete semiconductor devices. It is configured to turn on in response to the rising edge of the control signal and maintain its conducting state through an internal feedback path after turning on, thereby continuously outputting a stable drive signal. It can be understood that the drive signal is a high-level active signal, and its amplitude can be close to the supply signal voltage. Utilizing the self-locking structure of the first circuit 11, after initial conduction under the rising edge of the control signal, the first circuit 11 no longer depends on the continuous effectiveness of the control signal to maintain conduction. Thus, even if the control signal subsequently returns to an inactive state or disappears completely, the drive signal remains active.

[0032] In this embodiment, to distinguish whether the low level of the control signal represents a drive signal shutdown operation under normal system operation or an MCU failure under system abnormality, the second circuit 12 receives the control signal and the safety logic signal respectively, and makes a combined judgment based on the control signal and the safety logic signal. Only when the control signal is low and the safety logic signal is high will the output of the drive signal be shut off, that is, the drive signal becomes low. This responds to the drive signal shutdown operation under normal system operation, so that the drive signal is accurately reset.

[0033] The drive holding circuit 10 provided in this embodiment utilizes the first loop 11 to generate and latch the drive signal at the control signal transition edge, thus ensuring a continuous output of a valid drive level even when the control signal source subsequently fails. Furthermore, a collaborative judgment mechanism between the control signal and safety logic signal is introduced through the second loop 12. The control signal indicates whether the drive function is enabled, while the safety logic signal indicates whether the system is operating normally. The drive signal's self-locking release operation is only executed when both the control signal and the safety logic signal simultaneously meet preset conditions, preventing erroneous shutdown caused by a single signal anomaly. Compared to related technologies, this embodiment ensures a continuous and effective output of the drive signal even when the control signal fails, enabling the system to drive the backend load normally under single-point-of-failure conditions. This effectively avoids the impact of a single fault on the functionality of electronic equipment and significantly improves system reliability.

[0034] Figure 2 A schematic diagram of the circuit structure of the first loop 11 described above is shown, as follows: Figure 2 As shown, in some embodiments of this application, the first circuit 11 includes a first switch Q1 and a second switch Q2. The first switch Q1 is configured to conduct when a control signal and / or a drive signal is valid. The second switch Q2 is configured to conduct when the first switch Q1 is on, so as to output a valid drive signal.

[0035] Specifically, in some embodiments of this application, the drive signal is active high and inactive low. When the control signal changes from low to high, it first triggers the first switch Q1 to turn on, and then the turn-on of the first switch Q1 triggers the turn-on of the second switch Q2, thereby causing the drive holding circuit 10 to output a high-level drive signal. Subsequently, the high-level drive signal is fed back to the first switch Q1, causing the first switch Q1 to continue to conduct under the action of the drive signal, so that the entire first loop 11 tends to be in dynamic equilibrium. It can be understood that even if the control signal becomes low, the first loop 11 can still maintain the first switch Q1 on, so that the drive holding circuit 10 does not need to rely on continuous control signal excitation, and only needs a single effective transition to start signal self-locking.

[0036] Furthermore, such as Figure 2 As shown, the first circuit 11 further includes a first diode D1, wherein the anode of the first diode D1 is adapted to receive a control signal, and the cathode of the first diode D1 is connected to the control terminal of the first switching transistor Q1. The control terminal of the first switching transistor Q1 is adapted to receive a control signal, the first terminal of the first switching transistor Q1 is adapted to receive a power supply signal, and the second terminal of the first switching transistor Q1 is grounded. The control terminal of the second switching transistor Q2 is connected to the first terminal of the first switching transistor Q1, the first terminal of the second switching transistor Q2 is adapted to receive a power supply signal, the second terminal of the second switching transistor Q2 is connected to the control terminal of the first switching transistor Q1, and the second terminal of the second switching transistor Q2 is adapted to output a drive signal.

[0037] In one example of an embodiment of this application, the first switching transistor Q1 is an NPN transistor, and the second switching transistor Q2 is a PNP transistor. The first diode D1 is a unidirectional rectifier diode, with its anode connected to the control signal and its cathode connected to the base of the first switching transistor Q1, enabling unidirectional transmission of the control signal and ensuring the accuracy of the logic that triggers the switching transistor to turn on. It should be noted that the selection of the device types of the first switching transistor Q1 and the second switching transistor Q2 in this embodiment is merely illustrative. In actual applications, other power electronic devices with switching characteristics, such as MOSFETs and thyristors, can be selected according to the actual needs of the scenario, and this is not intended to limit this application.

[0038] Specifically, a resistor R1 is connected between the cathode of the first diode D1 and the base of the first switching transistor Q1, a resistor R2 is connected between the base and emitter of the first switching transistor Q1, a resistor R3 is connected between the collector of the first switching transistor Q1 and the base of the second transistor Q2, a resistor R4 is also connected between the collector of the first switching transistor Q1 and the power supply module 30, and the collector of the second switching transistor Q2 is connected to the cathode of the first diode D1 in sequence via resistors R5 and R6, and the connection node A where resistors R5 and R6 are connected serves as the output terminal of the first circuit 11.

[0039] The truth table corresponding to the input and output signals of the first loop 11 is shown in Table 1 below.

[0040] Table 1 As shown in Table 1, when the processor module 20 has no output or the output control signal is low, both the first switch Q1 and the second switch Q2 are turned off. Therefore, the first circuit 11 is in an open circuit state, and the first circuit 11 outputs a low level, that is, there is no drive signal output.

[0041] When the control signal switches from low to high, the first switch Q1 turns on, pulling the base level of the second switch Q2 low, thus turning on Q2. At this time, the power supply signal flows into resistor R5 due to the conduction of Q2, resulting in a high-level drive signal output at connection node A. Then, through the feedback path formed by resistors R6 and R1, the drive signal is fed back to the base of the first switch Q1, keeping Q1 continuously on.

[0042] When the control signal switches from high level to low level, due to the feedback of the drive signal in the first circuit 11, the first switch Q1 and the second switch Q2 will still remain on. In other words, once the first switch Q1 and the second switch Q2 are turned on for the first time, their conduction state will not depend on the level of the control signal, thus achieving self-locking of the drive signal.

[0043] Therefore, the first circuit 11, through the first switch Q1 and the second switch Q2, forms a positive feedback self-locking circuit structure. When the control signal changes from invalid to valid, the first switch Q1 turns on first, pulling down the control terminal potential of the second switch Q2, causing it to turn on and output a drive signal. Subsequently, this drive signal feeds back to the control terminal of the first switch Q1, causing the first circuit 11 to tend towards dynamic equilibrium, thereby achieving level self-locking of the drive signal. In this way, the first circuit 11, with its simple circuit structure composed of discrete components, can achieve the holding of the drive signal without the need for complex and redundant integrated chips, significantly reducing circuit costs. In addition, this application utilizes the first diode D1 to prevent reverse connection interference of the drive signal, thus improving the reliability of the self-locking structure.

[0044] Figure 3 The circuit structure diagram of the second loop 12 described above is shown below. Figure 3 As shown, in some embodiments of this application, the second circuit 12 includes a third switch Q3 and a fourth switch Q4. The third switch Q3 is configured to turn on when the control signal is invalid, and the fourth switch Q4 is configured to turn on when the safety logic signal is valid. The second circuit 12 is configured to release the self-locking of the drive signal when both the third switch Q3 and the fourth switch Q4 are simultaneously turned on.

[0045] Specifically, the third switch Q3 and the fourth switch Q4 are connected in series between the aforementioned connection node A and ground. It can be understood that when the control signal is invalid while the safety logic signal is valid, the valid safety logic signal indicates normal system operation. The processor module 20 performs a drive signal shutdown operation by converting the control signal to invalid. At this time, both the third switch Q3 and the fourth switch Q4 are turned on, grounding connection node A and releasing the self-locking of the drive signal. In other cases, at least one of the third switch Q3 and the fourth switch Q4 is in the off state, thus maintaining the drive signal's validity.

[0046] Furthermore, such as Figure 3 As shown, the control terminal of the third switch Q3 is adapted to receive control signals, and the first terminal of the third switch Q3 is adapted to receive drive signals. The control terminal of the fourth switch Q4 is adapted to receive safety logic signals, the first terminal of the fourth switch Q4 is connected to the second terminal of the third switch Q3, and the second terminal of the fourth switch Q4 is grounded.

[0047] In one example of an embodiment of this application, the third switch Q3 is a PNP transistor, and the fourth switch Q4 is an NPN transistor. It should be noted that the selection of the device types for the third switch Q3 and the fourth switch Q4 in this embodiment is merely illustrative. In practical applications, other power electronic devices with switching characteristics, such as MOSFETs and thyristors, can be selected according to the specific needs of the application, and this is not intended to limit the scope of this application.

[0048] Specifically, the base of the third switch Q3 is connected to the processor module 20 via resistor R7 to receive control signals. The base of the fourth switch Q4 is connected to the safety logic output module 40 via resistor R8 to receive safety logic signals. A resistor R9 is also connected between the base and emitter of the fourth switch Q4. Furthermore, the base of the third switch Q3 is connected to the aforementioned connection node A as the input terminal of the second loop 12, and a connection node B is also provided at the base of the third switch Q3. This connection node B serves as the output terminal of the second loop 12, used to send drive signals to the downstream load.

[0049] Furthermore, the truth table corresponding to the input and output signals of the second loop 12 is shown in Table 2 below.

[0050] Table 2 As shown in Table 1, when the power supply signal is low, that is, the power supply module 30 is not powered and the drive holding circuit 10 is not powered, the signals connecting node A and connecting node B are low regardless of the level of the control signal and the safety logic signal, meaning that the drive holding circuit will not output a valid drive signal.

[0051] Under normal conditions, the processor module 20 can output either a high or low level control signal, while the safety logic output module 40 outputs a high level safety logic signal. However, in the event of a malfunction, the processor module 20 can only output a low level control signal, and the safety logic output module 40 outputs a low level safety logic signal.

[0052] When the power supply signal is high, the drive holding circuit 10 is powered on. At this time, the high-level drive signal output by the first circuit 11 will be input to the second circuit 12 through connection node A. When both the control signal and the safety logic signal are high, it indicates that the current system is operating normally and the processor module 20 is performing a drive signal output operation. At this time, the third switch Q3 is turned off and the fourth switch Q4 is turned on. Therefore, connection node A is not grounded, so the high-level drive signal will be output through connection node B.

[0053] When the control signal is low and the safety logic signal is high, it indicates that the current system is running normally and the processor module 20 is performing a drive signal shutdown operation. At this time, both the third switch Q3 and the fourth switch Q4 are turned on, so the connection node A is grounded, causing the high-level drive signal to flow to ground, resulting in a low level at the connection node B, which achieves the shutdown of the drive signal.

[0054] When the control signal is high and the safety logic signal is low, it indicates that the processor module 20 is performing a drive signal output operation. However, the safety logic output module 40 fails and outputs a low level incorrectly. At this time, the third switch Q3 is turned off and the fourth switch Q4 is turned on. Therefore, the connection node A is not grounded, so the high-level drive signal will be output through the connection node B. It can be understood that this effectively avoids the situation where the drive signal is mistakenly turned off due to the failure of the safety logic output module.

[0055] When the control signal is low and the safety logic signal is low, it indicates that the processor module 20 has failed and the current system is operating abnormally. At this time, the third switch Q3 is turned on and the fourth switch Q4 is turned off. Therefore, the connection node A is not grounded, so the high-level drive signal will be output through the connection node B. It can be understood that this effectively avoids the situation where the drive signal is mistakenly turned off due to the failure of the processor module 20.

[0056] Therefore, the second circuit 12 implements precise self-locking release logic for the drive signal through the third switch Q3 and the fourth switch Q4. Only when both conditions are met simultaneously—the control signal has been confirmed invalid and the safety logic signal is valid—is the system in a normal operating state where the drive signal can be turned off. The third switch Q3 and the fourth switch Q4 are turned on together, forcibly pulling the drive signal output node low, thereby releasing the self-locking. This ensures that the output of the drive signal can be effectively turned off and also effectively prevents the drive signal from being mistakenly turned off, greatly improving the system reliability.

[0057] In some embodiments of this application, the drive-hold circuit 10 further includes a third circuit 13. Figure 4 The circuit structure diagram of the third loop 13 mentioned above is shown below. Figure 4 As shown, in some embodiments of this application, the drive holding circuit 10 further includes a second diode D2, which is configured to regulate the drive signal so that the effective level of the drive signal output by the drive holding circuit 10 matches the back-end load to be driven.

[0058] Specifically, the cathode of the second diode D2 is connected to the aforementioned connection node B through resistor R10. This connection node B serves as the input terminal of the third circuit 13. The anode of the second diode D2 is grounded, and the cathode of the second diode D2 is connected to the downstream load through connection node C. This connection node C serves as the output terminal of the third circuit 13 to output a drive signal.

[0059] Furthermore, the correspondence between the final level of the output drive signal of the third circuit 13 and the model of the second diode D2 is shown in Table 3 below.

[0060] Table 3 As shown in Table 3 above, the second diode D2 can be a Zener diode of different types. The drive holding circuit 10 can output an output signal adapted to different load levels at the connection node C by selecting the second diode D2.

[0061] Therefore, by utilizing the voltage regulation effect of the second diode D2, the drive holding circuit 10 can flexibly adapt to drive loads with different rated operating voltages, eliminating the need to design dedicated drive circuits for loads with specific voltage requirements, thus significantly improving the circuit's versatility and adaptability. Simultaneously, the stabilized drive signal can prevent abnormal load operation due to voltage fluctuations, further ensuring the stability and reliability of the load operation.

[0062] The following describes the operation of the drive holding circuit 10 using the scenario of the vehicle power-on (ON3) of a new energy vehicle as an example. ON3 is an essential power source for vehicle operation. During vehicle movement, the drive holding circuit 10 proposed in this embodiment ensures that the ON3 power supply is maintained even in the event of a system malfunction, thereby guaranteeing the vehicle's controllability. Specifically, as... Figure 5 As shown, after the battery supplies power, it first determines whether the system is operating normally. If the system is operating normally, it outputs a high-level safety logic signal; otherwise, it outputs a low-level safety logic signal.

[0063] Based on the output of a high-level safety logic signal, if the MCU outputs a high-level control signal, a drive signal is generated. Simultaneously, the system continuously checks for malfunctions. If no malfunction occurs, the drive signal remains high, driving the vehicle's ON3 power supply. If a system malfunction occurs, a low-level safety logic signal is output.

[0064] Based on the low-level safety logic signal output, the drive signal output by the drive holding circuit maintains the logic of the previous normal state. If the drive signal was high in the previous normal state, the ON3 power supply output is driven; otherwise, the ON3 power supply output is turned off.

[0065] Accordingly, this application also provides an electronic device, which includes the drive-hold circuit 10 provided in the above embodiments.

[0066] The specific configuration and further functional description of the electronic device are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0067] The electronic device proposed in this embodiment receives control signals through a drive holding circuit 10 and generates and latches the drive signal at the control signal's transition edge, thus ensuring a continuous output of a valid drive level even if the control signal source subsequently fails. Furthermore, a collaborative judgment mechanism between the control signal and safety logic signals is introduced. The control signal indicates whether the drive function is enabled, while the safety logic signal indicates whether the system is operating normally. The drive signal's self-locking release operation is only executed when both the control signal and the safety logic signal simultaneously meet preset conditions, preventing erroneous shutdown caused by a single signal anomaly. Compared with related technologies, this embodiment ensures a continuous and effective output of the drive signal even when the control signal fails, enabling the system to drive the backend load normally under single-point-of-failure conditions. This effectively avoids the impact of a single fault on the electronic device's functionality and significantly improves system reliability.

[0068] Accordingly, this application also provides a vehicle that includes the electronic equipment provided in the above embodiments.

[0069] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0070] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0071] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0072] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0073] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A drive-hold circuit, characterized in that, The drive holding circuit includes: The first circuit (11) is adapted to receive a power supply signal and a control signal, and to be turned on when the control signal switches from invalid to valid, so as to generate a drive signal according to the power supply signal and to self-lock the drive signal so that the drive signal remains valid; The second circuit (12) is adapted to receive the drive signal and the safety logic signal, and release the self-locking of the drive signal when the control signal and the safety logic signal meet the preset conditions, so that the drive signal fails.

2. The drive-hold circuit according to claim 1, characterized in that, The first circuit (11) includes a first switch Q1 and a second switch Q2; The first switch Q1 is configured to be turned on when the control signal is valid and / or the drive signal is valid; The second switch Q2 is configured to turn on when the first switch Q1 is turned on, so as to output the valid drive signal.

3. The drive-hold circuit according to claim 2, characterized in that, The first circuit (11) also includes a first diode D1; Wherein, the anode of the first diode D1 is adapted to receive the control signal, and the cathode of the first diode D1 is connected to the control terminal of the first switching transistor Q1; The control terminal of the first switch Q1 is adapted to receive the control signal, the first terminal of the first switch Q1 is adapted to receive the power supply signal, and the second terminal of the first switch Q1 is grounded. The control terminal of the second switch Q2 is connected to the first terminal of the first switch Q1. The first terminal of the second switch Q2 is adapted to receive the power supply signal. The second terminal of the second switch Q2 is connected to the control terminal of the first switch Q1 and the second terminal of the second switch Q2 is adapted to output the drive signal.

4. The drive-hold circuit according to claim 2 or 3, characterized in that, The first switching transistor Q1 is an NPN transistor, and the second switching transistor Q2 is a PNP transistor.

5. The drive-hold circuit according to claim 1, characterized in that, The second circuit (12) includes a third switch Q3 and a fourth switch Q4; The third switch Q3 is configured to be turned on when the control signal is invalid, and the fourth switch Q4 is configured to be turned on when the safety logic signal is valid. The second circuit (12) is configured to release the self-locking of the drive signal when the third switch Q3 and the fourth switch Q4 are simultaneously turned on.

6. The drive-hold circuit according to claim 5, characterized in that, The control terminal of the third switch Q3 is adapted to receive the control signal, and the first terminal of the third switch Q3 is adapted to receive the drive signal; The control terminal of the fourth switch Q4 is adapted to receive the safety logic signal. The first terminal of the fourth switch Q4 is connected to the second terminal of the third switch Q3, and the second terminal of the fourth switch Q4 is grounded.

7. The drive-hold circuit according to claim 5 or 6, characterized in that, The third switch Q3 is a PNP transistor, and the fourth switch Q4 is an NPN transistor.

8. The drive-hold circuit according to claim 1, characterized in that, The drive holding circuit further includes a second diode D2, which is configured to regulate the drive signal so that the effective level of the drive signal output by the drive holding circuit matches the drive load.

9. An electronic device, characterized in that, The electronic device includes a drive-hold circuit as described in any one of claims 1 to 8.

10. A vehicle, characterized in that, The vehicle includes the electronic equipment as described in claim 9.

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