A chip terminal connector detection method, device, electronic equipment and system

Abstract

The application discloses a chip terminal connector detection method, device, electronic equipment and system, and belongs to the field of electronic testing. The application scheme covers two dimensions of physical connection and electrical performance through the method of visual detection, vibration simulation test, and impedance detection and DCT detection linkage, can effectively identify hidden defects such as poor connection, poor contact, and slight deviation, and achieves the technical effects of improving detection accuracy and reducing the after-sales failure rate. And through the vibration simulation test, the mechanical environment in the transportation and installation process before leaving the factory can be simulated, potential terminal loosening problems can be exposed in advance, and product reliability is improved.

Description

Technical Field

[0001] This application relates to the field of electronic testing technology, and in particular to a chip terminal connection detection method, apparatus, electronic device, and system. Background Technology

[0002] In chip packaging, the reliability of terminal connections directly affects the performance and lifespan of electronic products. Current technologies typically employ a single Direct Current Test (DCT) to assess electrical performance after terminal connection, lacking direct verification of the physical connection status and making it difficult to detect potential connection defects early on. Furthermore, in certain extreme cases, such as when a terminal is not fully inserted but has slight contact with the motherboard solder joint, the circuit may still conduct after power-on testing, and the DCT test cannot detect this anomaly, leading to missed detections. During transportation and installation, terminals may be affected by external factors such as vibration, causing their condition to change from poor connection to complete detachment, with these potential defects only becoming apparent after the product leaves the factory, increasing after-sales maintenance costs. Therefore, a comprehensive terminal connection defect detection method is urgently needed to improve the accuracy and comprehensiveness of the detection. Summary of the Invention

[0003] To overcome the shortcomings of the prior art, this application provides a chip terminal connection detection method, apparatus, electronic device and system to solve the problem that the existing technology usually uses a single DCT (Direct Current Test) test, which is difficult to meet the requirements of actual use.

[0004] The technical solution adopted by this application to solve its technical problem is: Firstly, a method for detecting chip terminal connection is provided, including: Vibration simulation test is performed on the chip under test, which is used to simulate the mechanical environment of the chip under test during transportation and installation. DCT testing is performed on the chip under test after vibration simulation testing.

[0005] As an optional implementation of this application, before performing vibration simulation testing on the chip to be tested, the following steps are also included: Perform visual inspection on the chip to be inspected; If the visual inspection results are satisfactory, a vibration simulation test is performed on the chip under test; if the visual inspection results are unsatisfactory, it is determined that the terminal connection is faulty.

[0006] As an optional implementation of this application, the chip to be inspected is subjected to visual inspection; Obtain an actual image of the terminal area of ​​the chip to be tested; The actual image is processed to obtain the actual terminal outline; The actual terminal profile is compared with a preset standard profile to obtain the profile offset, which includes a lateral deviation value in the X direction, a longitudinal deviation value in the Y direction, and an angular deviation value. If all contour offsets meet the corresponding requirements, the visual inspection result is deemed acceptable; if any contour offset does not meet the corresponding requirements, the visual inspection result is deemed unacceptable.

[0007] As an optional implementation of this application, the vibration simulation test on the chip to be tested includes: The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

[0008] As an optional implementation of this application, it also includes: Obtain transportation routes; Based on the curvature of each position along the transportation route, the centripetal force experienced by the chip under test at each position is determined. The direction and magnitude of the partial acceleration are determined based on the centripetal force.

[0009] As an optional implementation of this application, the step of performing DCT testing on the chip under test after vibration simulation testing includes: A preset DC current is applied to the terminals of the chip under test, and the voltage drop between the terminals is measured. If the voltage drop exceeds the preset voltage drop, a poor connection is determined; if the voltage drop does not exceed the preset voltage drop, an AC signal is applied to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal. If the resistance is greater than the preset resistance or the absolute value of the reactance is greater than the preset reactance value, the connection is determined to be faulty; if the resistance is less than or equal to the preset resistance or the absolute value of the reactance is less than or equal to the preset reactance value, the connection is determined to be normal.

[0010] As an optional implementation of this application, the step of applying an AC signal to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal includes: An AC signal of a preset magnitude is applied at a preset frequency, and the impedance between terminals is measured. The resistance and reactance of the terminal are obtained based on the impedance, where Z = R + jX, Z is the impedance, R is the resistance, and X is the reactance.

[0011] Secondly, a chip terminal insertion detection device is provided, comprising: The vibration simulation test module is used to perform vibration simulation tests on the chip under test, and the vibration simulation test is used to simulate the mechanical environment of the chip under test during transportation and installation. The DCT test module is used to perform DCT tests on the chip under test after vibration simulation testing.

[0012] Thirdly, an electronic device is provided, comprising: At least one processor and at least one memory; The memory stores the executable instructions of the processor; The processor is configured to perform the chip terminal connection detection method described in any of the preceding claims.

[0013] Fourthly, a chip terminal insertion detection system is provided, which applies the chip terminal insertion detection method described in any of the above claims.

[0014] Beneficial effects: This application provides a chip terminal connection detection method, apparatus, electronic device, and system. The chip terminal connection detection method includes: performing a vibration simulation test on the chip under test, wherein the vibration simulation test simulates the mechanical environment of the chip under test during transportation and installation; and performing a Direct Current Transmission (DCT) test on the chip under test after the vibration simulation test. This application effectively overcomes the limitations of a single electrical testing method by introducing a vibration simulation test before the DCT test. The vibration simulation test replicates the mechanical environment during transportation and installation, enabling early exposure of potential problems caused by poor physical connections such as improper terminal insertion or loose connections, especially critical defects that may still be barely conductive during static electrical testing. The subsequent DCT test accurately verifies the electrical performance after vibration. This combination of mechanical excitation followed by electrical testing significantly improves the early identification capability of poor connection, avoids post-shipment failures caused by terminal loosening due to vibration and other factors, thereby greatly improving the accuracy and comprehensiveness of the detection, reducing after-sales maintenance costs, and ensuring the long-term reliability of electronic products. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a chip terminal insertion detection method provided in an embodiment of this application; Figure 2This is a flowchart of a vibration simulation testing method provided in an embodiment of this application; Figure 3 This is a flowchart of a DCT testing method provided in an embodiment of this application; Figure 4 This is a flowchart of another chip terminal insertion detection method provided in the embodiments of this application; Figure 5 This is a flowchart of a visual inspection method provided in an embodiment of this application; Figure 6 This is a flowchart of a specific chip terminal insertion detection method provided in an embodiment of this application; Figure 7 This is a schematic diagram of a chip terminal insertion detection device provided in an embodiment of this application; Figure 8 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] It should be noted that in the field of electronics manufacturing, DCT test stands for Direct Current Test, which is an electrical test method used to evaluate the static DC parameters of electronic components, circuit boards, or semiconductor devices.

[0019] It primarily verifies whether a component meets design specifications by applying a precise DC voltage or current to a specific pin and measuring its response. The core of DCT testing is measuring static parameters, that is, the performance of the device under stable operating conditions (rather than during dynamic switching). Common test items include open / short circuit testing, leakage current, breakdown voltage, threshold voltage, and on-resistance.

[0020] This test is typically performed by a high-precision DC parameter tester or automated testing equipment. Its characteristics include high accuracy, good repeatability, and the ability to detect minute changes in electrical characteristics. In the wafer probing and finished product testing stages of integrated circuits, as well as in the power-on testing of PCB boards, DCT testing is a crucial step in ensuring product quality, screening for early failures, and conducting fault analysis. For example, CN115097284A provides a test device for motherboard standalone testing fixtures and DCT docking testing, including a test fixture base and at least one probe socket, control switch, and indicator light configured on the test fixture base. The probe socket is used to electrically connect to the test points of the motherboard under test. The probe socket is connected to the DCT test host via wires to transmit test signals. The control switch and indicator light are electrically connected to the DCT test host. It also includes an independent heat dissipation module, which is pressed onto the heat dissipation area of ​​the motherboard under test via a heat dissipation bracket. This invention adopts a completely new independent DCT docking motherboard testing and independent heat dissipation module, changing the original assembled heat dissipation and wiring-based testing to independent modular heat dissipation and testing, greatly reducing testing conditions, reducing the number of testing steps for employees, reducing operation time, and solving the safety problems of traditional test fixtures using terminal block mode, which involves high-voltage parts and poses a risk of electric shock during testing.

[0021] However, the inventors of this application have discovered in practice that existing testing methods can only guarantee passability during the test. In reality, due to poor contact or weak connections, the DCT test may be met during the test, but the terminals may break during transportation and installation. If testing is performed after transportation and installation, it becomes inconvenient. Even disregarding the testing issue, reinstallation is required after a test fails.

[0022] To address this issue, this application performs vibration simulation testing on the inserted chip. The specific implementation is shown in the following example: Example 1: Reference Figure 1 This application provides a chip terminal connection detection method, including: S11: Perform vibration simulation test on the chip under test, wherein the vibration simulation test is used to simulate the mechanical environment of the chip under test during transportation and installation; The vibration simulation test performed on the chip under test includes: The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

[0023] In one embodiment, the rate and acceleration are set directly based on experience. For example, the vibration frequency range is set to 5Hz~200Hz according to the ISTA-3A transport standard, the peak acceleration is 10g, and the duration is 30 minutes. A six-degree-of-freedom vibration table is used, and vibration excitations are applied in the X, Y, and Z directions respectively, with the vibration directions applied sequentially and cyclically, each direction vibrating for 10 minutes.

[0024] In another embodiment, the acceleration on a straight line is set according to a preset range. However, in actual operation, the chip will also experience centripetal force on curves in the road. That is, this embodiment uses actual forces to simulate the forces acting on the chip under test during actual transportation and installation. Because the above-mentioned testing method following a preset order does not match the actual situation, the magnitude and magnitude of the forces may be the same as in reality, but the order is different. Testing revealed that different force sequences in actual operation have different effects on the chip. Therefore, to ensure the test matches reality... Figure 2 As shown, this application also includes: S111: Obtain the transportation route; not only the origin and destination, but also the specific route. This is because there are multiple routes between some origins and destinations.

[0025] S112: Based on the curvature of each position along the transport route, determine the centripetal force acting on the chip under test at each position; S113: Determine the direction and magnitude of the partial acceleration based on the centripetal force.

[0026] Regarding the forces applied during the installation process, since the installation process is mostly automated, the order, magnitude, and direction of the forces are basically the same, and this application will not describe them in detail in the embodiments.

[0027] S12: Perform DCT test on the chip under test after vibration simulation test.

[0028] like Figure 3 As shown, the chip under test undergoes DCT testing after vibration simulation testing, including: S121: Apply a preset DC current to the terminals of the chip under test and measure the voltage drop between the terminals; S122: If the voltage drop exceeds the preset voltage drop, a poor connection is determined; if the voltage drop does not exceed the preset voltage drop, an AC signal is applied to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal. S123: If the resistance is greater than the preset resistance or the absolute value of the reactance is greater than the preset reactance value, the connection is determined to be faulty; if the resistance is less than or equal to the preset resistance or the absolute value of the reactance is less than or equal to the preset reactance value, the connection is determined to be normal.

[0029] The step of applying an AC signal to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal includes: An AC signal of a preset magnitude is applied at a preset frequency, and the impedance between terminals is measured. The resistance and reactance of the terminal are obtained based on the impedance, where Z = R + jX, Z is the impedance, R is the resistance, and X is the reactance.

[0030] The chip terminal connection detection method provided in this application first performs a vibration simulation test on the chip under test. This vibration simulation test simulates the mechanical environment of the chip under test during transportation and installation. Then, a Direct Current Transmission (DCT) test is performed on the chip under test after the vibration simulation test. This application's solution effectively overcomes the limitations of a single electrical testing method by introducing a vibration simulation test before the DCT test. The vibration simulation test replicates the mechanical environment during transportation and installation, enabling early exposure of potential problems caused by poor physical connections such as improper terminal insertion or loose connections, especially critical defects that may still be barely conductive during static electrical testing. The subsequent DCT test accurately verifies the electrical performance after vibration. This combination of mechanical excitation followed by electrical testing significantly improves the early identification capability of poor connection, avoids post-shipment failures caused by terminal loosening due to vibration and other factors, thereby greatly improving the accuracy and comprehensiveness of the test, reducing after-sales maintenance costs, and ensuring the long-term reliability of electronic products.

[0031] Example 2: Reference Figure 4 This application provides another method for detecting chip terminal connection, including: S21: Perform visual inspection on the chip to be inspected; like Figure 5 As shown, the chip to be inspected undergoes visual inspection; S211: Obtain an actual image of the terminal area of ​​the chip to be tested; S212: Process the actual image to obtain the actual terminal outline; S213: The actual terminal profile is compared with the preset standard profile to obtain the profile offset. The profile offset includes a lateral deviation value in the X direction, a longitudinal deviation value in the Y direction, and an angular deviation value. The angular deviation value is obtained by the angle between the actual terminal profile and the preset standard profile along the same line, such as the angle between the leftmost line of the actual terminal profile and the leftmost line of the preset standard profile, or the angle between the center lines of the actual terminal profile and the preset standard profile.

[0032] S214: If all contour offsets meet the corresponding requirements, the visual inspection result is deemed qualified; if any contour offset does not meet the corresponding requirements, the visual inspection result is deemed unqualified.

[0033] S22: When the visual inspection result is qualified, a vibration simulation test is performed on the chip to be tested. The vibration simulation test is used to simulate the mechanical environment of the chip to be tested during transportation and installation. The vibration simulation test performed on the chip under test includes: The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

[0034] In one embodiment, the rate and acceleration are set directly based on experience. For example, the vibration frequency range is set to 5Hz~200Hz according to the ISTA-3A transport standard, the peak acceleration is 10g, and the duration is 30 minutes. A six-degree-of-freedom vibration table is used, and vibration excitations are applied in the X, Y, and Z directions respectively, with the vibration directions applied sequentially and cyclically, each direction vibrating for 10 minutes.

[0035] In another embodiment, the acceleration on a straight line is set according to a preset range. However, in actual operation, the chip will also experience centripetal force on curves in the road. That is, this embodiment uses actual forces to simulate the forces acting on the chip under test during actual transportation and installation. Because the above-mentioned testing method following a preset order does not match the actual situation, the magnitude and magnitude of the forces may be the same as in reality, but the order is different. Testing revealed that different force sequences in actual operation have different effects on the chip. Therefore, to ensure that the test matches reality, this application also includes: Obtain transportation routes; this requires not only obtaining the origin and destination, but also the specific routes. This is because there are often multiple routes between the origin and destination.

[0036] Based on the curvature of each position along the transportation route, the centripetal force experienced by the chip under test at each position is determined. The direction and magnitude of the partial acceleration are determined based on the centripetal force.

[0037] Regarding the forces applied during the installation process, since the installation process is mostly automated, the order, magnitude, and direction of the forces are basically the same, and this application will not describe them in detail in the embodiments.

[0038] S23: Perform DCT testing on the chip under test after vibration simulation testing.

[0039] DCT testing is performed on the chip under test after vibration simulation testing, including: A preset DC current is applied to the terminals of the chip under test, and the voltage drop between the terminals is measured. If the voltage drop exceeds the preset voltage drop, a poor connection is determined; if the voltage drop does not exceed the preset voltage drop, an AC signal is applied to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal. If the resistance is greater than the preset resistance or the absolute value of the reactance is greater than the preset reactance value, the connection is determined to be faulty; if the resistance is less than or equal to the preset resistance or the absolute value of the reactance is less than or equal to the preset reactance value, the connection is determined to be normal.

[0040] The step of applying an AC signal to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal includes: An AC signal of a preset magnitude is applied at a preset frequency, and the impedance between terminals is measured. The resistance and reactance of the terminal are obtained based on the impedance, where Z = R + jX, Z is the impedance, R is the resistance, and X is the reactance.

[0041] The chip terminal connection detection method provided in this application first performs visual inspection on the chip under test. After the visual inspection result is qualified, a vibration simulation test is performed on the chip under test. The vibration simulation test is used to simulate the mechanical environment of the chip under test during transportation and installation. A DCT test is then performed on the chip under test after the vibration simulation test. This application's solution effectively compensates for the limitations of a single electrical testing method by introducing a vibration simulation test before the DCT test. The vibration simulation test reproduces the mechanical environment during transportation and installation, and can expose potential problems caused by poor physical connections such as improper terminal insertion or loose connections in advance, especially those critical defects that can still barely conduct during static electrical testing. The subsequent DCT test accurately verifies the electrical performance after vibration. This combination of mechanical excitation followed by electrical testing significantly improves the early identification capability of poor connection, avoids post-shipment failure caused by terminal loosening due to vibration and other factors, thereby greatly improving the accuracy and comprehensiveness of the test, reducing after-sales maintenance costs, and ensuring the long-term reliability of electronic products.

[0042] Example 3: Reference Figure 6 This application provides a specific method for detecting chip terminal insertion, and the core inventive points specifically include the following technical elements: 1. Use visual inspection to determine whether the terminals are properly connected; 2. Simulate the mechanical environment during transportation and installation through vibration testing; 3. Test whether the terminals can pass the DCT test to verify their electrical performance; 4. Perform a secondary confirmation of the physical connection status using terminal impedance testing methods; 5. Multiple detection methods work together to form a closed-loop detection process, improving the comprehensiveness and reliability of detection.

[0043] Specifically, the following steps are included: 1. Visual Inspection Stage: After the terminal insertion operation is completed, a high-resolution industrial camera is used to acquire images of the terminal insertion area. Image recognition algorithms are used to analyze whether the terminal is fully inserted and whether there is any offset or tilting, to preliminarily determine whether the insertion status is qualified.

[0044] (1) Image acquisition: Using an industrial camera with a resolution of 0.02mm / pixel, and a ring LED light source, the terminal area is photographed from multiple angles (0°, 45°, 90°) to obtain RGB color images.

[0045] (2) Image preprocessing: Gaussian filtering is used to denoise the image, and the Canny edge detection algorithm is used to extract the edge contour of the terminal.

[0046] (3) Three-dimensional position matching: Based on the template matching algorithm, the actual terminal contour is compared with the standard template, and the contour offsets Δx, Δy, and Δθ are calculated to determine whether they exceed the preset tolerance range (e.g., Δx ≤ 0.05mm, Δy ≤ 0.05mm, Δθ ≤ 1.5°). Here, Δx, Δy, and Δθ represent the differences in the x-direction, y-direction, and line segment angle θ between the terminal contour obtained after contact and the standard contour of the well-fitted sample, respectively, on any point on the continuous contour.

[0047] (4) Judgment criteria: If any offset exceeds the tolerance range, it is determined that the connection is not in place and an alarm is triggered; otherwise, proceed to the next stage.

[0048] 2. Vibration simulation test stage: Place the chip under test on the vibration test platform and simulate the environment that may be encountered during transportation and installation according to the preset vibration frequency and acceleration.

[0049] (1) Vibration parameter setting: The vibration frequency range is set to 5Hz~200Hz, the peak acceleration is 10g, and the duration is 30 minutes, according to the ISTA-3A transportation standard.

[0050] (2) Multi-axis vibration test: A six-degree-of-freedom vibration table was used to apply vibration excitation in the X, Y and Z directions respectively. The vibration directions were applied in sequence and cycled, with each direction vibrating for 10 minutes.

[0051] The vibration direction is X→Y→Z, or when the transportation route is known, the sequence and magnitude are determined based on the actual route, and random interference is added near each intersection and curve.

[0052] 3. DCT test stage: The chip that has passed the vibration test is subjected to DCT (Direct Current Test) test to detect the current conduction between the terminals and verify whether its basic electrical performance meets the requirements.

[0053] (1) Test procedure: Apply a 100mA DC current to the terminals and measure the voltage drop between the terminals.

[0054] (2) Judgment criteria: If the voltage drop exceeds 10mV, the contact resistance is abnormal and there is a poor connection.

[0055] 4. Impedance Detection Stage: An AC signal is applied to the terminal connection area using an impedance measuring device to measure its contact impedance value. By setting an impedance threshold, it is determined whether poor contact is caused by oxidation, insufficient contact area, or uneven pressure, thus achieving a secondary confirmation of the terminal connection status.

[0056] (1) Measurement procedure: Apply a 1Vrms AC signal at a frequency of 1kHz and measure the complex impedance Z between the terminals (Note: Z = R + jX, where R is the resistance part and X is the reactance part).

[0057] (2) Judgment criteria: Under normal connection conditions, R should be less than 0.1Ω and X should be close to 0. If R > 0.1Ω or |X| > 0.02Ω, it is judged as poor contact.

[0058] 5. Judgment and Feedback: The test results of the above stages are integrated and analyzed. If any stage fails the test, the terminal is judged to be faulty and an alarm or automatic rework process is triggered.

[0059] This application solution utilizes a combination of visual inspection, vibration simulation testing, and impedance testing with DCT testing to cover both physical connection and electrical performance dimensions in terminal connection status detection. This effectively identifies latent defects such as improper connection, poor contact, and minor misalignment, thereby improving detection accuracy and reducing after-sales failure rates. Furthermore, vibration simulation testing can simulate the mechanical environment during transportation and installation before shipment, revealing potential terminal loosening issues in advance and enhancing product reliability.

[0060] It should be noted that any process or method description in the flowchart or otherwise described herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which the embodiments of this application pertain.

[0061] Furthermore, in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0062] Example 4: Reference Figure 7 This application provides a chip terminal insertion detection device, comprising: The visual inspection module 71 is used to perform visual inspection on the chip to be inspected; The chip to be inspected is subjected to visual inspection. Obtain an actual image of the terminal area of ​​the chip to be tested; The actual image is processed to obtain the actual terminal outline; The actual terminal profile is compared with a preset standard profile to obtain the profile offset, which includes a lateral deviation value in the X direction, a longitudinal deviation value in the Y direction, and an angular deviation value. If all contour offsets meet the corresponding requirements, the visual inspection result is deemed acceptable; if any contour offset does not meet the corresponding requirements, the visual inspection result is deemed unacceptable.

[0063] For example, after the terminal insertion operation is completed, a high-resolution industrial camera is used to acquire images of the terminal insertion area. Image recognition algorithms are then used to analyze whether the terminal is fully inserted and whether there is any offset or tilting, thus making a preliminary judgment on whether the insertion status is acceptable.

[0064] (1) Image acquisition: Using an industrial camera with a resolution of 0.02mm / pixel, and a ring LED light source, the terminal area is photographed from multiple angles (0°, 45°, 90°) to obtain RGB color images.

[0065] (2) Image preprocessing: Gaussian filtering is used to denoise the image, and the Canny edge detection algorithm is used to extract the edge contour of the terminal.

[0066] (3) Three-dimensional position matching: Based on the template matching algorithm, the actual terminal contour is compared with the standard template, and the contour offsets Δx, Δy, and Δθ are calculated to determine whether they exceed the preset tolerance range (e.g., Δx ≤ 0.05mm, Δy ≤ 0.05mm, Δθ ≤ 1.5°). Δx, Δy, and Δθ represent the differences in the x-direction, y-direction, and line segment angle θ between the terminal contour obtained after contact and the standard contour of the well-fitted sample, respectively.

[0067] (4) Judgment criteria: If the offset exceeds the tolerance range, it is determined that the connection is not in place and an alarm is triggered; otherwise, proceed to the next stage.

[0068] The vibration simulation test module 72 is used to perform vibration simulation test on the chip under test when the visual inspection result is qualified. The vibration simulation test is used to simulate the mechanical environment of the chip under test during transportation and installation. As a preferred implementation of this application, the vibration simulation test on the chip to be tested includes: The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

[0069] The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

[0070] Also includes: Obtain transportation routes; Based on the curvature of each position along the transportation route, the centripetal force experienced by the chip under test at each position is determined. The direction and magnitude of the partial acceleration are determined based on the centripetal force.

[0071] It should be noted that if the visual inspection results are unsatisfactory, it indicates that the terminal connection is faulty.

[0072] Alternatively, the chip to be tested can be placed on a vibration test platform, and the environment that may be encountered during transportation and installation can be simulated according to the preset vibration frequency and acceleration.

[0073] (1) Vibration parameter setting: The vibration frequency range is set to 5Hz~200Hz, the peak acceleration is 10g, and the duration is 30 minutes, according to the ISTA-3A transportation standard.

[0074] (2) Multi-axis vibration test: A six-degree-of-freedom vibration table was used to apply vibration excitation in the X, Y and Z directions respectively. The vibration directions were applied in sequence and cycled, with each direction vibrating for 10 minutes.

[0075] DCT test module 73 is used to perform DCT test on the chip under test after vibration simulation test.

[0076] The DCT test performed on the chip under test after vibration simulation testing includes: A preset DC current is applied to the terminals of the chip under test, and the voltage drop between the terminals is measured. If the voltage drop exceeds the preset voltage drop, a poor connection is determined; if the voltage drop does not exceed the preset voltage drop, an AC signal is applied to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal. If the resistance is greater than the preset resistance or the absolute value of the reactance is greater than the preset reactance value, the connection is determined to be faulty; if the resistance is less than or equal to the preset resistance or the absolute value of the reactance is less than or equal to the preset reactance value, the connection is determined to be normal.

[0077] The method of applying an AC signal to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal includes: An AC signal of a preset magnitude is applied at a preset frequency, and the impedance between terminals is measured. The resistance and reactance of the terminal are obtained based on the impedance, where Z = R + jX, Z is the impedance, R is the resistance, and X is the reactance.

[0078] For example, a DCT (Direct Current Test) is performed on a chip that has passed the vibration test to detect the current conduction between the terminals and verify whether its basic electrical performance meets the requirements.

[0079] (1) Test procedure: Apply a 100mA DC current to the terminals and measure the voltage drop between the terminals.

[0080] (2) Judgment criteria: If the voltage drop exceeds 10mV, the contact resistance is abnormal and there is a poor connection.

[0081] An impedance measuring device is used to apply an AC signal to the terminal connection point and measure its contact impedance value. By setting an impedance threshold, it is determined whether the terminal has poor contact due to oxidation, insufficient contact area, or uneven pressure, thereby achieving a secondary confirmation of the terminal connection status.

[0082] (1) Measurement procedure: Apply a 1Vrms AC signal at a frequency of 1kHz and measure the complex impedance Z between the terminals (Note: Z = R + jX, where R is the resistance part and X is the reactance part).

[0083] (2) Judgment criteria: Under normal connection conditions, R should be less than 0.1Ω and X should be close to 0. If R > 0.1Ω or |X| > 0.02Ω, it is judged as poor contact.

[0084] Finally, the test results of each stage are integrated and analyzed. If any stage fails the test, the terminal is determined to be faulty and an alarm or automatic rework process is triggered.

[0085] The chip terminal insertion testing device provided in this application first performs visual inspection on the chip to be tested. After the visual inspection result is qualified, a vibration simulation test is performed on the chip to be tested. The vibration simulation test is used to simulate the mechanical environment of the chip to be tested during transportation and installation. After the vibration simulation test, a DCT test is performed on the chip to be tested. This application solution effectively makes up for the limitations of a single electrical testing method by introducing a vibration simulation test before the DCT test. The vibration simulation test reproduces the mechanical environment during transportation and installation, and can expose potential hidden dangers caused by poor physical connections such as improper terminal insertion or loose connection in advance, especially those critical defects that can still barely conduct during static electrical testing. The subsequent DCT test accurately verifies the electrical performance after vibration. This combination of mechanical excitation followed by electrical testing significantly improves the early identification capability of poor insertion, avoids post-shipment failure caused by terminal loosening due to vibration and other factors, thereby greatly improving the accuracy and comprehensiveness of testing, reducing after-sales maintenance costs, and ensuring the long-term reliability of electronic products.

[0086] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the chip terminal insertion detection method provided in any of the above embodiments.

[0087] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0088] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0089] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0090] The storage media mentioned above can be read-only memory, disk, or optical disk, etc.

[0091] The computer-readable storage medium provided in this application embodiment stores a computer program, which, when executed by a processor, implements the steps of the chip terminal insertion detection method provided in any of the above embodiments. First, the chip to be tested undergoes visual inspection. After the visual inspection result is satisfactory, a vibration simulation test is performed on the chip to be tested. This vibration simulation test simulates the mechanical environment of the chip to be tested during transportation and installation. A DCT test is then performed on the chip to be tested after the vibration simulation test. This application solution effectively overcomes the limitations of a single electrical testing method by introducing a vibration simulation test before the DCT test. The vibration simulation test reproduces the mechanical environment during transportation and installation, and can expose potential problems caused by poor physical connections such as improper terminal insertion or loose connections, especially critical defects that may still be barely conductive during static electrical testing. The subsequent DCT test accurately verifies the electrical performance after vibration. This combination of mechanical excitation followed by electrical testing significantly improves the early identification capability of poor insertion, avoids post-shipment failures caused by terminal loosening due to vibration and other factors, thereby greatly improving the accuracy and comprehensiveness of the test, reducing after-sales maintenance costs, and ensuring the long-term reliability of electronic products.

[0092] Based on the same inventive concept, such as Figure 8 As shown, this application also provides an electronic device 80, comprising: At least one processor 81 and at least one memory 82; The memory stores the executable instructions of the processor; The processor is configured to perform the chip terminal insertion detection method provided in the above embodiments.

[0093] The electronic device provided in this application stores executable instructions of the processor in a memory. When these executable instructions are executed, the processor first performs visual inspection on the chip to be tested. After the visual inspection result is qualified, a vibration simulation test is performed on the chip to be tested. The vibration simulation test is used to simulate the mechanical environment of the chip to be tested during transportation and installation. A DCT test is then performed on the chip to be tested after the vibration simulation test. This application's solution effectively compensates for the limitations of a single electrical testing method by introducing a vibration simulation test before the DCT test. The vibration simulation test reproduces the mechanical environment during transportation and installation, and can expose potential hazards caused by poor physical connections such as improper terminal insertion or loose connections in advance, especially those critical defects that can still barely conduct during static electrical testing. The subsequent DCT test accurately verifies the electrical performance after vibration. This combination of mechanical excitation followed by electrical testing significantly improves the early identification capability of poor insertion, avoids post-shipment failure caused by terminal loosening due to vibration and other factors, thereby greatly improving the accuracy and comprehensiveness of testing, reducing after-sales maintenance costs, and ensuring the long-term reliability of electronic products.

[0094] Based on the same inventive concept, this application provides a chip terminal connection detection system, which applies the following chip terminal connection detection method: Step 1: Perform visual inspection on the chip to be inspected; The chip to be inspected is subjected to visual inspection. Obtain an actual image of the terminal area of ​​the chip to be tested; The actual image is processed to obtain the actual terminal outline; The actual terminal profile is compared with a preset standard profile to obtain the profile offset, which includes a lateral deviation value in the X direction, a longitudinal deviation value in the Y direction, and an angular deviation value. If all contour offsets meet the corresponding requirements, the visual inspection result is deemed acceptable; if any contour offset does not meet the corresponding requirements, the visual inspection result is deemed unacceptable.

[0095] For example, after the terminal insertion operation is completed, a high-resolution industrial camera is used to acquire images of the terminal insertion area. Image recognition algorithms are then used to analyze whether the terminal is fully inserted and whether there is any offset or tilting, thus making a preliminary judgment on whether the insertion status is acceptable.

[0096] (1) Image acquisition: Using an industrial camera with a resolution of 0.02mm / pixel, and a ring LED light source, the terminal area is photographed from multiple angles (0°, 45°, 90°) to obtain RGB color images.

[0097] (2) Image preprocessing: Gaussian filtering is used to denoise the image, and the Canny edge detection algorithm is used to extract the edge contour of the terminal.

[0098] (3) Three-dimensional position matching: Based on the template matching algorithm, the actual terminal contour is compared with the standard template, and the contour offsets Δx, Δy, and Δθ are calculated to determine whether they exceed the preset tolerance range (e.g., Δx ≤ 0.05mm, Δy ≤ 0.05mm, Δθ ≤ 1.5°). Δx, Δy, and Δθ represent the differences in the x-direction, y-direction, and line segment angle θ between the terminal contour obtained after contact and the standard contour of the well-fitted sample, respectively.

[0099] (4) Judgment criteria: If the offset exceeds the tolerance range, it is determined that the connection is not in place and an alarm is triggered; otherwise, proceed to the next stage.

[0100] Step 2: When the visual inspection result is qualified, a vibration simulation test is performed on the chip to be tested. The vibration simulation test is used to simulate the mechanical environment of the chip to be tested during transportation and installation. As a preferred implementation of this application, the vibration simulation test on the chip to be tested includes: The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

[0101] The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

[0102] Also includes: Obtain transportation routes; Based on the curvature of each position along the transportation route, the centripetal force experienced by the chip under test at each position is determined. The direction and magnitude of the partial acceleration are determined based on the centripetal force.

[0103] It should be noted that if the visual inspection results are unsatisfactory, it indicates that the terminal connection is faulty.

[0104] Alternatively, the chip to be tested can be placed on a vibration test platform, and the environment that may be encountered during transportation and installation can be simulated according to the preset vibration frequency and acceleration.

[0105] (1) Vibration parameter setting: The vibration frequency range is set to 5Hz~200Hz, the peak acceleration is 10g, and the duration is 30 minutes, according to the ISTA-3A transportation standard.

[0106] (2) Multi-axis vibration test: A six-degree-of-freedom vibration table was used to apply vibration excitation in the X, Y and Z directions respectively. The vibration directions were applied in sequence and cycled, with each direction vibrating for 10 minutes.

[0107] Step 3: Perform DCT testing on the chip under test after vibration simulation testing.

[0108] The DCT test performed on the chip under test after vibration simulation testing includes: A preset DC current is applied to the terminals of the chip under test, and the voltage drop between the terminals is measured. If the voltage drop exceeds the preset voltage drop, a poor connection is determined; if the voltage drop does not exceed the preset voltage drop, an AC signal is applied to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal. If the resistance is greater than the preset resistance or the absolute value of the reactance is greater than the preset reactance value, the connection is determined to be faulty; if the resistance is less than or equal to the preset resistance or the absolute value of the reactance is less than or equal to the preset reactance value, the connection is determined to be normal.

[0109] The method of applying an AC signal to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal includes: An AC signal of a preset magnitude is applied at a preset frequency, and the impedance between terminals is measured. The resistance and reactance of the terminal are obtained based on the impedance, where Z = R + jX, Z is the impedance, R is the resistance, and X is the reactance.

[0110] For example, a DCT (Direct Current Test) is performed on a chip that has passed the vibration test to detect the current conduction between the terminals and verify whether its basic electrical performance meets the requirements.

[0111] (1) Test procedure: Apply a 100mA DC current to the terminals and measure the voltage drop between the terminals.

[0112] (2) Judgment criteria: If the voltage drop exceeds 10mV, the contact resistance is abnormal and there is a poor connection.

[0113] An impedance measuring device is used to apply an AC signal to the terminal connection point and measure its contact impedance value. By setting an impedance threshold, it is determined whether the terminal has poor contact due to oxidation, insufficient contact area, or uneven pressure, thereby achieving a secondary confirmation of the terminal connection status.

[0114] (1) Measurement procedure: Apply a 1Vrms AC signal at a frequency of 1kHz and measure the complex impedance Z between the terminals (Note: Z = R + jX, where R is the resistance part and X is the reactance part).

[0115] (2) Judgment criteria: Under normal connection conditions, R should be less than 0.1Ω and X should be close to 0. If R > 0.1Ω or |X| > 0.02Ω, it is judged as poor contact.

[0116] Finally, the test results of each stage are integrated and analyzed. If any stage fails the test, the terminal is determined to be faulty and an alarm or automatic rework process is triggered.

[0117] The chip terminal insertion testing system provided in this application first performs visual inspection on the chip under test. After the visual inspection result is qualified, a vibration simulation test is performed on the chip under test. The vibration simulation test is used to simulate the mechanical environment of the chip under test during transportation and installation. A DCT test is then performed on the chip under test after the vibration simulation test. This application's solution effectively compensates for the limitations of a single electrical testing method by introducing a vibration simulation test before the DCT test. The vibration simulation test reproduces the mechanical environment during transportation and installation, and can expose potential problems caused by poor physical connections such as improper terminal insertion or loose connections in advance, especially those critical defects that can still barely conduct during static electrical testing. The subsequent DCT test accurately verifies the electrical performance after vibration. This combination of mechanical excitation followed by electrical testing significantly improves the early identification capability of poor insertion, avoids post-shipment failures caused by terminal loosening due to vibration and other factors, thereby greatly improving the accuracy and comprehensiveness of the test, reducing after-sales maintenance costs, and ensuring the long-term reliability of electronic products.

[0118] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0119] It should be noted that in the description of this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means at least two.

[0120] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for detecting chip terminal insertion, characterized in that, include: Vibration simulation test is performed on the chip under test, which is used to simulate the mechanical environment of the chip under test during transportation and installation. DCT testing is performed on the chip under test after vibration simulation testing.

2. The method according to claim 1, characterized in that: Before performing vibration simulation testing on the chip under test, the following steps are also included: Perform visual inspection on the chip to be inspected; If the visual inspection results are satisfactory, a vibration simulation test is performed on the chip under test; if the visual inspection results are unsatisfactory, it is determined that the terminal connection is faulty.

3. The method according to claim 2, characterized in that: The chip to be inspected is subjected to visual inspection; Obtain an actual image of the terminal area of ​​the chip to be tested; The actual image is processed to obtain the actual terminal outline; The actual terminal profile is compared with a preset standard profile to obtain the profile offset, which includes a lateral deviation value in the X direction, a longitudinal deviation value in the Y direction, and an angular deviation value. If all contour offsets meet the corresponding requirements, the visual inspection result is deemed acceptable; if any contour offset does not meet the corresponding requirements, the visual inspection result is deemed unacceptable.

4. The method according to claim 1, characterized in that: The vibration simulation test performed on the chip under test includes: The chip to be tested is placed on a vibration test platform, and vibration during transportation and installation is simulated according to a preset rate and acceleration.

5. The method according to claim 4, characterized in that, Also includes: Obtain transportation routes; Based on the curvature of each position along the transportation route, the centripetal force experienced by the chip under test at each position is determined. The direction and magnitude of the partial acceleration are determined based on the centripetal force.

6. The method according to claim 1, characterized in that: The DCT test performed on the chip under test after vibration simulation testing includes: A preset DC current is applied to the terminals of the chip under test, and the voltage drop between the terminals is measured. If the voltage drop exceeds the preset voltage drop, a poor connection is determined; if the voltage drop does not exceed the preset voltage drop, an AC signal is applied to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal. If the resistance is greater than the preset resistance or the absolute value of the reactance is greater than the preset reactance value, the connection is determined to be faulty; if the resistance is less than or equal to the preset resistance or the absolute value of the reactance is less than or equal to the preset reactance value, the connection is determined to be normal.

7. The method according to claim 6, characterized in that: The method of applying an AC signal to the terminal connection using an impedance measuring device to measure the resistance and reactance of the terminal includes: An AC signal of a preset magnitude is applied at a preset frequency, and the impedance between terminals is measured. The resistance and reactance of the terminal are obtained based on the impedance, where Z = R + jX, Z is the impedance, R is the resistance, and X is the reactance.

8. A chip terminal insertion detection device, characterized in that, include: The vibration simulation test module is used to perform vibration simulation tests on the chip under test, and the vibration simulation test is used to simulate the mechanical environment of the chip under test during transportation and installation. The DCT test module is used to perform DCT tests on the chip under test after vibration simulation testing.

9. An electronic device, characterized in that, include: At least one processor and at least one memory; The memory stores the executable instructions of the processor; The processor is configured to perform the method according to any one of claims 1-7.

10. A chip terminal insertion detection system, characterized in that: The method described in any one of claims 1-7.

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