Semiconductor memory device and memory system including the same

Abstract

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes memory cells, local bit lines, global bit lines, word lines, control lines, local bit line multiplexers, and first and second control contacts. The memory cells are arranged along a first direction, a second direction, and a third direction. Each local bit line extends along the first direction and is shared by the memory cells adjacent to a first side and a second side of each local bit line. The global bit lines are disposed on the local bit lines. The control lines are disposed on the word lines. Each word line and each control line extends along the third direction. The local bit line multiplexers control electrical connections between the local bit lines and the global bit lines. At least two of the local bit line multiplexers share one of the control lines. The first and second control contacts are connected to first and second ends of the control lines, respectively. Each of the first and second control contacts extends along the first direction.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0183405, filed on December 11, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically to three-dimensional (3D) semiconductor memory devices and memory systems including 3D semiconductor memory devices. Background Technology

[0003] The demand / expectation for miniaturization, multifunctionality, and / or high performance in electronic products has led to a demand for high-capacity semiconductor memory devices. To provide high-capacity semiconductor memory devices, increased integration is required / desired. Since the integration density of existing two-dimensional (2D) semiconductor memory devices is primarily determined by the area occupied by a single memory cell, its improvement has been limited. Therefore, three-dimensional (3D) semiconductor memory devices have been proposed to increase memory capacity by stacking multiple memory cells vertically on a substrate. Summary of the Invention

[0004] Various exemplary embodiments of this disclosure provide a semiconductor memory device capable of having improved electrical characteristics and reliability.

[0005] Various exemplary embodiments of this disclosure provide a memory system including a semiconductor memory device.

[0006] According to an example embodiment, a semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of control lines, a plurality of local bit line multiplexers, a plurality of first control contacts, and a plurality of second control contacts. The plurality of memory cells are disposed on a substrate and arranged along a first direction, a second direction, and a third direction. The first direction is perpendicular to the upper surface of the substrate. The second direction and the third direction are parallel to the upper surface of the substrate and intersect each other. The plurality of local bit lines are disposed on the substrate and connected to the plurality of memory cells. Each of the plurality of local bit lines extends along the first direction and is shared by memory cells adjacent to a first side and a second side of each of the plurality of local bit lines. The plurality of global bit lines are disposed on the plurality of local bit lines. The plurality of word lines are disposed on the substrate and connected to the plurality of memory cells. Each of the plurality of word lines extends along a third direction. The plurality of control lines are disposed on the plurality of word lines. Each of the plurality of control lines extends along a third direction. Multiple local bit line multiplexers control the electrical connections between multiple local bit lines and multiple global bit lines. At least two of the multiple local bit line multiplexers share one of the multiple control lines. Multiple first control contacts are connected to first ends of the multiple control lines. Each of the multiple first control contacts extends along a first direction. Multiple second control contacts are connected to second ends of the multiple control lines. Each of the multiple second control contacts extends along the first direction.

[0007] According to an example embodiment, a semiconductor memory device includes local bit lines, first memory cells, second memory cells, first word lines, second word lines, global bit lines, first control lines, select transistors, first control contacts, and second control contacts. The local bit lines are disposed on a substrate. Each of the local bit lines extends along a first direction perpendicular to the upper surface of the substrate. The local bit lines are spaced apart from each other in a third direction (a second direction and a third direction). The second direction and the third direction are parallel to the upper surface of the substrate and intersect each other. The first memory cell is disposed on the substrate, connected to the local bit lines, and arranged along the first direction and the third direction adjacent to a first side of the local bit lines. The second memory cell is disposed on the substrate, connected to the local bit lines, and arranged along the first direction and the third direction adjacent to a second side of the local bit lines. The first word lines are disposed on the substrate and arranged along the first direction. Each of the first word lines extends along the third direction and connects to a memory cell at the same level in the first memory cell. The second word lines are disposed on the substrate and arranged along the first direction. Each of the second word lines extends along the third direction and connects to a memory cell at the same level in the second memory cell. Each global bit line is selectively connected to one local bit line. A first control line is disposed on the first word line and extends along a third direction. A select transistor controls the electrical connection between the local bit lines and the global bit lines. The first control line is shared by the select transistor. A first control contact and a second control contact are respectively connected to a first end and a second end of the first control line. Each of the first and second control contacts extends along a first direction.

[0008] According to an example embodiment, a memory system includes a memory controller and a semiconductor memory device configured to be controlled by the memory controller. The semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of control lines, a plurality of local bit line multiplexers, a plurality of first control contacts, and a plurality of second control contacts. The plurality of memory cells are disposed on a substrate and arranged along a first direction, a second direction, and a third direction. The first direction is perpendicular to the upper surface of the substrate. The second direction and the third direction are parallel to the upper surface of the substrate and intersect each other. The plurality of local bit lines are disposed on the substrate and connected to the plurality of memory cells. Each of the plurality of local bit lines extends along the first direction and is shared by memory cells adjacent to a first side and a second side of each of the plurality of local bit lines. The plurality of global bit lines are disposed on the plurality of local bit lines. The plurality of word lines are disposed on the substrate and connected to the plurality of memory cells. Each of the plurality of word lines extends along a third direction. The plurality of control lines are disposed on the plurality of word lines. Each of the multiple control lines extends along a third direction. Multiple local bit line multiplexers control the electrical connections between the multiple local bit lines and the multiple global bit lines. At least two of the multiple local bit line multiplexers share one of the multiple control lines. Multiple first control contacts are connected to a first end of the multiple control lines. Each of the multiple first control contacts extends along a first direction. Multiple second control contacts are connected to a second end of the multiple control lines. Each of the multiple second control contacts extends along a first direction.

[0009] In the semiconductor memory device and memory system according to the example embodiments, adjacent memory cells can share local bit lines. Furthermore, a local bit line multiplexer controlling the electrical connection between the local bit lines and global bit lines can be provided on each local bit line, and the structure at the topmost level of the memory cell array can serve as a local bit line multiplexer. Further, two control contacts for signal application can be provided at both ends of a control line connected to the local bit line multiplexer. Therefore, the semiconductor memory device can have improved electrical characteristics and improved reliability.

[0010] For example, local bit lines and global bit lines can be selectively connected and disconnected using a local bit line multiplexer, thereby reducing bit line capacitance and increasing sensing margin. Furthermore, the signals used to turn the local bit line multiplexer on and off can be applied to the control line using two control contacts, which can reduce the delay time when the local bit line multiplexer is turned on / off and improve operational performance. Attached Figure Description

[0011] The illustrative, non-limiting exemplary embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a perspective view of a semiconductor memory device according to an example embodiment.

[0013] Figure 2 This illustrates an example embodiment. Figure 1 Circuit diagram of a semiconductor memory device.

[0014] Figure 3 and Figure 4 These are perspective and plan views used to describe a semiconductor memory device according to an example embodiment.

[0015] Figure 5 , Figure 6 , Figure 7 and Figure 8 It is used to describe according to the example embodiments Figure 3 and Figure 4 A cross-sectional view of a semiconductor memory device.

[0016] Figure 9A and Figure 9B This is a diagram used to describe the operation of a semiconductor memory device according to an example embodiment.

[0017] Figure 10 and Figure 11 It is used to describe according to the example embodiments Figure 3 and Figure 4 A cross-sectional view of a semiconductor memory device.

[0018] Figure 12 , Figure 13 , Figure 14 and Figure 15 These are perspective and plan views used to describe a semiconductor memory device according to an example embodiment.

[0019] Figure 16 This is a perspective view of a semiconductor memory device according to an example embodiment.

[0020] Figure 17 and Figure 18 These are perspective and cross-sectional views of a semiconductor memory device according to an example embodiment.

[0021] Figure 19 This illustrates an example embodiment. Figure 16 and Figure 17 Circuit diagram of a semiconductor memory device.

[0022] Figure 20 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0023] Figure 21This is a block diagram illustrating a memory system according to an example embodiment. Detailed Implementation

[0024] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments described herein. Throughout this application, the same reference numerals refer to the same elements.

[0025] In the following description (not necessarily in the claims), the vertical direction perpendicular to the upper surface of the substrate may be referred to as the first direction D1, and two intersecting directions in the horizontal direction parallel to the upper surface of the substrate may be referred to as the second direction D2 and the third direction D3, respectively. For example, the second direction D2 and the third direction D3 may be perpendicular to each other. Each of the first direction D1, the second direction D2, and the third direction D3 may include not only the direction shown in the drawings but also its opposite direction.

[0026] Figure 1 This is a perspective view of a semiconductor memory device according to an example embodiment.

[0027] Reference Figure 1 This illustrates a portion of a memory cell array of a semiconductor memory device. For example, the memory cell array (or a portion thereof) may be formed, disposed, and / or arranged on a substrate (e.g., Figure 3 On the substrate (SUB) in the middle.

[0028] The semiconductor memory device includes multiple memory cells MC11, MC21, MC31, MC41, MC12, MC22, MC32 and MC42, multiple local bit lines LBL11, LBL21, LBL12 and LBL22, multiple global bit lines GBL1 and GBL2, multiple word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24 and WL34, multiple control lines CL1 and CL2, multiple local bit line multiplexers MUX11, MUX21, MUX12 and MUX22, multiple first control contacts CC11 and CC21, and multiple second control contacts CC12 and CC22.

[0029] Multiple memory cells MC11, MC21, MC31, MC41, MC12, MC22, MC32, and MC42 are disposed on a substrate and arranged along a first direction D1, a second direction D2, and a third direction D3. Unlike a two-dimensional (2D) semiconductor memory device in which memory cells are arranged only along the second direction D2 and the third direction D3, the semiconductor memory device according to the example embodiment can be a three-dimensional (3D) semiconductor memory device in which multiple memory cells MC11, MC21, MC31, MC41, MC12, MC22, MC32, and MC42 are arranged not only along the second direction D2 and the third direction D3, but also along the first direction D1.

[0030] Multiple local bit lines LBL11, LBL21, LBL12, and LBL22 are disposed on a substrate and electrically connected to multiple memory cells MC11, MC21, MC31, MC41, MC12, MC22, MC32, and MC42. Each of the multiple local bit lines LBL11, LBL21, LBL12, and LBL22 extends along a first direction D1. The multiple local bit lines LBL11, LBL21, LBL12, and LBL22 may be spaced apart from each other in a second direction D2 and a third direction D3.

[0031] In some example embodiments, memory cells may be disposed between two local bit lines arranged adjacently along a second direction D2. Memory cells arranged adjacently along a first direction D1 extending along each local bit line may be electrically connected to the same local bit line. For example, memory cells arranged along the first direction D1 may form a cell string, and each cell string and the memory cells it contains may be electrically connected to a local bit line. In some example embodiments, memory cells arranged adjacently along the second direction D2 may be electrically connected to the same local bit line. For example, two cell strings arranged adjacent to a first side and a second side of a local bit line along the second direction D2, and the memory cells they contain, may be electrically connected to that local bit line and may share that local bit line.

[0032] For example, memory cells MC21 and MC31 can be disposed between adjacent local bit lines LBL11 and LBL21 along the second direction D2. Although in Figure 1 The memory cell MC11 and other memory cells (not shown) may be disposed between local bit line LBL11 and another local bit line (not shown) adjacent to local bit line LBL11 in the second direction D2, and memory cell MC41 and other memory cells (not shown) may be disposed between local bit line LBL21 and another local bit line (not shown) adjacent to local bit line LBL21 in the second direction D2.

[0033] For example, memory cells MC11 and MC21 can be adjacent in the second direction D2 and can share a local bit line LBL11. For example, memory cell MC11 arranged along the first direction D1 can be adjacent to a first side (e.g., the left side) of local bit line LBL11 and can be electrically connected to the same local bit line (e.g., local bit line LBL11). For example, memory cell MC21 arranged along the first direction D1 can be adjacent to a second side (e.g., the right side) of local bit line LBL11 and can be electrically connected to the same local bit line (e.g., local bit line LBL11).

[0034] For example, memory cells MC31 and MC41 can be adjacent in the second direction D2 and can share a local bit line LBL21. For example, memory cell MC31 arranged along the first direction D1 can be adjacent to the first side of local bit line LBL21 and can be electrically connected to the same local bit line (e.g., local bit line LBL21). For example, memory cell MC41 arranged along the first direction D1 can be adjacent to the second side of local bit line LBL21 and can be electrically connected to the same local bit line (e.g., local bit line LBL21).

[0035] Similarly, memory cells MC12 and MC22 can be adjacent to the first and second sides of local bit line LBL12, respectively, can be electrically connected to local bit line LBL12, and can share local bit line LBL12. Memory cells MC32 and MC42 can be arranged adjacent to the first and second sides of local bit line LBL22, respectively, can be electrically connected to local bit line LBL22, and can share local bit line LBL22.

[0036] As mentioned above, a local bit line can be shared by adjacent memory cells, thereby enabling semiconductor memory devices to have increased integration and improved characteristics.

[0037] Multiple global bit lines GBL1 and GBL2 are set on multiple local bit lines LBL11, LBL21, LBL12, and LBL22. For example, each of the multiple global bit lines GBL1 and GBL2 can extend along the second direction D2.

[0038] Each of the multiple global bit lines GBL1 and GBL2 is selectively electrically connected to one of the multiple local bit lines LBL11, LBL21, LBL12, and LBL22. For example, global bit line GBL1 can be selectively electrically connected to one of the local bit lines LBL11 and LBL21, and global bit line GBL2 can be selectively electrically connected to one of the local bit lines LBL12 and LBL22.

[0039] Multiple word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34 are disposed on the substrate and electrically connected to multiple memory cells MC11, MC21, MC31, MC41, MC12, MC22, MC32, and MC42. Each of the multiple word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34 extends along a third direction D3. Multiple word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24 and WL34 can be spaced apart from each other in the first direction D1 and the second direction D2.

[0040] In some example embodiments, memory cells arranged adjacent to each other in the third direction D3 at the same level and extending along each word line can be electrically connected to the same word line. For example, memory cells arranged in the third direction D3 at the same level can form a cell column, and each cell column and the memory cells included therein can be electrically connected to a word line.

[0041] For example, in adjacent memory cells MC11 and MC12 on the third-direction D3, memory cells at the same level can be electrically connected to the same word line among word lines WL11, WL21, and WL31. For example, in memory cells MC11 and MC12, the memory cell at the top level can be electrically connected to word line WL11, the memory cell at the middle level can be electrically connected to word line WL21, and the memory cell at the bottom level can be electrically connected to word line WL31.

[0042] For example, in adjacent memory cells MC21 and MC22 on the third-direction D3, memory cells at the same level can be electrically connected to the same word line among word lines WL12, WL22, and WL32. For example, in memory cells MC21 and MC12, the memory cell at the top level can be electrically connected to word line WL12, the memory cell at the middle level can be electrically connected to word line WL22, and the memory cell at the bottom level can be electrically connected to word line WL32.

[0043] Similarly, among the memory cells MC31 and MC32 that are adjacent to each other on the third direction D3, memory cells at the same level can be electrically connected to the same word line among word lines WL13, WL23, and WL33. Among the memory cells MC41 and MC42 that are adjacent to each other on the third direction D3, memory cells at the same level can be electrically connected to the same word line among word lines WL14, WL24, and WL34.

[0044] Multiple control lines CL1 and CL2 are provided on multiple word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34. Each of the multiple control lines CL1 and CL2 extends along a third direction towards D3. For example, each of the multiple control lines CL1 and CL2 can be connected to at least one of multiple local bit line multiplexers MUX11, MUX21, MUX12, and MUX22.

[0045] Multiple local bit line multiplexers MUX11, MUX21, MUX12 and MUX22 control the electrical connections between multiple local bit lines LBL11, LBL21, LBL12 and LBL22 and multiple global bit lines GBL1 and GBL2.

[0046] For example, local bit line multiplexer MUX11 can control the electrical connection between local bit line LBL11 and global bit line GBL1, and local bit line multiplexer MUX21 can control the electrical connection between local bit line LBL21 and global bit line GBL1. Similarly, local bit line multiplexer MUX12 can control the electrical connection between local bit line LBL12 and global bit line GBL2, and local bit line multiplexer MUX22 can control the electrical connection between local bit line LBL22 and global bit line GBL2. Although not shown, each of local bit line multiplexers MUX11 and MUX21 may include bit line sense amplifiers (BLSAs) coupled to local bit lines LBL11 and LBL21, respectively, and each of local bit line multiplexers MUX12 and MUX22 may include BLSAs coupled to local bit lines LBL12 and LBL22, respectively. For example, a BLSA can sense and amplify the voltage detected on a selected local bit line to provide the amplified voltage to the local bit line and / or a selected global bit line.

[0047] At least two of the multiple local bit line multiplexers MUX11, MUX21, MUX12, and MUX22 share one of the multiple control lines CL1 and CL2. For example, local bit line multiplexers arranged adjacent to each other along the third direction D3 can be electrically connected to the same control line.

[0048] For example, local bit line multiplexers MUX11 and MUX12, which are adjacent on the third-direction D3, can be electrically connected to the same control line (e.g., control line CL1). Similarly, local bit line multiplexers MUX21 and MUX22, which are adjacent on the third-direction D3, can be electrically connected to the same control line (e.g., control line CL2). Although Figure 1 This invention illustrates that adjacent local bit line multiplexers share a control line, but the invention is not limited thereto, and three or more adjacent local bit line multiplexers may share a control line.

[0049] Multiple first control contacts CC11 and CC21 are connected to the first ends of multiple control lines CL1 and CL2. Each of the multiple first control contacts CC11 and CC21 extends along a first direction D1. For example, first control contact CC11 may be electrically connected to the first end of control line CL1, and first control contact CC21 may be connected to the first end of control line CL2.

[0050] Multiple second control contacts CC12 and CC22 are connected to the second ends of multiple control lines CL1 and CL2. Each of the multiple second control contacts CC12 and CC22 extends along a first direction D1. For example, second control contact CC12 may be connected to the second end of control line CL1, and second control contact CC22 may be connected to the second end of control line CL2.

[0051] In some example embodiments, a first control contact and a second control contact can be connected to a control line. Therefore, the number of control lines CL1 and CL2, the number of first control contacts CC11 and CC21, and the number of second control contacts CC12 and CC22 can be the same as each other.

[0052] Although Figure 1 Examples of semiconductor memory devices including a specific number of memory cells, local bit lines, global bit lines, word lines, control lines, local bit line multiplexers, and control contacts are shown, but the invention is not limited thereto.

[0053] Figure 2 This illustrates an example embodiment. Figure 1 Circuit diagram of a semiconductor memory device.

[0054] Reference Figure 2 It shows that in Figure 1 This example illustrates components in a semiconductor memory device connected to local bit lines LBL11 and LBL21 and global bit line GBL1. For simplicity, the connections to these components will be omitted. Figure 1 The description is repetitive or overlapping.

[0055] Each of the memory cells MC1a, MC1b, MC1c, MC2a, MC2b, MC2c, MC3a, MC3b, MC3c, MC4a, MC4b, and MC4c may include one of the cell transistors CT1a, CT1b, CT1c, CT2a, CT2b, CT2c, CT3a, CT3b, CT3c, CT4a, CT4b, and CT4c, and one of the capacitors C1a, C1b, C1c, C2a, C2b, C2c, C3a, C3b, C3c, C4a, C4b, and C4c, and may be connected to one of the local bit lines LBL11 and LBL21 and one of the word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34. For example, a semiconductor memory device may be a dynamic random access memory (DRAM) device, and each memory cell may be a DRAM cell having a 1T-1C structure including a unit transistor and a capacitor.

[0056] Each of the unit transistors CT1a, CT1b, CT1c, CT2a, CT2b, CT2c, CT3a, CT3b, CT3c, CT4a, CT4b, and CT4c may include a gate electrode connected to one of word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34; a first source / drain connected to one of local bit lines LBL11 and LBL21; and a second source / drain connected to a first terminal of one of capacitors C1a, C1b, C1c, C2a, C2b, C2c, C3a, C3b, C3c, C4a, C4b, and C4c. Capacitors C1a, C1b, C1c, C2a, C2b, C2c, C3a, C3b, C3c, C4a, C4b, and C4c can be connected together to the plate (or plate electrode) PP. For example, the second terminal of each of capacitors C1a, C1b, C1c, C2a, C2b, C2c, C3a, C3b, C3c, C4a, C4b, and C4c can be connected together to the plate PP.

[0057] For example, memory cell MC1a may include a cell transistor CT1a and a capacitor C1a. Cell transistor CT1a may have a gate electrode connected to word line WL11 and may be connected between local bit line LBL11 and capacitor C1a. Capacitor C1a may be connected between cell transistor CT1a and board PP. Similarly, memory cell MC1b may include a cell transistor CT1b and capacitor C1b, and may be connected to word line WL21 and local bit line LBL11. Memory cell MC1c may include a cell transistor CT1c and capacitor C1c, and may be connected to word line WL31 and local bit line LBL11. Although not shown, bit line selection transistors may be disposed between each of cell transistors CT1a, CT1b, CT1c, CT2a, CT2b, and CT2c and local bit line LBL11. For example, when one of the cell transistors CT1a, CT1b, CT1c, CT2a, CT2b, and CT2c is selected by a word line, the selected cell transistor can be electrically connected to the local bit line LBL11 via the selected bit line selection transistor. Memory cells MC1a, MC1b, and MC1c can correspond to... Figure 1 The memory unit MC11 in the memory.

[0058] Similarly, each of the memory cells MC2a, MC2b, and MC2c may include one of the cell transistors CT2a, CT2b, and CT2c, and one of the capacitors C2a, C2b, and C2c, and may be connected to one of the word lines WL12, WL22, and WL32, and the local bit line LBL11, and may correspond to Figure 1 The memory cell MC21 in the memory. Each of the memory cells MC3a, MC3b, and MC3c may include one of the cell transistors CT3a, CT3b, and CT3c and one of the capacitors C3a, C3b, and C3c, and may be connected to one of the word lines WL13, WL23, and WL33 and the local bit line LBL21, and may correspond to Figure 1 The memory cell MC31 is shown. Although not shown, a bit line selection transistor may be disposed between each of the cell transistors CT1a, CT1b, CT1c, CT2a, CT2b, CT2c, CT3a, CT3b, CT3c, CT4a, CT4b, and CT4c and the local bit line LBL11. Each of the memory cells MC4a, MC4b, and MC4c may include one of the cell transistors CT4a, CT4b, and CT4c and one of the capacitors C4a, C4b, and C4c, which may be connected to one of the word lines WL14, WL24, and WL34 and the local bit line LBL21, and may correspond to... Figure 1 The memory unit MC41 in the memory.

[0059] Each of the local bit line multiplexers MUX11 and MUX21 may include two transistors. Of these two transistors, one transistor may be connected between one of the local bit lines LBL11 and LBL21 and the global bit line GBL1, and the other transistor may be connected between one of the local bit lines LBL11 and LBL21 and the precharge voltage VBL.

[0060] For example, the local bit line multiplexer MUX11 may include transistors T11a and T11b. Transistor T11a may be connected between the local bit line LBL11 and the global bit line GBL1, and may have a gate electrode connected to the control line CL1a. Transistor T11b may be connected between the local bit line LBL11 and the pre-charge voltage VBL, and may have a gate electrode connected to the control line CL1b.

[0061] Similarly, the local bit line multiplexer MUX21 may include a transistor T21a connected between the local bit line LBL21 and the global bit line GBL1 and having a gate electrode connected to the control line CL2a, and may include a transistor T21b connected between the local bit line LBL21 and the precharge voltage VBL and having a gate electrode connected to the control line CL2b.

[0062] Among the transistors T11a, T11b, T21a, and T21b included in the local bit line multiplexers MUX11 and MUX21, transistors T11a and T21a that control the electrical connection between local bit lines and global bit lines can be referred to as selection transistors, and transistors T11b and T21b connected to the precharge voltage VBL can be referred to as holding transistors. For example, transistors T11a, T11b, T21a, and T21b can be n-type metal-oxide-semiconductor (NMOS) transistors, but the present invention is not limited thereto.

[0063] In some example embodiments, the local bit line multiplexers MUX11 and MUX21 include transistors T11a, T11b, T21a and T21b, control lines CL1a, CL1b, CL2a and CL2b connected to transistors T11a, T11b, T21a and T21b, and unit transistors CT1a, CT1b and CT1c included in memory cells MC1a, MC1b, MC1c, MC2a, MC2b, MC2c, MC3a, MC3b, MC3c, MC4a, MC4b and MC4c. CT2a, CT2b, CT2c, CT3a, CT3b, CT3c, CT4a, CT4b and CT4c, and word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24 and WL34 connected to unit transistors CT1a, CT1b, CT1c, CT2a, CT2b, CT2c, CT3a, CT3b, CT3c, CT4a, CT4b and CT4c can be formed or manufactured using the same manufacturing process.

[0064] For example, control lines CL1a, CL1b, CL2a, and CL2b, and word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34 may include multiple structures formed by the same manufacturing process. Among the multiple structures, the uppermost structure can be used as control lines CL1a, CL1b, CL2a, and CL2b, and the remaining structures can be used as word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34. For example, control line CL1b can be set on word lines WL11, WL21 and WL31, control line CL1a can be set on word lines WL12, WL22 and WL32, control line CL2b can be set on word lines WL13, WL23 and WL33, and control line CL2a can be set on word lines WL14, WL24 and WL34.

[0065] For example, multiple transistors connected to multiple structures can be formed. Among the multiple transistors, the topmost transistor connected to the topmost structure can be used as transistors T11a, T11b, T21a, and T21b, and the remaining transistors connected to the other structures besides the topmost transistor can be used as unit transistors CT1a, CT1b, CT1c, CT2a, CT2b, CT2c, CT3a, CT3b, CT3c, CT4a, CT4b, and CT4c. For example, capacitors connected to the remaining transistors can be formed and used as capacitors C1a, C1b, C1c, C2a, C2b, C2c, C3a, C3b, C3c, C4a, C4b, and C4c, and the formation of the capacitor connected to the topmost transistor can be omitted.

[0066] As described above, the structure at the topmost level of the memory cell array included in a 3D semiconductor memory device can be used as a local bit line multiplexer instead of a memory cell, thus enabling the semiconductor memory device to have improved electrical characteristics and improved reliability.

[0067] The first control contact CC11a and the second control contact CC12a can be connected to the first and second ends of the control line CL1a, respectively, and the first control contact CC21a and the second control contact CC22a can be connected to the first and second ends of the control line CL2a, respectively. A signal for turning the local bit line multiplexer MUX11 on and off via the switching transistor T11a can be simultaneously applied to both ends of the control line CL1a via the first control contact CC11a and the second control contact CC12a. For example, this signal can be applied via the lines connected to the first control contact CC11a and the second control contact CC12a (e.g., ...). Figure 7 The UCL1a signal is simultaneously applied to the first control contact CC11a and the second control contact CC12a. The signal used to turn the local bit line multiplexer MUX21 on and off via the switching transistor T21a can be simultaneously applied to both ends of the control line CL2a via the first control contact CC21a and the second control contact CC22a. For example, this signal can be simultaneously applied to the first control contact CC21a and the second control contact CC22a via a line (not shown) connected to the first control contact CC21a and the second control contact CC22a.

[0068] As described above, the control line can be driven using control contacts at both ends, thus enabling the semiconductor memory device to have improved electrical characteristics and reliability. The operation of driving the control line using control contacts at both ends can be referred to as a two-sided drive (TSD) scheme.

[0069] In some example embodiments, such as referring to Figure 7 The semiconductor memory device may further include a plurality of word line contacts, wherein each word line contact is connected to one of word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24, and WL34. In some example embodiments, as will be referred to Figure 10 The semiconductor memory device may further include at least one control contact connected to one of the control lines CL1b and CL2b.

[0070] Although not shown in detail, components connected to local bit lines LBL12 and LBL22 and global bit line GBL12 (e.g., memory cells MC12, MC22, MC32 and MC42, and local bit line multiplexers MUX12 and MUX22) can also be similar to those shown in the reference. Figure 2 The aforementioned implementations. Therefore, the select transistor and hold transistor included in the local bit line multiplexers MUX11 and MUX12 can share control lines CL1a and CL1b respectively, and the select transistor and hold transistor included in the local bit line multiplexers MUX21 and MUX22 can share control lines CL2a and CL2b respectively.

[0071] In some example embodiments, although in Figure 2 Not shown, but semiconductor memory devices can be implemented using a word-line merging structure, where word lines (e.g., word lines WL12 and WL13) connected to memory cells (e.g., memory cells MC2a and MC3a) that do not share local bit lines can be merged into a single word line. In some example embodiments, although in Figure 2 Not shown, but the semiconductor memory device can be implemented such that the local bit line multiplexers MUX11 and MUX21 are connected to different global bit lines instead of the same global bit line (e.g., global bit line GBL1).

[0072] In the semiconductor memory device according to the example embodiment, adjacent memory cells can share local bit lines. Furthermore, a local bit line multiplexer controlling the electrical connection between the local bit lines and global bit lines can be provided on each local bit line, and the structure at the topmost level of the memory cell array can serve as a local bit line multiplexer. Further, two control contacts for signal application can be provided at both ends of a control line connected to the local bit line multiplexer. Therefore, the semiconductor memory device can have improved electrical characteristics and improved reliability.

[0073] For example, local bit lines and global bit lines can be selectively connected and disconnected using a local bit line multiplexer, thereby reducing bit line capacitance (e.g., bit line capacitance (CBL)) and increasing sensing margin. Furthermore, the signals used to turn the local bit line multiplexer on and off can be applied to the control line using two control contacts, which can reduce the delay time when the local bit line multiplexer is turned on / off and improve operational performance.

[0074] Figure 3 and Figure 4 These are perspective and plan views used to describe a semiconductor memory device according to an example embodiment.

[0075] Reference Figure 3 and Figure 4 This illustrates a portion of a memory cell array and / or a portion of a sub-cell array included in a memory cell array of a semiconductor memory device.

[0076] A semiconductor memory device may include word lines WL, word line contacts (or contact plugs) WC, control lines CL, control contacts CC, local bit lines LBL, global bit lines GBL, memory cells, and local bit line multiplexers formed or disposed on a substrate SUB. Although not shown in detail, the semiconductor memory device may also include an insulating interlayer disposed on the substrate SUB and covering the above-described structures. For ease of explanation, in Figure 4 Global bit line (GBL) is omitted in this code.

[0077] The substrate SUB may include semiconductor materials such as silicon, germanium, silicon-germanium, or III-V compound semiconductors such as GaP, GaAs, and GaSb. In some example embodiments, the substrate SUB may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0078] The substrate SUB may include a first region and a second region. The first region may be the region forming a memory cell, and the second region may be the region forming word line contacts WC and control contacts CC for transmitting electrical signals to the memory cell. The first region and the second region may be referred to as the cell region and the extension region, respectively.

[0079] The substrate SUB may also include a third region forming a peripheral circuit pattern including a sense amplifier, etc. The third region may be referred to as a peripheral circuit region. In some example embodiments, the third region may at least partially surround the first and second regions, or may be disposed below or above the substrate SUB, thereby enabling the semiconductor memory device to have a cell-on-periphery (COP) structure or a cell-on-periphery (POC) structure. As used herein, the phrase "at least partially surround" is understood to mean that the surrounding element contacts the surrounding element on at least one side or part of the surrounded element, may contact the surrounding element on both sides, whether these sides are opposite or adjacent, may contact the surrounding element on more than both sides, or may even completely surround the surrounded element.

[0080] Each of the local bit lines LBL can extend along a first direction D1 on a first region of the substrate SUB, and multiple local bit lines LBL can be spaced apart from each other along a second direction D2 and a third direction D3. Memory cells and transistors included in the local bit line multiplexer can be formed between two adjacent local bit lines LBL.

[0081] Each of the global bit lines GBL can extend along the second direction D2 on the first region of the substrate SUB and on the local bit line LBL, and multiple global bit lines GBL can be spaced apart from each other on the third direction D3.

[0082] Each word line WL and each control line CL can extend along a third direction D3 on a first and second region of the substrate SUB. Multiple word lines WL and multiple control lines CL can be spaced apart from each other in a second direction D2, and some word lines WL and one control line CL can be stacked in a first direction D1. Each word line contact WC and each control contact CC can extend along the first direction D1 on a second region of the substrate SUB and can be electrically connected to one of the word lines WL and one of the control lines CL, respectively.

[0083] Figure 5 , Figure 6 , Figure 7 and Figure 8 It is used to describe according to the example embodiments Figure 3 and Figure 4 A cross-sectional view of a semiconductor memory device. For example, Figure 5 It is along Figure 4 A cross-sectional view taken from line I-I' in the diagram. Figure 6 yes Figure 5 Detailed cross-sectional view of region X in the middle. Figure 7 It is along Figure 4 The cross-sectional view taken from line II-II' in the diagram, and Figure 8 yes Figure 7 Detailed cross-sectional view of region Y in the middle.

[0084] Reference Figure 5 , Figure 6 , Figure 7 and Figure 8 The memory cell may include a cell transistor CT and a capacitor CAP, and the local bit line multiplexer may include a select transistor T1 and a hold transistor T2.

[0085] For example, Figure 6 Structures 532 and 534 in the diagram may represent or correspond to two local bit lines that extend along a first direction D1 and are spaced apart in a second direction D2. For example, the upper surface of each of the local bit lines 532 and 534 may have a shape such as a polygon, a polygon with rounded corners, a circle, an ellipse, etc.

[0086] Between two adjacent local bit lines 532 and 534, two memory cells can be formed at all levels except the topmost level. For example, each memory cell may include a capacitor CAP and a cell transistor CT. For example, in... Figure 6 In this configuration, one unit transistor may be formed between the capacitor 470 on the left and the local bit line 532, and another unit transistor may be formed between the capacitor 470 on the right and the local bit line 534. For example, each unit transistor may include a second source / drain 490, a channel 125, and a first source / drain 520 sequentially disposed between each of the capacitors 470 and each of the local bit lines 532 and 534, and a gate structure 230 surrounding the channel 125.

[0087] In some example embodiments, capacitor 470 may include: a first capacitor electrode 380 having a columnar shape extending along a second direction D2; a dielectric pattern 440 having a hollow cylindrical shape that may surround the surface of the first capacitor electrode 380 (e.g., a lower surface and an upper surface, and opposing sidewalls in a third direction D3); and a second capacitor electrode 460 having a hollow cylindrical shape that may surround the surface of the dielectric pattern 440, such as the lower surface and an upper surface, and opposing outer sidewalls in a third direction D3. However, the example embodiments are not necessarily limited thereto; for example, the first capacitor electrode 380 may have a hollow cylindrical shape instead of a columnar shape, and the second capacitor electrode 460 may have a hollow cylindrical shape instead of a columnar shape.

[0088] In some example embodiments, the cross-section of the first capacitor electrode 380 in the third direction D3 may have a rectangular shape. However, the example embodiments are not necessarily limited to this, and the cross-section of the first capacitor electrode 380 in the third direction D3 may have, for example, a polygon, a polygon with rounded corners, a circle, an ellipse, or the like.

[0089] Each of the first capacitor electrode 380 and the second capacitor electrode 460 may include a conductive material, such as a metal, a metal nitride, a metal silicide, doped silicon-germanium, etc. The dielectric pattern 440 may include a metal oxide (e.g., hafnium oxide, zirconium oxide, etc.) or a ferroelectric material having a high dielectric constant. As used herein, the phrase "high dielectric constant" can be understood as a dielectric constant higher than that of silicon oxide.

[0090] Channel 125 may include semiconductor materials, such as silicon, germanium, silicon-germanium, etc. Alternatively, channel 125 may include oxide semiconductor materials, such as zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), and indium oxide (InO) x In₂O₃), tin oxide (SnO₂), titanium oxide (TiO₂) x ), Zinc oxide (Zn) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O a Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Snz O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a ) and / or indium gallium silicon oxide (InGaSiO).

[0091] Each of the first source / drain 520 and the second source / drain 490 may comprise substantially the same material as the channel 125, but may be doped with n-type or p-type impurities. The first source / drain 520 and the second source / drain 490 may comprise impurities of the same conductivity type.

[0092] In some example embodiments, the gate structure 230 may include a gate insulating pattern 210 covering the surfaces of the channel 125 (e.g., the lower and upper surfaces and opposing sidewalls in the third direction D3) and a gate electrode 220 covering the surfaces of the gate insulating pattern 210 (e.g., the lower and upper surfaces and opposing outer sidewalls in the third direction D3). Therefore, the channel 125 may extend through the gate structure 230 in the second direction D2, and the gate structure 230 may have a gate all-around (GAA) structure surrounding the channel 125.

[0093] Alternatively, the gate structure 230 may have a single-gate structure or a dual-gate structure instead of a GAA structure. For example, the gate structure 230 may be disposed above or below the channel 125, or the two gate structures 230 may be disposed above and below the channel 125 respectively, instead of surrounding the channel 125.

[0094] Therefore, if only the gate structure 230 is electrically connected to the channel 125, the gate structure 230 can have various other types of structures.

[0095] Furthermore, between two adjacent local bit lines 532 and 534, a select transistor T1 and a hold transistor T2 can be formed at the topmost level. For example, each of the select transistor T1 and the hold transistor T2 can have the same structure as the cell transistor CT included in each memory cell. For example, the select transistor T1 can be connected to the global bit line GBL via a vertical via, and the hold transistor T2 can be connected to the bit line voltage VBL via a vertical via. For example, the structure corresponding to the capacitor 470 may not be formed at the topmost level, and the structure may be omitted.

[0096] In some example embodiments, a channel 125 arranged at the same level along the third direction D3 and a gate insulating pattern 210 covering the channel 125 and gate electrodes 220 disposed adjacent to each other on the third direction D3 can be connected to each other, thereby forming a word line WL and / or a control line CL extending along the third direction D3 on a first region and a second region of the substrate SUB. For example, the gate electrode 220 at the uppermost level can form the control line CL, and the gate electrodes 220 at the remaining levels other than the uppermost level can form the word line WL.

[0097] The gate electrode 220 may include a conductive material, such as a metal, a metal nitride, a metal silicide, etc., and the gate insulating pattern 210 may include an oxide, such as silicon oxide, a metal oxide, etc.

[0098] In some example embodiments, each of the word line contacts WC and each of the control contacts CC may extend along a first direction D1 on a second region of the substrate SUB and may be electrically connected to one of the word lines WL and one of the control lines CL, respectively. For example, the control line CL and the word line WL may be arranged in a ladder-like configuration, i.e., in a stepped shape on the second region of the substrate SUB (e.g., in a stepped manner on a third direction D3). For example, the lengths of the control line CL and the word line on the third direction D3 may increase from the uppermost layer to the lowermost layer.

[0099] For example, such as Figure 7 As shown, the control line CL1a connected to the selection transistor T1 and the word lines WL1a, WL2a, WL3a, WL4a, WL5a and WL6a located below the control line CL1a and connected to the memory cell can be arranged and formed in a stepped shape.

[0100] For example, the first control contact CC11a can be connected to the first end of the control line CL1a, and the second control contact CC12a can be connected to the second end of the control line CL1a. The first control contact CC11a and the second control contact CC12a can be connected via the upper wiring UCL1a, and the signal for turning the local bit line multiplexer (e.g., selecting transistor T1) on and off can be simultaneously applied to both ends of the control line CL1a via the upper wiring UCL1a and the control contacts CC11a and CC12a.

[0101] For example, word line contacts WC1a, WC2a, WC3a, WC4a, WC5a, and WC6a can be connected to word lines WL1a, WL2a, WL3a, WL4a, WL5a, and WL6a, respectively. For example, when the lowest word line (e.g., word line WL6a at the lowest level) is defined as the first word line, word lines WL2a, WL4a, and WL6a can be defined as word lines at odd-numbered levels, and word lines WL1a, WL3a, and WL5a can be defined as word lines at even-numbered levels. In this example, among the word line contacts WC1a, WC2a, WC3a, WC4a, WC5a, and WC6a, word line contacts WC2a, WC4a, and WC6a can be connected to the first ends of word lines WL2a, WL4a, and WL6a at odd-numbered levels, and word line contacts WC1a, WC3a, and WC5a can be connected to the second ends of word lines WL1a, WL3a, and WL5a at even-numbered levels.

[0102] Although not shown in detail, wiring similar to the upper wiring UCL1a can be formed on top of word line contacts WC1a, WC2a, WC3a, WC4a, WC5a and WC6a.

[0103] As described above, the areas where word line contacts are configured for word lines connected to odd-numbered levels and the areas where word line contacts are configured for word lines connected to even-numbered levels can be different from each other. However, the example embodiment is not limited to this. For example, word lines can be arbitrarily divided into two groups, and the areas where word line contacts are configured for one group of word lines and the areas where word line contacts are configured for the other group of word lines can be different from each other.

[0104] Figure 9A and Figure 9B This is a diagram used to describe the operation of a semiconductor memory device according to an example embodiment.

[0105] Reference Figure 9A This illustrates an example of the operation of a semiconductor memory device according to an example embodiment, wherein two control contacts connected to both ends of a control line are used to drive the control line. For example, Figure 9A This illustrates the voltage changes on the word line WL, bit line BL, and control line CL connected to a specific memory cell when that memory cell is accessed. When a specific memory cell is selected, the bit line BL can be electrically connected to the local bit line LBL and the global bit line GBL.

[0106] At time t1, bit line BL can have a pre-charged state.

[0107] Subsequently, when the control line CL transitions from low to high, the selection transistor T1 included in the local bit line multiplexer can be turned on. Therefore, at time t2, the local bit line LBL and the global bit line GBL can be electrically connected to each other. Because the signal is applied using the two control contacts at both ends of the control line CL, the RC delay time can be reduced, and the delay time TD for the control line CL to transition from low to high can be relatively short.

[0108] Subsequently, when the word line WL transitions from low to high, the corresponding memory cell can be accessed. At time t3, the bit line BL can be in a charge-sharing state, and at time t4, the bit line BL can be in a signal-developing state. Therefore, operations on the corresponding memory cell (e.g., read operations) can be performed.

[0109] Reference Figure 9B This illustrates an example of the operation of a conventional semiconductor memory device, where a single control contact connected to one end of a control line is used to drive the control line. For simplicity, the details are omitted. Figure 9A The description is repetitive or overlapping.

[0110] At time t1', bit line BL can be in a pre-charge state. Subsequently, at time t2', the local bit line LBL and the global bit line GBL can be electrically connected to each other. Subsequently, at time t3', bit line BL can be in a charge-sharing state, and at time t4', bit line BL can be in a signal amplification state. Because a control contact is used to apply the signal when the local bit line LBL and the global bit line GBL are electrically connected, the RC delay time can be increased, and the delay time TD' for the control line CL' to transition from low to high will be relatively large.

[0111] Figure 10 and Figure 11 It is used to describe according to the example embodiments Figure 3 and Figure 4 A cross-sectional view of a semiconductor memory device. For example, Figure 10 and Figure 11 It is along Figure 4 The cross-sectional view taken from line III-III' in the diagram. For simplicity, the details are omitted. Figure 7 The description is repetitive or overlapping.

[0112] Reference Figure 10 The control line CL1b connected to the holding transistor T2, and the word lines WL1b, WL2b, WL3b, WL4b, WL5b and WL6b below the control line CL1b and connected to the memory cell, can be arranged and formed in a stepped shape.

[0113] For example, the first control contact CC11b can be connected to the first end of the control line CL1b. For example, unlike the control line CL1a connected to the gate electrode of the select transistor T1, the control line CL1b connected to the gate electrode of the hold transistor T2 can be implemented without a dual-sided drive scheme and can be connected to only one control contact CC11b.

[0114] For example, word line contacts WC1b, WC2b, WC3b, WC4b, WC5b, and WC6b can be connected to word lines WL1b, WL2b, WL3b, WL4b, WL5b, and WL6b, respectively. For example, among word line contacts WC1b, WC2b, WC3b, WC4b, WC5b, and WC6b, word line contacts WC2b, WC4b, and WC6b can be connected to the first ends of word lines WL2b, WL4b, and WL6b at odd-numbered levels, and word line contacts WC1b, WC3b, and WC5b can be connected to the second ends of word lines WL1b, WL3b, and WL5b at even-numbered levels.

[0115] Reference Figure 11 The arrangement of control line CL1b and word lines WL1b, WL2b, WL3b, WL4b, WL5b and WL6b, as well as the arrangement of word line contacts WC1b, WC2b, WC3b, WC4b, WC5b and WC6b, can be consistent with the reference. Figure 10 The descriptions are the same.

[0116] For example, the first control contact CC11b can be connected to the first end of the control line CL1b, and the second control contact CC12b can be connected to the second end of the control line CL1b. For example, similar to the control line CL1a connected to the gate electrode of the select transistor T1, the control line CL1b connected to the gate electrode of the hold transistor T2 can also be implemented using a dual-sided drive scheme. In this example, the first control contact CC11b and the second control contact CC12b can be connected via the upper wiring UCL1b, and the signal for applying the pre-charge voltage VBL (e.g., the signal for turning on and off the hold transistor T2) can be simultaneously applied to both ends of the control line CL1b via the upper wiring UCL1b and the control contacts CC11b and CC12b.

[0117] Figure 12 , Figure 13 , Figure 14 and Figure 15 These are perspective and plan views used to describe a semiconductor memory device according to an example embodiment. For example, Figure 12 and Figure 14 It is a three-dimensional diagram of a semiconductor memory device, and Figure 13 It is along Figure 12A cross-sectional view taken from line IV-IV' in the diagram. Figure 15 It is along Figure 14 The cross-sectional view taken by line V-V' in the diagram. For simplicity, the details are omitted. Figure 4 and Figure 7 The description is repetitive or overlapping.

[0118] Reference Figure 12 and Figure 13 The control line CL1a connected to the select transistor T1, and the word lines WL1a', WL2a', WL3a', WL4a', WL5a', and WL6a' below the control line CL1a and connected to the memory cell, can be arranged and formed in a stepped shape. The control line CL1a, control contacts CC11a and CC12a, and upper wiring UCL1a can be referenced. Figure 7 The descriptions are the same.

[0119] For example, word line contacts WC11a, WC21a, WC31a, WC41a, WC51a, and WC61a can be connected to word lines WL1a', WL2a', WL3a', WL4a', WL5a', and WL6a', respectively. For example, word line contacts WC11a, WC21a, WC31a, WC41a, WC51a, and WC61a can be connected to the first end of word lines WL1a', WL2a', WL3a', WL4a', WL5a', and WL6a', respectively. For example, with... Figure 7 Unlike other examples, word line contacts that connect to all word lines can be located in the same area (e.g., the left side area).

[0120] Reference Figure 14 and Figure 15 The control line CL1a connected to the select transistor T1, and the word lines WL1a", WL2a", WL3a", WL4a", WL5a", and WL6a" below the control line CL1a and connected to the memory cell, can be arranged and formed in a stepped shape. The control line CL1a, control contacts CC11a and CC12a, and upper wiring UCL1a can be referenced. Figure 7 The descriptions are basically the same.

[0121] For example, word line contacts WC11a, WC12a, WC21a, WC22a, WC31a, WC32a, WC41a, WC42a, WC51a, WC52a, WC61a and WC62a can be connected to word lines WL1a", WL2a", WL3a", WL4a", WL5a" and WL6a". For example, word line contacts WC11a, WC21a, WC31a, WC41a, WC51a, and WC61a can be connected to the first ends of word lines WL1a", WL2a", WL3a", WL4a", WL5a", and WL6a", respectively, and word line contacts WC12a, WC22a, WC32a, WC42a, WC52a, and WC62a can be connected to the second ends of word lines WL1a", WL2a", WL3a", WL4a", WL5a", and WL6a", respectively. In other words, similar to control line CL1a, each word line can be driven using two word line contacts connected to both ends of each word line.

[0122] Although Figures 3 to 15 Examples of semiconductor memory devices including a specific number and configuration of control lines, control line contacts, word lines, and word line contacts are shown, but the invention is not limited thereto.

[0123] Figure 16 This is a perspective view of a semiconductor memory device according to an example embodiment. For the sake of brevity, [the following will be omitted]. Figure 1 The description is repetitive or overlapping.

[0124] Reference Figure 16 This illustrates a portion of a memory cell array of a semiconductor memory device, and a portion of peripheral circuitry connected to that portion of the memory cell array. Figure 1 Compared to semiconductor memory devices, Figure 16 The semiconductor memory device may also include multiple sense amplifiers SA1 and SA2.

[0125] For example, multiple memory cells MC11, MC21, MC31, MC41, MC12, MC22, MC32 and MC42, multiple local bit lines LBL11, LBL21, LBL12 and LBL22, multiple global bit lines GBL1 and GBL2, multiple word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24 and WL34, multiple control lines CL1 and CL2, multiple local bit line multiplexers MUX11, MUX21, MUX12 and MUX22, multiple first control contacts CC11 and CC21, and multiple second control contacts CC12 and CC22 may be included in the memory cell array (or a portion thereof). For example, multiple sense amplifiers SA1 and SA2 may be included in the peripheral circuitry (or a portion thereof).

[0126] Multiple sense amplifiers SA1 and SA2 can be electrically connected to multiple global bit lines GBL1 and GBL2, and can drive multiple local bit lines LBL11, LBL21, LBL12 and LBL22 as well as multiple global bit lines GBL1 and GBL2.

[0127] For example, the sense amplifier SA1 can be electrically connected to the global bit line GBL1. When the local bit line LBL11 and the global bit line GBL1 are electrically connected through the local bit line multiplexer MUX1, the local bit line LBL11 and the global bit line GBL1 can be driven. When the local bit line LBL21 and the global bit line GBL1 are electrically connected through the local bit line multiplexer MUX21, the local bit line LBL21 and the global bit line GBL1 can be driven.

[0128] Similarly, the sense amplifier SA2 can be electrically connected to the global bit line GBL2. When the local bit line LBL12 and the global bit line GBL2 are electrically connected through the local bit line multiplexer MUX12, the sense amplifier SA2 can drive the local bit line LBL12 and the global bit line GBL2. And when the local bit line LBL22 and the global bit line GBL2 are electrically connected through the local bit line multiplexer MUX22, the sense amplifier SA2 can drive the local bit line LBL22 and the global bit line GBL2.

[0129] Figure 17 and Figure 18 These are perspective and cross-sectional views of a semiconductor memory device according to an example embodiment.

[0130] Reference Figure 17 and Figure 18 The semiconductor memory device 10 includes a first semiconductor layer L1 and a second semiconductor layer L2.

[0131] A first semiconductor layer L1 and a second semiconductor layer L2 are disposed or stacked in a first direction D1. For example, the second semiconductor layer L2 may be stacked on top of the first semiconductor layer L1 in the first direction D1, and the first semiconductor layer L1 may be disposed below the second semiconductor layer L2 in the first direction D1 (e.g., directly or indirectly below it). However, the exemplary embodiments are not limited to this. For example, the semiconductor memory device 10 may be flipped during the manufacturing process, so the first semiconductor layer L1 may be stacked on top of the second semiconductor layer L2 in the first direction D1.

[0132] The first semiconductor layer L1 may include a first substrate SUB1, a memory cell array MCA, multiple word lines WL, and multiple local bit lines LBL. The first semiconductor layer L1 may also include a first bonding pad PD_L1, a first contact CT_L1, and a first insulating layer IL1. Therefore, the first semiconductor layer L1 may be referred to as a memory cell region (MCR), a cell wafer, or a cell chip.

[0133] The first substrate SUB1 may be a support layer for components (or elements) supporting the first semiconductor layer L1. For example, the first substrate SUB1 may be a silicon substrate and may be referred to as a base substrate. The first insulating layer IL1 may cover the components of the first semiconductor layer L1. For example, the first insulating layer IL1 may include multiple insulating layers.

[0134] A memory cell array MCA, multiple word lines WL, and multiple local bit lines LBL can be disposed and / or formed on a first substrate SUB1. For example, each of the multiple word lines WL can extend along a third direction D3, and the multiple word lines WL can be arranged along a first direction D1 and a second direction D2. For example, the multiple word lines WL can be spaced apart from each other in the first direction D1 and the second direction D2. For example, each of the multiple local bit lines LBL can extend along the first direction D1, and the multiple local bit lines LBL can be arranged along the second direction D2 and the third direction D3. For example, the memory cell array MCA may include multiple memory cells MC arranged along the first direction D1, the second direction D2, and the third direction D3, and each memory cell of the multiple memory cells MC can be electrically connected to one of the multiple word lines WL and one of the multiple local bit lines LBL.

[0135] The second semiconductor layer L2 may include a second substrate SUB2 and peripheral circuitry PCKT. The second semiconductor layer L2 may also include a second bonding pad PD_L2, a second contact CT_L2, and a second insulating layer IL2. Therefore, the second semiconductor layer L2 may be referred to as the peripheral circuitry region (PCR), peripheral wafer, core wafer, or peripheral chip.

[0136] Similar to the first substrate SUB1 and the first insulating layer IL1, the second substrate SUB2 can be a support layer for the components supporting the second semiconductor layer L2, and the second insulating layer IL2 can cover the components of the second semiconductor layer L2.

[0137] The peripheral circuitry PCKT can be disposed and / or formed on the second substrate SUB2. For example, the peripheral circuitry PCKT may include multiple transistors TR, and various circuits can be formed from the multiple transistors TR. For example, as will be referred to... Figure 20 The peripheral circuit PCKT described may include a sense amplifier unit, input / output gating circuit, etc.

[0138] In some example embodiments, a first semiconductor layer L1 and a second semiconductor layer L2 can be fabricated separately, and then the first semiconductor layer L1 and the second semiconductor layer L2 can be connected to each other by a bonding scheme (or method). For example, a bonding scheme can refer to a method of electrically or physically connecting a bonding metal pattern (e.g., a first bonding pad PD_L1) formed in the first semiconductor layer L1 to a bonding metal pattern (e.g., a second bonding pad PD_L2) formed in the second semiconductor layer L2. For example, bonding pads PD_L1 and PD_L2 can be formed of copper (Cu), and the bonding scheme can be a Cu-Cu bonding scheme. Alternatively, bonding pads PD_L1 and PD_L2 can be formed of aluminum (Al) or tungsten (W).

[0139] For example, the memory cell array MCA (e.g., word line WL and local bit line LBL) of the first semiconductor layer L1 and the peripheral circuitry PCKT of the second semiconductor layer L2 can be electrically connected to each other via first bonding pad PD_L1 and second bonding pad PD_L2. For example, the memory cell MC and the transistor TR can be electrically connected to each other via first contact CT_L1 and second contact CT_L2, and first bonding pad PD_L1 and second bonding pad PD_L2. For example, the memory cell MC can be electrically connected to the first contact CT_L1 and the first bonding pad PD_L1, the transistor TR can be electrically connected to the second contact CT_L2 and the second bonding pad PD_L2, and the memory cell MC and the transistor TR can be electrically connected to each other by electrically connecting the first bonding pad PD_L1 and the second bonding pad PD_L2. Although not shown in detail, at least one conductive line and / or contact can be further formed to connect the memory cell MC to the first bonding pad PD_L1, and at least one conductive line and / or contact can be further formed to connect the transistor TR to the second bonding pad PD_L2.

[0140] However, the example embodiments are not limited thereto, and various bonding schemes (such as hybrid bonding schemes and dielectric bonding schemes) can be used to electrically or physically connect the first semiconductor layer L1 to the second semiconductor layer L2.

[0141] The semiconductor memory device 10 according to the example embodiment may have or employ a structure of stacked peripheral circuitry (PCKT) and memory cell array (MCA). For example, the memory cell array (MCA) is formed on a lower cell-on-periphery (POC) structure, and then the peripheral circuitry (PCKT) is stacked on the memory cell array (MCA). Therefore, the semiconductor memory device 10 can have a relatively small size. For example, a first semiconductor layer L1 can be fabricated by forming the memory cell array (MCA) on a first substrate SUB1, and a second semiconductor layer L2 can be fabricated by forming the peripheral circuitry (PCKT) on a second substrate SUB2. The first semiconductor layer L1 can be flipped, and bonding pads PD_L1 and PD_L2 can be connected using a bonding scheme. Therefore, the first semiconductor layer L1 and the second semiconductor layer L2 can be electrically connected in a first direction D1.

[0142] However, the example embodiment is not limited thereto. The semiconductor memory device 10 may have or employ a peripheral upper cell (COP) structure with the peripheral circuitry PCKT formed below, and then the memory cell array MCA is stacked on the peripheral circuitry PCKT.

[0143] Figure 19 This illustrates an example embodiment. Figure 16 and Figure 17 Circuit diagram of a semiconductor memory device.

[0144] Reference Figure 19 It shows that in Figure 16 and Figure 17 Examples of components connected to local bit lines LBL11 and LBL21 and global bit line GBL1 in a semiconductor memory device. For simplicity, the connections to... Figure 2 , Figure 16 , Figure 17 and Figure 18 The description is repetitive or overlapping.

[0145] Local bit lines LBL11 and LBL21, word lines WL11, WL21, WL31, WL12, WL22, WL32, WL13, WL23, WL33, WL14, WL24 and WL34, memory cells MC1a, MC1b, MC1c, MC2a, MC2b, MC2c, MC3a, MC3b, MC3c, MC4a, MC4b and MC4c, local bit line multiplexers MUX11 and MUX21, control lines CL1a, CL1b, CL2a and CL2b, control contacts CC11a, CC12a, CC21a and CC22a, and global bit line GBL1 may be disposed in the first semiconductor layer L1 (e.g., in the cell wafer) and may be disposed on the first substrate SUB1.

[0146] The sense amplifier SA1 may be disposed in the second semiconductor layer L2 (e.g., in the peripheral wafer) and may be disposed on a second substrate SUB2, which is different from the first substrate SUB1. In some example embodiments, the sense amplifier SA1 may be disposed below the second substrate SUB2 when the second semiconductor layer L2 is flipped and when the first semiconductor layer L1 and the second semiconductor layer L2 can be connected by a bonding scheme.

[0147] However, the example embodiment is not limited thereto, and at least one component may be additionally disposed in the second semiconductor layer L2.

[0148] In some exemplary embodiments, the semiconductor memory device according to the exemplary embodiments can be combined with reference to Figures 1 to 19 Implement two or more of the examples described.

[0149] Figure 20 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0150] Reference Figure 20 The semiconductor memory device 1200 may include peripheral circuitry 1201 and a memory cell array 1300. The peripheral circuitry 1201 may include control logic circuitry 1210, an address register 1220, a bank control logic circuit (BCLC) 1230, a row address multiplexer (RA MUX) 1240, a refresh counter 1245, a column address latch 1250, a row decoder (FBRD) 1260, a column decoder (FBCD) 1270, a sense amplifier unit (FBSA) 1285, an input / output (I / O) gating circuit 1290, and a data I / O buffer 1295. For example, the semiconductor memory device 1200 may be one of various volatile memory devices, such as a dynamic random access memory (DRAM) device.

[0151] The memory cell array 1300 may include first memory arrays 1310 to eighth memory arrays 1380 (e.g., first memory arrays to eighth memory arrays 1310, 1320, 1330, 1340, 1350, 1360, 1370, and 1380). The row decoder 1260 may include first memory cell row decoders 1260a to 1260h connected to the first memory arrays 1310 to 1380, respectively. The column decoder 1270 may include first memory cell column decoders 1270a to 1270h connected to the first memory arrays 1310 to 1380, respectively. The sense amplifier unit 1285 may include first memory cell sense amplifiers 1285a to 1285h connected to the first memory arrays 1310 to 1380, respectively.

[0152] First memory bank arrays 1310 to 1380, first memory bank row decoders 1260a to 1260h, first memory bank column decoders 1270a to 1270h, and first memory bank sense amplifiers 1285a to 1285h can form first to eighth memory banks. Each of the first memory bank arrays 1310 to 1380 can include multiple word lines WL, multiple bit lines BL, and multiple memory cells MC located at the intersections of word lines WL and bit lines BL. For example, each of the multiple bit lines BL can be connected to a local bit line LBL and a global bit line GBL selectively connected by a local bit line multiplexer. For example, when the local bit line multiplexer is selected, one of the multiple bit lines BL can be electrically connected to the local bit line LBL and the global bit line GBL.

[0153] Although Figure 20 A semiconductor memory device 1200 is shown that includes eight memory banks (and an array of eight memory banks, eight line decoders, etc.), but the semiconductor memory device 1200 may include any number of memory banks; for example, one, two, four, eight, sixteen or thirty-two memory banks, or any number between one and thirty-two.

[0154] Address register 1220 can be accessed from the memory controller (e.g., Figure 21The memory controller 2200 receives an address ADDR including the bank address BANK_ADDR, the row address ROW_ADDR, and the column address COL_ADDR. The address register 1220 can provide the received bank address BANK_ADDR to the bank control logic circuit 1230, the received row address ROW_ADDR to the row address multiplexer 1240, and the received column address COL_ADDR to the column address latch 1250.

[0155] The memory bank control logic circuit 1230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first memory bank row decoders 1260a to the eighth memory bank row decoder 1260h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and one of the first memory bank column decoders 1270a to the eighth memory bank column decoder 1270h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0156] The row address multiplexer 1240 can receive the row address ROW_ADDR from the address register 1220 and the refresh row address REF_ADDR from the refresh counter 1245. The row address multiplexer 1240 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row selection address RA. The row selection address RA output from the row address multiplexer 1240 can be applied to the row decoders 1260a to 1260h of the first to eighth memory banks.

[0157] One of the first to eighth bank row decoders 1260a can decode the row selection address RA output from the row address multiplexer 1240 and can activate the word line WL corresponding to the row selection address RA in the corresponding bank array. For example, the activated bank row decoder can generate a word line drive voltage and apply the word line drive voltage to the word line WL corresponding to the row selection address RA.

[0158] Column address latch 1250 can receive column address COL_ADDR from address register 1220 and can temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode, column address latch 1250 can generate a column address incremented from the received column address COL_ADDR. Column address latch 1250 can apply the temporarily stored or generated column address COL_ADDR' to the first memory bank column decoders 1270a to the eighth memory bank column decoders 1270h.

[0159] One of the first to eighth memory bank column decoders 1270a to 1270h is activated to decode the column address COL_ADDR' output from the column address latch 1250 and can control the I / O strobe circuit 1290 to output the data corresponding to the column address COL_ADDR'.

[0160] I / O strobing circuit 1290 may include circuitry configured to strobe input / output data. I / O strobing circuit 1290 may also include a read data latch configured to store data output from first memory array 1310 to eighth memory array 1380, and may also include a write driver for writing data to first memory array 1310 to eighth memory array 1380.

[0161] Data DAT read from one of the first memory arrays 1310 to the eighth memory array 1380 can be sensed by a sense amplifier connected to that memory array from which data DAT is to be read, and can be stored in a read data latch. The data DAT stored in the read data latch can be provided to the memory controller via a data I / O buffer 1295. Data DAT to be written to one of the first memory arrays 1310 to the eighth memory array 1380 can be provided from the memory controller to an I / O gating circuit 1290 via the data I / O buffer 1295, and the I / O gating circuit 1290 can write the data DAT to that memory array via a write driver.

[0162] Control logic circuitry 1210 can control the operation of semiconductor memory device 1200. For example, control logic circuitry 1210 can generate control signals for semiconductor memory device 1200 to perform write and / or read operations. Control logic circuitry 1210 may include command decoder 1211 for decoding command CMD received from memory controller, and mode register 1212 for setting the operating mode of semiconductor memory device 1200. In some example embodiments, the operations described herein as being performed by control logic circuitry 1210 may be performed by a processing circuitry system. For example, command decoder 1211 can generate control signals corresponding to command CMD by decoding write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc.

[0163] The semiconductor memory device 1200 can be the above reference. Figures 1 to 19The semiconductor memory device described is based on an example embodiment. For example, the memory cell array 1300 may have a structure where adjacent memory cells share local bit lines. Furthermore, the structure at the topmost level of the memory cell array 1300 can be used as a local bit line multiplexer. Further, two control contacts for signal application can be provided at both ends of a control line connected to the local bit line multiplexer. Therefore, the semiconductor memory device 1200 can have improved electrical characteristics and improved reliability. Figure 16 The sense amplifiers SA1 and SA2 can be included in sense amplifier unit 1285.

[0164] Figure 21 This is a block diagram illustrating a memory system according to an example embodiment.

[0165] Reference Figure 21 The memory system 2000 includes a memory controller 2200 and a semiconductor memory device 2400. The memory system 2000 may also include multiple signal lines 2300 that electrically connect the memory controller 2200 to the semiconductor memory device 2400.

[0166] Semiconductor memory device 2400 is controlled by memory controller 2200. For example, based on a request from a host (not shown), memory controller 2200 can store data (e.g., write or program) into semiconductor memory device 2400, or retrieve data from semiconductor memory device 2400 (e.g., read or sense). Semiconductor memory device 2400 can be the memory device described previously. For example, in semiconductor memory device 2400, adjacent memory cells can share local bit lines, the structure at the topmost level of the memory cell array can be used as a local bit line multiplexer, and a dual-side drive (TSD) scheme can be implemented, wherein two control contacts for signal application are located at both ends of a control line connected to the local bit line multiplexer. Therefore, semiconductor memory device 2400 can have improved electrical characteristics and improved reliability.

[0167] The multiple signal lines 2300 may include control lines, command lines, address lines, data input / output (I / O) lines, and power lines. The memory controller 2200 can transmit commands (CMD), addresses (ADDR), and control signals (CTRL) to the semiconductor memory device 2400 via the command lines, address lines, and control lines; exchange data signals (DS) with the semiconductor memory device 2400 via the data I / O lines; and transmit power supply voltage (PWR) to the semiconductor memory device 2400 via the power lines. Although not shown in detail, the multiple signal lines 2300 may also include a DQS line for transmitting a data strobe signal (DQS).

[0168] The example embodiments can be applied to a wide variety of electronic devices and systems, including semiconductor memory devices. For example, the example embodiments can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptops, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and the like.

[0169] Although the invention has been specifically shown and described with reference to its embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device, comprising: A plurality of memory cells are located on a substrate and are arranged along a first direction, a second direction and a third direction, wherein the first direction is perpendicular to the upper surface of the substrate, and the second direction and the third direction are parallel to the upper surface of the substrate and intersect each other. Multiple local bit lines are located on the substrate and connected to the multiple memory cells. Each of the multiple local bit lines extends along the first direction and is shared by memory cells adjacent to a first side and a second side of each of the multiple local bit lines. Multiple global bit lines located on the multiple local bit lines; Multiple word lines located on the substrate, the multiple word lines connecting to the multiple memory cells, each of the multiple word lines extending along the third direction; Multiple control lines located on the multiple word lines, each of the multiple control lines extending along the third direction; Multiple local bit line multiplexers are configured to control electrical connections between multiple local bit lines and multiple global bit lines, wherein at least two of the multiple local bit line multiplexers share one of the multiple control lines. A plurality of first control contacts, the plurality of first control contacts being connected to a first end of the plurality of control lines, each of the plurality of first control contacts extending along the first direction; as well as A plurality of second control contacts are connected to the second ends of the plurality of control lines, each of the plurality of second control contacts extending along the first direction.

2. The semiconductor memory device as claimed in claim 1, in, The plurality of local bit lines includes the first local bit line. The plurality of memory cells include a first memory cell connected to the first local bit line and arranged along the first direction adjacent to a first side of the first local bit line. The plurality of word lines include a first word line arranged along the first direction and connected to the first memory cell, and Among them, the multiple control lines include the first control line located on the first word line.

3. The semiconductor memory device as claimed in claim 2, in, The plurality of first control contacts include a third control contact connected to a first end of the first control line, and The plurality of second control contacts include a fourth control contact connected to the second end of the first control line.

4. The semiconductor memory device as claimed in claim 2, in, The plurality of global bit lines includes a first global bit line, and The plurality of local bit line multiplexers include a first local bit line multiplexer connected to the first control line and configured to control the electrical connection between the first local bit line and the first global bit line.

5. The semiconductor memory device of claim 4, wherein, The first local bit line multiplexer includes: A first transistor is connected between the first local bit line and the first global bit line, and the first transistor has a gate electrode connected to the first control line.

6. The semiconductor memory device of claim 5, wherein, The first local bit line multiplexer further includes: The second transistor is connected between the first local bit line and the precharge voltage.

7. The semiconductor memory device of claim 6, wherein, The multiple control lines also include: The second control line is connected to the gate electrode of the second transistor.

8. The semiconductor memory device of claim 7, wherein, The plurality of first control contacts include: The fifth control contact is connected to the first end of the second control line.

9. The semiconductor memory device of claim 8, wherein, The plurality of second control contacts include: The sixth control contact is connected to the second end of the second control line.

10. The semiconductor memory device as claimed in claim 7, in, The plurality of memory cells also includes a second memory cell connected to the first local bit line and arranged along the first direction adjacent to a second side of the first local bit line. The plurality of word lines further includes second word lines arranged along the first direction, spaced apart from each other, and connected to the second memory cell. The second control line is located on the second word line.

11. The semiconductor memory device of claim 1, further comprising: A plurality of word line contacts, each of which is connected to the plurality of word lines and extends along the first direction.

12. The semiconductor memory device of claim 11, wherein, The plurality of word line contacts include: First word line contact connected to the first end of the plurality of word lines; and A second word line contact connected to the second end of the plurality of word lines.

13. The semiconductor memory device as claimed in claim 12, in, The first word line contact is connected to the word line at the odd-numbered level among the plurality of word lines, and The second word line contact is connected to the word line at the even-numbered level among the plurality of word lines.

14. A semiconductor memory device, comprising: Local bit lines located on a substrate, each of the local bit lines extending along a first direction perpendicular to the upper surface of the substrate, the local bit lines being spaced apart from each other in a third direction and a third direction, the second direction and the third direction being parallel to the upper surface of the substrate and intersecting each other; A first memory cell located on the substrate, the first memory cell being connected to the local bit line, the first memory cell being arranged along the first direction and the third direction to be adjacent to a first side of the local bit line; A second memory cell located on the substrate, the second memory cell being connected to the local bit line, the second memory cell being arranged along the first direction and the third direction to be adjacent to a second side of the local bit line; A first word line located on the substrate, the first word line being arranged along the first direction, each of the first word lines extending along the third direction, and each of the first word lines being connected to a memory cell at the same level in the first memory cell; A second word line located on the substrate, the second word line being arranged along the first direction, each of the second word lines extending along the third direction, and each of the second word lines being connected to a memory cell at the same level in the second memory cell; Global bit lines, each of which is selectively connected to one of the local bit lines; A first control line located on the first character line, the first control line extending along the third direction; A selection transistor is configured to control the electrical connection between the local bit line and the global bit line, the first control line being shared by the selection transistor; as well as A first control contact and a second control contact are respectively connected to a first end and a second end of the first control line, and each of the first control contact and the second control contact extends along the first direction.

15. The semiconductor memory device of claim 14, further comprising: A second control line located on the second character line, the second control line extending along the third direction; as well as A holding transistor is connected between the local bit line and the precharge voltage, and the second control line is shared by the holding transistor.

16. The semiconductor memory device of claim 15, further comprising: The third control contact is connected to the first end of the second control line.

17. The semiconductor memory device of claim 16, further comprising: The fourth control contact is connected to the second end of the second control line.

18. The semiconductor memory device of claim 14, further comprising: A plurality of word line contacts are connected to the first word line and the second word line, each of the plurality of word line contacts extending along the first direction.

19. The semiconductor memory device of claim 18, wherein, The plurality of word line contacts include: A first word line contact, which is connected to the first end of the word line at an odd-numbered level among the first and second word lines; and The second word line contact is connected to the second end of the word line at the even-numbered level of the first and second word lines.

20. A memory system, comprising: Memory controller; as well as A semiconductor memory device configured to be controlled by the memory controller, the semiconductor memory device comprising: A plurality of memory cells are located on a substrate and are arranged along a first direction, a second direction and a third direction, wherein the first direction is perpendicular to the upper surface of the substrate, and the second direction and the third direction are parallel to the upper surface of the substrate and intersect each other. Multiple local bit lines are located on the substrate and connected to the multiple memory cells. Each of the multiple local bit lines extends along the first direction and is shared by memory cells adjacent to a first side and a second side of each of the multiple local bit lines. Multiple global bit lines located on the multiple local bit lines; Multiple word lines located on the substrate, the multiple word lines connecting to the multiple memory cells, each of the multiple word lines extending along the third direction; Multiple control lines located on the multiple word lines, each of the multiple control lines extending along the third direction; Multiple local bit line multiplexers are configured to control electrical connections between multiple local bit lines and multiple global bit lines, wherein at least two of the multiple local bit line multiplexers share one of the multiple control lines. A plurality of first control contacts, each of which is connected to a first end of a plurality of control lines and extends along the first direction; and A plurality of second control contacts are connected to the second ends of the plurality of control lines, each of the plurality of second control contacts extending along the first direction.

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