Double-warehouse rice milling data acquisition and transmission system

Abstract

The application relates to the field of grain processing automation and industrial data acquisition, and discloses a double-warehouse rice milling data acquisition and transmission system which comprises a double warehouse, an electronic flow scale, a high-frequency vibration sensor and an edge computing terminal. The edge computing terminal adopts a heterogeneous system-on-chip, integrates a field programmable gate array logic unit and a central processing unit. The central processing unit determines a physical transmission delay time according to flow data, adjusts the cache depth of a first-in-first-out queue buffer module, and makes a digital vibration sequence and flow data time-aligned; and according to the change amplitude of a flow mixing ratio, the central processing unit dynamically adjusts the analysis window length of a fast Fourier transform of the field programmable gate array logic unit; the field programmable gate array logic unit completes feature extraction by using the adjusted parameters, and the edge computing terminal sends operation results to a cloud database server. The application realizes physical space-time fusion and adaptive feature extraction of multi-source heterogeneous data, and improves monitoring precision.

Description

Technical Field

[0001] This invention relates to the fields of grain processing automation and industrial data acquisition, specifically a dual-silo rice milling data acquisition and transmission system. Background Technology

[0002] In the modern grain processing industry, rice milling processes using dual or multiple grain silos for combined feeding are widely used. By adjusting the mixing ratio of paddy rice with different physical properties, the taste and yield of the finished rice can be optimized. To monitor the stability of the processing and the health of the equipment, electronic flow scales are usually installed at the grain silo outlet to monitor the material flow, and vibration sensors are installed in core components of the rice milling machine (such as the whitening chamber) to collect data on the machine's operating status.

[0003] However, in actual production line layouts, there is a fixed physical distance between the grain silo outlet and the rice milling machine, and the material needs to undergo a certain physical transmission time to travel from the flow detection point to the milling processing point. Most existing data acquisition systems employ a synchronous sampling strategy based on absolute system time, assuming that flow data and vibration data collected at the same moment are correlated. This approach ignores the physical lag caused by material transmission, resulting in the collected flow fluctuation data not correctly corresponding to the mechanical vibration response that caused the fluctuation on the time axis. When performing multi-source data fusion analysis, this misalignment in time and space can lead to deviations in the causal relationship analysis between load changes and equipment responses, resulting in misjudgments in operating condition identification.

[0004] The rice milling process includes a long-term, stable constant flow processing stage and a transient switching stage with dynamic adjustments to the mixing ratio. Traditional vibration signal analysis typically employs a Fast Fourier Transform (FFT) algorithm with a fixed window length. While a longer analysis window can achieve higher frequency resolution to identify subtle mechanical wear characteristics, it leads to insufficient temporal resolution under transient conditions of rapidly changing mixing ratios, making it difficult to capture the impact characteristics during flow ratio switching. Conversely, a shorter analysis window, while improving temporal resolution, sacrifices frequency details. Existing monitoring technologies struggle to simultaneously achieve both steady-state high-frequency resolution and transient high temporal response within the same system. Furthermore, simply changing the analysis window length often causes a shift in the energy amplitude dimensions of the spectrum, resulting in a lack of a unified physical benchmark for characteristic data under different operating conditions, hindering continuous and effective comparisons.

[0005] High-frequency vibration monitoring generates massive amounts of data. Uploading all raw waveform data to a cloud server in real time would consume significant industrial network bandwidth and increase cloud storage costs. Uploading only processed statistical features would lack the raw waveform data to support in-depth fault tracing when equipment malfunctions. Furthermore, edge computing resources are limited; relying solely on general-purpose processors cannot simultaneously meet the demands of high-throughput signal preprocessing, complex feature extraction, and network communication protocol stack processing. This can easily create data processing bottlenecks, impacting the real-time performance and reliability of the monitoring system. Summary of the Invention

[0006] This invention provides a dual-silo rice milling data acquisition and transmission system, which solves the technical problems in existing grain processing monitoring caused by the spatiotemporal asynchrony of multi-source data, the distortion of feature extraction due to dynamic changes in operating conditions, and the limited bandwidth of data transmission on the edge side.

[0007] A dual-silo rice milling data acquisition and transmission system includes a first silo, a second silo, a first electronic flow scale, a second electronic flow scale, a rice milling machine, a high-frequency vibration sensor, and an edge computing terminal. The edge computing terminal includes a heterogeneous system-on-a-chip (SoC), which physically integrates a field-programmable gate array (FPGA) logic unit and a central processing unit (CPU), achieving separation between hardware logic operations and software logic control.

[0008] To address the time lag issue in the physical transmission of multi-source heterogeneous data, the central processing unit determines the physical transmission delay time based on the flow rate data and adjusts the buffer depth of the first-in-first-out (FIFO) queue buffer module within the field-programmable gate array (FPGA) logic unit. This processing mechanism controls the delay time of the digital vibration sequence in the buffer based on the transmission time of the material from the flow scale to the whitening chamber, ensuring that the digital vibration sequence entering the subsequent signal processing flow corresponds to the current flow rate data in the time dimension, thus eliminating data correlation deviations caused by material transmission lag.

[0009] To address the varying signal analysis resolution requirements during steady-state and transient conditions in the rice milling process, the central processing unit (CPU) monitors the variation in the flow mixing ratio and dynamically adjusts the analysis window length of the field-programmable gate array (FPGA) logic unit (FPGA) for Fast Fourier Transform (FFT). When the mixing ratio variation is small, the system uses a long window to achieve high frequency resolution and extract steady-state wear characteristics of mechanical components. When the mixing ratio variation exceeds a set threshold, the system switches to a short window to achieve high temporal resolution and respond to vibration changes during ratio switching. The FPGA then uses the adjusted analysis window length to perform feature extraction on the time-aligned digital vibration sequence, and the edge computing terminal sends the results to the cloud database server.

[0010] The edge computing terminal also includes a high-speed analog-to-digital converter (ADC), a communication interface circuit, a storage unit, and a network interface circuit integrated on the same printed circuit board. The high-speed ADC connects a high-frequency vibration sensor to a field-programmable gate array (FPGA) logic unit, converting analog voltage signals into digital vibration sequences. The communication interface circuit connects the first and second electronic flow scales to the central processing unit (CPU). The FPGA and CPU interact via an on-chip high-speed bus, performing parallel signal processing, logic control, and network protocol stack processing, respectively.

[0011] In the specific implementation of data alignment, the central processing unit calculates the sum of the first flow data from the first electronic flow scale and the second flow data from the second electronic flow scale as the total flow, and determines the physical transmission delay time according to a preset flow delay mapping relationship. The buffer depth of the first-in-first-out queue buffer module is set to the integer part of the product of the physical transmission delay time and the sampling rate of the high-speed analog-to-digital converter circuit, so that the delay time of the digital signal is consistent with the physical transmission time.

[0012] To address the issue of inconsistent energy dimensions caused by variations in the analysis window length, the field-programmable gate array (FPGA) logic unit internally operates normalized power spectral density (PSD) calculation logic. This logic performs a division operation on the raw power spectral density data output from the Fast Fourier Transform (FFT) using a dynamic normalization factor. The dynamic normalization factor is determined by multiplying the sampling rate of the high-speed analog-to-digital converter (ADC) circuit by the sum of the energy of the coefficient sequence of the currently used discrete window function. Through this operation, the physical dimensions of the normalized PSD data are independent of the analysis window length, maintaining consistency in the physical benchmark for feature comparison.

[0013] In addition, the field-programmable gate array (FPGA) logic unit internally operates physical band mapping logic to address the frequency band index drift problem caused by changes in frequency resolution. This logic calculates the frequency resolution value by dividing the sampling rate by the current analysis window length, uses this value to convert the frequency boundary values ​​of the preset physical characteristic frequency bands into a discrete spectral index range, and integrates the normalized power spectral density data within this range to generate physical band energy characteristic data.

[0014] To correct the physical transmission delay model, the central processing unit (CPU) runs adaptive calibration logic for delay parameters. This logic marks the moment of abrupt changes in flow by monitoring the time rate of change of total flow, and then monitors the short-time energy change rate of vibration data within a subsequent search window to mark the moment of vibration response. The CPU calculates the time difference between the vibration response moment and the moment of the flow abrupt change, and uses this difference to update the flow delay mapping relationship, correcting the deviation between the theoretical model and the actual process.

[0015] In terms of operating condition identification, the central processing unit runs a support vector machine classification logic. This logic receives a high-dimensional feature vector composed of mixed ratio values, total flow data, physical frequency band energy characteristic data, and spectral entropy characteristic data, and outputs a grinding state category representing the current operating condition of the system. This category includes at least a stable operating state and an abnormal state.

[0016] Based on the operating condition identification results, the system adopts a differential data transmission strategy to reduce network bandwidth consumption. The central processing unit internally runs transmission strategy scheduling logic. When the grinding state category is stable operation, the feature telemetry mode is executed, encapsulating only the high-dimensional feature vector into a lightweight telemetry data packet and sending it to the cloud database server to achieve state monitoring. When the grinding state category is abnormal, the fault recording mode is executed, triggering the retrospective extraction of the original digital vibration sequence while sending the lightweight telemetry data packet.

[0017] In the specific implementation of fault recording, the storage unit includes a double-rate synchronous dynamic random access memory (DRAM) with a large-capacity circular buffer. In fault recording mode, the central processing unit controls the direct memory access controller to calculate the start and end addresses of the read operation based on the timestamp of the anomaly, and directly reads the original digital vibration sequence within the historical time period from the large-capacity circular buffer. This sequence is then processed using a lossless compression algorithm and published to a cloud database server, providing the original waveform data before and after the fault for fault analysis.

[0018] This invention achieves the fusion of flow and vibration data through a heterogeneous computing architecture, balances time-frequency resolution using adaptive windowing technology, ensures feature consistency through normalization processing, and reduces data transmission and storage resource consumption while ensuring monitoring accuracy by combining differential transmission strategy.

[0019] This invention provides a dual-silo rice milling data acquisition and transmission system. It has the following beneficial effects: 1. This invention achieves physical time alignment between flow data and vibration data by calculating the physical transmission delay time through a central processing unit and dynamically adjusting the buffer depth of the first-in-first-out (FIFO) queue buffer module. This mechanism solves the material transmission lag problem caused by the different installation positions of the electronic flow scale and vibration sensor, ensuring that the digital vibration sequence entering the signal processing flow corresponds to the current flow data in physical time and space, avoiding misjudgment of operating conditions due to data association errors, and improving the accuracy of multi-source heterogeneous data fusion analysis.

[0020] 2. This invention dynamically adjusts the analysis window length of the Fast Fourier Transform (FFT) using a mixed ratio change rate, and performs normalized power spectral density calculations within a field-programmable gate array (FPGA) logic unit. When the flow ratio is stable, the system uses a long window to improve frequency resolution and monitor the steady-state characteristics of mechanical components; when the flow ratio changes, a short window is used to improve time resolution and respond to transient impacts. Combined with normalization processing and physical frequency band mapping, the energy dimension drift caused by changes in window length is eliminated, ensuring the physical consistency of characteristic data under different analysis modes, and balancing steady-state monitoring accuracy with transient response speed.

[0021] 3. This invention employs a heterogeneous system-on-a-chip (SoC) architecture combined with a differential data transmission strategy, optimizing the utilization efficiency of edge computing resources and network bandwidth. Field-programmable gate arrays (FPGAs) handle high-throughput signal preprocessing and feature extraction tasks, reducing the load on the central processing unit (CPU). Under stable operating conditions, the system only sends lightweight feature data, triggering the retrospective and compressed transmission of historical waveforms only when an abnormal state is detected. This reduces network bandwidth consumption and cloud storage costs while preserving crucial waveform details for fault tracing. Attached Figure Description

[0022] Figure 1 This is a diagram showing the overall hardware architecture and data flow of the data acquisition and transmission system according to an embodiment of the present invention. Figure 2 This is a logic diagram of the adaptive signal processing based on rheological coordination according to an embodiment of the present invention; Figure 3 This is a logic diagram of intelligent state recognition and differential transmission according to an embodiment of the present invention; Figure 4 This is a flowchart illustrating the dynamic operation of the data acquisition and transmission system of the present invention. Detailed Implementation

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Please see the appendix Figure 1 This invention provides a dual-silo rice milling data acquisition and transmission system, comprising: a first silo, a second silo, a first electronic flow scale, a second electronic flow scale, a rice milling machine, a whitening chamber, a high-frequency vibration sensor, an edge computing terminal, and a cloud database server.

[0025] Edge computing terminals establish communication connections with cloud database servers via wired or wireless communication networks. The first and second grain silos are used to store paddy rice with different physical properties, respectively. A first electronic flow scale is installed at the discharge port of the first grain silo to measure the flow rate of the first material from the first grain silo in real time. A second electronic flow scale is installed at the discharge port of the second grain silo to measure the flow rate of the second material from the second grain silo in real time. The whitening chamber, located inside the rice milling machine, receives the mixed first and second materials and performs peeling and whitening processing.

[0026] A high-frequency vibration sensor is rigidly fixed to the outer wall of the whitening chamber to collect mechanical vibration signals generated during the whitening process. The high-frequency vibration sensor is a piezoelectric accelerometer, with a frequency response range covering 0 Hz to 20000 Hz. An edge computing terminal is electrically connected to the first electronic flow scale, the second electronic flow scale, and the high-frequency vibration sensor.

[0027] Edge computing terminals include: heterogeneous system-on-a-chip (SoC), high-speed analog-to-digital converter (ADC), communication interface circuit, storage unit, and network interface circuit. These components are integrated onto the same printed circuit board.

[0028] The heterogeneous system-on-a-chip (SoC) comprises physically integrated field-programmable gate arrays (FPGAs) and a central processing unit (CPU). The FPGAs and CPU interact via an on-chip high-speed bus. The FPGAs perform parallel processing and feature extraction operations for high-frequency signals. The CPU performs logic control, model inference, and network transmission protocol stack operations for low-frequency data.

[0029] The input of the high-speed analog-to-digital converter (ADC) is connected to a high-frequency vibration sensor, and the output is connected to a field-programmable gate array (FPGA) logic unit in a heterogeneous system-on-a-chip (SoC). The ADC is configured to operate at a preset sampling rate. The analog voltage signal output by the high-frequency vibration sensor 7 is converted into a digital vibration sequence. And transmit it to the field programmable gate array logic unit.

[0030] The communication interface circuit is connected to both the first and second electronic flow scales, and also to the central processing unit (CPU) in the heterogeneous system-on-a-chip (SoC). The communication interface circuit uses either the RS485 serial communication standard or the Controller Area Network (CLAN) bus standard. The CPU periodically reads the first flow rate data output by the first electronic flow scale through the communication interface circuit. Second flow data output by the second electronic flow scale .

[0031] The storage unit is connected to a heterogeneous system-on-a-chip (SoC) and includes Double Data Rate (DDR) synchronous dynamic random access memory (DRAM) and non-volatile flash memory. The DDR is used to cache runtime data and construct a large-capacity circular buffer. The non-volatile flash memory is used to store the system boot image, bitstream files, and pre-trained support vector machine model parameters.

[0032] The field-programmable gate array (FPGA) logic unit is internally configured with a first-in-first-out (FIFO) queue buffer module. This FIFO queue buffer module is used to buffer digital vibration sequences from high-speed analog-to-digital converter circuits. The cache depth of the first-in-first-out queue buffer module. The central processing unit dynamically configures the system based on the physical transport delay of the materials.

[0033] The central processing unit based on the first flow data Second flow data Calculate total flow The physical transmission delay time is determined based on a preset traffic delay mapping relationship. Physical transmission delay time Defined as the time required for material to fall from the first or second electronic flow scale into the whitening chamber. Buffer depth of the first-in, first-out (FIFO) queue buffer module. The following relationship must be satisfied:

[0034] in, This indicates the number of sampling points that the first-in-first-out (FIFO) queue buffer module needs to buffer, expressed in units of points. This represents the physical transmission delay time, in seconds. The sampling rate of a high-speed analog-to-digital converter circuit is expressed in Hertz (Hz); symbol This indicates the floor function.

[0035] The field-programmable gate array (FPGA) logic unit also includes a Fast Fourier Transform (FFT) module and a spectral entropy calculation module. The FFT module performs frequency domain transformation on the vibration data output from the first-in-first-out (FIFO) queue buffer module. The spectral entropy calculation module calculates the spectral entropy characteristics of the vibration data.

[0036] The central processing unit internally operates a support vector machine (SVM) classification module and a data transmission control module. The SVM classification module determines the grinding state based on the feature data output by the field-programmable gate array (FPGA) logic unit. The data transmission control module sends data to the cloud database server via a network interface circuit.

[0037] Please see the appendix Figure 2The field-programmable gate array (FPGA) logic unit is internally configured with data synchronization and caching logic, which specifically includes: a high-speed data receiving interface, a ring buffer storage area, a write address controller, a read address controller, and a delay parameter configuration register.

[0038] The high-speed data receiving interface is connected to the digital output of the high-speed analog-to-digital converter circuit. The high-speed data receiving interface is configured to receive the raw digital vibration sequence at a clock frequency synchronized with the sampling rate. The ring buffer is constructed by cascading block random access memories integrated within the field-programmable gate array (FPGA) logic units, or by partitioning the space of an external double-rate synchronous dynamic random access memory (DRAM) accessed by the FPGA logic units via a high-bandwidth bus. The ring buffer is configured with a storage capacity sufficient to cover the maximum physical transmission delay.

[0039] The write address controller is connected to the high-speed data receiving interface and is configured to sequentially write the received digital vibration data to the ring buffer memory in each sampling clock cycle. The write address controller maintains a cyclically incrementing write address pointer, which automatically wraps back to the starting address when it reaches the maximum address of the ring buffer memory.

[0040] The delay parameter configuration register communicates with the central processing unit (CPU) via the on-chip interconnect bus. This register stores the delay offset calculated and issued by the CPU. The delay offset represents the number of sampling points corresponding to the physical time required for material to travel from the electronic flow scale position to the whitening chamber position. The value of the delay offset is equal to the integer part of the product of the physical transmission delay time and the sampling rate.

[0041] The read address controller is connected to both the write address controller and the delay parameter configuration register. The read address controller is configured to generate a read address pointer in each processing clock cycle. The value of the read address pointer equals the value of the write address pointer at the current moment minus the delay bias stored in the delay parameter configuration register. When the calculation result is negative, the read address controller automatically performs a modulo operation to locate the correct wraparound position in the ring buffer memory. Based on the generated read address pointer, the read address controller extracts vibration data from the ring buffer memory; the extracted vibration data is the time-aligned vibration data that is physically and causally strictly corresponding to the current flow data.

[0042] The central processing unit internally operates a closed-loop calibration logic for delay parameters. This logic is configured to monitor the rate of change of the total flow data (the sum of the first and second flow data) in real time. When the rate of change of the total flow data exceeds a preset flow mutation threshold, the closed-loop calibration logic marks the current moment as the flow mutation moment.

[0043] Within a preset search window following the flow mutation moment, the delay parameter closed-loop calibration logic performs sliding monitoring of the short-time energy of the time-aligned vibration data read from the circular buffer storage area. When the rate of change of the short-time energy exceeds a preset vibration response threshold, the delay parameter closed-loop calibration logic marks this moment as the vibration response moment. The delay parameter closed-loop calibration logic calculates the time difference between the vibration response moment and the flow mutation moment and uses this time difference as the corrected physical transmission delay time. The central processing unit recalculates the delay offset based on the corrected physical transmission delay time and writes the updated delay offset to the delay parameter configuration register, thereby dynamically adjusting the phase difference between the read address controller and the write address controller to eliminate the deviation between the theoretical model and the actual physical process.

[0044] The system provided by this invention has a mixed-proportion dynamic analysis logic configured inside the central processing unit and a variable-length truncation control logic configured inside the field-programmable gate array logic unit.

[0045] The dynamic analysis logic for the mixing ratio is configured to periodically acquire first and second flow data. It calculates the proportion of the first flow data in the sum of the first and second flow data to obtain the instantaneous mixing ratio value. The dynamic analysis logic further calculates the absolute change of the instantaneous mixing ratio value within a preset time sliding window, and divides this absolute change by the length of the preset time sliding window to obtain the mixing ratio change rate value.

[0046] The dynamic analysis logic for the mixing ratio internally stores a window length mapping relationship. This window length mapping relationship is configured to establish a correspondence between the mixing ratio change rate and the Fast Fourier Transform analysis window length using a piecewise step function. Specifically, a preset stability threshold is set. Set the mixing ratio change rate to a value of .

[0047] when At that time, the window length of the mapped output is [value missing]. ,in This is a preset maximum window length value (e.g., 4096 points) used to obtain the highest frequency resolution. At that time, the window length value of the mapping output satisfy:

[0048] The above mapping relationship ensures that as the mixing ratio change rate increases, the window length decreases by a power of 2, thereby enabling the system to achieve higher time resolution under transient conditions.

[0049] The central processing unit writes the calculated target window length value into the global configuration register inside the field-programmable gate array logic unit via the on-chip high-speed bus.

[0050] The variable-length truncation control logic is connected to the global configuration register, the data synchronization and caching logic, and the Fast Fourier Transform (FFT) module. Internally, the variable-length truncation control logic includes a counter state machine. This counter state machine reads the target window length value from the global configuration register in real time. It also counts the time-aligned vibration data output from the data synchronization and caching logic. When the number of received data points equals the target window length, the counter state machine generates a complete data packet and sends a transform start signal to the FFT module.

[0051] The variable-length truncation control logic is also configured to dynamically reconstruct the computational structure of the Fast Fourier Transform (FFT) module based on the target window length. Specifically, when the target window length changes, the variable-length truncation control logic adjusts the number of butterfly operation stages and the read address range of the twiddle factor coefficient table within the FFT module via a configuration interface. If the target window length decreases, the variable-length truncation control logic disables the butterfly operation stages at the end of the FFT module; if the target window length increases, the variable-length truncation control logic activates more butterfly operation stages. This dynamic reconstruction mechanism ensures that the system can seamlessly switch between analysis windows of different lengths in real time during continuous data stream processing without requiring a system reset.

[0052] The field-programmable gate array (FPGA) logic unit is internally configured with adaptive windowing operation logic, fast Fourier transform operation core, and normalized power spectral density calculation logic.

[0053] The input of the adaptive windowing logic is connected to the output of the variable-length truncation control logic. The adaptive windowing logic integrates a read-only memory (ROM) pre-stored with multiple sets of discrete window function coefficient tables. These tables correspond to different target window lengths supported by the system. Each table contains discrete sampled values ​​of either the Hanning or Hamming window function. The adaptive windowing logic is configured to address and read the corresponding length of the discrete window function coefficient sequence from the ROM based on the target window length value in the current global configuration register. The logic includes a parallel multiplier array configured to perform point-by-point multiplication on the input time-aligned vibration data and the read discrete window function coefficient sequence to generate a windowed vibration data sequence. The adaptive windowing logic improves the accuracy of subsequent spectral analysis by suppressing spectral leakage at signal truncation points.

[0054] The Fast Fourier Transform (FFT) computation core is connected to the adaptive windowing computation logic, and the FFT computation core adopts a radix-2 or radix-4 pipelined architecture. The FFT computation core is configured to receive windowed vibration data sequences and perform a Discrete Fourier Transform (DFT) operation on the corresponding number of points based on the target window length. The FFT computation core outputs a complex spectrum sequence of the transformed result, which contains the real and imaginary parts corresponding to different frequency components.

[0055] The normalized power spectral density calculation logic is connected to the core of the fast Fourier transform operation. This logic is used to eliminate inconsistencies in the physical meaning of spectral energy amplitudes caused by variations in window length. The normalized power spectral density calculation logic is first configured to perform modulus-square operation, that is, to calculate the sum of the squares of the real and imaginary parts of the data at each frequency point in the complex spectral sequence, thus obtaining the original power spectral data.

[0056] The normalized power spectral density calculation logic is further configured to perform energy normalized division. This energy normalized division operation uses a dynamic normalization factor as the divisor. Internally, the normalized power spectral density calculation logic maintains a normalization factor lookup table, which stores normalization coefficient values ​​corresponding one-to-one with different target window lengths. Each normalized coefficient value The calculation follows the following definition:

[0057] in, The sampling rate of the high-speed analog-to-digital converter circuit as defined above; This is the current target window length value; For the coefficient sequence of discrete window functions of corresponding length, the first... The coefficient value of the point.

[0058] The normalized power spectral density calculation logic retrieves the normalization factor lookup table based on the current target window length, divides the original power spectral data by the retrieved normalization coefficient value, and outputs the normalized power spectral density. This process unifies the physical dimensions of the normalized power spectral density data. Its physical dimensions do not change with the length of the Fast Fourier Transform analysis window, thus providing a unified physical benchmark for subsequent feature extraction.

[0059] The field-programmable gate array (FPGA) logic unit is internally configured with physical band mapping logic, band energy integration logic, and spectrum entropy calculation logic.

[0060] The physical band mapping logic is connected to both the global configuration register and the normalized power spectral density calculation logic. Internally, the physical band mapping logic has preset frequency boundary values ​​for multiple physical characteristic frequency bands, including but not limited to the low-frequency mechanical resonance band, the mid-frequency grinding and friction band, and the high-frequency grain fracture acoustic emission band. The physical band mapping logic is configured to calculate the current frequency resolution value in real time, which is equal to the sampling rate of the high-speed analog-to-digital converter divided by the current target window length.

[0061] The physical frequency band mapping logic converts preset physical characteristic frequency bands into discrete spectral index ranges using frequency resolution values. Specifically, the logic divides the starting frequency of each physical characteristic frequency band by the current frequency resolution value and rounds down to obtain the starting spectral index value; it also divides the ending frequency by the current frequency resolution value and rounds up to obtain the ending spectral index value. The logic outputs a dynamic index range for each physical characteristic frequency band. This dynamic index range automatically expands and contracts as the target window length changes, ensuring that it always covers the same physical frequency range.

[0062] The frequency band energy integration logic is connected to the physical frequency band mapping logic and the normalized power spectral density calculation logic. The frequency band energy integration logic is configured to perform a summation operation on the normalized power spectral density data within the corresponding dynamic index range for each physical characteristic frequency band, obtaining the spectral line energy and value. The frequency band energy integration logic is further configured to multiply the spectral line energy and value by the current frequency resolution value, outputting the physical frequency band energy characteristic data. By introducing the frequency resolution value as the calculation method for integration weights, the physical frequency band energy characteristic data restores the true power amplitude of the vibration signal within a specific physical frequency band, eliminating the energy dimension drift caused by changes in the Fast Fourier Transform window length.

[0063] The spectral entropy calculation logic is connected to the normalized power spectral density calculation logic. The spectral entropy calculation logic is used to assess the degree of disorder in the vibration energy distribution during the current grinding process. The spectral entropy calculation logic first performs full-band accumulation on the input normalized power spectral density data and calculates the ratio of the power spectral density value at each frequency point to the total energy of the entire frequency band, generating a probability distribution sequence.

[0064] The spectral entropy calculation logic integrates a logarithmic operation unit or logarithmic lookup table based on a coordinate rotation digital computer algorithm. The logic is configured to perform a base-2 logarithmic operation on each probability value in the probability distribution sequence and multiply the result by the original probability value. The logic then sums and inverts the products of all frequency points to obtain the spectral entropy feature data. This feature data quantifies the flatness of the spectrum; when broadband random noise caused by increased fragmentation occurs, the spectral entropy feature data will exhibit a significant numerical change.

[0065] Field-programmable gate array (FPGA) logic units package and write the calculated physical band energy characteristic data and spectral entropy characteristic data into the shared memory area of ​​the heterogeneous system-on-a-chip (SoC) through the on-chip direct memory access interface, so that the central processing unit can read them and perform subsequent pattern recognition.

[0066] The system provided by this invention has traffic data preprocessing logic, mixing ratio calculation logic, and delay parameter adaptive calibration logic running inside the central processing unit.

[0067] The flow data preprocessing logic is connected to the communication interfaces of the first and second electronic flow scales, respectively. The flow data preprocessing logic is configured to perform digital filtering on the acquired raw first and second flow data. The digital filtering uses either a moving average filtering algorithm or a Kalman filtering algorithm to eliminate random measurement noise caused by mechanical vibration or belt tension fluctuations in the electronic flow scales, outputting smoothed first and second flow data.

[0068] The mixing ratio calculation logic is connected to the flow data preprocessing logic. The mixing ratio calculation logic is configured to perform a division operation, dividing the smoothed first flow data by the sum of the smoothed first flow data and the smoothed second flow data to obtain the current mixing ratio value. The mixing ratio calculation logic further calculates the absolute value of the difference between the current mixing ratio value and the previous mixing ratio value, and divides this absolute value by the sampling time interval to obtain the mixing ratio change rate value. The mixing ratio calculation logic transmits the calculated mixing ratio change rate value to the aforementioned window length mapping logic, which drives the field-programmable gate array (FPGA) logic unit to dynamically adjust the analysis window.

[0069] The adaptive calibration logic for delay parameters addresses the problem that fixed flow delay models cannot adapt to changes in the physical properties of materials. Internally, this logic maintains a flow event history queue and a vibration characteristic history queue. The flow event history queue stores timestamped data on the total flow rate change, while the vibration characteristic history queue stores timestamped data on the physical frequency band energy characteristics.

[0070] The adaptive calibration logic for delay parameters is configured to perform event matching and correlation analysis. When the total flow rate change exceeds a preset flow step threshold, the adaptive calibration logic identifies a flow mutation event and records the first timestamp of the event. Subsequently, the adaptive calibration logic searches the vibration characteristic history queue within a time window centered on the first timestamp plus the current estimated delay time.

[0071] During the search process, the delay parameter adaptive calibration logic calculates the temporal gradient of the physical frequency band energy characteristic data. When the temporal gradient of the physical frequency band energy characteristic data exceeds a preset response threshold, the delay parameter adaptive calibration logic identifies a vibration response event and records a second timestamp of the vibration response event.

[0072] The adaptive calibration logic for delay parameters calculates the time difference between the second timestamp and the first timestamp to obtain the actual physical transmission delay time. This actual physical transmission delay time is then compared with the estimated delay time currently used by the system. If the deviation exceeds a preset tolerance range, the adaptive calibration logic updates a preset traffic delay mapping table using the actual physical transmission delay time. The updated traffic delay mapping table is used for delay parameter calculations in subsequent cycles, ensuring that the first-in-first-out queue buffer module in the field-programmable gate array (FPGA) logic unit always maintains accurate physical alignment.

[0073] Please see the appendix Figure 3 The system provided by this invention has feature vector assembly logic and support vector machine classification logic running inside the central processing unit.

[0074] The feature vector assembly logic is connected to both the mixing ratio calculation logic and the shared memory area. The feature vector assembly logic is configured to perform spatiotemporal fusion operations on multi-source heterogeneous data. Within one processing cycle, the feature vector assembly logic reads the current mixing ratio value, total flow data, physical frequency band energy characteristic data output by the field-programmable gate array (FPGA) logic unit, and spectral entropy characteristic data.

[0075] The feature vector assembly logic concatenates the data from the different physical dimensions according to a preset order to construct a high-dimensional feature vector. Since the aforementioned physical frequency band mapping logic and frequency band energy integration logic have eliminated the influence of changes in the Fast Fourier Transform window length on the energy dimension, the high-dimensional feature vector constructed by the feature vector assembly logic has resolution-independent characteristics. This means that regardless of whether the field-programmable gate array (FPGA) logic unit currently uses a long window mode or a short window mode, the energy components in the high-dimensional feature vector always represent the same physical frequency band power, thus allowing subsequent classification models to operate within a single unified feature space without needing to train multiple parallel classification models for different window lengths.

[0076] The Support Vector Machine (SVM) classification logic is connected to the feature vector assembly logic. The SVM classification logic internally loads pre-trained SVM model parameters, including support vector weights, bias terms, and kernel function parameters. The SVM classification logic uses radial basis functions as the kernel function to map the input high-dimensional feature vectors to a high-dimensional feature space.

[0077] The Support Vector Machine (SVM) classification logic calculates the geometric distance between the high-dimensional feature vector and the preset optimal hyperplane in the feature space, and determines the current milling state category based on the sign and magnitude of the geometric distance. Milling state categories include, but are not limited to, stable operation, abnormal flow ratio, and excessive broken rice rate. The SVM classification logic is configured to output discrete state labels or continuous anomaly probability scores.

[0078] The support vector machine classification logic is also equipped with a state smoothing filter. This filter employs a sliding window majority voting mechanism or a weighted average mechanism to smooth the state labels or anomaly probability scores over multiple consecutive periods. The state smoothing filter suppresses classification result jitter caused by sporadic signal spikes, only outputting a definitive anomaly trigger signal to the subsequent data transmission control module when an anomaly persists for more than a preset number of confirmation frames. This mechanism ensures that the system maintains sensitivity to transient faults while possessing an extremely low false alarm rate.

[0079] The system provided by this invention has transmission strategy scheduling logic, raw waveform backtracking extraction logic, data compression encoding logic, and network protocol stack processing logic running inside the central processing unit.

[0080] The input of the transmission strategy scheduling logic is connected to the output of the support vector machine (SVM) classification logic. The transmission strategy scheduling logic is configured to switch data transmission modes in real time based on the grinding state category or anomaly probability score output by the SVM classification logic. The transmission strategy scheduling logic predefines a feature telemetry mode and a fault recording mode. When the grinding state category indicates that the system is in a stable operating state, the transmission strategy scheduling logic activates the feature telemetry mode; when the grinding state category indicates that the system is in an abnormal or warning state, the transmission strategy scheduling logic activates the fault recording mode.

[0081] In feature-based telemetry mode, the transmission strategy scheduling logic only calls the network protocol stack processing logic to encapsulate the aforementioned high-dimensional feature vectors. The network protocol stack processing logic combines the mixed ratio value, total traffic data, physical frequency band energy characteristic data, spectral entropy characteristic data, and the current timestamp to generate a lightweight telemetry data packet. The data payload of the lightweight telemetry data packet is controlled at the kilobyte level, ensuring that the system consumes extremely low network bandwidth resources during long-term monitoring.

[0082] In fault recording mode, the transmission strategy scheduling logic sends a trigger command to the original waveform backtracking extraction logic while generating lightweight telemetry data packets. The original waveform backtracking extraction logic has direct memory access to the double-rate synchronous dynamic random access memory (DRAM) external to the heterogeneous system-on-a-chip. The DRAM maintains a large-capacity circular buffer written to by field-programmable gate array (FPGA) logic units, which stores the original digital vibration sequences of historical moments.

[0083] The original waveform backtracking extraction logic is configured to calculate the start and end addresses of the read operation in a large circular buffer based on the anomaly occurrence timestamp carried in the trigger command. The start address corresponds to a preset preceding record time length before the anomaly occurrence timestamp, and the end address corresponds to a preset following record time length after the anomaly occurrence timestamp. The original waveform backtracking extraction logic uses a direct memory access controller to losslessly copy the original digital vibration sequence within a specified time period from the large circular buffer, forming an event snapshot data block.

[0084] The data compression encoding logic is connected to the original waveform backtracking extraction logic. The data compression encoding logic is configured to perform lossless compression processing on the event snapshot data blocks. The lossless compression algorithm uses either the Lempel-Ziv-Welch algorithm or the Huffman coding algorithm to reduce the data volume without losing any vibrational detail information. The data compression encoding logic outputs the compressed event waveform data packet.

[0085] The network protocol stack processing logic is connected to the transmission strategy scheduling logic and the data compression encoding logic, respectively. The network protocol stack processing logic employs either a message queue telemetry transmission protocol or a hypertext transfer protocol. It is configured to establish a transmission control protocol connection with the cloud database server. The network protocol stack processing logic publishes lightweight telemetry data packets to the status monitoring topic and compressed event waveform data packets to the fault analysis topic. This event-driven differential transmission mechanism ensures that the cloud database server acquires high-bandwidth raw waveforms only when necessary, thereby achieving accurate monitoring around the clock in industrial environments where edge computing resources and network bandwidth are limited.

[0086] The dual-barrel rice milling data acquisition and transmission system provided by this invention performs a series of initialization and parameter configuration operations upon power-on startup to ensure that all hardware modules and software logic enter a predictable initial working state.

[0087] After the system powers on, the bootloader of the heterogeneous system-on-a-chip first loads the pre-compiled hardware bitstream file from non-volatile flash memory into the field-programmable gate array (FPGA) logic units. The hardware bitstream file defines the internal hardware logic structure of the FPGA logic units, including the complete circuit implementation of data synchronization and caching logic, adaptive window control logic, dynamic spectrum analysis logic, and feature mapping and extraction logic.

[0088] Simultaneously, the central processing unit's bootloader loads the operating system kernel and applications. During application initialization, a global configuration file is first read from a specific configuration area of ​​the non-volatile flash memory. The global configuration file stores the system's static runtime parameters in key-value pairs.

[0089] Static operating parameters include: the sampling rate of the high-speed analog-to-digital conversion circuit, the communication protocol type and device address of the first and second electronic flow scales, the IP address and port number of the network interface circuit used for network communication, and the address information of the cloud database server.

[0090] Static operating parameters also include algorithm-related thresholds and boundary conditions. Specifically, these include: flow step thresholds and vibration response thresholds for the delay parameter closed-loop calibration logic; stability thresholds, maximum window length values, minimum window length values, and sensitivity coefficients in the window length mapping relationship for the adaptive window control logic. Furthermore, they include frequency boundary values ​​for the physical feature bands used in the feature mapping and extraction logic, and the number of abnormal state confirmation frames used by the intelligent state recognition module.

[0091] The initialization logic of the central processing unit (CPU) writes the read static operating parameters into the global variable area in memory and configures the relevant hardware drivers and software modules based on these parameters. For example, it configures the control register of the high-speed analog-to-digital converter circuit according to the sampling rate value; and initializes the serial communication interface according to the communication protocol of the flow scale.

[0092] The central processing unit (CPU) further loads the pre-trained offline support vector machine (SVM) model file from non-volatile flash memory. The model file contains parameters such as the SVM kernel type, support vector weight matrix, and decision bias terms. The CPU loads these model parameters into the memory space of the SVM classification logic, completing the deployment of the classification model.

[0093] After completing the above configuration, the central processing unit sends an initialization command to the field-programmable gate array (FPGA) logic unit. This command includes the initial delay offset and the initial target window length. The initial delay offset is calculated based on a default or historical total throughput value. The initial target window length is typically set to a preset maximum window length, allowing the system to analyze at the highest frequency resolution during initial startup.

[0094] After receiving the initialization command, the Field Programmable Gate Array (FPGA) logic unit writes the initial delay bias to the delay parameter configuration register and the initial target window length to the global configuration register. At this point, both the FPGA logic unit and the central processing unit are ready, and the entire dual-barrel rice milling data acquisition and transmission system has completed initialization, awaiting the reception of real-time vibration and flow data, and entering the subsequent steady-state operation process.

[0095] Please see the appendix Figure 4 The dual-silo rice milling data acquisition and transmission system provided by this invention, after entering the steady-state operation phase, mainly performs a cyclical workflow of high-frequency resolution feature extraction and low-bandwidth telemetry data transmission. The steady-state operation phase is defined as the condition where the discharge flow rate of the dual silos remains constant or the rate of change of the mixing ratio is lower than a preset stability threshold.

[0096] During steady-state operation, the dynamic analysis logic for the mixing ratio within the central processing unit (CPU) first reads the current flow values ​​of the first and second electronic flow scales via the communication interface circuit at a preset polling cycle. The dynamic analysis logic calculates the current mixing ratio change rate and compares it with a preset stability threshold. When the mixing ratio change rate is less than or equal to the stability threshold, the dynamic analysis logic determines that the system is in a steady state. At this point, the dynamic analysis logic determines the target window length as the preset maximum window length based on the window length mapping relationship. The CPU writes this maximum window length value into the global configuration register within the field-programmable gate array (FPGA) logic unit.

[0097] After the variable-length truncation control logic inside the field-programmable gate array (FPGA) detects the maximum window length value in the global configuration register, the control data synchronization and caching logic accumulates a sufficient amount of time-aligned vibration data in the ring buffer storage area. When the number of data points reaches the maximum window length value, the variable-length truncation control logic triggers the Fast Fourier Transform (FFT) operation core to perform a long-point Discrete Fourier Transform. Due to the use of the maximum window length, the frequency resolution at this point reaches the highest accuracy of the system design. The high-precision frequency resolution allows the subsequent physical frequency band mapping logic to more finely divide the spectrum, thereby accurately capturing the minute wear characteristics of the mechanical components inside the grinding chamber under stable operation or the harmonic components of specific frequencies.

[0098] After the physical frequency band energy characteristic data and spectral entropy characteristic data are calculated by the field-programmable gate array (FPGA) logic unit, they are written to the shared memory area of ​​the heterogeneous system-on-a-chip (SoC). The feature vector assembly logic inside the central processing unit (CPU) reads this feature data and combines it with the current flow data to construct a high-dimensional feature vector. The support vector machine (SVM) classification logic then infers from this high-dimensional feature vector. Under steady-state operation, due to the smooth mechanical operation and constant material load, the high-dimensional feature vector in the feature space typically falls within the hyperplane region of a predefined steady-state category. The SVM classification logic outputs a state label representing the steady-state operation.

[0099] Upon receiving the stable operation status label, the transmission strategy scheduling logic automatically locks into feature telemetry mode. In feature telemetry mode, the transmission strategy scheduling logic only instructs the network protocol stack processing logic to package and send the high-dimensional feature vector to the cloud database server. At this time, the original waveform backtracking extraction logic is in standby mode and does not perform any large-capacity reading or transmission operations on the original digital vibration sequence.

[0100] This steady-state processing ensures that the system can monitor subtle changes in the rice milling process with the highest spectral accuracy for the vast majority of production time, while saving network uplink bandwidth and cloud storage resources, retaining only the most statistically significant feature data for long-term equipment health trend analysis.

[0101] When the dual-silo rice milling data acquisition and transmission system provided by this invention encounters drastic fluctuations in the mixing ratio of the two silos or abnormal characteristics in the milling process, the system automatically leaves the steady-state operation mode and enters the transient response process or abnormal working condition response process.

[0102] When the dynamic analysis logic of the mixing ratio inside the central processing unit detects that the rate of change of the mixing ratio exceeds a preset stability threshold, the system determines that it is currently in a transient operating condition phase. At this time, the dynamic analysis logic of the mixing ratio outputs a smaller target window length value based on the nonlinear window length mapping relationship stored internally. This smaller target window length value is immediately written into the global configuration register inside the field-programmable gate array (FPGA) logic unit. The variable length truncation control logic inside the FPGA logic unit responds to the change, reducing the number of truncation points for time-aligned vibration data and reconstructing the number of operation stages of the fast Fourier transform operation core. This adjustment significantly improves the system's time resolution, enabling it to capture transient vibration characteristics generated during the flow ratio switching at a higher time refresh rate. Although the reduced analysis window length leads to a decrease in frequency resolution, the physical frequency band energy characteristic data in the shared memory area of ​​the heterogeneous system-on-a-chip (SoC) still maintains the consistency of physical dimensions due to the resolution-independent normalization processing mechanism of the aforementioned feature mapping and extraction logic, ensuring the continuous comparability of the data on the time axis.

[0103] When the support vector machine (SVM) classification logic calculates a state category based on high-dimensional feature vectors indicating an abnormal flow ratio or excessive broken rice rate, the system enters the abnormal operating condition response process. The SVM classification logic first confirms the classification results of multiple consecutive processing cycles using a state smoothing filter. Only when the duration of the abnormal state exceeds a preset number of confirmation frames does the SVM classification logic send a fault trigger signal to the transmission strategy scheduling logic.

[0104] Upon receiving a fault trigger signal, the transmission strategy scheduling logic immediately switches its operating mode to fault recording mode. In fault recording mode, the transmission strategy scheduling logic activates the original waveform backtracking extraction logic. This logic reads the current system timestamp as the time of the anomaly and, based on preset preceding and following recording time lengths, calculates the start and end physical addresses of the read operation in the large-capacity circular buffer of the double-rate synchronous dynamic random access memory.

[0105] The original waveform backtracking extraction logic utilizes a direct memory access controller to bypass the central processing unit's cache system and directly retrieve the original digital vibration sequence within a specified address range from a large-capacity circular buffer. This mechanism enables the system not only to record data after a fault occurs but also to completely backtrack the evolution of the vibration waveform just before the fault occurred, providing crucial time-domain details for subsequent fault cause analysis.

[0106] The acquired raw digital vibration sequence is fed into data compression encoding logic for lossless compression, generating a reduced-size event waveform data packet. The network protocol stack processing logic establishes a high-priority transmission control protocol connection, publishing the event waveform data packet containing detailed fault information to the fault analysis topic on the cloud database server. Simultaneously, the transmission of lightweight telemetry data packets continues in the background, ensuring the continuity of system status monitoring. Once the state determined by the support vector machine classification logic returns to a stable operating state, the transmission strategy scheduling logic automatically stops the operation of the raw waveform backtracking extraction logic and switches the system back to the feature telemetry mode that only sends feature data, thus completing a full closed-loop response process.

[0107] This embodiment presents performance tests based on a real-world prototype system and simulation environment. The test platform includes a simulated dual-barrel feeding system and an industrial-grade heterogeneous SoC (using a Xilinx Zynq-7000 series chip). The control group is configured with a pure software processing scheme, i.e., the FPGA logic units are disabled, and only the homogeneous ARM processor is used to perform signal acquisition, Fast Fourier Transform (FFT), and data transmission tasks.

[0108] Computational load and heterogeneous collaborative performance analysis: The test conditions were set as follows: high-frequency vibration sensor sampling rate of 20kHz, FFT analysis points of 4096 points. The test lasted for 1 hour, during which 5 step changes in the flow mixing ratio were simulated.

[0109] Table 1 shows a comparison of the computational resource consumption of the two schemes: Table 1. Comparison of Computational Resource Usage

[0110] Experimental data shows that in the scheme of this invention, the Field Programmable Gate Array (FPGA) logic unit undertakes most of the signal preprocessing tasks, including windowing, FFT operation, modulus squaring, and frequency band integration. This reduces the average load of the central processing unit to 18.6%, avoiding network protocol stack congestion or data packet loss caused by exhaustion of computing resources.

[0111] Bandwidth usage and storage cost analysis: The test simulated a 24-hour continuous operation scenario. The system was set to operate stably for 98% of the time, and in an abnormal or fluctuating state for 2%. The control group used a full raw data upload mode; the experimental group used the differential transmission strategy of this invention.

[0112] Table 2. Comparison of Network Bandwidth and Cloud Storage Data

[0113] Test results show that, through the transmission strategy scheduling logic, the system can reduce the average daily data transmission volume by about 96.5% while retaining the original waveform during the fault period for source tracing analysis, effectively reducing the communication bandwidth requirements of the industrial site and the storage pressure on the cloud database.

[0114] Physical alignment and feature consistency verification: The test introduces the Pearson correlation coefficient to measure the time synchronization between flow data and vibration characteristic data; and introduces the characteristic variation coefficient to measure the fluctuation of characteristic values ​​caused by window length switching under steady-state conditions.

[0115] Data alignment accuracy: The correlation coefficient of the control group was 0.65, indicating that there was a time lag between the flow and vibration data; after enabling the adaptive calibration logic of the delay parameter in the experimental group of this invention, the correlation coefficient increased to 0.94, which verified the effectiveness of physical transmission delay compensation.

[0116] Feature consistency: Forced switching between long and short windows was performed under steady-state conditions. The eigenvalue fluctuation of the control group (unnormalized) exceeded 300%; the coefficient of variation of the eigenvalues ​​of the experimental group of this invention (with normalized power spectral density calculation enabled) was 1.2%. This data confirms that normalization processing and physical band mapping logic can eliminate the influence of window length changes on energy dimensions, ensuring the physical consistency of feature data under different analysis modes.

Claims

1. A dual-barrel rice milling data acquisition and transmission system, characterized in that, It includes a first grain silo, a second grain silo, a first electronic flow scale, a second electronic flow scale, a rice milling machine, a high-frequency vibration sensor, and an edge computing terminal. The edge computing terminal includes a heterogeneous system-on-a-chip (SoC), which integrates a field-programmable gate array (FPGA) logic unit and a central processing unit. The central processing unit determines the physical transmission delay time based on the traffic data and adjusts the buffer depth of the first-in-first-out queue buffer module inside the field-programmable gate array logic unit to align the digital vibration sequence with the traffic data time. The central processing unit monitors the change in the traffic mixing ratio and dynamically adjusts the analysis window length of the field-programmable gate array logic unit for fast Fourier transform based on the change. The field-programmable gate array logic unit uses the adjusted analysis window length to perform feature extraction operations on the time-aligned digital vibration sequence, and the edge computing terminal sends the operation results to the cloud database server.

2. The dual-barrel rice milling data acquisition and transmission system according to claim 1, characterized in that, The edge computing terminal also includes a high-speed analog-to-digital conversion circuit, a communication interface circuit, a storage unit, and a network interface circuit integrated on the same printed circuit board. The high-speed analog-to-digital converter circuit connects the high-frequency vibration sensor and the field-programmable gate array logic unit to convert the analog voltage signal into a digital vibration sequence. The communication interface circuit connects the first electronic flow scale, the second electronic flow scale, and the central processing unit. The field-programmable gate array (FPGA) logic unit interacts with the central processing unit (CPU) via an on-chip high-speed bus. The FPGA logic unit performs parallel signal processing, while the CPU performs logic control and network protocol stack processing.

3. The dual-barrel rice milling data acquisition and transmission system according to claim 2, characterized in that, The central processing unit determines the cache depth in the following ways: The central processing unit calculates the sum of the first flow data of the first electronic flow scale and the second flow data of the second electronic flow scale as the total flow; The central processing unit determines the physical transmission delay time based on the flow delay mapping relationship. The physical transmission delay time represents the time required for the material to travel from the position of the electronic flow scale to the position of the whitening chamber. The buffer depth is equal to the integer part of the product of the physical transmission delay time and the sampling rate of the high-speed analog-to-digital converter circuit.

4. The dual-barrel rice milling data acquisition and transmission system according to claim 3, characterized in that, The central processing unit adjusts the analysis window length according to the following rules: The central processing unit calculates the rate of change of the mixing ratio value within a time sliding window; When the rate of change is lower than the stability threshold, the central processing unit sets the analysis window length to a preset maximum window length value. When the rate of change is higher than the stability threshold, the central processing unit reduces the length of the analysis window in a stepwise manner according to the increase of the rate of change, and the reduced length of the analysis window remains an integer power of 2.

5. The dual-barrel rice milling data acquisition and transmission system according to claim 4, characterized in that, The field-programmable gate array logic unit internally runs normalized power spectral density calculation logic; The normalized power spectral density calculation logic uses a dynamic normalization factor to perform a division operation on the original power spectral data output by the fast Fourier transform; The dynamic normalization factor is equal to the product of the sampling rate of the high-speed analog-to-digital converter circuit and the sum of the energy of the coefficient sequence of the currently used discrete window function; The physical dimensions of the normalized power spectral density data obtained by the division operation do not change with the length of the analysis window.

6. The dual-barrel rice milling data acquisition and transmission system according to claim 5, characterized in that, The field-programmable gate array logic unit internally operates physical frequency band mapping logic; The physical frequency band mapping logic calculates the frequency resolution value by dividing the sampling rate by the current analysis window length. The physical frequency band mapping logic uses the frequency resolution value to convert the frequency boundary value of the preset physical characteristic frequency band into a discrete spectrum index range, and integrates the normalized power spectral density data within the discrete spectrum index range to generate physical frequency band energy characteristic data.

7. A dual-barrel rice milling data acquisition and transmission system according to claim 3, characterized in that, The central processing unit internally operates delay parameter adaptive calibration logic, which performs the following steps: When the time change rate of the total flow exceeds the flow step threshold, mark the moment of the flow change. Within the search window following the moment of the sudden change in flow rate, the short-time energy change rate of the vibration data is monitored, and the vibration response moment is marked when it exceeds the vibration response threshold. The central processing unit calculates the time difference between the vibration response time and the flow rate change time, and uses the time difference to update the flow rate delay mapping relationship.

8. A dual-barrel rice milling data acquisition and transmission system according to claim 6, characterized in that, The central processing unit internally runs support vector machine classification logic; The support vector machine classification logic receives a high-dimensional feature vector composed of the mixing ratio value, total flow data, physical frequency band energy feature data, and spectral entropy feature data. The output of the support vector machine classification logic represents the grinding state category of the current operating condition of the system, and the grinding state category includes at least a stable operating state and an abnormal state.

9. A dual-barrel rice milling data acquisition and transmission system according to claim 8, characterized in that, The central processing unit internally runs transmission strategy scheduling logic. When the grinding state category is the stable operation state, the transmission strategy scheduling logic executes the feature telemetry mode, which only encapsulates the high-dimensional feature vector into a lightweight telemetry data packet and sends it to the cloud database server. When the grinding state category is the abnormal state, the transmission strategy scheduling logic executes the fault recording mode, and triggers the backtracking extraction of the original digital vibration sequence while sending the lightweight telemetry data packet.

10. A dual-barrel rice milling data acquisition and transmission system according to claim 9, characterized in that, The storage unit includes a double-rate synchronous dynamic random access memory, in which a large-capacity circular buffer is constructed. In the fault recording mode, the central processing unit controls the direct memory access controller to calculate the start address and end address of the read based on the timestamp of the abnormality, and directly reads the original digital vibration sequence within the historical time period from the large-capacity circular buffer. The original digital vibration sequence is processed by a lossless compression algorithm and then published to the cloud database server.

Images