A current-voltage effective value calculation method and device for a smart meter chip
By combining a self-multiplication module and a second-order low-pass filter with a successive approximation method to calculate the effective values of current and voltage, the accuracy and stability problems of smart meters under non-ideal power grid conditions are solved, achieving efficient and low-cost electricity metering.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING XINLONG SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2026-03-18
- Publication Date
- 2026-06-19
AI Technical Summary
Existing smart meters struggle to simultaneously achieve high accuracy, low latency, low resource consumption, and high robustness in calculating the effective values of current and voltage under non-ideal power grid conditions. In particular, their metering accuracy and stability are insufficient under frequency fluctuations, harmonic distortion, and transient interference.
The method employs a self-multiplication module to perform point-by-point squaring operations on the current and voltage signals, filters out high-frequency AC components using a second-order low-pass filter while retaining DC components, and uses a successive approximation method to perform square root operations, thereby realizing the calculation of the effective values of voltage and current.
It significantly improves computational accuracy and robustness, reduces hardware resource consumption, improves real-time performance and response speed, and is suitable for scenarios with rapid load changes and impulsive power fluctuations, meeting the needs of different metering accuracy standards.
Smart Images
Figure CN122238700A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of smart meter metering and relates to a method and apparatus for calculating the effective values of current and voltage of a smart meter chip. Background Technology
[0002] In modern smart meters, the root mean square (RMS) values of voltage and current are among the most critical parameters for accurate energy metering, power quality analysis, and real-time load monitoring. The accurate calculation of these RMS values directly impacts the fairness of metering, the system's adaptability to nonlinear loads, and the reliability of fault diagnosis.
[0003] Currently, the vast majority of commercial smart meters adopt the following two mainstream effective value calculation schemes: The first type is the direct discrete RMS algorithm based on a fixed sampling rate. This method uses an analog-to-digital converter (ADC) to sample the voltage or current signal at equal intervals at a fixed frequency, obtaining a discrete sampling sequence within one or more periods, and then directly applies the RMS definition formula. RMS = √[(1 / N)Σ(x_i²)] The effective value is obtained by squaring, summing, averaging, and then taking the square root of the sampled points. This method is relatively simple to implement in hardware and requires low computational resources, but its accuracy is highly dependent on whether the sampling window contains an integer number of signal cycles. When the grid frequency deviates (e.g., the actual frequency deviates from 50Hz or 60Hz) or the signal contains abundant harmonic components, a fixed sampling window is prone to spectral leakage and the picket fence effect, leading to significant deviations in the effective value calculation. In common nonlinear load scenarios where the harmonic distortion rate (THD) exceeds 5%–10%, the error of this type of algorithm often exceeds 0.5%–1%, making it difficult to meet the accuracy requirements of 0.2S or even 0.1-level energy meters.
[0004] The second category involves sampling and calculation schemes that incorporate synchronization mechanisms. To overcome the inherent errors caused by asynchronous sampling, some mid-to-high-end smart meters have added hardware phase-locked loops (PLLs) or software-implemented zero-crossing detection and frequency tracking algorithms to dynamically adjust the ADC's sampling frequency or number of sampling points, ensuring the sampling window is aligned as closely as possible to the fundamental integer period of the power grid. Performing RMS calculations on this basis can reduce errors caused by frequency drift and harmonics to some extent. However, this type of scheme has the following significant drawbacks: 1) Hardware phase-locked loop circuits significantly increase the area, power consumption, and design complexity of the chip's analog section, thereby increasing the overall cost of the chip; 2) Software zero-crossing detection is prone to misjudgment or missed judgment when there is DC offset, severe harmonic distortion or noise interference, resulting in frequency tracking failure or instability; 3) Regardless of whether it is a hardware or software synchronization mechanism, the locking and stabilization process takes a certain amount of time (usually tens to hundreds of milliseconds), which is not conducive to real-time response to rapid transient load changes; 4) Under the influence of short-term impact interference (such as switching of high-power equipment, short-circuit faults, electric arcs, etc.), the synchronization mechanism often loses lock briefly, causing drastic jumps in the effective value calculation, affecting the stability of metering and the reliability of anti-theft criteria.
[0005] In addition, the following common problems exist in existing technologies: There is an irreconcilable contradiction between computation window length and real-time performance and accuracy. Using a longer window (covering multiple cycles) can improve accuracy and harmonic rejection, but it will significantly increase response delay and is not suitable for scenarios that require rapid response to power changes; conversely, shortening the window can improve real-time performance, but it will significantly sacrifice accuracy and anti-interference ability. The algorithm lacks an adaptive calculation strategy based on the actual operating conditions of the power grid (frequency deviation, harmonic content, interference intensity, etc.), resulting in poor robustness. Most high-precision implementation schemes rely on complex computing units (such as high-order filters, CORDIC square root extractors, large-capacity square root lookup tables, etc.), which leads to a significant increase in the number of logic gates and chip area in the digital part, which contradicts the strong demand of smart meters for low cost and low power consumption.
[0006] In summary, existing smart meter RMS calculation technologies still fall short in their ability to simultaneously achieve high accuracy, low latency, low resource consumption, and high robustness under non-ideal power grid conditions (frequency fluctuations, harmonic distortion, transient interference, DC offset, etc.). A new computing architecture and technical approach are urgently needed to address these contradictions. Summary of the Invention
[0007] In view of this, the purpose of the present invention is to provide a method and apparatus for calculating the effective values of current and voltage of a smart meter chip.
[0008] To achieve the above objectives, the present invention provides the following technical solution: A method for calculating the effective values of current and voltage in a smart meter chip, the method comprising the following steps: The original voltage digital signal U or current digital signal I obtained by the analog-to-digital converter in the smart meter chip is input to the self-multiplication module. The self-multiplication module performs point-by-point squaring operation to obtain the output result U² or I² of the self-multiplication module. The output result U² or I² of the self-multiplication module is input into a second-order low-pass filter. The high-frequency AC component in the output result U² or I² of the self-multiplication module is filtered out by the second-order low-pass filter, while the DC component in the output result U² or I² of the self-multiplication module is retained, thus obtaining the output result of the second-order low-pass filter. The output of the second-order low-pass filter is sent to the square root module, which performs a square root operation on the output of the second-order low-pass filter to obtain the root mean square (RMS) of voltage or the root mean square (RMS) of current.
[0009] Furthermore, the output result U² or I² of the self-multiplication module is equivalent to a DC signal and a high-frequency component.
[0010] Furthermore, the second-order low-pass filter adopts the Chebyshev type II filter model.
[0011] Furthermore, the cutoff frequency of the second-order low-pass filter is lower than the fundamental frequency of the power grid.
[0012] Furthermore, the square root module employs a successive approximation method to perform the square root operation.
[0013] A current and voltage RMS value calculation model based on a smart meter chip, the calculation model includes a self-multiplication module, a second-order low-pass filter, and a square root module; The input terminal of the self-multiplication module is used to receive the original voltage digital signal U or current digital signal I obtained by the analog-to-digital converter from the smart meter chip. The self-multiplication module is used to perform a point-by-point squaring operation on the original voltage digital signal U or current digital signal I to obtain the output result U of the self-multiplication module. 2 Or I 2 ; The input of the second-order low-pass filter is connected to the output of the self-multiplication module. The second-order low-pass filter is used to filter out the high-frequency AC components in the output result U² or I² of the self-multiplication module, while retaining the output result U² of the self-multiplication module. 2 Or I 2 The DC component in the filter is used to obtain the output of the second-order low-pass filter. The input terminal of the square root module is connected to the output terminal of the second-order low-pass filter. The square root module is used to perform square root operation on the output result of the second-order low-pass filter to obtain the effective voltage value RMS or the effective current value RMS.
[0014] Furthermore, the output result U² or I² of the self-multiplication module is equivalent to a DC signal and a high-frequency component.
[0015] Furthermore, the second-order low-pass filter adopts the Chebyshev type II filter model.
[0016] Furthermore, the cutoff frequency of the second-order low-pass filter is lower than the fundamental frequency of the power grid.
[0017] Furthermore, the square root module employs a successive approximation method to perform the square root operation.
[0018] The beneficial effects of this invention are as follows: (1) Significantly improved RMS calculation accuracy under non-ideal power grid conditions. By directly performing point-by-point squaring on the sampled signal in the front-end, the energy of the fundamental wave and each harmonic component is uniformly shifted to the DC and high-frequency even harmonic regions, so that only a low-order low-pass filter is needed to efficiently extract the DC component corresponding to the square of the RMS value. This processing method naturally suppresses the interference of harmonics on the RMS calculation. Even in severely distorted power grids with a total harmonic distortion rate (THD) of 15% to 20%, it can still maintain high measurement accuracy, which is better than the traditional direct discrete RMS algorithm and some synchronous sampling schemes without spectrum reconstruction.
[0019] (2) While ensuring computational accuracy, the hardware resource consumption and chip area are significantly reduced. Compared with traditional high-precision schemes that require high-order filters or complex synchronization circuits, this invention only uses a second-order Chebyshev II type low-pass filter to achieve sufficient attenuation of components above 100Hz in the square signal. The filter coefficient bit width and logic implementation scale are both small. At the same time, the square root operation adopts the successive approximation method, avoiding the large number of iterative multiplication and addition operations or large-capacity ROM lookup tables required by the CORDIC algorithm. The overall number of logic gates in the digital circuit part is significantly reduced, which is conducive to reducing the manufacturing cost and power consumption of smart meter metering chips.
[0020] (3) Significantly improves the real-time performance and response speed of the system. Since the core computation link only includes point-by-point squaring, second-order filtering, and a finite number of iterations of square root extraction, the delay of the entire calculation process is mainly determined by the settling time of the second-order filter. It usually only takes a few to a dozen fundamental cycles to reach steady-state output, which is much lower than the delay of traditional multi-cycle averaging or long-window synchronous RMS algorithms. This feature makes the present invention particularly suitable for scenarios that require rapid detection of load changes, impulsive power fluctuations, or short-term fault currents.
[0021] (4) The algorithm is more robust to various power grid disturbances. The self-multiplication operation itself is not sensitive to DC offset (the DC component is still DC after squaring, which can be retained by the low-pass filter and correctly participate in the effective value calculation); the squaring operation shifts the power spectrum of random noise and Gaussian white noise to the high-frequency region, making it easier to be suppressed by the low-pass filter; for transient impacts or spike interference, the impact of outliers after squaring will be significantly smoothed by subsequent low-pass filtering, and the RMS output jump amplitude is much smaller than the traditional method of directly calculating the root mean square of the original sampling points, thereby improving the stability of metering data and the reliability of anti-theft and anti-tampering criteria.
[0022] (5) It has good process portability and standardization adaptability. The computing link proposed in this invention is composed entirely of basic digital signal processing modules (multipliers, low-pass filters, and iterative square root extractors), without relying on specific analog phase-locked loops or high-precision analog front-end circuits, making it easy to reuse in different process nodes, different manufacturers' power metering SoCs, or dedicated metering chips. At the same time, by adjusting the filter cutoff frequency parameters and the number of square root iterations, it is possible to flexibly balance between various metering accuracy standards such as 0.5 level, 0.2 level, and even 0.1 level, to meet the needs of different markets and application scenarios.
[0023] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description
[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a block diagram illustrating the principle of a current and voltage RMS value calculation model based on a smart meter chip according to the present invention. Figure 2 This is a schematic diagram of the structure of a second-order low-pass filter in an embodiment of the present invention; Figure 3 This is a graph showing the amplitude-frequency response characteristics of a second-order Chebyshev type II low-pass filter in an embodiment of the present invention. Detailed Implementation
[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0026] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.
[0027] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.
[0028] Example 1 This embodiment provides a method for calculating the effective values of current and voltage based on a smart meter chip, applicable to the digital signal processing module inside the metering chip of a single-phase or three-phase smart energy meter.
[0029] Taking the voltage channel as an example, the calculation process is as follows: Step 1: Signal Acquisition and Self-Multiplication The analog-to-digital converter (ADC) of the smart meter chip samples the analog voltage signal at a fixed sampling rate (e.g., 3.2kHz in this embodiment, i.e., 64 samples per 50Hz cycle) to obtain a digitized voltage sampling sequence. U ( n )}, n =0,1,2,…
[0030] The sequence is fed point by point into the self-multiplication module, at each sampling time. n For the current sampled value U ( nPerform squaring operations to obtain a sequence of squares:
[0031] This squaring operation shifts the energy of the fundamental frequency (50Hz) and various harmonic components (100Hz, 150Hz, 250Hz, etc.) in the original signal, so that the DC component corresponds to the square of the effective voltage value, while the AC component is mainly concentrated near 100Hz, 200Hz and higher even frequencies.
[0032] Step 2: Low-pass filtering to extract DC component The square sequence { U 2 ( n The input is fed into a first-order or second-order digital low-pass filter. This embodiment uses a second-order Chebyshev Type II low-pass filter, whose transfer function is as follows:
[0033] Filter cutoff frequency f c Designed for 15Hz (far below 1 / 3 of the fundamental frequency of 50Hz), with a stopband start frequency of 80Hz, and attenuation of no less than -40dB at 100Hz. This design ensures sufficient suppression of second harmonics and higher components while also resulting in a small filter coefficient bit width (in this embodiment, the coefficients are represented using 12-bit fixed-point numbers), and low logic resource consumption.
[0034] After passing through this second-order low-pass filter, the output sequence is denoted as... P ( n After the filter reaches steady state, P ( n It approaches a stable DC value, which is theoretically equal to the square of the effective voltage value, i.e.:
[0035] Step 3: Restore valid values by performing square root operation The DC value P(n) output by the filter is fed into the square root module. This embodiment uses the Successive Approximation Square Root algorithm, specifically implemented as follows: (1) Initialize the root estimate , The input data bit width (in this example) P ( n (24 bits) Initialize to 2 12 =4096); (2) Use the bisection method or the positional trial method to determine each digit of the square root starting from the most significant digit; (3) Calculate the current estimate at each iteration step. The square of, and P ( n The comparison determines whether the next bit should be set to 1 or 0. (4) In this embodiment, 12 iterations are set (corresponding to 12 valid roots). After the 12th iteration, the final effective value estimate is obtained:
[0036] After the above three steps, a high-precision RMS voltage value can be obtained. Similarly, by performing the exact same processing procedure on the sampling sequence {I(n)} of the current channel, the effective value of the current can be obtained. .
[0037] Example 2 This embodiment, based on Embodiment 1, further illustrates the impact of filter parameters on performance.
[0038] In this embodiment, the cutoff frequencies of the second-order Chebyshev Type II filter were set to 10Hz, 15Hz, and 20Hz for comparative testing. Under typical harmonic power grid conditions with THD=10% (including the 3rd, 5th, 7th, and 11th harmonics), the test results show that: f c At 10Hz, the steady-state settling time is approximately 220ms, and the RMS error caused by harmonics under 50Hz fundamental conditions is <0.08%. f c At 15Hz, the steady-state settling time is approximately 140ms, with an error of <0.12%. f c At 20Hz, the steady-state settling time is approximately 100ms, with an error of <0.22%.
[0039] Taking into account accuracy, real-time performance, and resource efficiency, f c =15Hz is a better compromise.
[0040] Example 3 This embodiment provides a hardware implementation structure based on the above method, such as... Figure 1 As shown.
[0041] This structure comprises a self-multiplication module, a second-order low-pass filter, and a successive approximation square root module connected in series. The input signal is a 16-bit or 24-bit signed fixed-point number output by the ADC; the self-multiplication module is implemented using an 18×18 or 24×24 multiplier; the low-pass filter adopts a direct-type II structure (see...). Figure 2 It contains 2 multipliers, 4 adders and several registers; the square root module adopts a 12-step iterative successive approximation logic, requiring about 1 multiplier (reused) and a small number of comparators and registers.
[0042] With a 0.18μm or more advanced process, the above structure has a total number of logic gates of about 8k to 12k in the digital part, which is much lower than the traditional solution with the same precision using CORDIC or more than 32 FIR filters, making it suitable for integration into low-cost power metering SoC.
[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A method for calculating the effective values of current and voltage in a smart meter chip, characterized in that: The method includes the following steps: The original voltage digital signal U or current digital signal I obtained by the analog-to-digital converter in the smart meter chip is input to the self-multiplication module. The self-multiplication module performs point-by-point squaring operation to obtain the output result U² or I² of the self-multiplication module. The output result U² or I² of the self-multiplication module is input into a second-order low-pass filter. The high-frequency AC component in the output result U² or I² of the self-multiplication module is filtered out by the second-order low-pass filter, while the DC component in the output result U² or I² of the self-multiplication module is retained, thus obtaining the output result of the second-order low-pass filter. The output of the second-order low-pass filter is sent to the square root module, and the square root operation is performed on the output of the second-order low-pass filter by the square root module to obtain the effective voltage value RMS or the effective current value RMS.
2. The method for calculating the effective values of current and voltage based on a smart meter chip according to claim 1, characterized in that: The output result U² or I² of the self-multiplication module is equivalent to a DC signal and a high-frequency component.
3. The method for calculating the effective values of current and voltage based on a smart meter chip according to claim 1, characterized in that: The second-order low-pass filter adopts the Chebyshev Type II filter model.
4. The method for calculating the effective values of current and voltage based on a smart meter chip according to claim 1, characterized in that: The cutoff frequency of the second-order low-pass filter is lower than the fundamental frequency of the power grid.
5. The method for calculating the effective values of current and voltage based on a smart meter chip according to claim 1, characterized in that: The square root module uses a successive approximation method to perform square root operations.
6. A current and voltage RMS value calculation model based on a smart meter chip, characterized in that: The computational model includes a self-multiplication module, a second-order low-pass filter, and a square root module; The input terminal of the self-multiplication module is used to receive the original voltage digital signal U or current digital signal I obtained by the analog-to-digital converter from the smart meter chip. The self-multiplication module is used to perform a point-by-point squaring operation on the original voltage digital signal U or current digital signal I to obtain the output result U of the self-multiplication module. 2 Or I 2 ; The input of the second-order low-pass filter is connected to the output of the self-multiplication module. The second-order low-pass filter is used to filter out the high-frequency AC components in the output result U² or I² of the self-multiplication module, while retaining the output result U² of the self-multiplication module. 2 Or I 2 The DC component in the filter is used to obtain the output of the second-order low-pass filter. The input terminal of the square root module is connected to the output terminal of the second-order low-pass filter. The square root module is used to perform square root operation on the output result of the second-order low-pass filter to obtain the effective voltage value RMS or the effective current value RMS.
7. The current and voltage RMS value calculation model based on a smart meter chip according to claim 6, characterized in that: The output result U² or I² of the self-multiplication module is equivalent to a DC signal and a high-frequency component.
8. The current and voltage RMS value calculation model based on a smart meter chip according to claim 6, characterized in that: The second-order low-pass filter adopts the Chebyshev Type II filter model.
9. The current and voltage RMS value calculation model based on a smart meter chip according to claim 6, characterized in that: The cutoff frequency of the second-order low-pass filter is lower than the fundamental frequency of the power grid.
10. The current and voltage RMS value calculation model based on a smart meter chip according to claim 6, characterized in that: The square root module uses a successive approximation method to perform square root operations.