Method and device for dynamically adjusting base address register of PCIe endpoint device and storage medium

Abstract

This application provides a method, apparatus, and storage medium for dynamically adjusting the base address register of a PCIe endpoint device, relating to the field of computer technology. In this method, when the host system powers on or resets, the microcontroller controls the reset signal of the PCIe endpoint device according to a preset timing sequence, enabling the endpoint device to be in a configurable state before the host system performs standard PCIe enumeration. While the endpoint device is in this configurable state, the microcontroller dynamically adjusts the address space size parameter of the base address register through a debug interface. After the address space size parameter of the base address register is modified, the host system performs device enumeration and allocates resources according to the modified address space size parameter of each endpoint device. This method achieves dynamic adjustment and optimization of the PCIe device address space capability, improving the flexibility of system resource allocation and device compatibility.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus and storage medium for dynamically adjusting the base address register of a PCIe endpoint device. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a mainstream high-speed interconnect bus widely used in servers, personal computers, and embedded systems. PCIe endpoints (EPs) expose their memory or I / O resources to the host through the Base Address Register (BAR). The size of the BAR is typically set and fixed during the hardware design phase or the ROM (Read-Only Memory) phase. The host BIOS (Basic Input / Output System) reads and enumerates the BAR space during system startup, and then allocates the corresponding address resources.

[0003] With the rapid development of high-performance computing and big data applications, the demand for memory mapping space in PCIe devices is constantly increasing. Devices such as graphics cards and accelerator cards need to map their entire video memory onto the PCIe BAR to achieve P2P transmission with other PCIe devices like RDMA network cards, thus requiring support for BAR sizes much larger than those of traditional PCIe devices. Although PCIe 4.0 and later specifications introduced the resizable base address register (ResizableBAR) function, in practical applications, limitations imposed by motherboard BIOS, firmware, or the chip itself still result in insufficient configuration flexibility.

[0004] Therefore, improving the flexibility of adjusting the base address register memory capacity of existing PCIe devices has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for dynamically adjusting the base address register of a PCIe endpoint device, aiming to solve the technical problem of insufficient flexibility in adjusting the base address register memory capacity of existing PCIe devices.

[0006] In a first aspect, this application provides a method for dynamically adjusting the base address register of a PCIe endpoint device, the method comprising the following steps: When the host system is detected to be powered on or reset, the microcontroller controls the reset signal of the PCIeEP endpoint device according to a preset timing sequence to perform a reset operation on the endpoint device so that the endpoint device enters a configurable state. When the endpoint device is in the configurable state, the microcontroller accesses and modifies the base address register mask register inside the endpoint device through the debug interface to dynamically adjust the address space size parameter of the base address register; After the address space size parameter of the base address register is modified, the host system performs a device enumeration operation so that the host system allocates resources according to the modified address space size parameter of each endpoint device.

[0007] Secondly, this application also provides a dynamic adjustment device for the base address register of a PCIe endpoint device, the dynamic adjustment device for the base address register of the PCIe endpoint device comprising: The endpoint device reset module is used to reset the endpoint device by controlling the reset signal of the PCIeEP endpoint device according to a preset timing sequence when the host system is detected to be powered on or reset, so that the endpoint device can enter a configurable state. The register adjustment module is used to allow the microcontroller to access and modify the base address register mask register inside the endpoint device through a debug interface when the endpoint device is in the configurable state, so as to dynamically adjust the address space size parameter of the base address register. The device enumeration module is used to perform a device enumeration operation through the host system after the address space size parameter of the base address register is modified, so that the host system can allocate resources according to the modified address space size parameter of each endpoint device.

[0008] Thirdly, this application also provides a computer device, the computer device including a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the above-described method for dynamically adjusting the base address register of a PCIe endpoint device.

[0009] Fourthly, this application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described method for dynamically adjusting the base address register of a PCIe endpoint device.

[0010] This application provides a method, apparatus, computer device, and storage medium for dynamically adjusting the base address register of a PCIe endpoint device. In this method, when the host system powers on or resets, the microcontroller controls the reset signal of the PCIe EP endpoint device according to a preset timing sequence, ensuring the endpoint device enters a configurable state. This allows the endpoint device to be in a configurable state from the initial startup of the host system, avoiding the improper configuration timing problem caused by premature endpoint device initialization in traditional methods. When the endpoint device is in a configurable state, the microcontroller accesses and modifies the base address register mask register inside the endpoint device through a debug interface, dynamically adjusting the address space size parameter of the base address register. This achieves the goal of flexibly adjusting the BAR size of the endpoint device according to actual application needs, improving the resource allocation flexibility and adaptability of the endpoint device. After the address space size parameter of the base address register is modified, the host system performs device enumeration, enabling the host system to allocate resources according to the modified address space size parameter of each endpoint device. This ensures that the modified address space size parameter of the endpoint device can be correctly recognized and applied by the host system, thereby achieving optimized resource allocation and avoiding resource allocation errors or performance degradation caused by the host system's inability to recognize the new configuration. This technical solution enables dynamic adjustment of the base address register memory capacity of PCIe devices by precisely controlling timing, flexibly adjusting configuration parameters, and ensuring correct response from the host system, thereby comprehensively improving the flexibility and compatibility of PCIe devices in terms of memory capacity adjustment. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of a microcontroller-based EP device reset and configuration control architecture is provided for embodiments of this application. Figure 2 A flowchart illustrating an embodiment of a method for dynamically adjusting the base address register of a PCIe endpoint device provided in this application; Figure 3 A timing diagram illustrating how a microcontroller adjusts the address space size parameter of an endpoint device base address register via a debug interface, as provided in this application embodiment; Figure 4 This is a schematic diagram of an embodiment of a dynamic adjustment device for the base address register of a PCIe endpoint device provided in this application. Figure 5This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.

[0013] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0016] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0017] In this field, the BAR size of existing PCIe devices is typically fixed during the chip design and manufacturing stages. Users cannot flexibly adjust the BAR space according to their needs in practical applications, limiting the device's resource allocation capabilities in diverse scenarios. This fixed design leads to structural inflexibility, making it difficult to meet the demands of high-performance or specialized applications for larger BAR spaces.

[0018] Some new-generation PCIe devices and motherboards support the ResizableBAR extension of PCIe 4.0 and later specifications, theoretically allowing for dynamic adjustment of the BAR size via software. However, the actual effectiveness of this feature still heavily relies on the cooperation and support of the motherboard BIOS. For BIOSes that do not support this extension, users cannot modify the BAR space using this standard, resulting in insufficient compatibility and adaptability.

[0019] In the design and development of existing PCIe devices, debug interfaces such as IIC (Inter-Integrated Circuit) and JTAG (Joint Test Action Group) are typically used for chip register access, parameter configuration, and debugging operations. Many PCIe devices reserve debug interfaces to facilitate status monitoring, parameter adjustment, or troubleshooting via external controllers during R&D, production, or maintenance phases. However, current applications of debug interfaces are mainly focused on chip debugging and basic parameter configuration. For critical resource parameters such as BAR, existing technologies cannot accurately control the timing of their configuration. Solutions for dynamically adjusting resource parameters such as BAR before the host BIOS boots via debug interfaces are relatively rare and have not yet become a common practice. This, to some extent, limits the flexible configuration capabilities of PCIe devices in high-performance or special application scenarios.

[0020] For devices with specific high-performance data access requirements, to achieve high-performance data access such as RDMADirect, it is necessary to completely map the entire DDR space on the device to the host side so that the host can directly access and manage all physical memory resources. However, devices with specific high-performance data access requirements do not support ResizableBAR extensions. Even if some platforms have this function, the support varies between different host BIOSes, making it difficult to guarantee the complete mapping of large-capacity DDR space in practical applications. Limited by the existing BAR size configuration mechanism, it is impossible to meet the need for mapping large-capacity memory at once, which seriously restricts the implementation of key functions such as RDMADirect and the overall performance of the system. Therefore, there is an urgent need for a technical solution that does not rely on the motherboard BIOS and can flexibly and dynamically adjust the BAR size of PCIe devices to support large-capacity memory space mapping and comprehensively improve the system's scalability, compatibility, and operational efficiency.

[0021] This application provides a method for dynamically adjusting the base address register of a PCIe endpoint device. This method allows for flexible adjustment of the BAR mask register of the internal PCIe controller via an external microcontroller through a debugging interface (such as IIC) before the host BIOS enumerates the PCIe device. This method does not rely on the motherboard BIOS or the chip's native firmware, overcoming the limitations of traditional fixed design and BIOS compatibility. It enables PCIe devices to dynamically configure the BAR space according to actual needs, improving device adaptability and resource utilization.

[0022] In one embodiment, the method for dynamically adjusting the base address register of a PCIe endpoint device provided in this application is applied to, for example... Figure 1This illustrates a microcontroller-based EP device reset and configuration control architecture. For example... Figure 1 As shown, in this microcontroller-enabled EP device reset and configuration control architecture, the host simultaneously connects the PCIe reset signal to both the external microcontroller and the EP device. Upon receiving the PCIe reset signal, the external microcontroller controls the SYS reset signal of the EP device as needed, achieving a secondary reset of the EP device. After resetting the EP device, the external microcontroller communicates with the EP device via the IIC bus to promptly configure the relevant BAR register parameters, ensuring that the configuration is completed before the host BIOS enumeration. The overall process guarantees that the EP device can be correctly identified and resource-allocated by the host after power-on or reset, while also supporting flexible configuration of critical registers.

[0023] Before configuring the BAR-related register parameters of the EP device, the out-of-band management system first sends the relevant register configuration parameters to the microcontroller so that the microcontroller can configure the BAR size of the EP device according to the configuration parameters.

[0024] In one embodiment, the microcontroller receives target configuration parameters issued by the out-of-band management system, wherein: the target configuration parameters are validated for legality; after the validation of the target configuration parameters is passed, the target configuration parameters are stored in the encrypted partition of the microcontroller, and a configuration ready signal is sent to the host system so that the host system is powered on or reset.

[0025] The out-of-band management system sends new configuration parameters or firmware to the external microcontroller, which then prepares for subsequent BAR adjustment operations. The firmware updates for the external microcontroller are sent by the out-of-band management system, enabling batch adjustment of the BAR of PCIe devices without manual on-site operation, significantly reducing maintenance difficulty and costs.

[0026] The microcontroller receives target configuration parameters from the out-of-band management system (BMC or other remote management platform) through a dedicated out-of-band management interface (such as UART, SPI, or SMBus). These target configuration parameters include at least the target base address register size (such as 4KB, 16MB, etc.), the base address register number (such as BAR0, BAR1, etc.), and the access type (such as prefetchable, non-prefetchable, etc.).

[0027] The target configuration parameters include at least the target base address register size, base address register number, and access type. The target configuration parameters can be transmitted in the form of encrypted data packets to ensure they are not tampered with or stolen during transmission. Upon receiving the data packet, the microcontroller first verifies its digital signature to ensure data integrity and the reliability of its source. After successful signature verification, the microcontroller decrypts the data packet and extracts the target configuration parameters.

[0028] The microcontroller performs validity checks on the received target configuration parameters to ensure that these parameters meet the hardware capabilities and system requirements of the PCIe device. The verification process may include verification of the target base address register size, base address register number, access type, and resource conflict.

[0029] Specifically, the target base address register size check is used to check whether the target size is a power of 2 (such as 4KB, 8KB, 16MB, etc.) and to ensure that the size is within the range supported by the PCIe device. For example, some devices may only support a maximum BAR size of 256MB, and configurations exceeding this range will be rejected.

[0030] Base address register number check is used to verify whether the base address register number is valid. PCIe devices typically support 6 BARs (BAR0 to BAR5), and the microcontroller checks whether the number is within this range.

[0031] Access type validation is used to check whether the access type conforms to the modes supported by the device. For example, some devices may not support the prefetchable mode of certain BARs, and the microcontroller will perform validation based on the device capability table.

[0032] Once the target configuration parameters pass validity verification, the microcontroller stores these parameters in its internal encrypted partition. The encrypted partition uses hardware encryption mechanisms (such as AES-128 or AES-256 encryption) to protect the stored data and prevent unauthorized access or tampering of the configuration parameters.

[0033] Specifically, the microcontroller uses a built-in hardware encryption module to encrypt the target configuration parameters before writing them to a specific partition of non-volatile memory. After storage, the microcontroller performs integrity checks (such as CRC checks) on the stored data to ensure that the data has not been corrupted during storage. The microcontroller maintains version information of the configuration parameters in the encrypted partition so that it can quickly identify and roll back to the previous configuration in subsequent configuration operations.

[0034] After the external microcontroller firmware upgrade is complete, the host system needs to be powered on or reset to ensure the PCIe device is in a reset state for subsequent configuration. Therefore, after the target configuration parameters are successfully stored and verified, the microcontroller sends a configuration ready signal to the host system. This configuration ready signal can be transmitted via GPIO or other dedicated signal lines, notifying the host system that the configuration parameters are ready and that a power-on or reset operation can be performed to configure the BAR size of the EP device.

[0035] Specifically, the microcontroller can send a high-level pulse or low-level pulse to the host system via GPIO or other signal lines, with a duration of no less than 100 milliseconds, to ensure that the host system can reliably detect the signal. Upon receiving the configuration ready signal, the host system performs a power-on or reset operation. Since the microcontroller is powered by the host system, it also synchronously powers on or resets upon the host system's power-on or reset, entering a synchronous wait state to monitor the host system's reset signal (such as PERST#) to ensure that the host system has responded correctly and entered the reset process.

[0036] In this embodiment, the microcontroller ensures the legality, security, and reliability of the target configuration parameters by loading, verifying, and storing them. Through collaborative operation with the host system, it prepares for subsequent device enumeration and resource allocation, which not only improves the system's flexibility and maintainability but also enhances its security and stability.

[0037] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of a method for dynamically adjusting the base address register of a PCIe endpoint device provided in this application.

[0038] like Figure 2 As shown, the method for dynamically adjusting the base address register of the PCIe endpoint device includes steps S101 to S103.

[0039] S101. When the host system is detected to be powered on or reset, the microcontroller controls the reset signal of the PCIe EP endpoint device according to a preset timing sequence to perform a reset operation on the endpoint device so that the endpoint device enters a configurable state.

[0040] In one embodiment, combined with Figure 1 and Figure 3 The microcontroller receives the PCIe reset signal (PERST#) from the host system via its GPIO interface. This signal is crucial for the host system to initialize the PCIe bus and all connected devices during power-up or reset. The microcontroller monitors the received PERST# signal in real time, and confirms that the host system has entered the reset process when it detects that the signal is low and active.

[0041] To improve the accuracy and reliability of monitoring, the PERST# signal can be filtered in the hardware circuit to eliminate signal noise and jitter. Simultaneously, the microcontroller also employs a de-jitter algorithm in software to denoise the signal, ensuring its stability and reliability. In addition to monitoring the PERST# signal, the microcontroller can perform cross-verification using other signals (such as the host power status signal and system clock signal) to ensure that the host system is indeed in a power-on or reset state. The microcontroller records the low-level trigger timestamp of the PERST# signal for subsequent timing control and debugging analysis.

[0042] After the host system is powered on, the external microcontroller controls the reset signal of the PCIe EP chip to ensure that the EP chip of the endpoint device is in the correct initialization phase.

[0043] To ensure that the PCIeEP endpoint device can correctly enter the configurable state, the microcontroller precisely controls the system reset signal (SYS_RST#) of the endpoint device according to preset timing control logic. Specifically, after detecting that the SYS_RST# signal is valid, the microcontroller delays for a preset time window (e.g., 100 microseconds to 1 millisecond) to ensure that the reset operation of the host system's PCIe bus has stabilized. Subsequently, the microcontroller pulls the SYS_RST# signal low for at least 10 milliseconds to ensure that the endpoint device's hardware circuitry can complete the necessary reset operation. This delay and duration are set based on the endpoint device's hardware design requirements to ensure that the device can recover from any unstable state.

[0044] After keeping the SYS_RST# signal active for a period of time, the microcontroller releases the signal (i.e., pulls it high), thereby restoring the endpoint device from the reset state. At this point, the endpoint device's PCIe controller enters the initialization phase, preparing to receive configuration commands from the microcontroller.

[0045] To ensure that the endpoint device is ready to be configured, the microcontroller polls the PCIe initialization completion flag inside the endpoint device via a debug interface (such as IIC). This flag is set by the endpoint device after it has completed the initialization of its internal PCIe controller, indicating that the device has entered a configurable state.

[0046] Specifically, the microcontroller periodically reads the endpoint device's status register via the debug interface to check whether the endpoint device's PCIe controller initialization completion flag is correctly set. The polling interval can be set from 10 microseconds to 100 microseconds, depending on the device's initialization time. After confirming that the endpoint device's PCIe controller initialization completion flag is set, the microcontroller further confirms that the host system's PERST# signal remains valid, ensuring that the endpoint device's reset operation is synchronized with the host system's reset process.

[0047] Once the microcontroller detects that the PCIe initialization completion flag of the endpoint device is correctly set and confirms that the PERST# signal of the host system is still valid, it considers the endpoint device to have successfully entered the configurable state. At this point, the microcontroller can continue to perform subsequent base address register (BAR) configuration operations to dynamically adjust the address space size parameters of the endpoint device.

[0048] This embodiment not only ensures that the endpoint device can be correctly initialized after the host system is reset, but also provides the microcontroller with precise timing control capabilities, thereby completing the critical configuration operations of the endpoint device before the host BIOS begins to enumerate PCIe devices, improving the system's flexibility and compatibility.

[0049] S102. When the endpoint device is in the configurable state, the microcontroller accesses and modifies the base address register mask register inside the endpoint device through the debug interface to dynamically adjust the address space size parameter of the base address register.

[0050] After the PCIe EP chip ROM code in the endpoint device completes the PCIe controller initialization, that is, after the endpoint device enters the "configurable state", the microcontroller accesses and modifies the base address register mask register (BAR Mask Register) inside the endpoint device through the IIC debug interface, realizes the dynamic adjustment of the BAR size, and dynamically adjusts the memory capacity of the BAR from the factory fixed value to the size required by the business. Moreover, the whole process is much earlier than the host BIOS begins to enumerate the endpoint device.

[0051] Further, the microcontroller converts the target base address register size into a corresponding target mask value; the microcontroller sends a write command to the endpoint device through the debug interface to write the target mask value into the mask register; after the mask value is written, the microcontroller reads back the current mask value of the mask register through the debug interface to verify the writing result of the target mask value; when the current mask value is equal to the target mask value, it is determined that the target mask value has been successfully written, and the dynamic adjustment of the content capacity parameter of the base address register is completed.

[0052] In one embodiment, after receiving the target base address register size from the out-of-band management system, the microcontroller first performs a validity check to ensure that the size complies with PCIe specifications (e.g., it is a power of 2 and within the range supported by the device). After the check passes, the microcontroller calculates the corresponding target mask value based on the target size.

[0053] The microcontroller stores the calculated target mask value in an internal register or cache, ready for subsequent write operations.

[0054] The microcontroller sends a write command to the endpoint device through a debug interface (such as I²C) to write the target mask value into the mask register of the endpoint device.

[0055] Specifically, refer to Figure 3 The microcontroller configures the debug interface parameters, such as the I²C clock frequency (typically 100kHz or 400kHz), and sets the slave address of the endpoint device. The microcontroller constructs a write command containing the endpoint device's slave address, the offset address of the mask register, and the target mask value; then, it sends this write command through the debug interface. Upon receiving the write command, the endpoint device writes the target mask value to its internal mask register and returns an acknowledgment signal (such as ACK) indicating successful completion of the write operation.

[0056] In one embodiment, when writing the mask value, the microcontroller can dynamically adjust signal transmission parameters (such as clock frequency and data bit width) by monitoring the signal integrity of the debug interface (such as I²C) in real time. If a signal transmission anomaly is detected, it automatically switches to a backup communication link or adjusts the communication protocol to ensure the reliability of the write operation. Furthermore, eye diagrams, jitter, and other parameters of the signal can be collected in real time during the write process. The microcontroller can then dynamically adjust the signal transmission strategy based on these parameters, such as using differential signal transmission or adding signal pre-emphasis, to improve the integrity and reliability of the written signal.

[0057] In one embodiment, the microcontroller can also simultaneously write mask values ​​to the endpoint device through multiple debug interface channels (such as I²C and SPI). Each channel writes the same data, and channel calibration is performed before writing to eliminate time deviations between channels, improving the efficiency and reliability of redundant writing. The endpoint device compares and merges the received multi-channel data to ensure the correctness of the mask values, effectively addressing single-channel failures or interference and improving the write success rate.

[0058] After the mask value is written, the microcontroller reads back the current mask value in the mask register through the debug interface to verify the writing result of the target mask value.

[0059] Specifically, the microcontroller sends a readback command to the endpoint device via the debug interface, containing the slave address of the endpoint device and the offset address of the mask register. The endpoint device responds to the readback command by sending the current mask value of the mask register back to the microcontroller via the debug interface.

[0060] The microcontroller compares the received current mask value with the previously calculated target mask value. If the current mask value is equal to the target mask value, the microcontroller determines that the target mask value has been successfully written, completing the dynamic adjustment of the address space size parameter of the base address register. At this point, the microcontroller can continue to perform subsequent operations, such as notifying the host system to enumerate devices.

[0061] In one embodiment, if the current mask value is not equal to the target mask value, it is determined that the target mask value writing has failed; when the target mask value writing fails, the microcontroller performs a retry operation according to a preset intelligent retry strategy; if the target mask value still fails to be written within a preset number of retries, an alarm signal is triggered to perform fault diagnosis and maintenance based on the alarm signal.

[0062] If the current mask value is not equal to the target mask value, the microcontroller determines that the target mask value writing has failed. At this time, the microcontroller can perform error handling operations according to the preset intelligent retry strategy. For example, the microcontroller performs a retry operation and specifies that there are a maximum of three retries. If all three retries fail, an alarm signal is triggered, an error log is recorded, or an error is reported to the out-of-band management system.

[0063] In one embodiment, the microcontroller can employ an intelligent retry strategy when verifying the mask value. Specifically, if the initial verification fails, different retry methods (such as adjusting the reading timing or switching the reading channel) are selected based on the cause of failure (e.g., read error, verification failure). After multiple failed retries, an alarm signal is triggered, and the microcontroller automatically initiates a fault diagnosis process. Based on real-time collected fault information and a preset fault mode library, the microcontroller quickly locates the root cause of the problem, analyzes the hardware status of the endpoint device and the health of the communication link, and provides targeted solutions, thereby improving the system's maintenance efficiency.

[0064] In one embodiment, after confirming that the target mask value has been written correctly, the microcontroller ensures that the configuration cannot be changed during host BIOS enumeration by writing to the configuration lock register. Specifically, the microcontroller sends a write command to write to the configuration lock register, and the endpoint device's EP chip returns an acknowledgment signal, confirming that the configuration locking operation was successful.

[0065] In this embodiment, through the above steps, the microcontroller can accurately convert the target base address register size into a target mask value and write it into the mask register of the endpoint device through the debug interface. Simultaneously, a readback verification mechanism ensures the correctness of the write operation, thereby enabling dynamic adjustment of the address space size parameter of the base address register.

[0066] S103. After the address space size parameter of the base address register is modified, the host system performs a device enumeration operation so that the host system allocates resources according to the modified address space size parameter of each endpoint device.

[0067] After modifying the Base Address Register (BAR) address space size parameter, the host system performs device enumeration to ensure that the host system can correctly allocate resources to PCIe endpoint devices according to the modified address space size parameter.

[0068] Specifically, after modifying the BAR mask register and verifying successful writing, the microcontroller needs to confirm that all configuration operations have been completed. First, the microcontroller writes the configuration lock mask register through the debug interface to ensure that the value of the BAR mask register is not accidentally modified during the host BIOS enumeration process; then, the microcontroller reads the endpoint device's status register again to confirm that the device is ready to accept the host system's enumeration operation.

[0069] The microcontroller records the timestamp when the mask register configuration modification operation of the endpoint device is completed, and ensures that the entire process is completed in microseconds (e.g., <100 µs).

[0070] Furthermore, after the address space size parameter in the base address register is modified, the host system accesses the base address register of the endpoint device by configuring the read transaction layer packet to obtain the modified address space size parameter; according to the modified address space size parameter, it allocates system address space to the endpoint device and writes the base address corresponding to the allocated system address space into the base address register of the endpoint device.

[0071] After the BAR parameters are modified, the host BIOS begins the PCIe bus device enumeration process. The PCIe devices respond to the host with the new address space size parameters, and the host is able to correctly identify and allocate resources.

[0072] In one embodiment, after the mask register of the base address register (BAR) of the endpoint device is modified, the host system needs to detect the size of the address space requested by the BAR through a specific configuration transaction (write all 1s and then read back). Based on the detected size information, the system allocates the corresponding region in the physical address space and writes the allocated base address into the BAR.

[0073] Specifically, after the microcontroller completes the modification of the endpoint device's BAR mask register and releases the EP device's SYS reset signal for a period of time, the host system begins the device enumeration process. The host system's PCIe root complex is responsible for managing the PCIe bus initialization and device enumeration process.

[0074] At the start of enumeration, the host system first performs link training with the endpoint devices to ensure that the electrical characteristics and link status of the PCIe link meet the specification requirements. After the link training is complete, the host system discovers and accesses all devices connected to the PCIe bus by sending Configuration Read TLP packets.

[0075] The host system sends a configuration read transaction layer packet to the endpoint device via the PCIe bus. The goal is to access the base address register (BAR) in the endpoint device's configuration space. The configuration read transaction layer packet contains key information such as the device identifier and register offset address. The device identifier includes the bus number, device number, and function number, used to locate a specific PCIe device. The register offset address specifies the offset address of the base address register to be accessed, such as BAR0, BAR1, etc.

[0076] After receiving the configuration read transaction layer packet, the endpoint device reads the corresponding base address register value from its configuration space and returns this value as response data to the host system. At this time, the base address register value returned by the endpoint device has been updated according to the microcontroller's modification operation, reflecting the new address space size parameter.

[0077] After receiving the base address register value returned by the endpoint device, the host system parses the value to obtain the address space size parameter. The address space size parameter includes information such as a memory capacity mask, prefetch attributes, and a type identifier. Specifically, the memory capacity mask indicates the size of the memory space requested by the device; the prefetch attributes indicate whether the device supports prefetch operations; and the type identifier distinguishes between memory-mapped BARs and I / O-mapped BARs.

[0078] The host system calculates the required memory space for the device based on the memory capacity mask. Based on the parsed address space size parameters, the host system allocates system address space for the endpoint device. The host system's memory manager allocates a contiguous memory region from the system's available memory pool and determines the base address of that region. The size of the allocated memory region is consistent with the memory capacity requested by the endpoint device.

[0079] The host system writes the base address of the allocated system address space into the base address register of the endpoint device. This operation is accomplished by sending a Configuration Write Transaction Layer (TLP) packet. Upon receiving the TLP packet, the endpoint device writes the base address value into its base address register, completing the mapping of the system address space. The TLP packet contains information such as the device identifier, register offset address, and base address value. Specifically, the device identifier is the same as that used during configuration reading and is used to locate a specific PCIe device; the register offset address points to the base address register; and the base address value represents the base address of the system address space allocated by the host system.

[0080] Upon receiving a base address write operation, the endpoint device updates its internal state to indicate that resource allocation is complete. The host system confirms successful resource allocation by reading the endpoint device's status register or receiving an acknowledgment signal from the endpoint device. After the host system boots up, the PCIe devices have already completed resource allocation according to the latest configuration, requiring no additional driver support.

[0081] In one embodiment, during the host system enumeration process, key data (such as link training progress and configuration read response time) can be collected in real time and fed back to the microcontroller for anomaly detection via a dedicated communication link. If an enumeration anomaly is detected (such as link training failure or configuration read timeout), the microcontroller can trigger intervention measures, such as resending the configuration read command or adjusting the link parameters, to ensure the smooth progress of the enumeration process.

[0082] In multi-endpoint device scenarios, the microcontroller optimizes the initialization and enumeration process based on the functional characteristics of each device. Since each endpoint device (EP) contains an independent microcontroller for control, and the microcontroller is placed inside the endpoint device, it can adapt to any computer architecture. Therefore, the microcontroller can focus on optimizing the initialization and enumeration efficiency of its device, ensuring that the device can quickly complete initialization and be enumerated by the host system, thereby guaranteeing the rapid startup of the system's core functions.

[0083] This embodiment provides a method for dynamically adjusting the base address register (BAR) of a PCIe endpoint device. In this method, when the host system powers on or resets, the microcontroller controls the reset signal of the PCIe EP endpoint device according to a preset timing sequence, ensuring the endpoint device enters a configurable state. This allows the endpoint device to be in a configurable state from the initial startup of the host system, avoiding the improper configuration timing problem caused by premature endpoint device initialization in traditional methods. While the endpoint device is in a configurable state, the microcontroller accesses and modifies the base address register mask register inside the endpoint device through a debug interface, dynamically adjusting the address space size parameter of the base address register. This achieves the goal of flexibly adjusting the BAR size of the endpoint device according to actual application needs, improving the resource allocation flexibility and adaptability of the endpoint device. After the address space size parameter of the base address register is modified, the host system performs device enumeration, enabling the host system to allocate resources according to the modified address space size parameters of each endpoint device. This ensures that the modified address space size parameters of the endpoint devices can be correctly recognized and applied by the host system, thereby achieving optimized resource configuration and avoiding resource allocation errors or performance degradation caused by the host system's inability to recognize the new configuration. This technical solution enables dynamic adjustment of the base address register memory capacity of PCIe devices by precisely controlling timing, flexibly adjusting configuration parameters, and ensuring correct response from the host system, thereby comprehensively improving the flexibility and compatibility of PCIe devices in terms of memory capacity adjustment.

[0084] Please see Figure 4 , Figure 4 This is a schematic diagram of the current embodiment of a dynamic adjustment device for the base address register of a PCIe endpoint device provided in this application. The dynamic adjustment device for the base address register of the PCIe endpoint device is used to execute the aforementioned dynamic adjustment method for the base address register of the PCIe endpoint device.

[0085] like Figure 4 As shown, the PCIe endpoint device's base address register dynamic adjustment device 200 includes: an endpoint device reset module 201, a register adjustment module 202, and a device enumeration module 203.

[0086] The endpoint device reset module 201 is used to reset the endpoint device by controlling the reset signal of the PCIeEP endpoint device according to a preset timing sequence when the host system is detected to be powered on or reset, so that the endpoint device enters a configurable state. The register adjustment module 202 is used to allow the microcontroller to access and modify the base address register mask register inside the endpoint device through a debug interface when the endpoint device is in the configurable state, so as to dynamically adjust the address space size parameter of the base address register. The device enumeration module 203 is used to perform a device enumeration operation through the host system after the address space size parameter of the base address register is modified, so that the host system can allocate resources according to the modified address space size parameter of each endpoint device.

[0087] It should be noted that those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device and each module described above can be referred to the corresponding process in the aforementioned embodiment of the method for dynamically adjusting the base address register of the PCIe endpoint device, and will not be repeated here.

[0088] The apparatus provided in the above embodiments can be implemented as a computer program, which can be used in, for example... Figure 5 It runs on the computer device shown.

[0089] Please see Figure 5 , Figure 5 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device may be a server.

[0090] See Figure 5 The computer device includes a processor, memory, and network interface connected via a system bus, wherein the memory may include non-volatile storage media and internal memory.

[0091] Non-volatile storage media can store operating systems and computer programs. These computer programs include program instructions that, when executed, cause the processor to perform any method of dynamically adjusting the base address registers of a PCIe endpoint device.

[0092] The processor provides computing and control capabilities, supporting the operation of the entire computer device.

[0093] Internal memory provides an environment for the execution of computer programs in non-volatile storage media. When the computer program is executed by the processor, it enables the processor to perform any method of dynamically adjusting the base address register of a PCIe endpoint device.

[0094] This network interface is used for network communication, such as sending assigned tasks. Those skilled in the art will understand that... Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0095] It should be understood that the processor can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.

[0096] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps: When the host system is detected to be powered on or reset, the microcontroller controls the reset signal of the PCIe EP endpoint device according to a preset timing sequence to perform a reset operation on the endpoint device so that the endpoint device enters a configurable state. When the endpoint device is in the configurable state, the microcontroller accesses and modifies the base address register mask register inside the endpoint device through the debug interface according to the target configuration parameters, so as to dynamically adjust the address space size parameter of the base address register. After the address space size parameter of the base address register is modified, the host system performs a device enumeration operation so that the host system allocates resources according to the modified address space size parameter of each endpoint device.

[0097] The embodiments of this application also provide a computer-readable storage medium storing a computer program, the computer program including program instructions, and the processor executing the program instructions to implement any of the PCIe endpoint device base address register dynamic adjustment methods provided in the embodiments of this application.

[0098] The computer-readable storage medium may be an internal storage unit of the computer device described in the foregoing embodiments, such as the hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, SmartMediaCard (SMC), SecureDigital (SD) card, or FlashCard equipped on the computer device.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for dynamically adjusting the base address register of a PCIe endpoint device, characterized in that, The method includes: When the host system is detected to be powered on or reset, the microcontroller controls the reset signal of the PCIe EP endpoint device according to a preset timing sequence to perform a reset operation on the endpoint device so that the endpoint device enters a configurable state. When the endpoint device is in the configurable state, the microcontroller accesses and modifies the base address register mask register inside the endpoint device through the debug interface according to the target configuration parameters, so as to dynamically adjust the address space size parameter of the base address register. After the address space size parameter of the base address register is modified, the host system performs a device enumeration operation so that the host system allocates resources according to the modified address space size parameter of each endpoint device.

2. The method for dynamically adjusting the base address register of a PCIe endpoint device according to claim 1, characterized in that, Before the microcontroller controls the reset signal of the PCIeEP endpoint device according to a preset timing sequence to perform a reset operation on the endpoint device when the host system is detected to be powered on or reset, so that the endpoint device enters a configurable state, the following steps are also included: The microcontroller receives the target configuration parameters issued by the out-of-band management system; Perform a validity check on the target configuration parameters; After the validity of the target configuration parameters is verified, the target configuration parameters are stored in the encrypted partition of the microcontroller, and a configuration ready signal is sent to the host system so that the host system can be powered on or reset.

3. The method for dynamically adjusting the base address register of a PCIe endpoint device according to claim 1, characterized in that, The target configuration parameters include at least the target base address register size, the base address register number, and the access type.

4. The method for dynamically adjusting the base address register of a PCIe endpoint device according to claim 3, characterized in that, The microcontroller accesses and modifies the base address register mask register inside the endpoint device through a debug interface to dynamically adjust the address space size parameter of the base address register, including: The microcontroller converts the target base address register size into the corresponding target mask value; The microcontroller sends a write command to the endpoint device through the debug interface to write the target mask value into the mask register. After the mask value is written, the microcontroller reads back the current mask value of the mask register through the debug interface to verify the writing result of the target mask value; When the current mask value is equal to the target mask value, it is determined that the target mask value has been successfully written, and the dynamic adjustment of the content capacity parameter of the base address register is completed.

5. The method for dynamically adjusting the base address register of a PCIe endpoint device according to claim 4, characterized in that, After the mask value is written, and the microcontroller reads back the current mask value of the mask register through the debug interface to verify the writing result of the target mask value, the method further includes: If the current mask value is not equal to the target mask value, it is determined that the target mask value writing has failed; When the target mask value fails to be written, the microcontroller performs a retry operation according to a preset intelligent retry strategy; If the target mask value still fails to be written within the preset number of retries, an alarm signal is triggered to perform fault diagnosis and maintenance based on the alarm signal.

6. The method for dynamically adjusting the base address register of a PCIe endpoint device according to claim 1, characterized in that, After the address space size parameter in the base address register is modified, the host system performs a device enumeration operation, including: After the address space size parameter in the base address register is modified, the host system is driven to access the base address register of the endpoint device by configuring the read transaction layer packet to obtain the modified address space size parameter; Based on the modified address space size parameter, allocate system address space to the endpoint device and write the base address corresponding to the allocated system address space into the base address register of the endpoint device.

7. The method for dynamically adjusting the base address register of a PCIe endpoint device according to claim 1, characterized in that, The address space size parameter includes a memory capacity mask, prefetch attributes, and a type identifier.

8. A dynamic adjustment device for the base address register of a PCIe endpoint device, characterized in that, The base address register dynamic adjustment device for the PCIe endpoint device includes: The endpoint device reset module is used to reset the endpoint device by controlling the reset signal of the PCIeEP endpoint device according to a preset timing sequence when the host system is detected to be powered on or reset, so that the endpoint device can enter a configurable state. The register adjustment module is used to allow the microcontroller to access and modify the base address register mask register inside the endpoint device through a debug interface when the endpoint device is in the configurable state, so as to dynamically adjust the address space size parameter of the base address register. The device enumeration module is used to perform a device enumeration operation through the host system after the address space size parameter of the base address register is modified, so that the host system can allocate resources according to the modified address space size parameter of each endpoint device.

9. A computer device, characterized in that, The computer device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the method for dynamically adjusting the base address register of a PCIe endpoint device as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the method for dynamically adjusting the base address register of a PCIe endpoint device as described in any one of claims 1 to 7.

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