A 3D integrated circuit device

Abstract

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device layer comprising a first set of active devices; a second semiconductor device layer comprising a second set of active devices; a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure, the interconnect structure being arranged on a side of the first semiconductor device layer facing the second semiconductor device layer; and a logic circuit comprising a plurality of registers, each register comprising a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register, wherein the first active device is comprised in the first set of active devices of the first semiconductor device layer, and wherein the second active device is comprised in the second set of active devices of the second semiconductor device layer and connected to the clock distribution network to receive a clock signal.

Description

Technical Field

[0001] This invention generally relates to 3D integrated circuit devices. Background Technology

[0002] Clock allocation is an important consideration in the design of integrated circuit (IC) devices, including synchronization circuits.

[0003] A common implementation of clock distribution networks is a clock tree, such as an H-tree. The cumulative line length of a typical clock tree in an existing IC can be relatively long, for example, 1mm for a die. 2 In some sections, spanning over 200mm, a greater number of convergence nodes along the clock distribution network tends to be associated with increased line length.

[0004] The traditional method for clock distribution is to route the clock signal on the front side of the IC device die, i.e., using a back-end line (BEOL) interconnect structure ("front-side interconnect structure") on the front side of the die. Recently, IC designs have been proposed to instead use a BEOL interconnect structure on the back side of the die ("back-side interconnect structure") to route the clock signal.

[0005] The advantage of back-side routing of clock signals is that it reduces contention for routing resources in the front-side interconnect structure (which are also needed for routing non-clock signals). Summary of the Invention

[0006] While back-side routing of clock signals offers advantages, it can also introduce additional challenges in circuit design. For example, there is an area loss associated with connecting clock signals between active devices on the back and front sides, which is proportional to the number of times the signal is routed between the back and front sides. Furthermore, given the industry trend of incorporating power distribution networks (PDNs) into back-side interconnect structures (back-side PDNs), these interconnect structures typically include metal layers with relatively wide and closely spaced metal lines for power rails. This can limit the available space on the back side for contacts to route clock signals to the front side. Therefore, the numerous connections between clock signals and the back and front sides may require lower-density metal layers for power wiring and / or disrupt power rail continuity, both of which can degrade PDN performance.

[0007] In view of the above, an object of the present invention is to provide an improved method for designing IC devices that allows back-side routing of clock signals with minimal area loss. Furthermore, an object is to provide an improved method for designing IC devices that allows back-side routing of clock signals while requiring a smaller number of clock signal connections between the back and front sides. Further and alternative objectives will be understood from the following.

[0008] According to one aspect of the present invention, a 3D IC device is provided, comprising:

[0009] The first semiconductor device layer includes the first group of active devices;

[0010] The second semiconductor device layer includes the second group of active devices;

[0011] This includes a clock distribution network comprising multiple clock signal routing interconnects arranged in an interconnect structure, the interconnect structure being arranged on the side of the first semiconductor device layer facing the second semiconductor device layer; and

[0012] The logic circuit includes multiple registers, each register including a first active device arranged along the data path of the register and a second active device arranged along the clock path of the register.

[0013] The first active device is included in the first group of active devices in the first semiconductor device layer, and

[0014] The second active device is included in the second group of active devices in the second semiconductor device layer and is connected to the clock distribution network to receive clock signals.

[0015] The design of 3D IC devices is at least partly based on the understanding that by dividing registers into data paths and clock paths, and partitioning active devices (i.e., transistors) along corresponding paths between first and second semiconductor device layers, registers can be implemented with greater area efficiency, thereby enabling more area-efficient logic circuits and IC devices. Specifically, this design eliminates the need for direct connections between the active devices along the data path (“first active devices”) and the clock distribution network. Therefore, to implement the register, it is not necessary to provide contacts to route clock signals from the side of the first semiconductor device layer facing the second semiconductor device layer (“second side of the first semiconductor device layer”) through the first semiconductor device layer to the opposite side (“first side of the first semiconductor device layer”). This is because the active devices along the clock path (“second active devices”) are arranged in the second semiconductor device layer.

[0016] Furthermore, by arranging the first and second active devices of the register in different device layers, the area occupied by the second active device along the clock path in the first semiconductor device layer can be reduced. This further allows for a reduction in the area occupied by the respective registers, since the first and second active devices of the respective registers can thus be stacked on top of each other, i.e., have overlapping areas.

[0017] The active device arranged along the clock path of the corresponding register can specifically be each active device of the register, which includes a gate terminal configured to receive a clock signal from the clock distribution network. That is, each second active device of the corresponding register can be an active device of that register directly gated by the clock signal.

[0018] Conversely, the active device arranged along the data path of the corresponding register can be each active device of that register, which includes a gate terminal of a clock signal routing interconnect that is not connected to the clock distribution network for receiving clock signals. That is, each first active device of the corresponding register can be an active device of that register that is connected to the clock distribution network only via one or more second active devices of that register.

[0019] In some embodiments, the clock distribution network is a clock tree. Therefore, the clock distribution network can be implemented using one or more relatively sparse metal layers of an interconnect structure.

[0020] In some embodiments, the register includes a flip-flop and / or a latch. Therefore, this disclosure can be used to implement area-efficient implementations using both edge-triggered registers (flip-flops) and level-triggered registers (latches).

[0021] As will be understood, in this disclosure, the "first side" and "second side" of the first semiconductor device layer may refer to the front and back sides of the first semiconductor device layer, respectively. For example, in some embodiments, a first set of active devices of the first semiconductor device layer is included in the first front end line (FEOL) structure of the first die of the 3D IC, wherein the first set of active devices is arranged on the first side ("front side") of the first die, and includes an interconnect structure of multiple clock signal routing interconnects and a second semiconductor device layer is arranged on the second side ("back side") of the first die opposite to the first side. That is, the interconnect structure including the clock signal routing interconnects and the second semiconductor device layer including the second active devices of the clock path may each be arranged on the back side of the first die.

[0022] In some embodiments, a second set of active devices of the second semiconductor device layer is included in the second FEOL structure of the second die of the 3D IC device. The second set of active devices may be arranged on the side of the second die facing the first semiconductor device layer ("first side of the second die") or on the side of the second die facing away from the first semiconductor device layer ("second side of the second die").

[0023] Alternatively, in some embodiments, the second set of active devices are back-end transistors arranged in an interconnect structure that includes multiple clock signal routing interconnects. In this disclosure, the term "back-end transistor" refers to a BEOL-compatible transistor, i.e., a transistor that can be fabricated in a BEOL-compatible process (e.g., in a low / BEOL-compatible thermal budget). For example, a back-end transistor can be a thin-film transistor (TFT), such as a carbon nanotube (CNT) field-effect transistor (FET), a 2D channel FET, or an oxide semiconductor FET.

[0024] In some embodiments, the clock distribution network further includes a group of active clock devices formed by active devices included in the second group of active devices in the second semiconductor device layer.

[0025] Arranging the active components (i.e., transistors) of an active clock device in a second semiconductor device layer further contributes to the overall area efficiency of the IC device because the number of connections between the clock distribution network and the first semiconductor device layer is reduced compared to the conventional arrangement of the transistors in the first semiconductor device layer. Therefore, fewer contacts are needed to route the clock signal from the second side (e.g., the back side) of the first semiconductor device layer (or, depending on the case, the back side of the first die) through the first semiconductor device layer (e.g., the first die) to the opposite first side (e.g., the front side) of the first semiconductor device layer (or the first die).

[0026] In this disclosure, the term "active clock device" can refer to any transistor-based clock device in a clock distribution network, such as a clock driver, clock repeater, clock gate, or clock buffer (non-inverting or inverting).

[0027] Furthermore, by also arranging the active components of the active clock device in the second semiconductor device layer, the area occupied by the active components (i.e., transistors) of the active clock device in the clock distribution network (e.g., clock tree) in the first semiconductor device layer can be reduced. This also simplifies the design process by allowing for more flexible placement of the active clock devices in the second semiconductor device layer. That is, the active clock devices can be placed in locations within the second semiconductor device layer where they provide the greatest benefit to the performance of the clock distribution network (e.g., skew optimization), with less consideration given to the layout of the first semiconductor device layer. For example, some of the active components (transistors) of the active clock device can be arranged within the area occupied by circuit blocks implemented by active components in the first semiconductor device layer, including self-contained circuit blocks such as macros, IP blocks, or non-IP blocks. Therefore, the layout of the active clock device can be determined more freely compared to implementing the active clock device by active components in the first semiconductor device layer.

[0028] Therefore, in some embodiments, the group of active clock devices includes one or more active clock devices located within the occupied area of ​​a circuit block, which is any one of a macro, IP block, or non-IP block, and includes active devices in a first group of active devices in a first semiconductor device layer.

[0029] While this may be useful for all active clocking devices of the types described above, it can be particularly useful when applied to clock buffers. That is, specifically arranging the active devices (i.e., transistors) of the clock buffer in the second semiconductor device layer can facilitate clock tree balancing (e.g., for skew optimization purposes) because the passive devices of the clock buffer can be placed within the footprint of the self-contained circuit blocks of the types described above.

[0030] In some embodiments, the 3D IC device further includes a power distribution network (PDN) arranged in an interconnect structure comprising multiple clock signal routing interconnects and configured to supply power to the logic circuitry and the clock distribution network. This interconnect structure thus provides the dual functions of clock distribution and power distribution. Therefore, the interconnect structure can distribute power to active devices in the first and second semiconductor device layers (particularly the first and second active devices in the registers and any active clock devices), and distribute clock signals to second active devices in the registers and any active clock devices.

[0031] In some embodiments, the 3D IC device further includes a first interconnect structure disposed on one side of the first semiconductor device layer opposite to the second semiconductor device layer (i.e., the first side of the first semiconductor device layer) and configured to interconnect a first group of active devices. Therefore, the first group of active devices, including first active devices along the register data path, can be interconnected via the first interconnect structure. Since the clock signal routing interconnect (and optional PDN) is disposed in the interconnect structure on the opposite second side of the first semiconductor device layer, the first group of active devices can interconnect with less contention for routing resources with the clock distribution network (or PDN).

[0032] In some embodiments, the interconnect structure including multiple clock signal routing interconnects is a second interconnect structure and is arranged on the side of the second semiconductor device layer facing the first semiconductor device layer (i.e., the first side of the second semiconductor device layer). Therefore, the second interconnect structure can be arranged between the first and second semiconductor device layers. Thus, the second interconnect structure can provide routing resources for the first and second semiconductor device layers. In particular, when the second interconnect structure includes a PDN, power distribution to the first and second semiconductor device layers can be facilitated.

[0033] In embodiments where the first side and the second side of the first semiconductor device layer refer to the front and back sides of the first semiconductor device layer, respectively, the first interconnect structure may refer to a front interconnect structure disposed on the front side (e.g., on) of the first semiconductor device layer. Correspondingly, the second interconnect structure may refer to a back interconnect structure disposed on the back side of the first semiconductor device layer.

[0034] In embodiments in which a first semiconductor device layer is included in a first die and a first set of active devices, the first interconnect structure may refer to a front interconnect structure disposed on the front side (e.g., on) of the first die, and the second interconnect structure may refer to a back interconnect structure disposed on the back side (e.g., on) of the first die.

[0035] In some embodiments, the interconnect structure including multiple clock signal routing interconnects is a second interconnect structure and is arranged on the side of the second semiconductor device layer opposite to the first semiconductor device layer (i.e., the second side of the second semiconductor device layer). Therefore, clock signals can also be routed on the second side of the second semiconductor device layer (in some embodiments, the second side may correspond to the back side of the second semiconductor device layer, or, depending on the situation, to the back side of the second die including the second semiconductor element layer). In embodiments where the second interconnect structure also includes a PDN, this is correspondingly applicable to power distribution.

[0036] The 3D IC device may also include a third interconnect structure disposed on the side of the second semiconductor device layer facing the first semiconductor device layer (i.e., the first side of the second semiconductor device layer) and configured to interconnect a second set of active devices. Therefore, the second set of active devices, including second active devices along the register clock path and, where applicable, active devices of active clock devices, can be interconnected via the third interconnect structure on the first side (e.g., the front side) of the second semiconductor device layer. Since the clock signal routing interconnect (and optional PDN) is disposed in the second interconnect structure on the opposite second side (e.g., the back side) of the second semiconductor device layer, the second set of active devices can interconnect with less contention for routing resources with the clock distribution network (and PDN).

[0037] The principles of this disclosure are also applicable to multilayer IC designs that include two or more semiconductor device layers.

[0038] Therefore, in some embodiments, the 3D IC device further includes a third semiconductor device layer, which includes a third set of active devices.

[0039] The logic circuit includes multiple registers, which are multiple first registers. The logic circuit also includes multiple second registers, each of which includes a third active device arranged along the data path of the second register and a fourth active device arranged along the clock path of the second register.

[0040] The third active device is included in the third group of active devices in the third semiconductor device layer, and

[0041] The fourth active device is included in the second group of active devices in the second semiconductor device layer and is connected to the clock distribution network to receive clock signals.

[0042] Therefore, the second semiconductor device layer can be used to implement a corresponding clock path associated with the data path implemented by the first and third semiconductor device layers.

[0043] In some embodiments, the logic circuitry further includes a common register circuit shared by the first and second registers. The common register circuitry includes a fifth active device arranged along the clock paths of the first and second registers, wherein the fifth active device is included in a second group of active devices in the second semiconductor device layer and connected to the clock distribution network to receive the clock signal. Thus, logic allowing the sharing of clock paths between one or more of the first and second registers can be achieved. Consequently, redundancy in the register circuitry can be reduced, and area efficiency can be improved. Attached Figure Description

[0044] The foregoing contents, additional objects, embodiments, features, and advantages of this disclosure can be better understood through the following illustrative and non-limiting detailed description with reference to the accompanying drawings. Unless otherwise stated, the same reference numerals will be used for the same elements in the drawings.

[0045] Figure 1 A cross-section of a 3D IC device is schematically shown.

[0046] Figure 2 yes Figure 1 A schematic block diagram of the circuit configuration of a 3D IC device.

[0047] Figure 3a -b respectively shows Figure 2 A schematic perspective view of the 3D IC device, and the division of clock and data paths between the first and second circuit layers.

[0048] Figure 4 A cross-section of another 3D IC device is shown schematically.

[0049] Figure 5 yes Figure 4 A schematic block diagram of the circuit configuration of a 3D IC device.

[0050] Figure 6 It is included in (for example) Figure 1 or Figure 2 A circuit diagram of registers that divide the clock and data paths between the first and second circuit layers of a 3D IC device. Detailed Implementation

[0051] Example embodiments of 3D integrated circuits (ICs) or 3D IC devices will now be described with reference to the accompanying drawings. The drawings are schematic only, and the relative dimensions of some structures and layers may be exaggerated and not drawn to scale. Instead, dimensions may be adjusted to make the illustrations clear and easy to understand. When appearing in the drawings, the indicated axes X and Y always point in the horizontal and vertical directions, respectively. As used herein, the term "horizontal" refers to a direction parallel to the main extension plane of a device layer, die, or substrate of the 3D IC. The term "vertical" refers to a direction parallel to the normal direction of the main extension plane of the bottom of the device layer, die, or substrate, i.e., transverse to the horizontal direction. In other words, "horizontal" and "vertical" refer to in-plane and out-of-plane directions relative to the device layer, die, or substrate, respectively. In this disclosure, when an element (e.g., a layer or other structure) is referred to as being "on" another element, it can be directly on the other element or on one or more intermediate elements on the other element. Conversely, when an element is referred to as being "directly on another element," there are no intermediate elements, and therefore the element forms physical contact or adjacency with the other element. In this disclosure, when two elements are referred to as “connection” or “interconnection”, unless otherwise stated, this means that the elements are electrically connected or coupled directly or via one or more intermediate conductive structures (e.g., interconnections).

[0052] Figure 1 A schematic cross-section of a 3D IC device 100 according to some embodiments of the present disclosure is shown. The IC device 100 includes a stack of circuit layers, including a first circuit layer 110 and a second circuit layer 120. As seen along the Y direction, the first circuit layer 110 is stacked on top of, i.e., disposed above, the second circuit layer 120. Although Figure 1 Two circuit layers 110 and 120 are shown, but the first and second circuit layers 110 and 120 can more generally be two of a plurality of stacked circuit layers. As further described below, in some embodiments, the first circuit layer 110 and the second circuit layer 120 may correspond to a first die and a second die in a die stack, respectively.

[0053] The first circuit layer 110 includes a first semiconductor device layer 111 (hereinafter referred to as the "device layer"). The second circuit layer 120 includes a second device layer 121. The first circuit layer 110 includes a first group of active devices 115. The second circuit layer 120 includes a second group of active devices 125. Figure 1As shown, the first device layer 111 may include a substrate 112 and a front-end line (FEOL) structure 114 disposed or formed on the substrate 112 and including a first set of active devices 115. Therefore, the first set of active devices 115 may be referred to as the front-end transistor of the FEOL structure 114. The second device layer 121 may have a corresponding structure, thus including a substrate 122 (corresponding to substrate 112) and an FEOL structure 124 (corresponding to FEOL structure 114) disposed or formed on the substrate 122 and including a second set of active devices 115. Therefore, the second set of active devices 125 may be referred to as the front-end transistor of the FEOL structure 124. Substrates 112 and 122 may each be conventional semiconductor substrates suitable for CMOS circuits and semiconductor device processing, such as Si, Ge, or SiGe semiconductor substrates. Other non-limiting examples include silicon-on-insulator (SOI) substrates, GeOI substrates, or SiGeOI substrates. The term "FEOL structure" as used herein refers to a layer, hierarchy, or vertical portion of an IC device, comprising an active semiconductor layer (i.e., an active region or pattern comprising an active device / transistor) and a gate layer (i.e., a gate comprising an active device). The active region may include the S / D region and channel region of the active device. An FEOL structure may also include local contact or interconnect layers (i.e., source / drain (S / D) contacts comprising active devices). Although referred to as a single layer, a local contact layer typically includes (at least) two metal layers: a bottom layer ("contact active" or "trench silicide") and a top layer or "plug" layer (e.g., TiN, Co, Ru, and / or W). Active devices in an FEOL structure may include NMOSFETs and PMOSFETs, implemented as horizontal channel FETs such as FinFETs, nanosheet FETs, or nanowire FETs. The active semiconductor layer may be formed from semiconductors such as Si, Ge, or SiGe, or other bulk / 3D semiconductors conventionally used to implement CMOS devices. The active semiconductor layer can be formed on the substrate or in a thickness portion of the substrate (e.g., the corresponding substrate 112 or 122 in the illustrated example).

[0054] IC device 100 also includes first and second interconnect structures 116, 126, such as back-end line (BEOL) interconnect structures. The term "BEOL interconnect structure" (or simply "interconnect structure") refers herein to a vertical stack of interconnect layers, each interconnect layer including interconnects (typically metallic) embedded in an interlayer dielectric, such as horizontal wiring interconnects (conductive traces or lines) or vertical wiring interconnects ("vias"). A horizontal wiring interconnect layer may be referred to as a "metal wiring layer" (or simply "wiring layer"). A vertical wiring interconnect layer may be referred to as a via layer. Thus, via layers can provide vertical routing of signals between different metal wiring layers, or between wiring layers and conductive elements (e.g., gates or S / D contacts) of the BEOL structure.

[0055] A first interconnect structure 116 is disposed on a first side 111a of the first device layer 111. As shown, the first side 111a is the side of the first device layer 111 facing away from the second device layer 121. A second interconnect structure 126 is disposed on a second side 111b of the first device layer 111. As shown, the second side 111b is the opposite side of the first device layer 111 facing the second device layer 121. Therefore, the second interconnect structure 126 is disposed between the first and second device layers 111 and 121. In the example shown, the first side 111a defines the front side 111a of the FEOL structure 114 and the first device layer 111, while the second side 111b defines the back side 111b of the FEOL 114 and the first device layer 111. Therefore, with respect to the FEOL structure 114 and the first device layer 111, the first interconnect structure 116 can be referred to as the (first) front interconnect structure 116, and the second interconnect structure 126 can be referred to as the back interconnect structure 126.

[0056] exist Figure 1 In this disclosure, a first device layer 111 and a first / front-side interconnect structure 116 are shown as being included in a first circuit layer 110, while a second device layer 121 and a second / back-side interconnect structure 126 are shown as being included in a second circuit layer 120. In some embodiments, the division of the IC device 100 into first and second circuit layers 110, 120 may correspond to the actual structure and / or manufacturing-related division of the IC device 100. For example, in the case where the IC device 100 comprises a die stack, the first circuit layer 110 and the second circuit layer 120 may correspond to a first die and a second die, respectively. In this disclosure, the term "die" is used to refer to the die structure or chip of an IC device. Therefore, the first (semiconductor) device layer 111 (e.g., including a substrate 112 and a FEOL structure 114) may be the device layer of the first die, and the first interconnect structure 116 may be the front-side interconnect structure of the first die. Therefore, the second (semiconductor) device layer 121 (e.g., including substrate 122 and FEOL structure 124) can be a device layer of the second die, and the second interconnect structure 126 can be a front-side interconnect structure of the second die. The first and second circuit layers / dies 110, 120 can be fabricated and then stacked and bonded via the second interconnect structure 126, which faces the back side 111b of the first die (i.e., back-facing). Thus, although the second interconnect structure 126 in this example is fabricated on the front side of the second die, it can define a back-side interconnect structure 126 relative to the first die after stacking and bonding. Die stacks can be formed using any of die-to-die bonding, wafer-to-die bonding, or wafer-to-wafer bonding.

[0057] In another example, a first portion of the second interconnect structure 126 (i.e., a first subset of the interconnect layer) may be formed during the backside processing of the first die / wafer, and a second portion of the second interconnect structure 126 (i.e., a second subset of the interconnect layer) may be formed during the frontside processing of the second die / wafer. In this case, the second interconnect structure 126 may be formed by bonding the first and second portions of the second interconnect structure 126 during the bonding process of the first and second dies / wafers, thereby forming a backside interconnect structure 126 defined relative to the first die. As another example, the second interconnect structure 126 may be formed exclusively during the backside processing of the first die / wafer, after which the first and second dies may be bonded to the second device layer 111 of the second die via the second interconnect structure 126.

[0058] Furthermore, in the illustrated example, each of the first and second device layers 111, 121 includes a respective substrate 112, 122. However, according to techniques known in the art itself, substrate or wafer thinning can be performed during device fabrication to provide access to active devices (e.g., source / drain contacts) from the back side. Therefore, substrates 112, 122 can be thinned prior to bonding. In cases of extreme substrate thinning, the substrate can be substantially removed, leaving only the FEOL structure 114 or 124 in the finished IC device 100. Therefore, in some embodiments, Figure 1 The substrates 112 and 122 shown can be considered optional.

[0059] In another example, the first and second dies can be bonded back-to-back, such that the front side 121a of the second device layer 121 faces away from the first device layer 111. In this case, similar to the device fabrication example described above, the second interconnect structure 126 can be formed by the following steps: exclusively forming the back-side interconnect structure of the second die / wafer during the back-side processing of the first die / wafer and subsequently bonding it to the back-side of the second die / wafer; forming a second portion of the second interconnect structure 126 during the back-side processing of the second die / wafer and forming a corresponding first portion of the second interconnect structure 126 during the back-side processing of the first die / wafer and subsequently bonding it to the second portion; or exclusively forming the back-side interconnect structure of the first die / wafer during the back-side processing of the first die / wafer and subsequently bonding it to the back-side of the second die / wafer.

[0060] In another example, the second device layer 121 can be implemented by back-end transistors arranged in the second / back-side interconnect structure 126. Examples of back-end transistors include TFTs, such as CNT FETs and / or 2D channel FETs. A CNT FET is a transistor device with a channel structure including one or more CNTs. A 2D channel FET is a transistor device with a channel structure including a 2D semiconductor. Examples of 2D semiconductors include transition metal dichalcogenides (TMD), IGZO, IGO, and other suitable 2D semiconductors commonly used to implement back-end transistors. The back-end transistors can be formed, for example, during the back-side processing of the first die / wafer. Fabrication of the back-end transistors can include process techniques known in the art itself, such as depositing channel material over the interconnect layer of the (BEOL) interconnect structure, patterning and doping the channel material to form channel regions and S / D regions, gate stacking, and S / D contact deposition, etc. After the formation of the back-end transistors is completed, additional interconnect layers can be processed over the back-end transistors, such as forming interconnects for the back-end transistors and / or interconnects for the back-side power distribution network (PDN), etc. Fabrication techniques that can be used to form back-end transistors include 3D sequential techniques (sometimes referred to as monolithic 3D integration), which involve transferring a blanket active layer onto a pre-fabricated FEOL structure and interconnect structure (below). In monolithic 3D integration, the back-end transistors need to be fabricated with a low thermal budget to avoid degradation of the front-end transistors of the FEOL structure, typically below 500°C. Therefore, the back-end transistors can advantageously be BEOL-compatible devices. Further details regarding the fabrication and integration of the back-end transistors are known in the art and will not be described further herein.

[0061] In each of the above example implementations, the second interconnect structure 126 is arranged between the first and second device layers 111, 121, and may be referred to as the back-side interconnect structure 126 relative to the first device layer 111 and the first FEOL structure 114. Accordingly, the second circuit layer 120 may be referred to as the back-side circuit layer 120 relative to the first device layer 111 and the first circuit layer 110.

[0062] Figure 2 This is a schematic block diagram illustrating the circuit configuration of the 3D IC device 100. For example... Figure 2As shown, IC device 100 includes logic circuitry 210 and clock distribution network 224. Logic circuitry 210 is included in both a first circuit layer 110 and a second circuit layer 120. In other words, logic circuitry 210 is defined by circuit portions or blocks of the first and second circuit layers 110 and 120. Clock distribution network 224 is included in the second circuit layer 120. Logic circuitry 210 includes multiple circuit portions or blocks 202, 214, and 216, at least some of which are synchronization circuits timed by clock distribution network 224. Each of circuit blocks 202, 214, and 216 includes active devices (transistors) included in the first set of active devices 115 of the first device layer 111. That is, the active devices of circuit blocks 202, 214, and 216 refer to any active devices / transistors (typically a subset) included in the first device layer 111 (e.g., the first FEOL structure 114) of logic circuitry 210. As further described below, logic circuit 210 includes a set of registers 202, which includes active devices 212 of the first device layer 111 and active devices 222 of the second device layer 121. For ease of explanation, the same reference numerals 202, 212, 222, 214, and 216 are used below to refer to the various circuit blocks of logic circuit 210 and the active devices included in or implementing these circuit blocks.

[0063] Clock distribution network 224 includes a group of active clock devices 225, 226 formed by active devices (transistors) included in the second group of active devices 125 of the second device layer 121. That is, the active devices (transistors) in this group of active clock devices 224 refer to any active device / transistor (typically a subset) included in the second group of active devices 125 (e.g., the second FEOL structure 124) of the group of active clock devices 225, 226. For ease of explanation, the same reference numerals 225, 226 are used below to refer to the individual active clock devices of clock distribution network 224 and the second active devices included in or implementing these active clock devices. Clock distribution network 224 also includes a plurality of clock signal routing interconnects arranged in the second / backside interconnect structure 126, schematically represented by horizontally oriented lines 227. The clock signal routing interconnects 227 can be implemented using a combination of routing layers and via layers of the backside interconnect structure 126. The clock signal routing interconnect 227 also includes inter-layer interconnects connected to the logic circuitry 210 of the first circuit layer 110 to vertically route the clock signal between the first and second circuit layers 110, 120. An example of the inter-layer interconnect is... Figure 2The vertically oriented line 228 is schematically represented in the diagram. Vertically oriented line 203 is a further example of an interlayer interconnect, however, it has a different function than interlayer interconnect 228, as described further below. The specific implementation of interlayer interconnects 203 and 228 may depend on the device technology used to implement the IC device 100. For example, in the case of a 3D sequential manufacturing process, interlayer interconnects can be implemented through a combination of horizontal wiring interconnects of one or more metal wiring layers, vias of one or more via layers of the back-side interconnect structure 126, and interlayer contacts. In the case of die / chip stacking, interlayer contacts can be implemented through back-side contacts or hybrid bonding pads, i.e., bonding pads of the first and second dies. Where the first device layer 111 includes a substrate 112, the interlayer contacts may also include through-silicon vias (TSVs) extending through the substrate 112 and connecting to the active device 115 of the first FEOL structure 114. In this disclosure, the term "TSV" refers to a through-hole structure (i.e., a vertical electrical interconnect) extending through a die substrate, regardless of the type of semiconductor material of the substrate, and is consistent with its typical use in the semiconductor industry.

[0064] The clock distribution network 224 can be implemented as a clock tree (e.g., an H-tree). However, other topologies are also possible, such as clock grids, clock ridges, clock fishbones, serpentine architectures, or combinations thereof. The active clocking devices of the clock distribution network 224 may include active clocking devices 225, 226, such as clock drivers, clock repeaters, clock gates, clock dividers, clock multiplexers, and / or clock buffers (input / output buffers and balancing buffers). For example, reference numeral 225 may denote any one of a clock driver, clock repeater, clock gate, clock divider, clock multiplexer, or clock tree balancing buffer. Furthermore, reference numeral 226 may denote a clock buffer configured to be connected to a clock signal output of one or more corresponding clock signal inputs of logic circuit 210.

[0065] Logic circuit 210 may include a set of clock inputs, each connected to the output of clock buffer 222 to receive a clock signal from clock distribution network 224. Each clock input of logic circuit 210 may be connected to a corresponding synchronization circuit section or block within logic circuit 210. Logic circuit 210 may include various combinations of registers, macros, IP blocks, and / or non-IP blocks.

[0066] For example, reference numeral 214 can represent any of a macro, an IP block, or a non-IP block. Reference numeral 216 can represent other logic circuit blocks, such as combinational logic circuit blocks. Reference numeral 202 represents a register of logic circuit 210. Each register 202 may include flip-flops and / or latches. Although Figure 2Although not explicitly shown, register 202 can be connected to other circuit blocks 214, 216 of logic circuit 210 to receive, store, and provide data processed by logic circuit 210. Each register 202 includes one or more clock inputs, each connected to a corresponding clock output of clock distribution network 220. Specifically, the clock inputs of register 202 can be connected to the clock output of clock buffer 226 of clock distribution network 224. Register 202 will be discussed in more detail below.

[0067] The advantage of implementing the active clock devices 225, 226 in the second device layer 121 of the second / backside circuit layer 120 is that the active clock devices 225, 226 can be placed flexibly with less consideration for the layout of the circuit blocks 212, 214, 216 of the logic circuit 210 of the first circuit layer 110. For example, clock drivers, clock repeaters, clock gates, and / or clock buffers 225, 226 can be positioned in the backside circuit layer 120 where they bring the greatest benefit to the performance of the clock distribution network 224. In conventional implementations of backside clock distribution networks, the active clock devices are implemented by active devices / transistors that have the same device layer (e.g., the same die) as the clock / synchronization logic and memory circuits. Therefore, the circuit layout needs to be designed with space (e.g., die area) to accommodate the active clock devices next to the logic and memory circuits. In contrast, according to this disclosure, since the active devices 115 implementing circuit blocks 214, 216 of logic circuit 210 and the active devices 125 implementing active clock devices 225, 226 are arranged in different circuit and device layers 110 / 111 and 120 / 121, the active clock devices 225, 226 can be arranged within the occupied area of ​​circuit blocks 214, 216 in logic circuit 210. Another advantage is that it allows back-side routing of the clock distribution network and reduces area loss. The reduced area loss stems from the fact that the active devices 225, 226 do not occupy any occupied area in the first device layer 111, and further from the fact that fewer connections are required between the clock distribution network 224 and the first device layer 110 compared to (as in conventional implementations) arranging the transistors of all active clock devices in the first semiconductor device layer 111.

[0068] Still referencing Figure 2 The clock distribution network 224 can be integrated with the power distribution network (PDN) 230 in the back circuitry layer 120 and the back interconnect structure 126. PDN 230 in Figure 2The diagram is shown in a highly schematic manner, but as those skilled in the art will understand, multiple power rails (e.g., VDD and VSS) may be included in the back-side interconnect structure and configured to power the logic circuit 210 and the clock distribution network 224. Consistent with the designation of the second circuit layer 120 and the second interconnect structure 126 as back-side circuit layer 120 and back-side interconnect structure 126, the PDN 230 may be referred to as back-side PDN 230, i.e., relative to the first device layer 111 and the first circuit layer 110.

[0069] In addition to the interconnects of the back-side interconnect structure 126 described above (e.g., clock signal routing interconnect 227, power rails of PDN 230, etc.), the back-side interconnect structure 26 may also include interconnects configured for signal routing between the second active devices 125 (e.g., in one or more metal routing and via layers). That is, the back-side interconnect structure 126 may also be configured to layer-interconnect the second active devices 125 to implement various circuit functions of the back-side circuit layer 120, such as the active clock devices 225, 226 discussed below and other clock path portions 222 of register 202.

[0070] Another advantage associated with the dedicated implementation of clock buffer 226 in the second device layer 121 is that clock buffer 226 can be arranged close to the connected register 202 with little or no area loss to the first device layer 111. This can be understood more fully from further discussion.

[0071] According to this disclosure, each register 202 is implemented by active devices 212 of a first device layer 111 and active devices 222 of a second device layer 121. More specifically, each register 202 includes a first active device arranged along the data path of register 202 and a second active device arranged along the clock path of register 202. The first active device is included in a first group of active devices 115 of the first semiconductor device layer 111, and the second active device is included in a second group of active devices 125 of the second semiconductor device layer 121 and connected to a clock distribution network 224 to receive a clock signal. The terms "data path portion" and "clock path portion" will be used below to refer to the circuit portions (transistors and interconnects) of register 202 that respectively implement the clock path and data path of register 202. For readability and brevity, the same reference numeral 212 may be used below to refer to the first active device of register 202 and the data path portion of register 202. Accordingly, the same reference numeral 222 may be used to refer to the second active device of register 202 and the clock path portion of register 202. Therefore, following this convention, the active device (transistor) of the clock path portion 222 of each register 202 has a gate terminal configured to receive a clock signal from the clock output of the clock distribution network 224. That is, each transistor in the clock path portion 222 is configured to be directly gated by the clock signal and thus timed (i.e., triggered) by the clock signal. The clock signal may specifically be received from the clock buffer 226. The clock buffer 226 may be arranged relatively close to the clock path portion 222, as both are located in the back circuit layer 120. Furthermore, the active device (transistor) of the data path portion 212 of each register 202 includes a gate terminal configured to receive a data signal (i.e., a non-clock signal) from the data input of the register 202. Figure 2 As shown, the interconnection between the data and clock path portions 212, 222 of each register 202 is implemented by one or more inter-layer interconnects 203.

[0072] Figure 6 This is a circuit diagram of an example implementation of register 202, which includes a data path portion 212 (“dash-dot” bounding box) and a clock path portion 222 (“dot” bounding box), which can be used in IC device 100 or discussed below. Figure 5 Another IC device, 300, will be further referenced below. Figure 1 and Figure 2 Describe the circuit diagram.

[0073] Register 202 is illustrated herein as a two-stage latch, but the design principles can be applied accordingly to other register implementations. In conventional implementations of two-stage latch registers in a die, the clock and data path portions are implemented on the front side of the die. Therefore, the register transistors are arranged in the FEOL structure, and the associated interconnects are arranged in the front BEOL interconnect structure. Furthermore, the transistors in the data path portion are typically arranged closer to the power rails (pull-up rail VDD and pull-down rail VSS) than the transistors in the clock path portion. That is, the transistors in the clock path portion are typically connected to the power rails only via one transistor in the data path portion. In contrast, according to this disclosure, the transistors in the data path portion 212 are located in the first device layer 111 (e.g., in the FEOL structure 114), and the transistors in the clock path portion 222 are located on the back side 111b of the second device layer 111. Furthermore, the interconnects within the data path portion 212 are routed via the front interconnect structure 116, while the interconnects within the clock path portion 222 are routed via the back interconnect structure 126. Figure 6 In the figure, the positions of the inter-layer interconnects 228 are represented by diamonds. Furthermore, as shown, the transistors (and cells) of the clock path portion 222 can be arranged closer to the power rails VDD / VSS than the transistors (and cells) of the data path portion 212. Therefore, the transistors of the data path portion 212 are typically connected to the power rails only via the transistors of the clock path portion 222. This effectively reduces the number of inter-layer interconnects 228 required in the implementation where the power distribution network (PDN) is co-integrated with the clock power distribution network 224 in the back-side circuitry layer 120 (described below).

[0074] Figure 3a -b respectively shows Figure 1 and Figure 2 A schematic perspective view of the IC device 100, and an example configuration of the clock buffer 226 and register 202, specifically the partitioning of data and clock path portions 212, 222 between the first and second circuit layers 110, 120. Figure 3a In the diagram, the clock distribution network 224 is depicted using an H-tree implementation. Figure 3b In this diagram, clock buffer 226 is exemplified by a first clock buffer 222-1 with a fan-out (FO) of 4, and connected to a set of second clock buffers 222-6 with a fan-out of FO=8. This set of second clock buffers 222-6 is further connected to a corresponding set of registers 202, depicted here using flip-flops as an example. The first and second clock buffers 226-1 and 226-2 may, for example, have drive strengths of 16 and 8, respectively.

[0075] In summary, dividing register 202 into data and clock path portions 212, 222 between the first and back-side circuitry layers 110, 120, in conjunction with the back-side routing of clock distribution network 224 and back-side PDN 230, achieves several advantages. First, it reduces the footprint of register 202 because the data and clock path portions 212, 222 can be arranged with overlapping footprints, and because the number of inter-layer connections between clock distribution network 224 and the first semiconductor device layer 111 can be reduced. Second, it facilitates clock tree skew balance, reducing area loss. Third, the layout and pin arrangement of the clock path portion 222 of register 202 can be more easily aligned with the design rules associated with the back-side interconnect structure 120, as they are independent of the design rules associated with the first device layer 111.

[0076] In the above discussion, only a single back-side interconnect structure 126 of the back-side circuit layer 120 is referred to, where the back-side interconnect structure 26 includes clock signal routing interconnects 227 of the clock distribution network 224, etc. However, as Figure 1 As shown, the back-side circuit layer 120 may include another back-side interconnect structure 128 disposed on the opposite side 121b of the second device layer 121, for example, on the back side of the second device layer 121. This provides further implementation options for back-side clock routing. In embodiments including back-side interconnect structures 126 and 128, the interconnect structure 116 of the first circuit layer 110 may be referred to as the first interconnect structure 116, the interconnect structure 128 of the back-side circuit layer 120 may be referred to as the second interconnect structure 128 (“back-side interconnect structure 128”), and the interconnect structure 126 may be referred to as the third interconnect structure 126 (“back-side interconnect structure 126”). Therefore, the back-side interconnect structure 128 refers to the interconnect structure of the back-side circuit layer 120 disposed on the back side 121b of the first device layer 121, while the back-side interconnect structure refers to the back-side circuit layer 120 disposed on the front side 121a of the second device layer 121, i.e., between the first and second active device layers 111, 121. In this configuration, a first subset of the clock signal routing interconnects 227 may be included in the back-side interconnect structure 128, allowing clock signals to be routed on the back side of the second device layer 121. Furthermore, a second subset of the clock signal routing interconnects 227 may be included in the back-side interconnect structure 126. For example, the first and second subsets of the clock signal routing interconnects 227 may be connected via TSVs through the second device layer 121. The back-side interconnect structure 126 may also include inter-layer interconnects 203 and 228.

[0077] The two rear-side interconnect structures 126, 128 also enable further options for rear-side power distribution. For example, in this case, Figure 2The rear PDN 230 may include a first set of power rails arranged in the rear interconnect structure 128 and configured to power the clock circuit portion 222 of the clock distribution network 224 and register 202, and a second set of power rails arranged in the rear interconnect structure 126 and configured to power the logic circuit 210.

[0078] Figure 4 A schematic cross-section of another IC device 300 according to some embodiments of the present disclosure is shown schematically. IC device 300 and... Figure 1 Like IC device 100, it includes a circuit layer stack, which includes a first circuit layer 110 and a second circuit layer 120. The first circuit layer 110 and the second circuit layer 120 of IC device 300 typically correspond to Figure 1 The IC device 300 has a first circuit layer 110 and a third circuit layer 120. Therefore, to avoid unnecessary repetition, for a description of the characteristics of the first and second circuit layers 110 and 120 of the IC device 300, please refer to... Figure 1 Discussion of the characteristics of the corresponding numbers.

[0079] The difference between IC device 300 and IC device 100 is that IC device 300 also includes a third circuit layer 130. The third circuit layer 130 typically corresponds to the first circuit layer 110 and includes a third semiconductor device layer 131. As shown, similar to the first device layer 111, the third device layer 131 may include a substrate 132 and a FEOL structure 134 disposed on or formed on the substrate 132 and including a third set of active devices 135. Therefore, the third set of active devices 135 may be referred to as the front-end transistor of the FEOL structure 134. The first, second, and third circuit layers 110, 120, and 130 can be similar to... Figure 1 The discussion of the first and second circuit layers 110 and 120 of the IC device 100, corresponding to the first, second and third dies, is arranged to form a die stack. Furthermore, as described with reference to the second device layer 121 of the IC device 100, if the substrate 132 of the third device layer 131 is removed by substrate thinning during device manufacturing, it is not necessary to have it.

[0080] The third circuit layer 130 also includes a third BEOL interconnect structure 136. The third interconnect structure 136 is arranged on a first side 131a of the third device layer 131. As shown, the first side 131a is the side of the third device layer 131 facing away from the third device layer 131. In the example shown, the first side 131a defines the front side 131a of the FEOL structure 134 and the third device layer 131. Therefore, with respect to the FEOL structure 134 and the third device layer 131, the third interconnect structure 136 can be referred to as the (third) front interconnect structure 136. The third interconnect structure 136 is configured to interconnect a third group of active devices 135, particularly implementing the logic circuit portions or blocks of the third circuit layer 130, as will be referred to below. Figure 5 Further description.

[0081] Compared with the previous Figure 1The discussion of circuit layers 110 and 120 of IC device 100 is similar. The division of IC device 300 into first, second, and third circuit layers 110, 120, and 130 may, but does not necessarily, correspond to the actual structure and / or manufacturing-related division of IC device 300. For example, in the case where IC device 300 includes a die stack, the first circuit layer 110, second circuit layer 120, and third circuit layer 130 may correspond to the first die, second die, and third die, respectively. Therefore, the first device layer 111 may be the device layer of the first die, and the first interconnect structure 116 may be the front interconnect structure of the first die. The second device layer 121 may be the device layer of the second die, and the second interconnect structure 126 may be the front interconnect structure of the second die. The third device layer 131 may be the device layer of the third die, and the third interconnect structure 136 may be the front interconnect structure of the third die. Therefore, the first, second, and third circuit layers / dies 110, 120, 130 can be fabricated on the respective wafers and subsequently stacked and bonded via a second interconnect structure 126 facing the back side 111b of the first die (i.e., back-facing) and a third interconnect structure 136 facing the back side 121b of the second die. Thus, although in this example the second and third interconnect structures 126, 136 are fabricated on the front side of the second and third dies respectively, they can define a back-side interconnect structure relative to the first die after stacking and bonding. However, similar to the previous discussion of the IC device 100, other fabrication methods are also possible. For example, a first portion of the third interconnect structure 136 (i.e., a first subset of the interconnect layers) can be formed during the back-side processing of the second die / wafer, and a second portion of the third interconnect structure 136 (i.e., a second subset of the interconnect layers) can be formed during the front-side processing of the third die / wafer. In this configuration, the third interconnect structure 136 can be formed during the bonding of the second and third dies / wafers by bonding the first and second portions of the third interconnect architecture 136, thereby forming a common / composite third interconnect structure 136 defining the backside interconnect structure 136 relative to the first and second dies. As another example, the third interconnect structure 136 can be formed during the backside processing of the second die / wafer, after which the second and third dies can be bonded to the third device layer 131 of the third die via the third interconnect architecture 136. As another example, although in Figure 4In this configuration, the front side 131a of the third device layer 131 faces the first and second device layers 111 and 121, but the opposite orientation is also possible. That is, the third device layer 131 can be arranged such that its back side 1 faces the first and second device layers 111 and 121. In this case, the third interconnect structure 136 can also define a back-side interconnect structure relative to the third device layer 131. In this case, the third circuit layer 130 may typically include another front-side interconnect structure arranged on the front side 131a of the third device layer 131 and configured to interconnect a third group of active devices 135, for example, to implement their circuit portions or blocks.

[0082] Figure 5 This is a schematic block diagram illustrating the circuit configuration of the 3D IC device 300. For example... Figure 5 As shown, IC device 300 includes logic circuitry 310. Furthermore, IC device 310 includes a clock distribution network 324, which is included in the second and third circuit layers 120 and 130, as further described below.

[0083] Clock distribution network 324 typically corresponds to clock distribution network 220 of IC device 100 and therefore includes a set of active clocking devices indicated by reference numeral 225, such as clock drivers, clock repeaters, clock gates, and / or clock tree balancing buffers, and clock buffers 226 configured to connect to clock signal outputs of one or more corresponding clock signal inputs of logic circuit 310. Active clocking devices 225, 226 are similar to clock distribution network 224 formed by the second set of active devices 125 included in the second device layer 121. Clock distribution network 324 also includes clock signal routing interconnects 227 and inter-layer interconnects 228, 229 for vertically routing clock signals between the first and second circuit layers 110, 120 and between the second and third circuit layers 120, 130. Inter-layer interconnect 229 is included in the third interconnect structure 136 and connected to the second clock circuit 310 of the third circuit layer 130 for vertically routing clock signals between the second and third circuit layers 120, 130.

[0084] Logic circuit 310 typically corresponds to logic circuit 210 of IC device 100; however, the difference is that logic circuit 310 is included in each of the first, second, and third circuit layers 110, 120, and 130. Therefore, logic circuit 310 includes circuit portions or blocks 202, 212, 214, and 216 corresponding to the corresponding numbered circuit blocks of logic circuit 210 of IC device 100. Furthermore, logic circuit 310 includes multiple other circuit portions or blocks 302, 314, and 316, at least some of which are synchronization circuits timed by clock distribution network 324. Each of circuit blocks 302, 314, and 316 includes active devices (transistors) included in the third group of active devices 135 of the third device layer 131. That is, the active devices of circuit blocks 302, 314, and 316 refer to any active device / transistor (typically a subset) included in the third device layer 131 (e.g., the third FEOL structure 134) of logic circuit 310.

[0085] The third circuit layer 130 may include various combinations of registers, macros, IP blocks, and / or non-IP blocks, each combination being implemented by a corresponding subset of the third set of active devices 135 of the third device layer 131. For example, reference numeral 314 may denote any one of a macro, IP block, or non-IP block. Reference numeral 316 may denote some other logic circuit block, such as combinational logic circuit block 316.

[0086] Furthermore, logic circuit 310 includes a first set of registers 202 corresponding to registers 202 of logic circuit 210, and thus includes a data path portion 212 in the first circuit layer 110 and a clock path portion 222T in the second circuit layer 120 interconnected via inter-layer interconnect 203. Logic circuit 310 also includes a second set of registers 302. According to this disclosure, each register 302 is implemented by active devices 312 of the third device layer 131 and active devices 322 of the second device layer 121. More specifically, each register 302 includes a third active device arranged along the data path of register 302 and a fourth active device arranged along the clock path of register 302. The third active device is included in a third set of active devices 135 of the third semiconductor device layer 131, and the fourth active device is included in a second set of active devices 125 of the second semiconductor device layer 121 and connected to the clock distribution network 324 to receive clock signals. Similar to the discussion of register 202 of IC device 100, each register 302 correspondingly includes a data path portion 312 implementing the data path of register 302 and a clock path portion 322 implementing the clock path of register 302. Therefore, the active device (transistor) of the clock path portion 322 of each register 302 has a gate terminal configured to receive a clock signal from the clock output of clock distribution network 324. That is, each transistor in the clock path portion 322 is configured to be directly gated by the clock signal and thus timed (i.e., triggered) by the clock signal. The clock signal may specifically be received from clock buffer 226. Furthermore, the active device (transistor) of the data path portion 312 of each register 302 includes a gate terminal configured to receive a data signal (i.e., a non-clock signal) from the data input of register 302. Figure 5 As shown, the interconnection between the data and clock path portions 312, 322 of each register 302 is implemented by one or more inter-layer interconnects 303. The inter-layer interconnects 303 can be implemented in the same manner as inter-layer interconnects 203, 228, and 229.

[0087] like Figure 5 As further shown, the second circuit layer 120 may also include a common register circuit 222C shared by the clock path portion 222T of the first register 202 and the clock path portion 222B of the second register 302. The common register circuit 222C may include a fifth active device, which is arranged along the clock paths of the first and second registers 202 and 302 and is included in the second group of active devices 125 and connected to the clock distribution network 324 to receive clock signals.

[0088] The clock distribution network 320 can also be integrated with the PDN 230 in the second circuit layer 120 and the second interconnect structure 126, just like the clock distribution network 220 of the IC device 100.

[0089] Therefore, the benefits discussed with reference to IC device 100, and the division of data and clock path portions 212, 222 of register 202 between the first and second circuit layers 110, 120, can also be applied to multilayer IC device 300. Furthermore, clock distribution network 324 can be shared by registers 202, 302, and any other circuit blocks 214, 216, 314, 316 of the first and third circuit layers 110, 130, which are timed by clock signals. This applies accordingly to PDN 230.

[0090] Those skilled in the art will recognize that the invention is by no means limited to the examples described above. Rather, many modifications and variations are possible within the scope of the appended claims. For example, in the examples shown above, each active clocking device, including the clock drivers, clock repeaters, clock gates, and / or input / output / balanced clock buffers of clock distribution networks 224, 324, is implemented by active devices of the second device layer 121. However, the active clocking devices of clock distribution networks 224, 324 may also be distributed across different circuit layers (for clock distribution network 244 between circuit layers 110, 120, and for clock distribution network 324 between two or more of circuit layers 110, 120, 130). Thus, only some of the active clocking devices in clock distribution networks 224, 324 may be implemented by the second group of active devices 125 of the second device layer 121, while other active clocking devices may be implemented by the first and / or third group of active devices 115, 135 of the first and / or third device layers 111, 131. Typically, it can be advantageous to implement at least a clock buffer (input / output / balance) for the clock distribution network 224, 324 via the second set of active devices 125 of the second device layer 121. This is because the aforementioned benefits of promoting clock tree balance can be maintained. Furthermore, since the connections between the clock buffer 226 and registers 202, 302 are typically more numerous than the connections to clock drivers or clock gates, it is conceivable that this can further contribute to minimizing the area loss of clock back-end routing.

Claims

1. A 3D integrated circuit (IC) device, comprising: The first semiconductor device layer includes the first group of active devices; The second semiconductor device layer includes the second group of active devices; The system includes a clock distribution network that interconnects multiple clock signal routes in an interconnect structure arranged on the side of the first semiconductor device layer facing the second semiconductor device layer. as well as The logic circuit includes multiple registers, each register including a first active device arranged along the data path of the register and a second active device arranged along the clock path of the register. The first active device is included in the first group of active devices in the first semiconductor device layer, and The second active device is included in the second group of active devices in the second semiconductor device layer and is connected to the clock distribution network to receive clock signals.

2. The 3D IC device of claim 1, wherein each of the second active devices includes a gate terminal configured to receive the clock signal from the clock distribution network.

3. The 3D IC device of claim 2, wherein each first active device of the corresponding register is an active device of the register connected to the clock distribution network only via one or more second active devices of the corresponding register.

4. The 3D IC device of claim 1, wherein the clock distribution network further comprises a group of active clock devices formed by the active devices included in the second group of active devices of the second semiconductor device layer.

5. The 3D IC device of claim 4, wherein the group of active clock devices includes a clock buffer.

6. The 3D IC device of claim 4, wherein the group of active clock devices includes one or more active clock devices located within the occupied area of ​​a circuit block, the circuit block being any one of a macro, IP block, or non-IP block, and including active devices from the first group of active devices of the first semiconductor device layer.

7. The 3D IC device of claim 1, wherein the clock distribution network is a clock tree.

8. The 3D IC device of claim 1, wherein each register is a flip-flop or a latch.

9. The 3D IC device as described in claim 1, characterized in that... It also includes a power distribution network arranged in an interconnection structure comprising multiple clock signal routing interconnections and configured to supply power to the logic circuit and the clock distribution network.

10. The 3D IC device of claim 1, wherein the 3D IC device further comprises a first interconnect structure disposed on the side of the first semiconductor device layer opposite to the second semiconductor device layer and configured to interconnect the first group of active devices.

11. The 3D IC device of claim 10, wherein the interconnect structure of the plurality of clock signal routing interconnects is a second interconnect structure and is arranged on the side of the second semiconductor device layer facing the first semiconductor device layer.

12. The 3D IC device of claim 10, wherein the interconnect structure of the plurality of clock signal routing interconnects is a second interconnect structure and is arranged on the side of the second semiconductor device layer opposite to the first semiconductor device layer, and The 3D IC device further includes a third interconnect structure, which is disposed on the side of the second semiconductor device layer facing the first semiconductor device layer and configured to interconnect the second group of active devices.

13. The 3D IC device as described in claim 1, characterized in that... It also includes a third semiconductor layer, which comprises a third set of active devices. The logic circuit includes multiple registers, which are multiple first registers. The logic circuit also includes multiple second registers, each of which includes a third active device arranged along the data path of the second register and a fourth active device arranged along the clock path of the second register. The third active device is included in the third group of active devices in the third semiconductor device layer, and The fourth active device is included in the second group of active devices in the second semiconductor device layer and is connected to the clock distribution network to receive the clock signal.

14. The 3D IC device of claim 13, wherein the logic circuitry further comprises a common register circuit shared by the first register and the second register, the common register circuitry comprising a fifth active device arranged along the clock path of the first register and the second register, wherein the fifth active device is included in the second group of active devices in the second semiconductor device layer and connected to the clock distribution network to receive the clock signal.

15. The 3D IC device of claim 1, wherein the first semiconductor device layer is included in a first front end line (FEOL) structure of the first die of the 3D IC device, wherein the first FEOL structure is disposed on the front side of the first die and includes an interconnect structure for interconnecting the plurality of clock signal routings and the second semiconductor device layer is disposed on the back side of the first die opposite to the first side of the first die.

16. The 3D IC device of claim 15, wherein the second set of active devices of the second semiconductor device layer is included in the second FEOL structure of the second die, or wherein the second set of passive devices is a back-end transistor arranged in an interconnect structure including the plurality of clock signal routing interconnects.

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