A semiconductor data test anomaly early warning method and system

Abstract

This invention discloses a semiconductor data testing anomaly early warning method and system, relating to the field of integrated circuit testing technology. The method includes: performing a stepped voltage test on the chip under test by calibrating a purely electronic current signal, while simultaneously monitoring changes in drain current, substrate current increments, and voltage states; calculating hot carrier injection efficiency parameters based on drain current changes and substrate current increments, and combining these parameters with the voltage states to generate photon detection commands; driving an InGaAs avalanche photodiode array to collect photon pulse counts based on the photon detection commands, and calculating a chip damage risk index based on the hot carrier injection efficiency parameters and photon pulse counts to generate a risk assessment report. This invention calculates the chip damage risk index using hot carrier injection efficiency parameters and photon pulse counts, achieving dynamic damage quantification analysis by integrating electrical parameters and optical data, thus achieving holographic perception and early risk identification of chip anomalies.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a semiconductor data testing anomaly early warning method and system. Background Technology

[0002] In the field of semiconductor device testing, anomaly early warning mechanisms that combine real-time monitoring of electrical parameters with statistical process control are commonly used. As process nodes move below 5nm, the quantum tunneling effect in high-frequency test signals significantly increases, while hot carrier injection under high electric fields intensifies, leading to current signal distortion and device reliability degradation. Current mainstream methods acquire current / voltage parameters using multi-channel data acquisition cards, combined with preset static threshold models to trigger early warnings. Some advanced solutions incorporate infrared thermal imaging technology to monitor local temperature rise; this technology is widely used in FinFET and GAA transistor testing scenarios.

[0003] However, existing methods still have two key limitations: First, high-frequency test signals do not effectively eliminate parasitic current components caused by quantum tunneling, which reduces the reliability of the original data for damage criteria. For example, signals above 10 GHz are susceptible to interference from gate dielectric tunneling. Second, hot carrier monitoring and photon radiation detection are decoupled in time window, lacking a synchronous correlation mechanism for electro-optic physical effects, which weakens the dynamic characterization ability of multi-physics coupling risks. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a semiconductor data testing anomaly early warning method to solve the problems of fundamental component distortion caused by quantum tunneling effect in high-frequency test signals and dynamic characterization failure of hot carrier-photon cross-physical field risk.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a semiconductor data testing anomaly early warning method, comprising: acquiring the tunneling current component based on a quantum tunneling compensation three-element dataset, calculating a nonlinear compensation coefficient based on the current wafer temperature, performing joint correction of the original current signal for quantum tunneling effect and temperature drift, and acquiring a calibrated pure electronic current signal; performing a stepped voltage test on the chip under test using the calibrated pure electronic current signal, while monitoring the drain current change, substrate current increment, and voltage state; calculating the hot carrier injection efficiency parameter based on the drain current change and substrate current increment, and combining it with the voltage state to generate a photon detection command; driving an InGaAs avalanche photodiode array to collect photon pulse counts based on the photon detection command, calculating a chip damage risk index based on the hot carrier injection efficiency parameter and photon pulse count, and generating a risk assessment report; performing spatiotemporal feature analysis on the risk assessment report, identifying the layer pulse frequency, and performing interruption control based on the layer pulse frequency to generate an anomaly early warning report.

[0007] In a preferred embodiment of the semiconductor data testing anomaly early warning method of the present invention, the steps for acquiring the calibration pure electronic current signal are as follows: The quantum tunneling compensation three-element dataset includes the original current signal of the chip under test, wafer temperature data, and dielectric barrier height and thickness values. Based on the dielectric barrier height and thickness values ​​in the quantum tunneling compensation three-element dataset, the tunneling current component is calculated using the Shockley quantum tunneling equation, and the nonlinear compensation coefficient is calculated using the temperature compensation function based on the current wafer temperature. Based on the tunneling current component and the nonlinear compensation coefficient, the original current signal is jointly corrected for quantum tunneling effect and temperature drift to obtain a calibrated purely electronic current signal.

[0008] As a preferred embodiment of the semiconductor data testing anomaly early warning method of the present invention, the step of performing a stepped voltage test on the chip under test by calibrating a purely electronic current signal, while simultaneously monitoring the drain current change, substrate current increment, and voltage state, is as follows. The calibration pure electronic current signal is input to the voltage control circuit of the test machine, and a stepped voltage is applied to the gate terminal of the chip under test according to a preset sequence. During the stepped voltage test, a current acquisition channel is established through the SPI bus to monitor the changes in drain current, substrate current increment, and voltage status of the chip under test in real time.

[0009] In a preferred embodiment of the semiconductor data testing anomaly early warning method of the present invention, the steps for generating the photon detection command are as follows: Based on the change in drain current and the increment of substrate current, the hot carrier injection efficiency parameter is calculated using the substrate-drain current increment ratio efficiency method. The hot carrier injection efficiency parameter is then input into the threshold comparator to activate the photon detection enable signal. Wavelength mapping is performed on the voltage state to obtain the spectral window control parameters of the InGaAs detector; The photon detection enable signal is combined with the spectral window control parameters of the InGaAs detector, and binary parameters are configured synchronously to generate photon detection commands.

[0010] As a preferred embodiment of the semiconductor data testing anomaly early warning method of the present invention, the steps for driving the InGaAs avalanche photodiode array to collect photon pulse counts are as follows: Based on photon detection commands, the InGaAs avalanche photodiode array is driven to start detection within a specified spectral window and collect the number of photon pulses.

[0011] In a preferred embodiment of the semiconductor data testing anomaly early warning method of the present invention, the steps for generating the risk assessment report are as follows: Based on the hot carrier injection efficiency parameter and the number of photon pulses, the chip damage risk index is calculated using an electro-optical weighted fusion algorithm, and a risk assessment report is generated.

[0012] In a preferred embodiment of the semiconductor data testing anomaly early warning method of the present invention, the steps for generating the anomaly early warning report are as follows: Scan the pulse timestamp sequence in the risk assessment report, mark the pulse events, calculate the pulse time interval, and identify the layer pulse frequency value F; The layer pulse frequency value is input into the interrupt control mapping table, and interrupt control is performed according to the layer pulse frequency value to generate an abnormal early warning report.

[0013] In a second aspect, the present invention provides a semiconductor data testing anomaly early warning system, comprising a signal acquisition module, a chip testing module, an instruction generation module, a risk assessment module, and a pulse control module; The signal acquisition module is used to acquire the tunneling current component based on the quantum tunneling compensation three-element dataset, and calculate the nonlinear compensation coefficient according to the current wafer temperature to jointly correct the original current signal for quantum tunneling effect and temperature drift, thereby acquiring a calibrated pure electronic current signal. The chip testing module is used to perform a stepped voltage test on the chip under test by calibrating a purely electronic current signal, while monitoring the change in drain current, the increment of substrate current, and the voltage state. The instruction generation module is used to calculate the hot carrier injection efficiency parameters based on the change in drain current and the increment of substrate current, and combine them with the voltage state to generate photon detection instructions. The risk assessment module is used to drive the InGaAs avalanche photodiode array to collect the number of photon pulses based on photon detection commands, and to calculate the chip damage risk index based on the hot carrier injection efficiency parameter and the number of photon pulses, and generate a risk assessment report. The pulse control module is used to perform spatiotemporal feature analysis on the risk assessment report, identify the layer pulse frequency, and perform interruption control according to the layer pulse frequency to generate an anomaly warning report.

[0014] Thirdly, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, wherein when the computer program is executed by the processor, it implements any step of the semiconductor data testing anomaly early warning method as described in the first aspect of the present invention.

[0015] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements any step of the semiconductor data testing anomaly early warning method as described in the first aspect of the present invention.

[0016] The beneficial effects of this invention are as follows: by jointly correcting based on the three-element dataset of quantum tunneling compensation, the quantum tunneling effect and temperature drift in the original current signal are effectively eliminated, providing a high-fidelity reference signal for subsequent testing, thereby improving the accuracy of signal measurement and the precision of device reliability assessment; by calculating the chip damage risk index based on the hot carrier injection efficiency parameter and the number of photon pulses, dynamic damage quantification analysis integrating electrical parameters and optical data is realized, achieving holographic perception of chip abnormal states and early risk identification. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart for a semiconductor data testing anomaly early warning method.

[0019] Figure 2 This is a schematic diagram of a semiconductor data testing anomaly early warning system.

[0020] Figure 3 This is a flowchart for generating photon detection instructions.

[0021] Figure 4 The flowchart for the decision to interrupt regulation. Detailed Implementation

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0024] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0025] Reference Figures 1-4 As an embodiment of the present invention, this embodiment provides a semiconductor data testing anomaly early warning method, comprising the following steps: S1. Based on the quantum tunneling compensation three-element dataset, the tunneling current component is obtained, and the nonlinear compensation coefficient is calculated according to the current wafer temperature. The original current signal is then jointly corrected for quantum tunneling effect and temperature drift to obtain a calibrated pure electronic current signal. The three-element dataset for quantum tunneling compensation includes the raw current signal of the chip under test, wafer temperature data, and dielectric barrier height and thickness values. It should be noted that the raw current signal of the chip under test is acquired by a high-speed analog-to-digital converter at a sampling rate of 20GS / s; the wafer temperature data is read directly by a temperature sensor integrated on the wafer; and the dielectric barrier height and thickness values ​​are extracted from a process parameter database. Based on the dielectric barrier height and thickness values ​​in the quantum tunneling compensation three-element dataset, the tunneling current component is calculated using the Shockley quantum tunneling equation, and the nonlinear compensation coefficient is calculated using the temperature compensation function based on the current wafer temperature. The expression for calculating the tunneling current component is: ; in, It is an effective Richardson constant. It is the real-time wafer temperature. It is the thickness of the dielectric barrier. It is the dielectric barrier height. It's a shed pressure. It is the base of the natural logarithm (a mathematical constant, a fixed value); The expression for calculating the nonlinear compensation coefficient is as follows: ; in, It is the compensation base for the zero-order term. It is a linear temperature coefficient. It is the quadratic temperature coefficient. It is the real-time wafer temperature; Furthermore, the dielectric barrier height and thickness values ​​in the quantum tunneling compensation three-element dataset are input to the Shockley quantum tunneling equation via the SPI interface to calculate the tunneling current component; at the same time, the wafer temperature data in the quantum tunneling compensation three-element dataset is input to the temperature compensation function, and the nonlinear compensation coefficient is calculated in real time by the digital signal processor. Based on the tunneling current component and the nonlinear compensation coefficient, the original current signal is jointly corrected for quantum tunneling effect and temperature drift to obtain a calibrated pure electronic current signal. Furthermore, the tunneling current component and nonlinear compensation coefficient are input into a high-speed multiplier, and IEEE 754 floating-point operations are performed in a field-programmable gate array to generate the compensation amount. At the same time, the original current signal is digitized at a rate of 1MS / s through a 24-bit Δ-Σ analog-to-digital converter, and the compensation amount is combined with the original current signal through a precision current mirror to eliminate the quantum tunneling effect and temperature drift in the original current signal, generating a processed pure electronic current signal. Finally, the processed pure electronic current signal is back-sampled and verified through an 18-bit analog-to-digital converter, and a calibrated pure electronic current signal is output. It should be noted that a field-programmable gate array (FPGA) is a semiconductor device that reconfigures digital circuits through programmable logic blocks and interconnect resources, including programmable logic blocks, DSP slices, block random access memory, clock management units, and high-speed interfaces.

[0026] S2. Perform a stepped voltage test on the chip under test by calibrating a purely electronic current signal, while monitoring the change in drain current, the increment of substrate current, and the voltage state. The calibration pure electronic current signal is input to the voltage control circuit of the test machine, and a stepped voltage is applied to the gate terminal of the chip under test according to a preset sequence. Furthermore, the calibration pure electronic current signal is transmitted to the signal input port of the test machine voltage control circuit through an isolation amplifier. The test machine voltage control circuit samples the calibration pure electronic current signal at 1MS / s, extracts the fundamental component using the FFT algorithm, performs RMS calculation to calculate the effective value, and then verifies the amplitude-voltage linearity using the least squares method, outputting the resolved amplitude characteristic parameters. The drive power supply output circuit generates stepped voltage amplitudes according to a preset sequence from the resolved amplitude characteristic parameters, and finally applies the stepped voltage amplitudes to the gate terminal of the chip under test through the shielded coaxial channel of the probe card. It should be noted that the preset sequence is a pre-defined voltage step change rule; it is formulated according to the process specifications and reliability testing standards of the chip under test; it includes voltage step values, duration of each step, and transition rate between steps.

[0027] During the stepped voltage test, a current acquisition channel is established through the SPI bus to monitor the changes in drain current, substrate current increment, and voltage status of the chip under test in real time. Furthermore, during the stepped voltage test, a 32-bit configuration frame containing range selection bits, filter type, and gain calibration value is sent to the 24-bit Δ-Σ analog-to-digital converter via the SPI bus. After receiving the 32-bit configuration frame, the ADC switches the internal reference source within 50μs according to the range selection bits, activates the differential input buffer, configures the PGA gain, establishes a physical channel through a three-wire shielded connection of IN+ / IN- / GND, synchronously initializes the digital filter, and verifies linearity with a 1mA standard current. The three-wire differential current acquisition channel is then established. Based on this channel, the drain terminal output of the chip under test is connected to the picoammeter input port through a three-coaxial shielded connection, and data is acquired at a rate of 1MS / s. The original current signal is digitally filtered to eliminate high-frequency noise, and then the current difference between adjacent sampling points is calculated using a sliding window differential algorithm to finally output the drain current change. The original substrate current is captured by a high-sensitivity current probe, and after the common-mode noise is eliminated by a differential amplifier, it is converted into a differential voltage. It is then synchronously sampled and quantized by an 18-bit analog-to-digital converter at a rate of 500 kS / s, and high-frequency noise is eliminated by a 128th-order FIR filter. Finally, the incremental value is calculated by a sliding window differential algorithm to output the substrate current increment. The 16-bit high-precision digital-to-analog converter built into the test machine acquires the gate voltage signal of the chip under test through the differential input channel, eliminates high-frequency noise by an anti-aliasing filter, and outputs the voltage status after analog-to-digital conversion at a rate of 200 kS / s. It should be noted that the drain terminal of the chip under test is a highly doped region in the MOSFET device that is symmetrical to the source terminal. After the layout coordinates are aligned by photolithography, an ohmic contact is formed using a tungsten needle probe card, and the result is obtained after verification by IV curve.

[0028] S3. Calculate the hot carrier injection efficiency parameters based on the change in drain current and the increment of substrate current, and combine them with the voltage state to generate photon detection commands. The hot carrier injection efficiency parameters are calculated using the substrate-drain current increment ratio efficiency method based on the change in drain current and the increment of substrate current. The expression for calculating the hot carrier injection efficiency parameter is: ; in, It is a parameter for hot carrier injection efficiency. It is the substrate current increment, reflecting the secondary carriers generated by impact ionization. It is the change in drain current, which reflects the loss of kinetic energy of channel carriers; Furthermore, the change in drain current is sampled and quantized by a 24-bit Δ-Σ analog-to-digital converter and then input into the numerator of the substrate-drain current increment ratio efficiency method calculation formula. At the same time, the substrate current increment is amplified by a high-precision transimpedance amplifier and then input into the denominator of the substrate-drain current increment ratio efficiency method calculation formula. The substrate-drain current increment ratio efficiency method calculation is performed to obtain the hot carrier injection efficiency parameter. The voltage state is wavelength-mapped to obtain the spectral window control parameters of the InGaAs detector, and the hot carrier injection efficiency parameter is input to the threshold comparator to activate the photon detection enable signal. Furthermore, the voltage state is sampled and quantized by a 12-bit analog-to-digital converter and then input to a wavelength mapping table. The spectral window control parameters of the InGaAs detector are obtained by reading the wavelength mapping table. At the same time, the hot carrier injection efficiency parameter is input to a threshold comparator and compared with a preset risk judgment threshold (value range: 1×10). −5 Up to 1×10 −4 When the hot carrier injection efficiency parameter is greater than the preset risk judgment threshold, the threshold comparator outputs a high level. After being latched by a D flip-flop and shaped by a Schmitt trigger, a stable 50MHz photon detection enable signal is generated, which drives the InGaAs detector to activate the photon detection enable signal. It should be noted that the wavelength mapping table is a lookup table that stores the correspondence between voltage values ​​and the spectral windows of the InGaAs detector, including voltage state, center wavelength and temperature compensation coefficient. It should be noted that the preset risk assessment threshold is the critical efficiency value for determining the risk of hot carrier damage, which is determined by statistically analyzing the median value of the hot carrier injection efficiency parameter when the chip fails during accelerated aging experiments. The photon detection enable signal is combined with the spectral window control parameters of the InGaAs detector, and binary parameters are configured synchronously to generate photon detection commands.

[0029] Furthermore, the photon detection enable signal is shaped by a Schmitt trigger and then input to the first input of the AND gate. The spectral window control parameters of the InGaAs detector are converted into binary parameters of the spectral control register by an 8-bit encoder. After being matched with the logic voltage by a level converter, the parameters are input to the second input of the AND gate. When both inputs of the AND gate are high, a stable photon detection command is generated.

[0030] S4. Based on the photon detection command, drive the InGaAs avalanche photodiode array to collect the number of photon pulses, and calculate the chip damage risk index according to the hot carrier injection efficiency parameter and the number of photon pulses to generate a risk assessment report. Based on photon detection commands, the InGaAs avalanche photodiode array is driven to start detection within a specified spectral window and collect the number of photon pulses. Furthermore, the photon detection command is input to the InGaAs avalanche photodiode array driver circuit via the LVDS interface. The spectral window control parameters and integration time parameters in the photon detection command are analyzed and transmitted to the FPGA of the driver circuit to generate four control signals. Under the coordinated control of the four control signals, the InGaAs avalanche photodiode array performs photoelectric conversion, driving the optical filter to accurately position itself to the target band specified by the spectral window control parameters. The digital potentiometer control signal synchronously stabilizes the bias voltage at 198V to trigger the avalanche effect. At this time, within the integration window started by the timer trigger signal, the pulse current generated by the photon impact is processed by the preamplifier adjusted by the programmable gain amplifier setting signal, and the output amplitude is stabilized at 1V±50mV as a standard pulse signal. The pulse signal is shaped by the comparator and accumulated by the 32-bit counter. Finally, at the end of the integration period, the precise photon pulse count is output by the SPI interface. It should be noted that the InGaAs avalanche photodiode array is a photodetector device; it includes an InGaAs photosensitive unit array, an integrated temperature control module, a low-noise front-end amplifier circuit, and a spectral selection filter; the specified spectral window is the specific light wavelength detection range of the InGaAs avalanche photodiode array, which is generated by voltage-state wavelength mapping. It should be noted that the four control signals include setting the bias voltage with a digital potentiometer, adjusting the optical filter to the target wavelength with a stepper motor, setting the gain level with a programmable gain amplifier, and starting a 10ms integration window with a timer. Based on the hot carrier injection efficiency parameter and the number of photon pulses, the chip damage risk index is calculated by an electro-optic weighted fusion algorithm, and a risk assessment report containing risk level and quantitative parameters is generated. The expression for calculating the chip damage risk index is: ; in, It is a chip damage risk index. It is a hot carrier injection efficiency parameter, reflecting the efficiency of carrier kinetic energy conversion. It is the number of photon pulses. These are the weighting coefficients for the hot carrier injection efficiency parameter. It is the weighting coefficient for the number of photon pulses; Furthermore, the hot carrier injection efficiency parameter and photon pulse count are input into the first calculation channel of the electro-optical co-weighted fusion algorithm for normalization, and then combined with the weighting coefficient of the hot carrier injection efficiency parameter to generate an electrical damage component. Simultaneously, the photon pulse count is preprocessed by a photoelectric counter and input into the second calculation channel of the electro-optical co-weighted fusion algorithm for normalization, and then fused with the weighting coefficient of the photon pulse count to generate an optical radiation damage component. The electrical damage component and the optical radiation damage component are then combined using a weighted fusion algorithm to synthesize a chip damage risk index, and the chip damage risk index is used to determine the risk level through threshold comparison, ultimately generating a risk assessment report containing the risk level and quantitative parameters.

[0031] S5. Perform spatiotemporal feature analysis on the risk assessment report, identify the layer pulse frequency, and perform interruption control based on the layer pulse frequency to generate an anomaly warning report.

[0032] Scan the pulse timestamp sequence in the risk assessment report, mark the pulse events, calculate the pulse time interval, and identify the layer pulse frequency value F; Furthermore, the pulse timestamp sequence in the risk assessment report is scanned, and all pulse event timestamp data with amplitudes exceeding three times the standard deviation of the baseline noise are extracted to generate the original timestamp sequence. The original timestamp sequence is marked, and a Hamming window finite impulse response filter is used to eliminate high-frequency interference to obtain the filtered timestamp sequence. At the same time, the filtered timestamp sequence is traversed with a sliding window width of 50μs to calculate the pulse time interval between adjacent pulses. Finally, the reciprocal of the pulse time interval is used as the pulse frequency value. According to the vertical layered structure (metal layer / active layer) of the chip under test, the layers are integrated to generate the layer pulse frequency value F. The layer pulse frequency value is input into the interrupt control mapping table, and interrupt control is performed according to the layer pulse frequency value to generate an abnormal early warning report.

[0033] Further, input the layer pulse frequency value into the address decoder of the interrupt regulation mapping table, quantize the layer pulse frequency value into a 16-bit fixed-point number through a 32-bit floating-point to fixed-point unit, and use a 12-cycle binary search algorithm to match 4096 preset frequency intervals. After hitting, output the corresponding 8-bit instruction code, and splice the 8-bit instruction code and the current test status through the LUT6 combinational logic of the FPGA to generate a 24-bit interrupt regulation command within a single clock cycle. Finally, the 24-bit interrupt regulation command triggers hardware execution and synchronously generates an exception warning report containing the layer pulse frequency value, instruction code, and timestamp.

[0034] It should be noted that the interrupt regulation mapping table refers to a lookup table storing frequency thresholds and corresponding control instructions, including frequency range, instruction code, operation type, and additional parameters; the preset frequency interval is the risk level threshold range divided according to the chip reliability test data. When F ≥ 180Hz, it is mapped to the emergency shutdown instruction code, save the exception snapshot and cut off the power supply. When 100Hz < F < 180Hz, it is mapped to the deceleration test instruction code, mark data anomalies. When F ≤ 100Hz, it is mapped to the normal instruction code, execute the normal instruction report.

[0035] This embodiment also provides a semiconductor data test exception warning system, including: a signal acquisition module, a chip test module, an instruction generation module, a risk assessment module, and a pulse regulation module. The signal acquisition module is used to obtain the tunneling current component based on the quantum tunneling compensation three-element dataset, calculate the nonlinear compensation coefficient according to the current wafer temperature, and perform joint correction of the quantum tunneling effect and temperature drift on the original current signal to obtain a calibrated pure electronic current signal. The chip test module is used to perform a stepped voltage test on the待测 chip through the calibrated pure electronic current signal, and simultaneously monitor the change in drain current, the increase in substrate current, and the voltage state. The instruction generation module is used to calculate the hot carrier injection efficiency parameter based on the change in drain current and the increase in substrate current, and combine it with the voltage state to generate a photon detection instruction. The risk assessment module is used to drive the InGaAs avalanche photodiode array to collect photon pulse numbers based on the photon detection instruction, and calculate the chip damage risk index according to the hot carrier injection efficiency parameter and the photon pulse numbers, and generate a risk assessment report. The pulse regulation module is used to analyze the spatio-temporal characteristics of the risk assessment report, identify the layer pulse frequency, and perform interrupt regulation according to the layer pulse frequency to generate an exception warning report.

[0036] This embodiment also provides a computer device applicable to the semiconductor data testing anomaly early warning method, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the semiconductor data testing anomaly early warning method proposed in the above embodiment.

[0037] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0038] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the semiconductor data testing anomaly warning method proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0039] In summary, this invention achieves effective elimination of quantum tunneling effects and temperature drift in the original current signal by jointly correcting it based on a dataset of three elements for quantum tunneling compensation, providing a high-fidelity reference signal for subsequent testing, thereby improving the accuracy of signal measurement and enhancing the precision of device reliability assessment. Furthermore, by calculating the chip damage risk index using hot carrier injection efficiency parameters and photon pulse count, it achieves dynamic damage quantification analysis by integrating electrical parameters and optical data, enabling holographic perception of chip abnormal states and early risk identification.

[0040] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for early warning of semiconductor data testing anomalies, characterized in that: include, Based on the quantum tunneling compensation three-element dataset, the tunneling current component is obtained, and the nonlinear compensation coefficient is calculated according to the current wafer temperature. The original current signal is then jointly corrected for quantum tunneling effect and temperature drift to obtain a calibrated pure electronic current signal. A stepped voltage test is performed on the chip under test by calibrating a purely electronic current signal, while monitoring the change in drain current, the increment of substrate current, and the voltage state. The hot carrier injection efficiency parameters are calculated based on the change in drain current and the increment of substrate current, and then combined with the voltage state to generate photon detection commands. Based on photon detection commands, the InGaAs avalanche photodiode array is driven to collect the number of photon pulses, and the chip damage risk index is calculated based on the hot carrier injection efficiency parameter and the number of photon pulses to generate a risk assessment report. The risk assessment report is analyzed for its spatiotemporal characteristics to identify the layer pulse frequency. Interruption control is then performed based on the layer pulse frequency to generate an anomaly warning report.

2. The semiconductor data testing anomaly early warning method as described in claim 1, characterized in that: The steps for obtaining the calibration purely electronic current signal are as follows: The quantum tunneling compensation three-element dataset includes the original current signal of the chip under test, wafer temperature data, and dielectric barrier height and thickness values. Based on the dielectric barrier height and thickness values ​​in the quantum tunneling compensation three-element dataset, the tunneling current component is calculated using the Shockley quantum tunneling equation, and the nonlinear compensation coefficient is calculated using the temperature compensation function based on the current wafer temperature. Based on the tunneling current component and the nonlinear compensation coefficient, the original current signal is jointly corrected for quantum tunneling effect and temperature drift to obtain a calibrated purely electronic current signal.

3. The semiconductor data testing anomaly early warning method as described in claim 2, characterized in that: The step-by-step voltage test of the chip under test is performed by calibrating a purely electronic current signal, while simultaneously monitoring the changes in drain current, substrate current increment, and voltage state. The steps are as follows. The calibration pure electronic current signal is input to the voltage control circuit of the test machine, and a stepped voltage is applied to the gate terminal of the chip under test according to a preset sequence. During the stepped voltage test, a current acquisition channel is established through the SPI bus to monitor the changes in drain current, substrate current increment, and voltage status of the chip under test in real time.

4. The semiconductor data testing anomaly early warning method as described in claim 1, characterized in that: The steps for generating the photon detection command are as follows: Based on the change in drain current and the increment of substrate current, the hot carrier injection efficiency parameter is calculated using the substrate-drain current increment ratio efficiency method. The hot carrier injection efficiency parameter is then input into the threshold comparator to activate the photon detection enable signal. Wavelength mapping is performed on the voltage state to obtain the spectral window control parameters of the InGaAs detector; The photon detection enable signal is combined with the spectral window control parameters of the InGaAs detector, and binary parameters are configured synchronously to generate photon detection commands.

5. The semiconductor data testing anomaly early warning method as described in claim 1, characterized in that: The number of photon pulses collected by driving the InGaAs avalanche photodiode array refers to the number of photon pulses collected by driving the InGaAs avalanche photodiode array to start detection within a specified spectral window based on photon detection commands.

6. The semiconductor data testing anomaly early warning method as described in claim 1, characterized in that: The generation of the risk assessment report refers to the calculation of the chip damage risk index based on the hot carrier injection efficiency parameter and the number of photon pulses using an electro-optical weighted fusion algorithm, and the generation of the risk assessment report.

7. The semiconductor data testing anomaly early warning method as described in claim 1, characterized in that: The steps for generating the anomaly warning report are as follows: Scan the pulse timestamp sequence in the risk assessment report, mark the pulse events, calculate the pulse time interval, and identify the layer pulse frequency value F; The layer pulse frequency value is input into the interrupt control mapping table, and interrupt control is performed according to the layer pulse frequency value to generate an abnormal early warning report.

8. A semiconductor data testing anomaly early warning system, based on the semiconductor data testing anomaly early warning method according to any one of claims 1 to 7, characterized in that: It includes a signal acquisition module, a chip testing module, an instruction generation module, a risk assessment module, and a pulse control module; The signal acquisition module is used to acquire the tunneling current component based on the quantum tunneling compensation three-element dataset, and calculate the nonlinear compensation coefficient according to the current wafer temperature. It performs joint correction of quantum tunneling effect and temperature drift on the original current signal to acquire the calibrated pure electronic current signal. The chip test module is used to perform stepped voltage tests on the chip under test by calibrating a purely electronic current signal, while monitoring the change in drain current, the increment of substrate current, and the voltage state. The instruction generation module is used to calculate the hot carrier injection efficiency parameters based on the change in drain current and the increment of substrate current, and combine them with the voltage state to generate photon detection instructions. The risk assessment module is used to drive the InGaAs avalanche photodiode array to collect the number of photon pulses based on photon detection commands, and calculate the chip damage risk index based on the hot carrier injection efficiency parameter and the number of photon pulses to generate a risk assessment report. The pulse control module is used to analyze the spatiotemporal characteristics of the risk assessment report, identify the layer pulse frequency, and perform interruption control based on the layer pulse frequency to generate an anomaly warning report.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the semiconductor data testing anomaly early warning method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the semiconductor data testing anomaly early warning method according to any one of claims 1 to 7.

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