Display device

Abstract

This disclosure provides a display device. The display device includes: a substrate including a first region, a second region, and a third region spaced apart from each other by a first recess and a second recess; a circuit layer disposed on the first region and including transistors; a first pad disposed on the second region; a second pad disposed on the third region; and a plurality of connecting lines and a plurality of bent lines connecting the circuit layer, the first pad, and the second pad, wherein a chip is disposed on the first pad.

Description

Technical Field

[0001] This disclosure relates to the field of displays, and more specifically, for example, but not limited to, display devices. Background Technology

[0002] Display devices are widely used as screens for various electronic devices, such as mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, ultra-portable personal computers (UMPCs), mobile phones, tablet PCs, watch phones, electronic tablets, wearable devices, portable information devices, vehicle control display devices, televisions, laptops, monitors, etc.

[0003] Recently, research and development have been conducted on display devices that can achieve maximum screen size by reducing the bezel area where images are not displayed under the same display panel size.

[0004] When the curved area of ​​a display is bent, the curved area, composed of organic film and lines, can form a C-shape with a predetermined radius of curvature. However, in the case of a display including a C-shaped curved area, there are structural limitations on reducing the non-display area (or bezel area) where no image is displayed due to the radius of curvature of the curved area.

[0005] Therefore, there is a need for a display panel and a display device including the display panel to allow for a structural reduction in the non-display area (or bezel area) and an increase in the rigidity of the curved area.

[0006] The descriptions provided in the background section should not be assumed to be prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0007] The embodiments of this specification provide a display panel and a display device including the display panel, wherein a narrow bezel can be achieved by structurally reducing the non-display area (or bezel area) where no image is displayed by using two grooves formed in the substrate.

[0008] Embodiments of this specification provide a display panel and a display device including the display panel, wherein structural rigidity can be improved by arranging a portion of a substrate between two recesses.

[0009] Embodiments of this specification provide a display panel and a display device including the display panel, wherein the display panel and the display device may use certain structures arranged in the display area as an etch-resistant layer to simplify the manufacturing process.

[0010] Embodiments of this specification provide a display panel and a display device including the display panel, which can use curved lines arranged in a curved area to reduce or prevent damage to connecting lines due to bending or to reduce or minimize the possibility of damage to connecting lines.

[0011] The embodiments of this specification provide a display panel and a display device including the display panel, which can reduce or minimize the resistance difference between multiple connecting lines.

[0012] The objectives to be addressed by the embodiments described in this specification are not limited to those described above, and other objectives not mentioned will be clearly understood by those skilled in the art from the following description.

[0013] A display device according to an embodiment of this specification includes: a substrate including a first region, a second region, and a third region spaced apart from each other by a first groove and a second groove; a circuit layer disposed on the first region and including transistors; a first pad disposed on the second region; a second pad disposed on the third region; and a plurality of connecting lines and a plurality of curved lines connecting the circuit layer, the first pad, and the second pad, wherein a chip is disposed on the first pad.

[0014] A display device according to an embodiment of this specification includes: a display area and a non-display area, an image being implemented in the display area, and a non-display area surrounding at least a portion of the display area, wherein the non-display area includes a first non-display area, a curved area including a groove, and a second non-display area, wherein a first pad is disposed in the curved area, a chip is disposed in the first pad, and wherein a second pad is disposed in the second non-display area overlapping the first non-display area by the curvature of the curved area, the second pad being connected to a circuit board.

[0015] A display device according to an embodiment of this specification includes: a display area and a non-display area, an image being implemented in the display area, and a non-display area surrounding at least a portion of the display area. The non-display area includes a first non-display area, a curved area including two recesses, and a second non-display area. A first pad is disposed between the two recesses, a chip is disposed in the first pad, and a second pad is disposed in the second non-display area overlapping the first non-display area due to the curvature of the curved area. The second pad is connected to a circuit board.

[0016] According to this specification, a narrow bezel can be achieved by structurally reducing the non-display area (or border area) where no image is displayed by using two grooves formed in the substrate.

[0017] According to this specification, structural rigidity can be improved by arranging a portion of the substrate between two grooves.

[0018] According to this specification, some structures arranged in the display area can be used as an etch-resistant layer.

[0019] According to this specification, the rigidity of a glass substrate can be maintained by using an etching process.

[0020] According to this specification, by using a planarization layer of organic material during the etching of a substrate formed of glass material, damage to bending lines arranged in bending areas can be reduced or prevented.

[0021] According to this specification, bending lines arranged in bending areas can reduce or prevent damage to the connecting lines due to bending, or reduce or minimize the possibility of damage to the connecting lines.

[0022] According to this specification, the bending lines can be protected by a pattern layer and a protective layer arranged on the bending lines. Therefore, the lifespan of the display panel can be increased, thereby reducing greenhouse gas emissions during the manufacturing process.

[0023] According to this specification, by providing embodiments illustrating various arrangements of the connecting lines, the design freedom of the connecting lines can be increased while minimizing the resistance difference between multiple connecting lines.

[0024] The various useful advantages and effects of the embodiments described herein are not limited to those described above, and those skilled in the art will clearly understand from the following description any effects not described above. It is intended that all such additional systems, methods, features, and advantages are included in this specification, fall within the scope of this disclosure, and are protected by the appended claims. Nothing in this section should be construed as limiting these claims. Further aspects and advantages will now be discussed in conjunction with embodiments of this disclosure. Attached Figure Description

[0025] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0026] Figure 1 This is a perspective view showing a display device according to an embodiment of this specification;

[0027] Figure 2 This is a plan view showing a display device according to an embodiment of this specification;

[0028] Figure 3 It is along Figure 2 A cross-sectional view taken from line I-I' in the diagram;

[0029] Figure 4A and Figure 4B yes Figure 3Enlarged views of some areas;

[0030] Figure 5 This is a view showing a neutral surface based on curvature;

[0031] Figure 6 This is a view showing the coating arranged in the display panel according to an embodiment of this specification;

[0032] Figure 7 This is a view showing the curved appearance of the display device according to an embodiment of this specification;

[0033] Figure 8 This is a view showing the heat-conducting member of a display device according to an embodiment of this specification;

[0034] Figure 9 This is a view showing one embodiment of the connecting lines arranged in a display panel according to an embodiment of this specification;

[0035] Figure 10 yes Figure 9 A magnified view of region C in the image;

[0036] Figure 11 This is a view showing one embodiment of the connecting lines arranged in a display panel according to an embodiment of this specification;

[0037] Figure 12 yes Figure 11 A magnified view of region D in the image;

[0038] Figure 13 This is a view illustrating one embodiment of the connecting lines arranged in a display panel according to an embodiment of this specification; and

[0039] Figure 14 yes Figure 13 A magnified view of region E in the image.

[0040] [List of reference numerals]

[0041] 10, 10a, 10b, 10c: Display panel 100: First substrate

[0042] 110: Zone 1; 120: Zone 2

[0043] 130: Third Region 200: Circuit Layer

[0044] 240: Planarization layer; 300: Liquid crystal layer

[0045] 400: Pattern layer; 500: Color filter layer

[0046] 600: Black Matrix; 700: Second Substrate

[0047] 800: Protective layer; 900: Coating

[0048] 1000: Thermal conductive component; BL: Bending line

[0049] G1: First groove; G2: Second groove

[0050] LL: Connector PAD1: First pad

[0051] PAD2: Second pad

[0052] Throughout the accompanying drawings and detailed embodiments, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0053] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Specifically, these embodiments will complete the disclosure and allow those skilled in the art to fully understand the scope of this disclosure. This disclosure is limited only to the scope of the appended claims.

[0054] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe embodiments of this disclosure are exemplary, and this disclosure is not limited to the illustrated items. The same reference numerals always denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of related known technologies will be omitted if it is determined that such detailed descriptions may unnecessarily obscure the subject matter of this disclosure.

[0055] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, references to the singular should be construed as including the plural.

[0056] When interpreting components, even if there is no separate description, they are interpreted as including the error range.

[0057] When describing the positional or interconnected relationship between two components (e.g., "on top", "above", "below", "near", "connected or linked", "cross", "intersect", etc.), one or more other components may be inserted between them unless "immediately adjacent" or "directly" is used.

[0058] When describing temporal contextual relationships (e.g., “after,” “following,” “next,” or “before”), they may not be discontinuous in time scale unless “immediately” or “directly” is used.

[0059] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or component name preceding the component.

[0060] The following implementation methods can be combined or associated with each other, either wholly or in part, and can be linked and driven in various ways. These implementation methods can be implemented independently of each other or together in an interconnected manner.

[0061] Throughout this specification, the same reference numerals denote the same components. Furthermore, to effectively describe the thickness, proportions, and dimensions of components, some portions of the figures may be exaggerated. For ease of description, the scale of the components depicted in the figures differs from the actual scale and is not limited to the scale depicted in the figures.

[0062] "And / or" includes all of one or more combinations that can be defined by the associated components. Throughout the specification, unless otherwise stated, the term "A and / or B" means A, B, or both A and B, and unless otherwise stated, the term "C to D" means C or more and D or fewer.

[0063] Unless the context clearly indicates otherwise, singular expressions used in this specification include plural expressions. In this application, terms such as “comprising” or “including” should not be construed as including all components or steps listed in the specification; some components or steps may be excluded, or additional components or steps may be included.

[0064] Furthermore, when referring to any size, relative size, etc., it should be assumed that numerical values ​​or corresponding information (e.g., level, range, etc.) for a component or feature include tolerances or error ranges that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "can".

[0065] Furthermore, when an element or layer is “connected,” “joined,” or “adhered” to another element or layer, unless otherwise specified, this means that the element or layer can not only be directly connected or adhered to the other element or layer, but also indirectly connected or adhered to the other element or layer by means of one or more intermediate elements or layers “set” or “inserted” between these elements or layers. It should be understood that this means the elements can be configured to be in direct contact with each other, or they can be configured not to be in direct contact with each other.

[0066] When describing quantitative or numerical relationships, terms such as "equal" and "identical" generally mean "substantially equal" and "substantially identical," or "similar or equal" and "similar or identical." That is, based on the premise that two elements are equal or identical, a certain margin of error is allowed, such as one percent, five percent, ten percent, etc.

[0067] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of this disclosure without departing from the technical spirit or scope thereof. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0068] The display device according to the embodiments of this disclosure may include the display device itself in the narrow sense, an application product including a display in the narrow sense, or even a complete set of devices as an end consumer device.

[0069] The display device according to the embodiments of this specification can be implemented using liquid crystal display (LCD), plasma display panel (PDP), field emission display (FED), electroluminescent display (ELD), organic light-emitting diode (OLED), quantum dot display, micro light-emitting diode (micro LED) display, etc. For example, the display area DA of the display device according to the embodiments of this specification is exemplified by a liquid crystal display utilizing a liquid crystal layer, but it is not limited thereto. For example, the display area DA can be implemented using any of OLED, QLED, and micro LED.

[0070] Figure 1 This is a perspective view showing a display device according to an embodiment of this specification. Figure 2 This is a plan view showing a display panel according to an embodiment of this specification. Figure 3 It is along Figure 2 The cross-sectional view taken from line I-I' in the diagram. Figure 4A and Figure 4B yes Figure 3 Enlarged views of some areas within. For example, Figure 4A It is shown Figure 3 A magnified view of region A. Figure 4B It is shown Figure 3 A magnified view of region B. Here, line I-I' can be an imaginary line passing through the center of the X-axis in the direction of the first pad PAD1.

[0071] Reference Figures 1 to 3The display device according to embodiments of this specification may include: a display panel 10, which includes a first recess G1 and a second recess G2; a chip 20 connected to a first pad PAD1 of the display panel 10; and a circuit board 30 connected to a second pad PAD2 of the display panel 10. An input image can be visually reproduced in the display area DA of the display panel 10. Here, the input image can be implemented using any of OLED, QLED, micro-LED, and LCD, but will be described below as being implemented using a liquid crystal display employing a liquid crystal layer 300.

[0072] A display device according to one embodiment of this specification may include a light source 40 that emits light toward the liquid crystal layer 300 of the display panel 10. Furthermore, an input image can be visually reproduced on the display panel 10. The light source 40 may be a backlight unit.

[0073] The display panel 10 may include a display area DA for displaying images and a non-display area NA for not displaying images. The display panel 10 may be a panel with a rectangular structure having a width along the X-axis, a length along the Y-axis, and a thickness along the Z-axis. In this case, the width and length of the display panel 10 can be set to various design values ​​depending on the application of the display device. The X-axis direction may refer to the width direction, row direction, or horizontal direction; the Y-axis direction may refer to the length direction, column direction, or vertical direction; and the Z-axis direction may refer to the up-down direction, vertical direction, or thickness direction. The X-axis, Y-axis, and Z-axis directions may be perpendicular to each other, or they may refer to different directions that are not perpendicular to each other. Therefore, each of the X-axis, Y-axis, and Z-axis directions can be described as any one of a first direction, a second direction, and a third direction. The planes extending along the X-axis and Y-axis directions may refer to horizontal planes.

[0074] The non-display area NA may include a first non-display area NA1, a curved area BA, and a second non-display area NA2.

[0075] The first non-display area NA1 can be an area surrounding at least a portion of the display area DA.

[0076] The curved region BA can be an area adjacent to at least one of the multiple edges of the first non-display region NA1, and can be a bendable region. Furthermore, the display panel 10 can be easily bent by using the first groove G1 and the second groove G2 arranged in the curved region BA. In this case, the first pad PAD1 can be arranged in the curved region BA. Thus, since the first pad PAD1 is arranged in the curved region BA instead of the second non-display region NA2, the size of the non-display region where no image is displayed can be structurally reduced.

[0077] Reference Figure 2 and Figure 3 The curved region BA is located between the first non-display region NA1 and the second non-display region NA2, and various structures such as organic layers, inorganic layers, and lines arranged in the curved region BA can be bent. For example, various structures such as organic layers, inorganic layers, and lines that overlap with the first groove G1 and the second groove G2 can be bent. In this case, the second region 120 of the substrate 100 arranged between the first groove G1 and the second groove G2 can remain unbent.

[0078] Since the display panel 10 according to the embodiments of this specification includes a second flat region 120 of the substrate 100, the radius of curvature at the curved region BA can be reduced compared to a display panel that is curved using a single groove. For example, the display panel 10 according to the embodiments of this specification may include two curved regions BA1 and BA2, corresponding to a first groove G1 and a second groove G2 spaced apart from each other. Furthermore, since the second region 120 of the flat substrate 100 is arranged between the first groove G1 and the second groove G2, the radius of curvature of each of the two curved regions BA1 and BA2 can be formed to be smaller than the radius of curvature of a display panel that is curved using a single groove. In this case, the width of the groove arranged in the display panel that is curved using a single groove can be equal to the sum of the width of the first groove G1, the width of the second region 120, and the width of the second groove G2, but is not necessarily limited to this.

[0079] In this way, since the display panel 10 according to the embodiment of this specification includes a second region 120 of the substrate 100 disposed between the first groove G1 and the second groove G2, the non-display area NA visible in the Z-axis direction when the display panel 10 is bent can be reduced, thereby achieving a narrow bezel.

[0080] The second non-display area NA2 may be an area adjacent to at least one of the multiple edges of the curved area BA, and the second pad PAD2 may be disposed in the second non-display area NA2. For example, the curved area BA may be in a curved state, and the remaining areas of the substrate 100 other than the curved area BA may be in a flat state. When the curved area BA is bent, the second non-display area NA2 may be located above the back side of the display area DA to overlap with it.

[0081] Chip 20 can be connected to display panel 10 via first pad PAD1.

[0082] Chip 20 may include driving circuitry. For example, chip 20 may be a driver IC. The driver IC may be connected to a data line to provide a voltage for a data signal to the data line. Furthermore, the driver IC may include a timing controller.

[0083] The circuit board 30 can be a flexible printed circuit board and can be connected to the display panel 10 via the pad portion PAD.

[0084] The liquid crystal layer 300 of the display area DA can be driven by receiving signals from one or more circuit boards 30 via lines of the display area DA and connection lines LL of the non-display area NA. For example, the lines of the display area DA can be lines used together with multiple connection lines LL to transmit signals output from the chip 20 and / or circuit board 30 to the liquid crystal layer 300 of the display area DA.

[0085] When only multiple connecting lines LL are arranged in the bending region BA, as the bending region BA bends, a portion of the multiple connecting lines LL may also bend. Therefore, stress may concentrate on a portion of the bent connecting line LL, and cracks may appear in the connecting line LL due to stress.

[0086] Therefore, when multiple connecting lines LL are arranged in a bending region BA, the possibility of damage to the connecting lines LL due to cracks or the like can be considered. For example, to reduce or prevent cracks that may occur in the multiple connecting lines LL during bending of the bending region BA, the connecting lines LL can be made of a conductive material with excellent ductility. Furthermore, the multiple connecting lines LL can be formed in various shapes to cope with cracks, etc. For example, at least a portion of the multiple connecting lines LL arranged in the bending region BA can have a shape in which a conductive pattern having at least one of the following shapes is repeatedly arranged: a diamond shape, a rhombus shape, a trapezoidal wave shape, a triangular wave shape, a sawtooth wave shape, a sine wave shape, a circular shape, and an omega (Ω) shape.

[0087] According to one embodiment of this specification, a display device can stably connect multiple connecting lines LL to the lines of the display area DA by using curved lines BL arranged on the curved area BA.

[0088] Multiple connecting lines LL can extend from multiple second pads PAD2 of the second non-display area NA2 toward the curved area BA. Furthermore, the multiple connecting lines LL can be electrically connected to the display area DA via multiple curved lines BL, but are not limited to this. For example, by arranging the curved lines BL to overlap with a portion of the connecting lines LL, the curved lines BL can be used as auxiliary lines to the connecting lines LL. As a result, even if the connecting lines LL are damaged due to the bending of the display panel 10, the signal applied through the connecting lines LL can still be transmitted to the line of the display area DA via the curved lines BL.

[0089] Therefore, the connecting line LL and the bending line BL arranged on the curved area BA can be used to reduce the possibility of failure due to the bending of the display panel 10. In this case, the display panel 10 according to the embodiment of this specification can protect the bending line BL by a pattern layer 400 and a protective layer 800 arranged on the bending line BL. For example, when exposed to air, the copper (Cu)-containing bending line BL will oxidize, and the resistance of the oxidized bending line BL will increase. The pattern layer 400 and the protective layer 800 can reduce or prevent the oxidation of the bending line BL. Therefore, the pattern layer 400 and the protective layer 800 can further reduce the possibility of failure of the bending line BL. Here, the connecting line LL can be a link line. In addition, the bending line BL can be a curved line.

[0090] The light source 40 can be arranged below the first region 110 to emit light toward the first region 110. For example, the light source 40 can emit light along the Z-axis direction. More specifically, the light source 40 can emit light toward the liquid crystal layer 300 arranged above the first region 110. Here, the light source 40 can be a backlight unit.

[0091] The display panel 10 can be manufactured based on flexible plastic materials such as polyimide or flexible glass substrates with a thin thickness. For example, considering the etching process, the substrate 100 of the display panel 10 can be formed of a transparent glass material.

[0092] Now refer to Figures 1 to 4B The display panel 10 according to an embodiment of this specification includes: a substrate 100, which includes a first region 110, a second region 120, and a third region 130 spaced apart from each other by a first recess G1 and a second recess G2; a circuit layer 200 disposed on the substrate 100; a liquid crystal layer 300 disposed on the circuit layer 200; a first pad PAD1 disposed on the second region 120 to connect to a chip 20; a second pad PAD2 disposed on the third region 130 to connect to a circuit board 30; and multiple connecting lines LL and multiple bent lines BL. Here, the multiple connecting lines LL and multiple bent lines BL can connect the lines of the circuit layer 200, the first pad PAD1, and the second pad PAD2. In addition, the circuit layer 200 may include a thin film transistor 210, a gate insulating layer 220, a first interlayer dielectric layer 230, a planarization layer 240, a first electrode 250, a second interlayer dielectric layer 260, and a second electrode 270. The thin-film transistor 210 may include a gate electrode 211, an active layer 212, a source electrode 213, and a drain electrode 214.

[0093] Furthermore, the display panel 10 according to the embodiments of this specification may also include a first etch resist layer ES1 disposed above the first recess G1 and a second etch resist layer ES2 disposed above the second recess G2. Here, the planarization layer 240 of the circuit layer 200 may extend to a portion of the curved region BA to be disposed above the upper part of the first recess G1. Therefore, the portion of the planarization layer 240 extending from the first region 110 to the second region 120 to cover the upper part of the first recess G1 may be configured as the first etch resist layer ES1. Therefore, during the etching of the substrate 100 to form the recesses G1 and G2, a portion of the planarization layer 240 may serve as an etch stop layer.

[0094] Furthermore, the display panel 10 according to the embodiments of this specification may also include a pattern layer 400 arranged on a curved line BL.

[0095] Furthermore, the display panel 10 according to the embodiments of this specification may also include a color filter layer 500 and a black matrix 600 disposed on the liquid crystal layer 300, a sealant 310 surrounding the liquid crystal layer 300, and at least one columnar member 320 disposed between the color filter layer 500 and the circuit layer 200.

[0096] Furthermore, the display panel 10 according to embodiments of this specification may also include a second substrate 700 disposed on the color filter layer 500 and the black matrix 600. Here, the substrate 100 including the first region 110, the second region 120 and the third region 130 may be the first substrate. The second substrate 700 may be a cover member.

[0097] Furthermore, the display panel 10 according to the embodiments of this specification may also include a protective layer 800 disposed on the pattern layer 400.

[0098] Furthermore, the display panel 10 according to the embodiments of this specification may also include a lower polarizing layer DPOL disposed below the first region 110 and an upper polarizing layer UPOL disposed above the second substrate 700. In this case, the lower polarizing layer DPOL and the upper polarizing layer UPOL may overlap with the color filter layer 500.

[0099] The substrate 100 may be made of glass, metal, plastic, etc., but is not limited to these. However, in order to simplify the process, the substrate 100 may be a glass substrate with a predetermined strength for the etching process.

[0100] The first substrate 100 may include a first region 110, a second region 120, and a third region 130 separated by a first groove G1 and a second groove G2. By bending the display panel 10, the third region 130 may overlap with the first region 110.

[0101] A first region 110 of the first substrate 100 can be disposed in the display region DA. A second region 120 can be disposed in the curved region BA of the non-display region NA. Furthermore, a third region 130 can be disposed in the second non-display region NA2 of the non-display region NA. Therefore, the first region 110 can be a display region substrate, the second region 120 can be a curved region substrate, and the third region 130 can be a non-display region substrate.

[0102] The first groove G1 and the second groove G2 can be formed in the first substrate 100, and the first substrate 100 can be divided into a first region 110, a second region 120 and a third region 130 by the first groove G1 and the second groove G2.

[0103] The first groove G1 and the second groove G2 can be arranged to correspond to the curved area BA of the display panel 10. For example, the curved area BA may include a first curved area BA1, a non-curved area NBA, and a second curved area BA2. Here, the non-curved area NBA may be a flat area.

[0104] When the display panel 10 is bent, the non-bent area NBA can remain flat because it corresponds to the second area 120 of the substrate 100. For example, when the first bent area BA1 and the second bent area BA2 are bent through the first groove G1 and the second groove G2, the second area 120 can be located between the first groove G1 and the second groove G2, thereby keeping the second area 120 flat.

[0105] As the display panel 10 bends, the first bending region BA1 and the second bending region BA2 of the display panel 10 can have different centers of curvature radius. Here, the first bending region BA1 is the region corresponding to the first groove G1, which can be bent to have a first curvature radius when the display panel 10 bends. Furthermore, the second bending region BA2 is the region corresponding to the second groove G2, which can be bent to have a second curvature radius when the display panel 10 bends. In this case, the first and second curvature radii can be the same, but are not necessarily limited to this. Furthermore, the width of the first groove G1 and the width of the second groove G2 can be the same in the Y-axis direction, but are not necessarily limited to this.

[0106] Therefore, the display panel 10 according to the embodiments of this specification may include two curved regions BA1 and BA2 with different curvature radii centers passing through the second region 120 of the substrate 100, so that the display panel 10 can be bent to have a radius smaller than the curvature radius of a display panel bent by using a single groove. As a result, when the display panel 10 is bent, the non-display area NA visible in the Z-axis direction can be reduced, thereby achieving a narrow bezel.

[0107] The first groove G1 and the second groove G2 may be recessed into the lower surface of the first substrate 100. Furthermore, the first groove G1 and the second groove G2 may be formed in a conical shape, but are not necessarily limited to this.

[0108] The first groove G1 and the second groove G2 can be formed in the first substrate 100 by an etching process. In this case, a plurality of display panels 10 can be manufactured using a single mother substrate including glass, and a cutting process can be performed on the mother substrate after the etching process to separate it into each of the plurality of display panels 10.

[0109] Multiple grooves formed in the mother substrate by an etching process can be formed as grooves G1 and G2 corresponding to each of the plurality of display panels 10. For example, multiple grooves can be formed in the mother substrate by etching a portion of the lower surface of the mother substrate using a patterned mask and an etching solution. Therefore, multiple grooves corresponding to grooves G1 and G2 of each of the plurality of display panels 10 can be formed on the lower surface side of the mother substrate in a single etching process, thereby achieving process optimization. Here, nitric acid (HNO3), hydrofluoric acid (HF), etc., can be used as etching solutions.

[0110] When grooves G1 and G2 are formed by etching, the gate insulating layer 220 and the first interlayer dielectric layer 230 of the circuit layer 200 can be removed together with the mother substrate.

[0111] Since the gate insulating layer 220 and the first interlayer dielectric layer 230 are not disposed in the first recess G1 and the second recess G2, damage (e.g., cracks) caused by bending stress will not occur in the gate insulating layer 220 and the first interlayer dielectric layer 230. For example, even if the gate insulating layer 220 and the first interlayer dielectric layer 230 are made of an inorganic insulating material that is susceptible to bending, since the gate insulating layer 220 and the first interlayer dielectric layer 230 are not disposed in the bending region BA, they will not be damaged by bending stress. In this case, since the second interlayer dielectric layer 260, made of an inorganic insulating material, is also not disposed in the bending region BA, the second interlayer dielectric layer 260 will not be damaged by bending stress.

[0112] Furthermore, since the first substrate 100, made of glass, is processed by an etching process to form grooves G1 and G2, the reduction in the rigidity of the glass substrate can be minimized. Therefore, the rigidity of the glass substrate can be maintained.

[0113] The display panel 10 may include an etch-resistant layer ES, which serves as an etch stop layer to resist etch solutions. For example, the etch-resistant layer ES of the display panel 10 may include a first etch-resistant layer ES1 disposed over a first recess G1 and a second etch-resistant layer ES2 disposed over a second recess G2. In this case, the planarization layer 240 of the circuit layer 200 may extend from the first region 110 of the substrate 100 to the second region 120 to serve as the first etch-resistant layer ES1.

[0114] The etch resist layer ES can be made of a material that is resistant to corrosion (or chemical resistance) to the etching solution used in the etching process. For example, the etch resist layer ES can include at least one of silicone-based organic materials, polyurethane, polyimide, and photoacrylic acid. Furthermore, the etch resist layer ES can include at least one of chromium (Cr), aluminum (Al), platinum (Pt), gold (Ag), and nickel (Ni). Here, the material of the etch resist layer ES can be the same as the material of the planarization layer 240 disposed in the circuit layer 200. For example, the first etch resist layer ES1 and the second etch resist layer ES2 can be formed together with the planarization layer 240 of the circuit layer 200 using the same mask process.

[0115] Since the resist layer ES can be formed from an organic insulating material that is highly resistant to etching solutions, the etching process is no longer performed by the resist layer ES. Therefore, grooves G1 and G2 can be formed by the etching process up to the resist layer ES, so that a portion of the lower surface of the resist layer ES can be exposed through grooves G1 and G2. For example, a portion of the lower surface of the first resist layer ES1 can be exposed through the first groove G1, and a portion of the lower surface of the second resist layer ES2 can be exposed through the second groove G2.

[0116] The etch resist layer ES is used to protect the structures located above the etch resist layer ES during the process of forming grooves G1 and G2 in the first substrate 100, and the etch resist layer ES can have a larger size (or width) than the areas overlapping with grooves G1 and G2 or larger size (or width) than the curved areas BA. For example, based on the Y-axis direction, the width of the first etch resist layer ES1 can be greater than the width W1 of the first groove G1, and the width of the second etch resist layer ES2 can be greater than the width W2 of the second groove G2. Therefore, the curved lines BL1 and BL2 arranged on the etch resist layer ES can be protected from the etch solution.

[0117] The etch resist layer ES can be formed using a slot coater, inkjet printer, or dispensing machine. Alternatively, the etch resist layer ES can be formed using a patterning process employing a photomask. Here, the etch resist layer ES can be an etch stop pattern, an etch stop pattern, or an etch mask pattern.

[0118] The first region 110 may include a display region DA and a first non-display region NA1, and may be formed of a transparent glass material.

[0119] The first region 110 may include a first upper surface 111 in contact with the circuit layer 200, a first lower surface 112 on the opposite side of the first upper surface 111, and a first side surface 113 connecting the first upper surface 111 and the first lower surface 112. The first region 110 may include a first upper edge where the first upper surface 111 and the first side surface 113 intersect, and a first lower edge where the first lower surface 112 and the first side surface 113 intersect. Here, the first side surface 113 may be an inclined surface with a predetermined slope relative to the first lower surface 112. Furthermore, since the first side surface 113 is formed by an etching process, the first lower edge where the first lower surface 112 and the first side surface 113 intersect may have a curved surface.

[0120] The second area 120 can be arranged in the non-curved area NBA of the curved area BA, and can be formed of transparent glass material.

[0121] The second region 120 may include a second upper surface 121 in contact with the gate insulating layer 220, a second lower surface 122 on the opposite side of the second upper surface 121, and a second side surface 123 and a third side surface 124 connecting the second upper surface 121 and the second lower surface 122. Here, the second side surface 123 may be a surface arranged to face the first side surface 113.

[0122] The second region 120 may include a second upper edge where the second upper surface 121 intersects with the second side surface 123, and a second lower edge where the second lower surface 122 intersects with the second side surface 123. Furthermore, the second region 120 may include a third upper edge where the second upper surface 121 intersects with the third side surface 124, and a third lower edge where the second lower surface 122 intersects with the third side surface 124. Here, the second side surface 123 and the third side surface 124 may be inclined surfaces with a predetermined slope relative to the second lower surface 122. Moreover, since the second side surface 123 and the third side surface 124 are formed by an etching process, the second lower edge and the third lower edge may have curved surfaces.

[0123] The third region 130 can be arranged in the second non-display region NA2 and can be formed of transparent glass material.

[0124] The third region 130 may include a third upper surface 131 in contact with the gate insulating layer 220, a third lower surface 132 on the opposite side of the third upper surface 131, and a fourth side surface 133 connecting the third upper surface 131 and the third lower surface 132. Here, the fourth side surface 133 may be a surface arranged to face the third side surface 124.

[0125] Furthermore, the third region 130 may include a fourth upper edge where the third upper surface 131 intersects with the fourth side surface 133, and a fourth lower edge where the third lower surface 132 intersects with the fourth side surface 133. Here, the fourth side surface 133 may be an inclined surface with a predetermined slope relative to the third lower surface 132. In addition, since the fourth side surface 133 is formed by an etching process, the fourth lower edge may have a curved surface.

[0126] The circuit layer 200 can be disposed in the display area DA, and some components of the circuit layer 200 can be disposed in the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, the circuit layer 200 can be disposed on the first upper surface 111 of the first area 110, and some components of the circuit layer 200 can be disposed in the first non-display area NA1, the curved area BA, and the second non-display area NA2. For example, the gate insulating layer 220, the first interlayer dielectric layer 230, and the second interlayer dielectric layer 260 can be disposed in the first non-display area NA1, the non-curved area NBA of the curved area BA, and the second non-display area NA2. In addition, the planarization layer 240 can be disposed in the first non-display area NA1, a portion of the curved area BA, and a portion of the second non-display area NA2.

[0127] The circuit layer 200 may include a thin-film transistor 210, a gate insulating layer 220 covering the gate electrode 211 of the thin-film transistor 210, an active layer 212 covering the thin-film transistor 210, a first interlayer dielectric layer 230 covering the source electrode 213 and the drain electrode 214, a planarization layer 240 disposed on the first interlayer dielectric layer 230, a first electrode 250 disposed on the planarization layer 240, a second interlayer dielectric layer 260 disposed on the first electrode 250, and a second electrode 270 disposed on the second interlayer dielectric layer 260.

[0128] The thin-film transistor 210 may include a gate electrode 211, an active layer 212, a source electrode 213, and a drain electrode 214.

[0129] The gate electrode 211 can be arranged on the first upper surface 111 of the first region 110.

[0130] The gate electrode 211 can be made of a conductive material. For example, the gate electrode 211 can be made of a metallic material. For example, the gate electrode 211 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0131] The gate insulating layer 220 can be disposed on the first substrate 100 and disposed in the display area DA, a portion of the first non-display area NA1, the curved area BA, and the second non-display area NA2 by etching by an etching process. For example, the gate insulating layer 220 can be disposed on the first region 110 to cover the gate electrode 211.

[0132] Since the gate insulating layer 220 can be made of inorganic insulating material, it can be etched using an etching process. Therefore, the gate insulating layer 220 can be separated into a gate insulating layer 220 disposed on the first region 110, a gate insulating layer 220 disposed on the second region 120, and a gate insulating layer 220 disposed on the third region 130.

[0133] The gate insulating layer 220 can be made of materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) x It is made of inorganic insulating materials such as inorganic insulating materials. The gate insulating layer 220 can be a single layer or multiple layers made of inorganic insulating materials, but is not limited thereto.

[0134] The active layer 212 can be disposed on the gate insulating layer 220 disposed on the first region 110. In addition, the active layer 212 can overlap with the gate electrode 211 along the Z-axis direction.

[0135] The active layer 212 can be made of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), oxide semiconductor, organic semiconductor, etc., but is not limited to these.

[0136] The source electrode 213 can be disposed on the active layer 212. For example, the source electrode 213 can be located in a different layer from the gate electrode 211. The source electrode 213 can be insulated from the gate electrode 211 through the gate insulating layer 220.

[0137] The source electrode 213 can be electrically connected to the source region of the active layer 212, and the source electrode 213 can include a region overlapping with the source region of the active layer 212. For example, the source electrode 213 can be in direct contact with the source region of the active layer 212.

[0138] The source electrode 213 may include a conductive material. For example, the source electrode 213 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0139] Drain electrode 214 can be disposed on active layer 212. For example, drain electrode 214 can be located in a different layer from gate electrode 211. Drain electrode 214 can be insulated from gate electrode 211 through gate insulating layer 220. Drain electrode 214 can be disposed in the same layer as source electrode 213. Drain electrode 214 can be disposed spaced apart from source electrode 213.

[0140] The drain electrode 214 can be electrically connected to the drain region of the active layer 212, and the drain electrode 214 can include a region overlapping with the drain region of the active layer 212. For example, the drain electrode 214 can be in direct contact with the drain region of the active layer 212.

[0141] The drain electrode 214 may include a conductive material. For example, the source electrode 213 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W).

[0142] Because etching is performed first, the first interlayer dielectric layer 230 disposed on the first substrate 100 can be disposed on the display area DA, the first non-display area NA1, a portion of the curved area BA, and the second non-display area NA2. For example, the first interlayer dielectric layer 230 can be disposed on the first region 110 to cover the gate electrode 211, etc.

[0143] The first interlayer dielectric layer 230 can be disposed on the active layer 212, the source electrode 213, and the drain electrode 214. In this case, the first interlayer dielectric layer 230 can cover the active layer 212, the source electrode 213, and the drain electrode 214 on the first region 110. Therefore, the first interlayer dielectric layer 230 can protect the active layer 212, the source electrode 213, and the drain electrode 214.

[0144] Furthermore, the first interlayer dielectric layer 230 can be disposed on the second pad layer PAD2b of the first pad PAD1 and the second pad PAD2. In this case, the first interlayer dielectric layer 230 can be disposed on the second region 120 and the third region 130.

[0145] The first interlayer dielectric layer 230 can be made of materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) x It is made of inorganic insulating materials such as inorganic insulating materials. The first interlayer dielectric layer 230 can be a single layer or multiple layers made of inorganic insulating materials, but is not limited thereto.

[0146] The planarization layer 240 can be disposed on the first interlayer dielectric layer 230. In this case, the planarization layer 240 of the circuit layer 200 can extend to a portion of the curved region BA to be disposed above the upper part of the first recess G1. For example, the planarization layer 240 can extend to the first pad PAD1 disposed in the curved region BA. Therefore, the planarization layer 240 can overlap with a portion of the second region 120.

[0147] The planarization layer 240 can be formed of a transparent organic insulating material. For example, the planarization layer 240 can be formed of one or more materials selected from polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, and benzocyclobutene, but is not limited thereto. Here, the planarization layer 240 can be a single layer or multiple layers made of organic insulating material.

[0148] Because the planarization layer 240 is formed of an organic insulating material that is more malleable than inorganic insulating materials, it can readily respond to bending of the display panel 10. For example, the planarization layer 240 extending from the circuit layer 200 of the display area DA can be arranged in the first bending area BA1, and the planarization layer 240 can be formed of an organic insulating material with good malleability, so that it can be easily bent without damage such as cracking.

[0149] A planarization layer 240 extending from the circuit layer 200 in the display area DA can be disposed above the first recess G1. For example, the planarization layer 240 can extend through the first non-display area NA1 to a portion of the second area 120, thereby covering the upper part of the first recess G1.

[0150] Since the planarization layer 240 can be formed from an organic insulating material that is highly resistant to etching solutions, the etching process is no longer performed through the planarization layer 240. In other words, the planarization layer 240, extending from the circuit layer 200 of the display area DA, can be used as an etching stop layer, thus serving as a first etch-resistant layer ES1. Therefore, a first groove G1 can be formed up to the planarization layer 240 by the etching process, and a portion of the lower surface of the planarization layer 240 can be exposed through the first groove G1.

[0151] In the display device according to the embodiments of this specification, when the planarization layer 240 is used as an etch stop layer, it is not necessary to arrange a separate anti-etch layer ES covering the upper part of the first groove G1, thereby improving process productivity. Furthermore, when the planarization layer 240 is used as an etch stop layer above the first groove G1, the first curved line BL1 arranged above the planarization layer 240 can be protected from the effects of the etching solution.

[0152] When etching the first substrate 100 to form the first recess G1, the planarization layer 240 may be formed of an organic insulating material with strong corrosion resistance to serve as an etch stop layer, but is not limited to this. For example, instead of extending the planarization layer 240 of the circuit layer 200 disposed in the display area DA to a portion of the second area 120, a separate first etch-resistant layer ES1 may be disposed above the first recess G1.

[0153] The first electrode 250 can be disposed on the planarization layer 240. Here, the first electrode 250 can be a common electrode.

[0154] The first electrode 250 can be formed of a transparent conductive material or an opaque conductive material. For example, the first electrode 250 can be indium tin oxide (ITO) or indium zinc oxide (IZO) or any other conductive material.

[0155] A voltage can be applied to the first electrode 250 and the second electrode 270. Therefore, the liquid crystal layer 300 can be driven to display an image. Here, the voltage can be applied to the second electrode 270 via the drain electrode 214.

[0156] The second interlayer dielectric layer 260 can be disposed in the display area DA, the first non-display area NA1, the curved area BA excluding the first curved area BA1 and the second curved area BA2, and the second non-display area NA2.

[0157] The second interlayer dielectric layer 260 can be disposed on the first electrode 250. For example, the second interlayer dielectric layer 260 can be disposed on the planarization layer 240 to cover the first electrode 250.

[0158] Furthermore, the second interlayer dielectric layer 260 can be disposed on the bend line BL. For example, the second interlayer dielectric layer 260 can be disposed above the etch resist layers ES1 and ES2 to cover a portion of the bend line BL. In this case, in the first non-display area NA1, based on the Z-axis direction, the second interlayer dielectric layer 260 can be disposed between the bend line BL and the first connection line LL1. Furthermore, in the non-bend area NBA, based on the Z-axis direction, the second interlayer dielectric layer 260 can be disposed between the bend line BL and the second connection line LL2 and / or between the bend line BL and the third connection line LL3.

[0159] Furthermore, in the non-curved area NBA and the second non-display area NA2, the second interlayer dielectric layer 260 can be disposed above the first interlayer dielectric layer 230.

[0160] The second interlayer dielectric layer 260 can be made of materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) xThe second interlayer dielectric layer 260 can be made of inorganic insulating materials such as inorganic insulating materials, but is not limited to this.

[0161] The second electrode 270 can be disposed on the second interlayer dielectric layer 260. The second electrode 270 can be electrically connected to the drain electrode 214 through contact holes formed in the planarization layer 240 and the second interlayer dielectric layer 260. The second electrode 270 can be a pixel electrode.

[0162] The second electrode 270 can be made of a transparent conductive material or an opaque conductive material. For example, the second electrode 270 can be made of indium tin oxide (ITO), indium zinc oxide (IZO), or other conductive materials.

[0163] The liquid crystal layer 300 can be disposed on the second interlayer dielectric layer 260, the second electrode 270 and the first connection line LL1, and can include an alignment film (not shown) to easily induce liquid crystal alignment.

[0164] The sealant 310 may surround the liquid crystal layer 300. For example, the sealant 310 may be disposed along the periphery of the liquid crystal layer 300 to seal the liquid crystal layer 300. Therefore, the sealant 310 may be a sealing member or a sealing line.

[0165] Reference Figure 3 The sealant 310 may be disposed above the second interlayer dielectric layer 260 and / or on the first connection line LL1. For example, based on the Z-axis direction, the sealant 310 may be disposed between the second interlayer dielectric layer 260 and the black matrix 600. Alternatively, based on the Z-axis direction, the sealant 310 may be disposed between the first connection line LL1 and the black matrix 600.

[0166] The sealant 310 can be a photocurable or thermocurable epoxy resin. The sealant 310 can form a gap (GAP) for liquid crystal injection between the second interlayer dielectric layer 260 and the color filter layer 500. Furthermore, the sealant 310 can be used to reduce or prevent liquid crystal leakage injected into the gap (GAP).

[0167] Furthermore, the sealant 310 may be a component for bonding the first substrate 100 and the second substrate 700. For example, the sealant 310 may be a component for bonding the second substrate 700, on which the color filter layer 500 and the black matrix 600 are disposed below, to the first substrate 100, on which the circuit layer 200 is disposed above.

[0168] Reference Figure 3 At least one pillar 320 may be disposed on the second interlayer dielectric layer 260. For example, based on the Z-axis direction, the pillar 320 may be disposed between the second interlayer dielectric layer 260 and the color filter layer 500. Thus, the pillar 320 can maintain a gap for liquid crystal injection.

[0169] The columnar part 320 may include a first columnar portion 321 and a second columnar portion 322.

[0170] The first columnar portion 321 can be arranged on the second interlayer dielectric layer 260.

[0171] The first columnar portion 321 can be formed of an organic insulating material and can be formed together with the pattern layer 400 using the same masking process used to form the pattern layer 400.

[0172] The second columnar portion 322 can be arranged on the first columnar portion 321 and can overlap with the first columnar portion 321.

[0173] The second columnar portion 322 may be formed of an organic insulating material.

[0174] A pattern layer 400 can be disposed on the bend line BL. Therefore, the pattern layer 400 can protect the bend line BL from physical and / or chemical impacts. For example, the pattern layer 400 can reduce or prevent moisture, impurities, etc., from penetrating into the bend line BL.

[0175] Pattern layer 400 can be disposed in a curved region BA, and when the curved region BA bends, pattern layer 400 can also bend accordingly. For example, pattern layer 400 can include a first pattern layer 400a disposed in a first curved region BA1 and a second pattern layer 400b disposed in a second curved region BA2. The first pattern layer 400a can overlap with a first groove G1, and the second pattern layer 400b can overlap with a second groove G2. Therefore, when the first curved region BA1 and the second curved region BA2 bend, the first pattern layer 400a and the second pattern layer 400b can bend.

[0176] The pattern layer 400 can be formed of an organic insulating material to withstand stress caused by bending. For example, the pattern layer 400 can be formed of organic materials including polyester-based polymers, acrylic-based polymers, etc.

[0177] Reference Figures 1 to 4B The pattern layer 400 can be configured as a structure with a predetermined width and height H1, and can be arranged along the X-axis direction. For example, the pattern layer 400 can be formed as a strip shape including a trapezoidal cross-section. Here, the height H1 of the pattern layer 400 can be a first height.

[0178] The pattern layer 400 can be formed to have a predetermined width. For example, the width of the first pattern layer 400a can be equal to or greater than the width W1 of the first groove G1. Furthermore, the width of the second pattern layer 400b can be equal to or greater than the width W2 of the second groove G2. In this case, the width of the first pattern layer 400a can be less than the length of the first curved line BL1, and the width of the second pattern layer 400b can be less than the length of the second curved line BL2.

[0179] The pattern layer 400 can be formed to have a predetermined height H1. Furthermore, the height H1 of the pattern layer 400 can be adjustable. Therefore, in the display panel 10 according to the embodiment of this specification, the height H1 of the pattern layer 400 can be adjusted to reduce or minimize the stress applied to the curved line BL.

[0180] Figure 5 This is a view showing a neutral surface based on curvature.

[0181] Reference Figure 5 The neutral plane can be defined as the plane where the stress state is zero during bending, and the magnitude of the tensile or compressive stress is proportional to the distance to the neutral plane. Based on the Z-direction, the neutral plane can be located at the center between the surface subjected to tensile stress and the surface subjected to compressive stress. Here, the surface subjected to compressive stress can be defined as the surface located near the center of curvature, and the surface subjected to tensile stress can be defined as the surface opposite to the surface subjected to compressive stress.

[0182] Components arranged in regions subjected to compressive stress are more prone to fracture than those arranged in regions subjected to tensile stress. For example, since the first bend line BL1 arranged in the first bend region BA1 of the display panel 10 and the second bend line BL2 arranged in the second bend region BA2 can be arranged in regions subjected to tensile stress, the likelihood of cracks appearing in the first bend line BL1 and / or the second bend line BL2 is relatively high due to the bending of the display panel 10. Because regions subjected to tensile stress are more prone to fracture than regions subjected to compressive stress during bending, the neutral plane can move closer to the first bend line BL1 and / or the second bend line BL2, thereby minimizing the stress applied to the first bend line BL1 and / or the second bend line BL2.

[0183] Therefore, when pattern layer 400 is arranged on curved line BL (see...) Figure 3According to one embodiment of this specification, the display device can position the neutral surface on the bending line BL or move the neutral surface closer to the bending line BL by adjusting the height H1 of the pattern layer 400 while determining the thickness from the pattern layer 400 to the bending line BL. Therefore, by using the pattern layer 400, the display panel 10 can reduce the stress applied to the bending line BL during bending of the display panel 10.

[0184] The color filter layer 500 can be disposed on the liquid crystal layer 300. In this case, the color filter layer 500 can be disposed in the display area DA. Furthermore, the color filter layer 500 can be formed on the same layer as the black matrix 600.

[0185] Color filter layer 500 may include red, green, and blue color filters. For example, color filter layer 500 may include acrylic resin and pigments. Depending on the type of pigment that achieves the color, color filter layer 500 may be classified as red, green, and blue.

[0186] The black matrix 600 can be arranged in the first non-display area NA1 and can be arranged on the liquid crystal layer 300 and the sealant 310.

[0187] Furthermore, the black matrix 600 can have a closed-loop shape surrounding the display area DA. Therefore, the black matrix 600 can prevent light leakage. In this case, the black matrix 600 can overlap with the color filter layer 500 along the X-axis and Y-axis directions.

[0188] The second substrate 700 can be disposed on the color filter layer 500 and the black matrix 600. Therefore, the second substrate 700 can protect the color filter layer 500 and the black matrix 600.

[0189] The end of the second substrate 700 may protrude further than the black matrix 600 along the Y-axis direction, but it is not limited to this. For example, the end of the second substrate 700 may also be arranged to overlap with the end of the black matrix 600 along the Z-axis direction.

[0190] The second substrate 700 can be made of transparent plastic material, glass material or reinforced glass material.

[0191] The upper polarizing layer UPOL can be disposed on the second substrate 700. The upper polarizing layer UPOL can overlap with the color filter layer 500 and can be disposed in the display area DA.

[0192] The lower polarizing layer DPOL can be disposed below the first region 110. For example, the lower polarizing layer DPOL can be attached to the underside of the first region 110 by means of an adhesive member.

[0193] The protective layer 800 can be disposed above the pattern layer 400. For example, the protective layer 800 can be disposed to cover the pattern layer 400. In this case, the protective layer 800 can cover the portion of the connecting line LL disposed above the etch resist layer ES.

[0194] Therefore, the protective layer 800, together with the pattern layer 400, can protect a portion of the curved line BL and / or the connecting line LL from physical and / or chemical impacts. Here, the protective layer 800 can be an upper micro-coating or an upper coating.

[0195] The protective layer 800 may be formed of an organic insulating material to withstand stress caused by bending. For example, the protective layer 800 may be formed of an organic material including acrylic-based materials (e.g., acrylate polymers), but is not limited to this.

[0196] The protective layer 800 can be formed with a predetermined width and height H2. Therefore, similar to the pattern layer 400, the position of the neutral surface can be adjusted by adjusting the height H2 of the protective layer 800. Here, the height H2 of the protective layer 800 can be a second height.

[0197] The protective layer 800 may include a first protective layer 800a and a second protective layer 800b spaced apart from each other along the Y-axis direction.

[0198] The first protective layer 800a can be disposed on the first pattern layer 400a and can overlap with the first groove G1. When the first bending region BA1 bends, the first protective layer 800a can also bend accordingly. In this case, the first protective layer 800a can cover the portion of the connecting line LL located above the first etch-resistant layer ES1.

[0199] A portion of the first protective layer 800a may be disposed within a groove G1ES1 recessed in the upper surface of the first etch-resistant layer ES1. Here, the groove G1ES1 of the first etch-resistant layer ES1 may be a first upper groove or a planarization groove.

[0200] Therefore, a portion of the first protective layer 800a may overlap with the first etch-resistant layer ES1 in the horizontal direction. In this case, a portion of the second connecting line LL2 may also be arranged inside the groove G1ES1 formed in the first etch-resistant layer ES1, but is not limited to this. For example, the grooves G1ES1 formed in the first etch-resistant layer ES1 may be spaced apart from each other in the X-axis direction, so that the second connecting line LL2 may be arranged between the grooves G1ES1. Here, the portion of the protective layer 800 arranged inside the groove G1ES1 may be the protrusion 810 or the first protrusion of the first protective layer 800a.

[0201] The first protective layer 800a can achieve a reinforcing structure, with a portion disposed within a groove G1ES1 formed in the first etch-resistant layer ES1. For example, a portion of the first protective layer 800a can be disposed within the groove G1ES1 of the first etch-resistant layer ES1 adjacent to the first bending region BA1, so that even if bending stress is applied to the first protective layer 800a, the portion of the first protective layer 800a disposed within the groove G1ES1 can be supported by the first etch-resistant layer ES1. Therefore, the first protective layer 800a can withstand stress caused by bending of the portion of the first protective layer 800a disposed within the groove G1ES1. For example, the engagement of the protrusion 810 of the first protective layer 800a with the groove G1ES1 enables the first protective layer 800a to resist deformation during bending.

[0202] The second protective layer 800b can be disposed on the second pattern layer 400b and can overlap with the second groove G2. When the second bending region BA2 bends, the second protective layer 800b can also bend accordingly. In this case, the second protective layer 800b can cover the portion of the connecting line LL located above the second etch-resistant layer ES2.

[0203] Some portions of the second protective layer 800b may be disposed within the recesses G2ES2 and G3ES2 recessed in the upper surface of the second etch-resistant layer ES2. For example, the second etch-resistant layer ES2 may include a second upper recess G2ES2 and a third upper recess G3ES2 spaced apart from each other, with a second curved line BL2 inserted between them.

[0204] Therefore, a portion of the second protective layer 800b may overlap with the second etch-resistant layer ES2 in the horizontal direction. In this case, a portion of the third connecting line LL3 and a portion of the fourth connecting line LL4 may also be arranged inside the grooves G2ES2 and G3ES2 formed in the second etch-resistant layer ES2, but are not limited thereto. For example, the grooves G2ES2 formed in the second etch-resistant layer ES2 may be spaced apart from each other in the X-axis direction, so that the third connecting line LL3 may be arranged between the grooves G2ES2. Furthermore, the grooves G3ES2 formed in the second etch-resistant layer ES2 may be spaced apart from each other in the X-axis direction, so that the fourth connecting line LL4 may be arranged between the grooves G3ES2. Here, the portion of the protective layer 800 arranged inside the second upper groove G2ES2 may be a protrusion 820 of the second protective layer 800b, an internal protrusion of the second protective layer 800b, or a second protrusion. Furthermore, the portion of the protective layer 800 arranged inside the third upper groove G3ES2 may be a protrusion 830 of the second protective layer 800b, an external protrusion of the second protective layer 800b, or a third protrusion.

[0205] The second protective layer 800b can achieve a reinforcing structure, with some portions disposed within the grooves G2ES2 and G3ES2 formed in the second etch-resistant layer ES2. For example, some portions of the second protective layer 800b can be disposed within the grooves G2ES2 and G3ES2 of the second etch-resistant layer ES2 arranged adjacent to the second bending region BA2, so that even if bending stress is applied to the second protective layer 800b, the portions of the second protective layer 800b disposed within the grooves G2ES2 and G3ES2 can be supported by the second etch-resistant layer ES2. Therefore, by using the portions of the second protective layer 800b disposed within the grooves G2ES2 and G3ES2, the second protective layer 800b can cope with bending stress. For example, the engagement of the protrusion 820 of the second protective layer 800b with the second upper groove G2ES2 and the engagement of the protrusion 830 of the second protective layer 800b with the third upper groove G3ES2 can allow the second protective layer 800b to resist deformation during bending.

[0206] By utilizing the portion of the second protective layer 800b arranged inside the grooves G2ES2 and G3ES2, the second protective layer 800b can improve its resistance to deformation caused by bending.

[0207] The display panel 10 may include two curved lines BL arranged corresponding to each of the first recess G1 and the second recess G2, and one of the two curved lines BL may overlap with the first recess G1 and the other may overlap with the second recess G2. Therefore, the first curved line BL1 may be disposed on the first etch resist layer ES1, and the second curved line BL2 may be disposed on the second etch resist layer ES2. If the first etch resist layer ES1 is a planarization layer 240 extending from the circuit layer 200, then the first curved line BL1 may be disposed on the planarization layer 240.

[0208] The curved line BL can be arranged in the first non-display area NA1, the curved area BA, and the second non-display area NA2.

[0209] Based on the Y-axis direction, the first curved line BL1 can be formed to be longer than the first curved region BA1. For example, the length of the first curved line BL1 along the Y-axis direction can be greater than the width W1 of the first groove G1. Therefore, the first curved line BL1 can be arranged in a portion of the first non-display area NA1 and a portion of the curved region BA.

[0210] Furthermore, based on the Y-axis direction, the second curved line BL2 can be formed to be longer than the second curved region BA2. For example, the length of the second curved line BL2 along the Y-axis direction can be greater than the width W2 of the second groove G2. Therefore, the second curved line BL2 can be arranged in a portion of the curved region BA and a portion of the second non-display region NA2.

[0211] The curved line BL can be formed from a conductive material. For example, the curved line BL can be formed from a metallic material. For example, the curved line BL can be a single layer or multiple layers made of any one of indium tin oxide (ITO), indium zinc oxide (IZO), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or their alloys, but is not limited to these. For example, the curved line BL can be formed as a double-layer structure.

[0212] The bending line BL may include a first layer BLL1 and a second layer BLL2. Furthermore, the first layer BLL1 and the second layer BLL2 may be made of different materials. Therefore, the bending line BL can readily respond to stresses caused by bending.

[0213] At least one of the first layer BLL1 and the second layer BLL2 of the curved line BL may include the same metal layer as the first electrode 250.

[0214] Furthermore, the first layer BLL1 and the second layer BLL2 of the curved line BL can be made of a material different from the material of the first electrode 250.

[0215] The first layer BLL1 can be disposed on the etch resist layers ES1 and ES2. Furthermore, the first layer BLL1 can be formed of transparent indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the first layer BLL1 can include the same material as the first electrode 250 and can be formed together with the first electrode 250 using the same masking process used to form the first electrode 250.

[0216] The second layer BLL2 can be placed on top of the first layer BLL1. Based on the Y-axis direction, the second layer BLL2 can have the same length as the first layer BLL1, but it is not limited to this.

[0217] The second layer BLL2 can be formed of a material different from that of the first layer BLL1. For example, the second layer BLL2 can be made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the second layer BLL2 may include copper (Cu).

[0218] Furthermore, the bending line BL can include a material different from that of the connecting line LL. For example, the connecting line LL can be formed of indium tin oxide (ITO) or indium zinc oxide (IZO), and the second layer BLL2 of the bending line BL can be formed of copper, thus the bending line BL can include a material different from that of the connecting line LL.

[0219] In this way, since the first connecting line LL1 and the second connecting line LL2 are connected via two bending lines BL, and the third connecting line LL3 and the fourth connecting line LL4 are connected, the display device according to the embodiment of this specification can easily respond to stress caused by bending. Furthermore, since the bending lines BL comprise at least two layers containing different materials, they can respond to stress caused by bending more effectively. Here, the first connecting line LL1 can be a first connecting line, the second connecting line LL2 can be a second connecting line, the third connecting line LL3 can be a third connecting line, and the fourth connecting line LL4 can be a fourth connecting line.

[0220] The connecting line LL may include a first connecting line LL1 arranged in the first non-display area NA1, a second connecting line LL2 and a third connecting line LL3 arranged in the non-bending area NBA, and a fourth connecting line LL4 arranged in the second non-display area NA2, with a first pad PAD1 inserted between the second connecting line LL2 and the third connecting line LL3.

[0221] The first connecting line LL1 and the second connecting line LL2 can be connected via a first curved line BL1. For example, based on the Y-axis direction, the first patterned layer 400a can be disposed between the first connecting line LL1 and the second connecting line LL2. In this case, the first curved line BL1 disposed below the first patterned layer 400a can be electrically connected to the first connecting line LL1 through a first contact hole CH1, and can be electrically connected to the second connecting line LL2 through a second contact hole CH2. Therefore, the first connecting line LL1 can contact one side of the first curved line BL1, and the second connecting line LL2 can contact the other side of the first curved line BL1. Here, the first contact hole CH1 and the second contact hole CH2 can be formed to penetrate the second interlayer dielectric layer 260.

[0222] The first connecting line LL1 can be arranged in the first non-display area NA1. For example, the first connecting line LL1 can be arranged on the second interlayer dielectric layer 260 of the first non-display area NA1. In addition, the first connecting line LL1 can be electrically connected to the first bent line BL1 through the first contact hole CH1 that penetrates the second interlayer dielectric layer 260 in the first non-display area NA1.

[0223] The second connecting line LL2 can be placed in the non-curved area of ​​the NBA.

[0224] The second connecting line LL2 may include a first part LL2a and a second part LL2b.

[0225] The first part LL2a of the second connecting line LL2 can be arranged on the second interlayer dielectric layer 260 of the non-bent region NBA, and can be electrically connected to the first bent line BL1 through the second contact hole CH2.

[0226] The second portion LL2b of the second connection line LL2 can be disposed on the gate insulating layer 220. Furthermore, the first portion LL2a and the second portion LL2b can be electrically connected through a third contact hole CH3. Here, the third contact hole CH3 can be a contact hole penetrating the first interlayer dielectric layer 230, the first etch resist layer ES1, and the second interlayer dielectric layer 260. In this case, the second portion LL2b can be electrically connected to the first intermediate pad layer PAD1M of the first pad PAD1. More specifically, the second portion LL2b can be electrically connected to the inner intermediate pad layer PAD1Ma of the first pad PAD1, but is not limited thereto. For example, the second portion LL2b can be electrically connected to the inner lower pad layer PAD1Da of the first lower pad layer PAD1D of the first pad PAD1. Here, the second portion LL2b and the inner intermediate pad layer PAD1Ma can be integrally formed using the same mask process. Here, the term "inner" can refer to the direction towards the display area DA, and the term "outer" can refer to the direction opposite to "inner".

[0227] The third connecting line LL3 and the fourth connecting line LL4 can be connected via the second curved line BL2. For example, based on the Y-axis direction, the second patterned layer 400b can be disposed between the third connecting line LL3 and the fourth connecting line LL4. In this case, the second curved line BL2 disposed below the second patterned layer 400b can be electrically connected to the third connecting line LL3 through the fifth contact hole CH5, and to the fourth connecting line LL4 through the sixth contact hole CH6. Therefore, the third connecting line LL3 can contact one side of the second curved line BL2, and the fourth connecting line LL4 can contact the other side of the second curved line BL2. Here, the fifth contact hole CH5 and the sixth contact hole CH6 can be formed to penetrate the second interlayer dielectric layer 260.

[0228] The third connecting line LL3 can be placed in non-curved areas of the NBA.

[0229] The third connecting line LL3 may include a third part LL3a and a fourth part LL3b.

[0230] The third part LL3a of the third connecting line LL3 can be arranged on the second interlayer dielectric layer 260 of the non-bending region NBA, and can be electrically connected to the second bending line BL2 through the fifth contact hole CH5.

[0231] The fourth portion LL3b of the third connection line LL3 can be disposed on the gate insulating layer 220. Furthermore, the third portion LL3a and the fourth portion LL3b can be electrically connected through a fourth contact hole CH4. Here, the fourth contact hole CH4 can be a contact hole penetrating the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260. In this case, the fourth portion LL3b can be electrically connected to the first intermediate pad layer PAD1M of the first pad PAD1. More specifically, the fourth portion LL3b can be electrically connected to the outer intermediate pad layer PAD1Mb of the first pad PAD1, but is not limited thereto. For example, the fourth portion LL3b can be electrically connected to the outer lower pad layer PAD1Db of the first lower pad layer PAD1D of the first pad PAD1. Here, the fourth portion LL3b and the outer intermediate pad layer PAD1Mb can be integrally formed using the same mask process.

[0232] The fourth connecting line LL4 can be placed in the second non-display area NA2.

[0233] The fourth connecting line LL4 may include a fifth part LL4a and a sixth part LL4b.

[0234] The fifth part LL4a of the fourth connecting line LL4 can be arranged on the second interlayer dielectric layer 260 of the second non-display area NA2, and can be electrically connected to the second bent line BL2 through the sixth contact hole CH6.

[0235] The sixth portion LL4b of the fourth connection line LL4 can be disposed on the gate insulating layer 220. Furthermore, the fifth portion LL4a and the sixth portion LL4b can be electrically connected through the seventh contact hole CH7. Here, the seventh contact hole CH7 can be a contact hole penetrating the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260. In this case, the sixth portion LL4b can be electrically connected to the second intermediate pad layer PAD2M of the second pad PAD2, but is not limited to this. For example, the sixth portion LL4b can be electrically connected to the second lower pad layer PAD2D of the second pad PAD2. Here, the fourth portion LL3b and the second intermediate pad layer PAD2M can be integrally formed using the same mask process.

[0236] The first pad PAD1 can be disposed in the non-bent area NBA. Furthermore, the first pad PAD1 can be formed to be exposed externally for connection with the chip 20.

[0237] Reference Figure 3 as well as Figure 4A and Figure 4BThe first pad PAD1 may include: a first lower pad layer PAD1D disposed on the second region 120; a first intermediate pad layer PAD1M disposed on the gate insulating layer 220 to overlap with the first lower pad layer PAD1D; and a first upper pad layer PAD1U disposed on the second interlayer dielectric layer 260 to overlap with the first intermediate pad layer PAD1M.

[0238] At least one of the first lower pad layer PAD1D, the first intermediate pad layer PAD1M, and the first upper pad layer PAD1U can be made of a material different from the material of the others. For example, the first upper pad layer PAD1U can be made of a material different from the material of the first lower pad layer PAD1D and / or the first intermediate pad layer PAD1M. For example, the first lower pad layer PAD1D, the first intermediate pad layer PAD1M, and the first upper pad layer PAD1U can be formed of different materials. Furthermore, the first lower pad layer PAD1D, the first intermediate pad layer PAD1M, and the first upper pad layer PAD1U can be formed using different manufacturing processes.

[0239] The first lower pad layer PAD1D can be formed together with the gate electrode 211 using the same mask process as the gate electrode 211. Furthermore, the first intermediate pad layer PAD1M can be formed together with the source electrode 213 and the drain electrode 214 using the same mask process as the source electrode 213 and the drain electrode 214. Additionally, the first upper pad layer PAD1U can be formed together with the interconnect line LL using the same mask process as the interconnect line LL.

[0240] The first upper pad layer PAD1U, the first middle pad layer PAD1M, and the first lower pad layer PAD1D can be electrically connected. For example, the first upper pad layer PAD1U can be electrically connected to the first middle pad layer PAD1M through contact holes penetrating the first interlayer dielectric layer 230 and the second interlayer dielectric layer 260. Furthermore, the first middle pad layer PAD1M can be electrically connected to the first lower pad layer PAD1D through contact holes penetrating the gate insulating layer 220.

[0241] The upper portion of the first upper pad layer PAD1U can be exposed to the outside for connection with the chip 20. Therefore, the chip 20 can be disposed on the exposed upper portion of the first upper pad layer PAD1U. In this case, the first upper pad layer PAD1U can be disposed between the first etch resist layer ES1 and the second etch resist layer ES2, and can overlap with the first etch resist layer ES1 and the second etch resist layer ES2 along the Y-axis direction. Furthermore, since the arrangement position of the first upper pad layer PAD1U is lower than the height of the first etch resist layer ES1 and the second etch resist layer ES2 based on the upper surface of the substrate 100, a groove can be formed between the first etch resist layer ES1 and the second etch resist layer ES2. Moreover, since the chip 20 is disposed in the groove, a narrow bezel of the display device can be easily achieved when the display panel 10 is bent.

[0242] The first upper pad layer PAD1U may include an inner upper pad layer PAD1Ua and an outer upper pad layer PAD1Ub arranged corresponding to the input terminals (or input terminals) and output terminals (or output terminals) of the chip 20, respectively. Furthermore, the inner upper pad layer PAD1Ua and the outer upper pad layer PAD1Ub may be spaced apart from each other. In this case, the inner upper pad layer PAD1Ua and the outer upper pad layer PAD1Ub can be electrically connected to the chip 20.

[0243] Furthermore, the first intermediate pad layer PAD1M may include an inner intermediate pad layer PAD1Ma connected to the inner upper pad layer PAD1Ua, and an outer intermediate pad layer PAD1Mb connected to the outer upper pad layer PAD1Ub. Additionally, the inner intermediate pad layer PAD1Ma and the outer intermediate pad layer PAD1Mb may be spaced apart from each other. Here, the inner intermediate pad layer PAD1Ma may be connected to the second portion LL2b of the second connection line LL2. Furthermore, the outer intermediate pad layer PAD1Mb may be connected to the fourth portion LL3b of the third connection line LL3.

[0244] Furthermore, the first intermediate pad layer PAD1M may include an inner lower pad layer PAD1Da connected to the inner intermediate pad layer PAD1Ma, and an outer lower pad layer PAD1Db connected to the outer intermediate pad layer PAD1Mb. The inner lower pad layer PAD1Da and the outer lower pad layer PAD1Db may be spaced apart from each other.

[0245] The second pad PAD2 can be placed in the second non-display area NA2.

[0246] Reference Figure 3 and Figure 5The second pad PAD2 may include: a second lower pad layer PAD2D disposed on the third region 130; a second intermediate pad layer PAD2M disposed on the gate insulating layer 220 to overlap with the second lower pad layer PAD2D; and a second upper pad layer PAD2U disposed on the second interlayer dielectric layer 260 to overlap with the second intermediate pad layer PAD2M. Here, the second upper pad layer PAD2U can be electrically connected to the circuit board 30. Furthermore, the second intermediate pad layer PAD2M can be connected to the sixth portion LL4b of the fourth connection line LL4.

[0247] At least one of the second lower pad layer PAD2D, the second intermediate pad layer PAD2M, and the second upper pad layer PAD2U can be made of a material different from the others. For example, the second upper pad layer PAD2U can be made of a material different from the materials of the second lower pad layer PAD2D and / or the second intermediate pad layer PAD2M. For example, the second lower pad layer PAD2D, the second intermediate pad layer PAD2M, and the second upper pad layer PAD2U can be formed of different materials. Furthermore, the second lower pad layer PAD2D, the second intermediate pad layer PAD2M, and the second upper pad layer PAD2U can be formed using different manufacturing processes.

[0248] The second lower pad layer PAD2D can be formed together with the gate electrode 211 using the same mask process as the gate electrode 211. Furthermore, the second intermediate pad layer PAD2M can be formed together with the source electrode 213 and the drain electrode 214 using the same mask process as the source electrode 213 and the drain electrode 214. Additionally, the second upper pad layer PAD2U can be formed together with the interconnect line LL using the same mask process as the interconnect line LL.

[0249] The second upper pad layer PAD2U, the second middle pad layer PAD2M, and the second lower pad layer PAD2D can be electrically connected. For example, the second upper pad layer PAD2U can be electrically connected to the second middle pad layer PAD2M through contact holes penetrating the first interlayer dielectric layer 230 and the second interlayer dielectric layer 260. Furthermore, the second middle pad layer PAD2M can be electrically connected to the second lower pad layer PAD2D through contact holes penetrating the gate insulating layer 220.

[0250] Figure 6 This is a view showing the coating arranged in a display panel according to an embodiment of this specification.

[0251] Reference Figure 6 The display panel 10 according to the embodiments of this specification may further include a coating 900 disposed in the grooves G1 and G2.

[0252] The coating 900 can be disposed below the resist layer ES to overlap with a portion of the curved line BL. Here, the lower surface 910 of the coating 900 can be formed recessed toward the resist layer ES, but is not limited to this. For example, the lower surface 910 of the coating 900 can be substantially flat.

[0253] The coating 900 can be formed from organic materials including polyester-based polymers or acrylic-based polymers.

[0254] Taking into account the position of the neutral surface, the coating 900 can be formed to have a predetermined thickness T.

[0255] By determining the thickness from the resist layer ES to the bend line BL, or from the resist layer ES to the pattern layer 400, or from the resist layer ES to the protective layer 800, the display device according to the embodiment of this specification can adjust the thickness T of the coating 900. Therefore, the neutral surface can be located on or near the bend line BL. Thus, by using the coating 900, the display panel 10 can reduce the stress applied to the bend line BL during bending of the display panel 10.

[0256] The coating 900 may include a first coating 900a disposed in the first groove G1 and a second coating 900b disposed in the second groove G2.

[0257] Figure 7 This is a view showing the curved appearance of the display device according to an embodiment of this specification.

[0258] Reference Figure 7 The display panel 10 of the display device according to the embodiments of this specification can be bent. For example, when the bending region BA bends, the display panel 10 can be bent so that the first region 110 and the third region 130 face each other. More specifically, when the first bending region BA1 and the second bending region BA2 bend, the display panel 10 can be bent so that the first region 110 and the third region 130 face each other.

[0259] The center of curvature of the first curved region BA1 may differ from the center of curvature of the second curved region BA2. For example, the first center of curvature C1 of the first curved line BL1 may differ from the second center of curvature C2 of the second curved line BL2. In this case, the first curved line BL1 may be curved to have a first radius of curvature R1. Furthermore, the second curved line BL2 may be curved to have a second radius of curvature R2. Here, the first radius of curvature R1 and the second radius of curvature R2 may be the same, but are not necessarily limited to this.

[0260] Since the gate insulating layer 220, the first interlayer dielectric layer 230, and the second interlayer dielectric layer 260, which are made of inorganic insulating materials, are not arranged in the first bending region BA1 and the second bending region BA2 of the display panel 10 according to the embodiment of this specification, damage to the gate insulating layer 220, the first interlayer dielectric layer 230, and the second interlayer dielectric layer 260 due to bending can be reduced or prevented in advance.

[0261] When the first curved region BA1 and the second curved region BA2 are curved, the light source 40 can be arranged between the first region 110 and the third region 130. Here, the light source 40 can emit light towards the first region 110. Therefore, the light source 40 can overlap with the first region 110 along the Z-axis direction.

[0262] The light source 40 may include a backlight unit 41 and a housing 42 surrounding the backlight unit 41.

[0263] The backlight unit 41 can emit light toward the first region 110. The light source used in the backlight unit 41 can be a light-emitting diode (LED), but is not limited to it.

[0264] The housing 42 may be arranged to surround the backlight unit 41 to protect the backlight unit 41. In addition, the housing 42 may include an opening OP formed to allow light from the backlight unit 41 to be emitted.

[0265] The opening OP can be arranged facing the first region 110. In addition, the lower polarizing layer DPOL can be arranged in the opening OP.

[0266] Figure 8 This is a view showing the heat-conducting member of a display device according to an embodiment of this specification.

[0267] Now refer to Figure 8 The display device according to the embodiments of this specification may include a heat-conducting member 1000.

[0268] The heat-conducting member 1000 can be disposed between the second region 120 and the housing 42. Therefore, the heat generated by the chip 20 can be transferred to the housing 42 via the second region 120 and the heat-conducting member 1000, and then dissipated. For example, because the housing 42 has a larger heat dissipation area than the second region 120, the heat generated by the chip 20 can be effectively dissipated after being transferred to the housing 42 via the heat-conducting member 1000. In this case, the housing 42 can be formed of a metallic material. Here, the heat-conducting member 1000 can be formed of at least one of a heat-transfer pad, a thermally conductive resin layer, and a hot grease with high thermal conductivity.

[0269] Furthermore, since the second region 120 is attached to the housing 42 via the heat-conducting member 1000, a reinforced structure resistant to external forces can be achieved. For example, when a predetermined load is applied to the second region 120, the second region 120 can be supported by the housing 42. Therefore, the rigidity of the non-bending region NBA against external forces can be improved.

[0270] Figure 9 This is a view showing one embodiment of the connecting lines arranged in a display panel according to an embodiment of this specification. Figure 10 yes Figure 9 A magnified view of region C in the image. For example, Figure 9 and Figure 10 This could be a diagram illustrating a second embodiment showing the connection relationship between the first pad PAD1, the second pad PAD2, and the connecting line LL arranged on the display panel. Furthermore, Figure 3 as well as Figure 4A and Figure 4B The display panel 10 shown may be a first embodiment of the display panel 10 that shows the connection relationship between the first pad PAD1, the second pad PAD2, and the connection line LL. Here, Figure 9 It could be a schematic diagram showing the connecting lines arranged on line I-I'.

[0271] Reference Figure 3 , Figure 4A and Figure 4B , Figure 9 and Figure 10 Comparing the display panel 10 according to the first embodiment and the display panel 10a according to the second embodiment, the display panel 10a according to the second embodiment may include a second portion LL2b of the second connecting line LL2, a fourth portion LL3b of the third connecting line LL3, and a sixth portion LL4b of the fourth connecting line LL4 located on the substrate 100. In this case, the display panel 10a according to the second embodiment can be applied to a display device according to the embodiments of this specification, rather than the display panel 10 according to the first embodiment.

[0272] In reference Figure 3 , Figure 4A and Figure 4B , Figure 9 and Figure 10 When describing the display panel 10a according to the second embodiment, the same reference numerals can be used to denote substantially the same components as the display panel 10 according to the first embodiment and the display panel 10a according to the second embodiment, thereby omitting or simplifying their detailed description.

[0273] Now refer to Figure 9 and Figure 10The display panel 10a includes: a substrate 100, which includes a first region 110, a second region 120, and a third region 130 spaced apart from each other by a first groove G1 and a second groove G2; a circuit layer 200 disposed on the substrate 100; a liquid crystal layer 300 disposed on the circuit layer 200; a first pad PAD1 disposed on the second region 120; a second pad PAD2 disposed on the third region 130; and multiple connecting lines LL and multiple curved lines BL. The display panel 10a may also include a first resist layer ES1, a second resist layer ES2, a sealant 310, pillars 320, a pattern layer 400, a color filter layer 500, a black matrix 600, a second substrate 700, a lower polarizing layer DPOL and an upper polarizing layer UPOL, a protective layer 800, and a coating layer 900.

[0274] The second connection line LL2 arranged in the display panel 10a may include a first portion LL2a and a second portion LL2b. The second portion LL2b may be electrically connected to the inner lower pad layer PAD1Da of the first lower pad layer PAD1D of the first pad PAD1.

[0275] The first part LL2a and the second part LL2b can be electrically connected through the third contact hole CH3. Here, the third contact hole CH3 can be a contact hole that penetrates the gate insulating layer 220, the first interlayer dielectric layer 230, the first etch resist layer ES1, and the second interlayer dielectric layer 260.

[0276] The third connection line LL3 arranged in the display panel 10a may include a third part LL3a and a fourth part LL3b. The fourth part LL3b may be electrically connected to the outer lower pad layer PAD1Db of the first lower pad layer PAD1D of the first pad PAD1.

[0277] The third part LL3a and the fourth part LL3b can be electrically connected through the fourth contact hole CH4. Here, the fourth contact hole CH4 can be a contact hole that penetrates the gate insulating layer 220, the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260.

[0278] The fourth connection line LL4 arranged in the display panel 10a may include a fifth part LL4a and a sixth part LL4b. The sixth part LL4b may be electrically connected to the second lower pad layer PAD2D of the second pad PAD2.

[0279] The fifth part LL4a and the sixth part LL4b can be electrically connected through the seventh contact hole CH7. Here, the seventh contact hole CH7 can be a contact hole that penetrates the gate insulating layer 220, the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260.

[0280] Reference Figure 2 Multiple second connection lines LL2 and third connection lines LL3 can be connected to a first pad PAD1. In this case, among the multiple second connection lines LL2 along the X-axis, when viewed along the Z-axis, the length of the second connection line LL2 connected to the center side of the first pad PAD1 and the length of the second connection line LL2 connected to the edge side of the first pad PAD1 can be different.

[0281] For example, the length of the second connection line LL2 adjacent to the edge side of the first pad PAD1 along the X-axis direction can be longer in the plane than the length of the second connection line LL2 connected to the center side of the first pad PAD1. As a result, when the connection lines LL are arranged as in the display panel 10 according to the first embodiment, the resistance of the second connection line LL2 connected to the edge side of the first pad PAD1 can be relatively greater than the resistance of the second connection line LL2 connected to the center side of the first pad PAD1. This resistance difference of the second connection line LL2 may affect signal transmission through the second connection line LL2. For example, the resistance difference between the second connection line LL2 connected to the center side of the first pad PAD1 and the second connection line LL2 connected to the edge side of the first pad PAD1 may affect signal transmission from the circuit board 30 to the circuit layer 200.

[0282] Multiple fourth connection lines LL4 can be connected to a second pad PAD2. In this case, the width of the second pad PAD2 along the X-axis can be different from the width of the first pad PAD1 along the X-axis. As a result, among the multiple fourth connection lines LL4 based on the X-axis direction, the length of the fourth connection line LL4 connected to the center side of the second pad PAD2 and the length of the fourth connection line LL4 connected to the edge side of the second pad PAD2 can be different in the plane. In other words, just like the second connection line LL2, the fourth connection lines LL4 can also have a resistance difference depending on their arrangement in the plane.

[0283] Therefore, in the display device according to the embodiments of this specification, by selecting the arrangement position and material of the second part LL2b, the arrangement position and material of the fourth part LL3b, and the arrangement position and material of the sixth part LL4b, the resistance can be adjusted according to the position of each connecting line LL. Therefore, the resistance difference of the connecting lines LL according to their positions can be minimized. For example, the connecting line LL connected to the center side of the first pad PAD1 can be arranged like the connecting line LL arranged in the display panel 10a according to the second embodiment (see...). Figure 9 and 10 Furthermore, the outermost connecting line LL, based on the center of the first pad PAD1, can be arranged in the same manner as the connecting line LL arranged in the display panel 10 according to the first embodiment (see...). Figure 3as well as Figure 4A and Figure 4B Therefore, each connecting line LL can be arranged differently on the cross section based on its position on the plane, thereby reducing or minimizing the resistance difference between the connecting lines LL.

[0284] Figure 11 This is a view showing one embodiment of the connecting lines arranged in a display panel according to an embodiment of this specification. Figure 12 yes Figure 11 An enlarged view of region D in the image. Figure 11 and Figure 12 The diagram may be a third embodiment illustrating the connection relationship between the first pad PAD1, the second pad PAD2, and the connecting line L1 arranged in the display panel according to an embodiment of this specification, but is not limited thereto. For example, the connecting lines of the first embodiment of the connection relationship between the first pad PAD1, the second pad PAD2, and the connecting line L1 (see...) Figure 3 as well as Figure 4A and Figure 4B ), the connecting line of the second embodiment (see Figure 9 and Figure 10 The connection line between the third embodiment and the third embodiment (see) Figure 11 and Figure 12 All of these can be arranged in a single display panel. Here, Figure 11 It could be a diagram showing the connecting lines arranged based on line I-I' at a first distance D1.

[0285] exist Figure 11 and Figure 12 In the display panel 10b shown, the second portion LL2b of the second connecting line LL2 and the fourth portion LL3b of the third connecting line LL3 can be located on the substrate 100. Furthermore, the sixth portion LL4b of the fourth connecting line LL4 can be located on the gate insulating layer 220.

[0286] In description Figure 11 and Figure 12 When referring to the display panel 10b shown, the same reference numerals can be used to denote substantially the same components as the display panel 10 according to the first embodiment and the display panel 10a according to the second embodiment, thereby allowing for the omission or simplification of their detailed descriptions.

[0287] Now refer to Figure 11 and Figure 12The display panel 10b includes: a substrate 100, which includes a first region 110, a second region 120, and a third region 130 spaced apart from each other by a first groove G1 and a second groove G2; a circuit layer 200 disposed on the substrate 100; a liquid crystal layer 300 disposed on the circuit layer 200; a first pad PAD1 disposed on the second region 120; a second pad PAD2 disposed on the third region 130; and multiple connecting lines LL and multiple curved lines BL. Furthermore, the display panel 10b may include a first etch resist layer ES1, a second etch resist layer ES2, a sealant 310, pillars 320, a pattern layer 400, a color filter layer 500, a black matrix 600, a second substrate 700, a lower polarizing layer DPOL and an upper polarizing layer UPOL, a protective layer 800, and a coating layer 900.

[0288] The second connection line LL2 arranged on the display panel 10b may include a first portion LL2a and a second portion LL2b electrically connected through a third contact hole CH3. The second portion LL2b may be electrically connected to the inner lower pad layer PAD1Da of the first lower pad layer PAD1D of the first pad PAD1. Here, the third contact hole CH3 may be a contact hole that penetrates the gate insulating layer 220, the first interlayer dielectric layer 230, the first etch resist layer ES1, and the second interlayer dielectric layer 260.

[0289] The third connection line LL3 arranged on the display panel 10b may include a third portion LL3a and a fourth portion LL3b electrically connected through a fourth contact hole CH4. The fourth portion LL3b may be electrically connected to the outer lower pad layer PAD1Db of the first lower pad layer PAD1D of the first pad PAD1. Here, the fourth contact hole CH4 may be a contact hole that penetrates the gate insulating layer 220, the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260.

[0290] The fourth connection line LL4 arranged in the display panel 10b may include a fifth portion LL4a and a sixth portion LL4b electrically connected through a seventh contact hole CH7. The sixth portion LL4b may be electrically connected to the second intermediate pad layer PAD2M of the second pad PAD2. Here, the seventh contact hole CH7 may be a contact hole that penetrates the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260.

[0291] Therefore, the connecting line LL of the display panel 10b according to the third embodiment can have a shorter length in the plane than the connecting line LL of the display panel 10 according to the first embodiment, but can have a longer length in the cross-section than the connecting line LL of the display panel 10 according to the first embodiment. Thus, the length of the connecting line LL of the display panel 10b according to the third embodiment and the length of the connecting line LL of the display panel 10 according to the first embodiment can be substantially the same, but it is not necessarily limited to this. For example, the lengths of the connecting line LL of the display panel 10b according to the third embodiment and the connecting line LL of the display panel 10 according to the first embodiment can be slightly different, but the resistance of the connecting line LL can be adjusted by the combination of materials used in the connecting line LL.

[0292] Figure 13 This is a view showing one embodiment of the connecting lines arranged in a display panel according to an embodiment of this specification. Figure 14 yes Figure 13 A magnified view of region E in the image. Figure 13 and Figure 14 The diagram may be a fourth embodiment illustrating the connection relationship between the first pad PAD1, the second pad PAD2, and the connecting line LL arranged in a display panel according to an embodiment of this specification, but is not limited thereto. For example, the connecting lines of the first embodiment showing the connection relationship between the first pad PAD1, the second pad PAD2, and the connecting line LL (see...) Figure 3 as well as Figure 4A and Figure 4B The connecting line in the second embodiment (see Figure 9 and Figure 10 ), the connecting line of the third embodiment (see Figure 11 and Figure 12 The connection line between the fourth embodiment and the fourth embodiment (see) Figure 13 and Figure 14 All of these can be arranged on a single display panel. Here, Figure 13 This could be a schematic diagram showing a connecting line arranged at a second distance D2 based on line I-I'. Furthermore, the second distance D2 can be greater than the first distance D1.

[0293] exist Figure 13 and Figure 14 In the display panel 10c shown, the second portion LL2b of the second connecting line LL2 can be located on the substrate 100. Furthermore, the fourth portion LL3b of the third connecting line LL3 and the sixth portion LL4b of the fourth connecting line LL4 can be located on the gate insulating layer 220.

[0294] In description Figure 13 and Figure 14When referring to the display panel 10c shown, the same reference numerals can be used to indicate the substantially the same components as the display panel 10 according to the first embodiment and the display panel 10b according to the third embodiment, thereby allowing for the omission or simplification of its detailed description.

[0295] Now refer to Figure 13 and Figure 14 The display panel 10c includes: a substrate 100, which includes a first region 110, a second region 120, and a third region 130 spaced apart from each other by a first groove G1 and a second groove G2; a circuit layer 200 disposed on the substrate 100; a liquid crystal layer 300 disposed on the circuit layer 200; a first pad PAD1 disposed on the second region 120; a second pad PAD2 disposed on the third region 130; and multiple connecting lines LL and multiple curved lines BL. Furthermore, the display panel 10c may include a first etch resist layer ES1, a second etch resist layer ES2, a sealant 310, pillars 320, a pattern layer 400, a color filter layer 500, a black matrix 600, a second substrate 700, a lower polarizing layer DPOL and an upper polarizing layer UPOL, a protective layer 800, and a coating layer 900.

[0296] The second connection line LL2 arranged in the display panel 10c may include a first portion LL2a and a second portion LL2b electrically connected through a third contact hole CH3. The second portion LL2b may be electrically connected to the inner lower pad layer PAD1Da of the first lower pad layer PAD1D of the first pad PAD1. Here, the third contact hole CH3 may be a contact hole that penetrates the gate insulating layer 220, the first interlayer dielectric layer 230, the first etch resist layer ES1, and the second interlayer dielectric layer 260.

[0297] The third connection line LL3 arranged in the display panel 10c may include a third portion LL3a and a fourth portion LL3b electrically connected through a fourth contact hole CH4. The fourth portion LL3b may be electrically connected to the outer lower pad layer PAD1Db of the first lower pad layer PAD1D of the first pad PAD1. Here, the fourth contact hole CH4 may be a contact hole that penetrates the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260.

[0298] The fourth connection line LL4 arranged in the display panel 10c may include a fifth portion LL4a and a sixth portion LL4b electrically connected through a seventh contact hole CH7. The sixth portion LL4b may be electrically connected to the second intermediate pad layer PAD2M of the second pad PAD2. Here, the seventh contact hole CH7 may be a contact hole that penetrates the first interlayer dielectric layer 230, the second etch resist layer ES2, and the second interlayer dielectric layer 260.

[0299] Therefore, the connecting line LL of the display panel 10c according to the fourth embodiment may have a shorter length in the plane than the connecting line LL of the display panel 10 according to the first embodiment, but a longer length in the cross-section than the connecting line LL of the display panel 10 according to the first embodiment. In this case, the connecting line LL of the display panel 10c according to the fourth embodiment may have a longer length in the plane than the connecting line LL of the display panel 10b according to the third embodiment, but a shorter length in the cross-section than the connecting line LL of the display panel 10b according to the third embodiment. Therefore, the length of the connecting line LL of the display panel 10c according to the fourth embodiment may be substantially the same as the length of the connecting line LL of the display panel 10 according to the first embodiment or the length of the connecting line LL of the display panel 10b according to the third embodiment, but is not necessarily limited to this.

[0300] The length of the connecting line LL of the display panel 10b according to the third embodiment may be slightly different from the length of the connecting line LL of the display panel 10 according to the first embodiment and / or the length of the connecting line LL of the display panel 10c according to the fourth embodiment. In this case, by adjusting the material applied to each portion of the connecting line LL of the display panel 10b according to the third embodiment, the resistance difference of each of the multiple connecting lines LL can be minimized.

[0301] The display device according to the embodiments of this specification can reduce or minimize the resistance difference of each of the multiple connection lines LL by combining the arrangement position and material of the second part LL2b, the arrangement position and material of the fourth part LL3b, and the arrangement position and material of the sixth part LL4b. For example, the resistance of the connection line LL connected to the center side of the first pad PAD1 and the resistance of the connection lines LL arranged spaced apart from the center side of the first pad PAD1 can be adjusted by the above combination. For example, the second part LL2b, the fourth part LL3b, and the sixth part LL4b can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys, so that the resistance of each of the second part LL2b, the fourth part LL3b, and the sixth part LL4b can be adjusted by the material.

[0302] because Figure 2 , Figure 3 and Figures 9 to 14The arrangement of the connecting lines shown represents one embodiment of the arrangement of the connecting lines. Therefore, the display device according to the embodiments of this specification is not limited to the arrangement of the connecting lines shown in the accompanying drawings. For example, by combining the arrangement position and material of the second part LL2b, the arrangement position and material of the fourth part LL3b, and the arrangement position and material of the sixth part LL4b, the display device according to the embodiments of this specification can realize various embodiments of the connecting lines LL other than those shown in the accompanying drawings.

[0303] The display device according to one or more embodiments of this specification can be described as follows.

[0304] A display device according to one or more embodiments of this specification may include: a substrate including a first region, a second region, and a third region spaced apart from each other by a first recess and a second recess; a circuit layer disposed on the first region and including transistors; a first pad disposed on the second region; a second pad disposed on the third region; and a plurality of connecting lines and a plurality of bent lines connecting the circuit layer, the first pad, and the second pad. A chip may be disposed on the first pad.

[0305] The display device according to one or more embodiments of this specification may further include a liquid crystal layer disposed on a circuit layer.

[0306] The display device according to one or more embodiments of this specification may further include a first etch-resistant layer and a second etch-resistant layer, the first etch-resistant layer being disposed above a first groove and the second etch-resistant layer being disposed above a second groove.

[0307] According to one or more embodiments of this specification, the circuit layer may include a planarization layer extending from a first region to a second region. A portion of the planarization layer may be configured as a first etch-resistant layer. The planarization layer may include an organic material.

[0308] According to one or more embodiments of this specification, the plurality of curved lines may include a first curved line and a second curved line. The first curved line may be disposed on a first etch-resistant layer disposed above a first groove, and the second curved line may be disposed on a second etch-resistant layer disposed above a second groove.

[0309] The display device according to one or more embodiments of this specification may further include: a first pattern layer disposed on a first curved line to overlap with a first groove; and a second pattern layer disposed on a second curved line to overlap with a second groove.

[0310] The display device according to one or more embodiments of this specification may further include: a first protective layer disposed on a first pattern layer; and a second protective layer disposed on a second pattern layer.

[0311] The display device according to one or more embodiments of this specification may further include: a first coating disposed in a first groove; and a second coating disposed in a second groove.

[0312] According to one or more embodiments of this specification, a plurality of connection lines may include: a first connection line connecting a circuit layer and a first bend line; a second connection line connecting the first bend line and a first pad; a third connection line connecting the first pad and a second bend line; and a fourth connection line connecting the second bend line and the second pad.

[0313] According to one or more embodiments of this specification, the first pad may include a first lower pad layer disposed in the second region, a first intermediate pad layer disposed on the first lower pad layer, and a first upper pad layer disposed on the first intermediate pad layer. The second connection line may be connected to either the first lower pad layer or the first intermediate pad layer.

[0314] According to one or more embodiments of this specification, the second connection line may include a first portion and a second portion connected to the first portion. The second portion may be connected to either a first lower pad layer or a first intermediate pad layer.

[0315] According to one or more embodiments of this specification, the first pad may include a first lower pad layer disposed in the second region, a first intermediate pad layer disposed on the first lower pad layer, and a first upper pad layer disposed on the first intermediate pad layer. A third connection line may be connected to either the first lower pad layer or the first intermediate pad layer.

[0316] According to one or more embodiments of this specification, the third connection line may include a third portion and a fourth portion connected to the third portion. The fourth portion may be connected to either the first lower pad layer or the first intermediate pad layer.

[0317] According to one or more embodiments of this specification, the second pad may include a second lower pad layer disposed in the third region, a second intermediate pad layer disposed on the second lower pad layer, and a second upper pad layer disposed on the second intermediate pad layer. The fourth connection line may be connected to either the second lower pad layer or the second intermediate pad layer.

[0318] According to one or more embodiments of this specification, the fourth connection line may include a fifth portion and a sixth portion connected to the fifth portion. The sixth portion may be connected to either the second lower pad layer or the second intermediate pad layer.

[0319] According to one or more embodiments of this specification, the first pad may include a first lower pad layer disposed in the second region, a first intermediate pad layer disposed on the first lower pad layer, and a first upper pad layer disposed on the first intermediate pad layer. The first lower pad layer, the first intermediate pad layer, and the first upper pad layer may be made of different materials.

[0320] According to one or more embodiments of this specification, the second pad may include a second lower pad layer disposed in the third region, a second intermediate pad layer disposed on the second lower pad layer, and a second upper pad layer disposed on the second intermediate pad layer. The second lower pad layer, the second intermediate pad layer, and the second upper pad layer may be made of different materials.

[0321] According to one or more embodiments of this specification, the curved line may include a first layer and a second layer, wherein the first layer and the second layer may be made of different materials.

[0322] According to one or more embodiments of this specification, some areas of the connecting line may be arranged on a curved line.

[0323] According to one or more embodiments of this specification, the first side surface of the first region, the second and third side surfaces of the second region, and the fourth side surface of the third region may be inclined surfaces with a predetermined angle.

[0324] According to one or more embodiments of this specification, the first substrate and the second substrate may include glass material.

[0325] According to one or more embodiments of this specification, the circuit layer may include a planarization layer and a first electrode disposed on the planarization layer, the curved line may include a first layer and a second layer, and at least one of the first layer and the second layer may include the same metal layer as the first electrode.

[0326] The display device according to one or more embodiments of this specification may further include: a liquid crystal layer disposed on a circuit layer; a backlight unit and a housing, the backlight unit emitting light toward the liquid crystal layer and the housing surrounding the backlight unit; and a heat-conducting member disposed between a second region and the housing, wherein the housing may include a metallic material.

[0327] According to one or more embodiments of this specification, a plurality of curved lines may include a first curved line and a second curved line, wherein the center of curvature of the first curved line and the center of curvature of the second curved line may be different.

[0328] A display device according to one or more embodiments of this specification may include: a display area and a non-display area, wherein an image is implemented in the display area, and the non-display area surrounds at least a portion of the display area. The non-display area may include a first non-display area, a curved area including a groove, and a second non-display area. In the curved area, a first pad may be disposed, and a chip is disposed on the first pad. In the second non-display area, which overlaps with the first non-display area through the curvature of the curved area, a second pad may be disposed, and a circuit board is connected to the second pad.

[0329] A display device according to one or more embodiments of this specification may include: a display area and a non-display area, an image being implemented in the display area, and a non-display area surrounding at least a portion of the display area, wherein the non-display area includes a first non-display area, a curved area including two recesses, and a second non-display area, wherein a first pad is disposed between the two recesses and a chip is disposed in the first pad, and wherein a second pad is disposed in a second non-display area that overlaps with the first non-display area through the curvature of the curved area, and the second pad is connected to a circuit board.

[0330] The display device according to one or more embodiments of this specification may further include: an etch-resistant layer disposed above a groove; a curved line disposed on the etch-resistant layer; a pattern layer disposed on the curved line; and a protective layer disposed on the pattern layer, wherein a portion of the protective layer may be disposed inside the groove recessed in the etch-resistant layer.

[0331] The objectives to be achieved by this disclosure, the means to achieve those objectives, and the effects of this disclosure do not specify the essential features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0332] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

[0333] Cross-references to related applications

[0334] This application claims priority and benefit to Korean Patent Application No. 10-2024-0196513, filed in Korea on December 26, 2024, the entire disclosure of which is expressly incorporated herein by reference, as is set forth herein.

Claims

1. A display device, the display device comprising: A substrate, the substrate comprising a first region, a second region and a third region spaced apart from each other by a first groove and a second groove; A circuit layer disposed in the first region, wherein the circuit layer includes transistors; A first pad is disposed in the second region; A second pad is disposed in the third region; and Multiple connecting lines and multiple curved lines connect the circuit layer, the first pad, and the second pad. The chip is placed on the first pad.

2. The display device according to claim 1, further comprising: A first etch-resistant layer and a second etch-resistant layer, wherein the first etch-resistant layer is disposed above the first groove and the second etch-resistant layer is disposed above the second groove.

3. The display device according to claim 2, wherein, The circuit layer includes a planarization layer extending from the first region to the second region, and A portion of the planarization layer is configured as the first etch-resistant layer.

4. The display device according to claim 1, wherein, The multiple curved lines include a first curved line and a second curved line. The first curved line is disposed on the first etch-resistant layer, which is disposed above the first groove, and The second curved line is disposed on the second anti-etching layer, which is disposed above the second groove.

5. The display device according to claim 4, further comprising: A first pattern layer and a second pattern layer, wherein the first pattern layer is arranged on the first curved line to overlap with the first groove, and the second pattern layer is arranged on the second curved line to overlap with the second groove.

6. The display device according to claim 5, further comprising: A first protective layer and a second protective layer, wherein the first protective layer is disposed on the first pattern layer and the second protective layer is disposed on the second pattern layer.

7. The display device according to claim 6, further comprising: A first coating and a second coating, wherein the first coating is disposed in the first groove and the second coating is disposed in the second groove.

8. The display device according to claim 4, wherein, The multiple connecting lines include: A first connecting line connects the circuit layer and the first bent line; The second connecting line connects the first curved line and the first pad; A third connecting line, the third connecting line connecting the first pad and the second curved line; and A fourth connecting line connects the second curved line and the second pad.

9. The display device according to claim 8, wherein, The first pad includes a first lower pad layer disposed in the second region, a first intermediate pad layer disposed on the first lower pad layer, and a first upper pad layer disposed on the first intermediate pad layer. The second connection line is connected to either the first lower pad layer or the first intermediate pad layer.

10. The display device according to claim 9, wherein, The second connecting line includes a first portion and a second portion connected to the first portion, and The second part is connected to either the first lower pad layer or the first intermediate pad layer.

11. The display device according to claim 8, wherein, The first pad includes a first lower pad layer disposed in the second region, a first intermediate pad layer disposed on the first lower pad layer, and a first upper pad layer disposed on the first intermediate pad layer. The third connection line is connected to either the first lower pad layer or the first intermediate pad layer.

12. The display device according to claim 11, wherein, The third connecting line includes a third portion and a fourth portion connected to the third portion, and The fourth part is connected to either the first lower pad layer or the first intermediate pad layer.

13. The display device according to claim 8, wherein, The second pad includes a second lower pad layer disposed in the third region, a second intermediate pad layer disposed on the second lower pad layer, and a second upper pad layer disposed on the second intermediate pad layer. The fourth connection line is connected to either the second lower pad layer or the second intermediate pad layer.

14. The display device according to claim 13, wherein, The fourth connecting line includes a fifth portion and a sixth portion connected to the fifth portion, and The sixth part is connected to either the second lower pad layer or the second intermediate pad layer.

15. The display device according to claim 1, wherein, The first pad includes a first lower pad layer disposed in the second region, a first intermediate pad layer disposed on the first lower pad layer, and a first upper pad layer disposed on the first intermediate pad layer. The first lower pad layer, the first intermediate pad layer, and the first upper pad layer are made of different materials.

16. The display device according to claim 1, wherein, The second pad includes a second lower pad layer disposed in the third region, a second intermediate pad layer disposed on the second lower pad layer, and a second upper pad layer disposed on the second intermediate pad layer. The second lower pad layer, the second middle pad layer, and the second upper pad layer are made of different materials.

17. The display device according to claim 1, wherein, The curved line includes a first layer and a second layer, and The first layer and the second layer are made of different materials.

18. The display device according to claim 1, wherein, The circuit layer includes a planarization layer and a first electrode disposed on the planarization layer. The curved line includes a first layer and a second layer, and At least one of the first layer and the second layer includes the same metal layer as the first electrode.

19. The display device according to claim 1, further comprising: A liquid crystal layer, wherein the liquid crystal layer is disposed on the circuit layer, A backlight unit and a housing, the backlight unit being configured to emit light toward the liquid crystal layer, the housing surrounding the backlight unit, and A heat-conducting component is disposed between the second region and the housing. The housing is made of metal.

20. The display device according to claim 1, wherein, The multiple curved lines include a first curved line and a second curved line, and The center of curvature of the first curved line is different from the center of curvature of the second curved line.

21. A display device, the display device comprising: A display area and a non-display area, wherein an image is implemented in the display area, and the non-display area surrounds at least a portion of the display area. The non-display area includes a first non-display area, a curved area including a groove, and a second non-display area. A first pad, in which a chip is disposed, and wherein the first pad is disposed in the curved region, and The second pad is connected to the circuit board, wherein the second pad is arranged in the second non-display area that overlaps with the first non-display area.

22. The display device according to claim 21, further comprising: An etch-resistant layer is disposed above the groove; A curved line, the curved line being arranged on the etch-resistant layer; A patterned layer, the patterned layer being arranged along the curved line; as well as A protective layer is disposed on the pattern layer. A portion of the protective layer is disposed inside the groove, which is recessed into the etch-resistant layer.

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