A dedicated protocol conversion device for vme bus and embedded system management circuit

Abstract

This invention discloses a dedicated protocol conversion device and embedded system management circuit for the VME bus, comprising: a PCIe interface circuit, a protocol conversion core circuit composed of a domestic FPGA chip (JFM7K325T), a VME bus driver circuit composed of an MS8T245TP-I bus transceiver, and a backplane interface circuit. The device completes the hardware conversion from PCIe to VME bus protocol using a single chip through an address decoder, data buffer, control state machine, and interrupt management logic embedded within the FPGA. This invention also integrates an embedded system hardware monitoring circuit, which is fixedly connected to a domestic RTC clock chip, temperature sensor chip, and EEPROM chip via an I2C bus, and uses hardware timers and hardware address generation logic to achieve periodic automatic hardware recording of log data. This invention solves the technical problems of high hardware redundancy, reliance on imported chips, and poor signal integrity in existing VME bus interface solutions, achieving complete independent control from the chip level to the circuit level.

Description

Technical Field

[0001] This invention relates to a VME bus protocol conversion hardware device for a domestically produced main control electronic box, and an embedded system hardware monitoring circuit integrated with the device, belonging to the field of embedded computer hardware technology. Background Technology

[0002] The VME bus, as a high-performance backplane bus, is widely used in military electronic equipment, industrial control, and aerospace fields. Traditional VME bus interface implementations rely on multi-chip cascading solutions using imported dedicated bridge chipsets: the CPU connects to a PCI bridge chip (such as the PCI9056) via a Local Bus, and the PCI bus is then converted to the VME bus protocol via a VME interface chip (such as the CA91C142D). This solution has the following technical drawbacks:

[0003] (1) High hardware redundancy: It requires the configuration of PCI bridge chip, VME interface chip and multiple level conversion and bus driver chips, resulting in a large number of board-level components, complex circuits and large physical space occupation; (2) Significant supply chain risks: Most of the above-mentioned dedicated bridging chips are imported components (such as Broadcom, IDT, etc.), and face risks of production stoppage, unstable supply and technology blockade; (3) Limited signal integrity: Cascading multiple chips results in long interconnection paths between chips and many signal conversion links, which can easily introduce transmission delays and potential fault points; (4) Lack of independent controllability: The functions of dedicated chips are fixed and cannot be flexibly tailored or upgraded according to system integration needs, which is not conducive to the continuation of the product technology life cycle.

[0004] To address the aforementioned issues, there have been attempts in this field to use Field Programmable Gate Arrays (FPGAs) to replace dedicated bridge chips. However, existing solutions still have the following shortcomings: First, FPGAs are only used as a "soft logic" replacement and do not form a definite hardware circuit connection relationship, leading to disputes over the eligibility of patent protection subject matter; second, there is a lack of hardware-level integration with system monitoring functions; and third, there is no hardware design to match the electrical characteristics of the PCIe interface and VME bus of the domestic processor (Loongson 2K1000). Summary of the Invention

[0005] This invention aims to overcome the technical defects of existing VME bus interface implementation schemes, such as high hardware redundancy, reliance on imported dedicated chips, and poor signal integrity. It provides a dedicated protocol conversion hardware device based on domestic FPGA, which realizes the protocol conversion from PCIe bus to VME bus with a fixed circuit connection relationship, and integrates embedded system monitoring functions through hardware architecture.

[0006] To achieve the above objectives, the first technical solution of the present invention discloses a dedicated protocol conversion device for the VME bus, characterized in that it includes: The physical layer is a PCIe interface circuit that conforms to the PCIe 2.0 specification. The PCIe interface circuit is directly connected to the PCIe controller pin of the Loongson 2K1000 processor through differential signal lines. The receiving end and the transmitting end of the PCIe interface circuit are respectively connected to the PCIe_TX and PCIe_RX pins of the Loongson 2K1000 processor through AC coupling capacitors. The protocol conversion core circuit uses a JFM7K325T FPGA chip from Fudan Microelectronics. The PCIe hard core IP pins of the FPGA chip are directly connected to the output of the PCIe interface circuit via dedicated differential traces, forming a fixed electrical path. The internal logic gate circuits of the FPGA chip are configured in a fixed connection state, constituting: The address decoder has its input connected to the PCIe configuration space register set and its output mapped to the VME address bus. The data buffer has bidirectional data ports that are connected to the PCIe data channel and the VME data channel, respectively. The control state machine has its clock input connected to an onboard 50MHz temperature-compensated crystal oscillator and its output connected to the VME bus control signal line. The VME bus driver circuit has its input terminal fixedly connected to the VME bus signal output terminal of the protocol conversion core circuit via PCB board-level traces. It adopts the Jiangsu Manwang MS8T245TP-I type 8-channel bus transceiver. The A terminal of the MS8T245TP-I type 8-channel bus transceiver is connected to the 3.3V IO BANK pin of the protocol conversion core circuit, and the B terminal is connected to the 5V level domain of the backplane VME bus, forming a fixed level conversion path. The VME backplane connector includes 32 address lines, 32 data lines, interrupt lines, clock lines, DTACK acknowledge lines, AS address strobe lines, and DS data strobe lines. All signal lines are led out through the VME bus driver circuit to a European connector conforming to the VME64 standard.

[0007] Preferably, the protocol conversion core circuit also integrates an interrupt management logic circuit, wherein the interrupt request input terminal of the interrupt management logic circuit is connected to the VME bus interrupt line and the interrupt output terminal is connected to the PCIe interrupt pin of the Loongson 2K1000 processor.

[0008] Preferably, the interrupt management logic circuit is fixedly implemented inside the FPGA chip through register transfer level (RTL) connections.

[0009] Preferably, the dedicated protocol conversion device further includes an embedded system hardware monitoring circuit, which is fixedly connected to the general purpose input / output (GPIO) pins of the protocol conversion core circuit via an I2C bus physical interface.

[0010] Preferably, the embedded system hardware monitoring circuit includes: an INS5902B domestic RTC clock chip, whose I2C data line SDA is fixedly connected to the first GPIO pin (GPIO[0]) of the protocol conversion core circuit through a pull-up resistor, and whose clock line SCL is fixedly connected to the second GPIO pin (GPIO[1]); a CT75 domestic temperature sensor chip, whose I2C data line SDA is fixedly connected to the third GPIO pin (GPIO[2]) of the protocol conversion core circuit, and whose clock line SCL is fixedly connected to the fourth GPIO pin (GPIO[3]); and an AT24C64 EEPROM chip, whose I2C data line SDA is fixedly connected to the fifth GPIO pin (GPIO[4]) of the protocol conversion core circuit, and whose clock line SCL is fixedly connected to the sixth GPIO pin (GPIO[5]).

[0011] Preferably, the protocol conversion device further includes a log storage hardware interface circuit, which includes a NAND Flash controller physical layer. Its data line is fixedly connected to the dedicated storage interface pin of the protocol conversion core circuit through a series termination resistor, and its address line is fixedly connected to the general-purpose IO pin of the protocol conversion core circuit. The NAND Flash controller physical layer implements a direct memory access (DMA) path with the internal DDR controller of the Loongson 2K1000 processor through hardware logic.

[0012] Preferably, the embedded system hardware monitoring circuit further includes: a hardware timer configured to generate periodic trigger pulses, the pulse signals triggering the I2C bus controller physical layer to start bus transactions via hardwired connections; the I2C bus controller physical layer configured to read time data from the RTC chip according to a preset timing sequence of the hardware state machine, and store it in parallel into the FPGA internal register group; the I2C bus controller physical layer configured to read temperature digital values ​​from the temperature sensor chip according to a preset timing sequence of the hardware state machine, convert them into floating-point format by the hardware logic unit, and store them in the data register; the time data and temperature data in the FPGA internal register group are written to the write buffer of the NAND Flash controller through the PCIe bus direct memory access engine; the NAND Flash controller physical layer is configured to automatically calculate the file system directory offset based on the year, month, and day information in the time data using hardware address generation logic, and write the temperature data and system status word to the corresponding physical page address.

[0013] The second technical solution of the present invention discloses an embedded system hardware monitoring method based on the above-mentioned dedicated protocol conversion device, characterized by comprising the following hardware execution steps: Step A: The hardware timer generates periodic trigger pulses, and the pulse signals trigger the I2C bus controller physical layer to start bus transactions through the hardwired internal wiring of the FPGA chip; Step B: The physical layer of the I2C bus controller sends a read command to the second register address of the RTC chip according to the timing preset by the hardware state machine, and reads the BCD format time data bit by bit from the data line and stores it in parallel into the pre-allocated register group inside the FPGA chip. Step C: The physical layer of the I2C bus controller sends a read command to the temperature register address of the temperature sensor chip according to the timing preset by the hardware state machine, reads the 16-bit temperature digital value, converts it into a single-precision floating-point number format conforming to the IEEE 754 standard by the hardware logic unit, and stores it in the data register. Step D: The time and temperature data in the FPGA's internal register group are written to the write buffer of the NAND Flash controller via the PCIe bus direct memory access hardware logic. Step E: The physical layer of the NAND Flash controller automatically calculates the file system directory offset based on the year, month, and day information in the time data using the hardware address generation logic, and writes the temperature data and system status word as a log record to the corresponding physical page address.

[0014] Preferably, the specific circuit connection relationship of the hardware address generation logic in step E is as follows: the 8-bit binary number of the year register output by the RTC chip is added to the reference year constant 2020 by the adder circuit to form the high-order address, and the month and date register values ​​are concatenated by combinational logic to form the low-order address. This address bus is directly connected to the column address latch input terminal of the NAND Flash controller.

[0015] The third technical solution of the present invention discloses an embedded system management circuit including the above-mentioned dedicated protocol conversion device. The embedded system management circuit's printed circuit board (PCB) integrates the following fixed electrical connections between chips: the PCIe controller pin of the Loongson 2K1000 processor is connected to the PCIe hard core pin of the JFM7K325T FPGA chip via differential traces; the VME bus output pin of the JFM7K325T FPGA chip is connected to the VME backplane connector via the MS8T245TP-I 8-channel bus transceiver; the I2C bus pins of the INS5902B RTC clock chip, the CT75 temperature sensor chip, and the AT24C64 EEPROM chip are connected to the GPIO pins of the JFM7K325T FPGA chip via pull-up resistors; all connections are fixed by PCB layout and routing, forming an unchangeable hardware topology.

[0016] Preferably, the PCB board adopts a ten-layer stacked structure, wherein the third layer is a complete ground plane, the fifth layer is a VME bus signal layer, the length error of differential signal lines is controlled within ±5mil, and the length error of address lines and data lines within the same group is controlled within ±10mil.

[0017] Compared with existing technical solutions, the present invention has the following beneficial effects: 1. Substantial simplification of hardware structure: This invention replaces the multi-chip combination architecture of PCI bridge chip, VME interface chip and multiple level conversion devices in the original solution with a single FPGA chip, reducing the number of board-level components by about 60%, reducing the PCB layout area by 35%, and significantly reducing the cost of component procurement and manufacturing. 2. Significantly Improved Signal Integrity: This invention replaces the long PCB traces between chips in the original solution with FPGA internal hard-wired logic, shortening the critical signal path by more than 80%. Actual measurements show a 42% improvement in VME bus read / write timing margin and a reduction in transmission error rate to 10%. -12 the following; 3. Enhanced self-control capability: All core chips (processor, FPGA, bus transceiver, RTC, temperature sensor, EEPROM) of this invention are domestically produced components, and the logic function of the FPGA is solidified by physical circuit connection, without relying on third-party intellectual property cores, achieving complete self-control from chip level to circuit level. 4. Breakthrough in functional integration: This invention integrates the VME protocol conversion function with the embedded system hardware monitoring function at the physical layer. It can simultaneously complete bus protocol conversion, timing generation, interrupt management and I2C bus control through the same FPGA chip, avoiding the hardware overhead of additional configuration of independent microcontrollers or monitoring chips in traditional solutions. 5. Enhanced Timing Determinism: This invention uses a hardware state machine to implement the log recording process. All operations are directly executed by the hardware circuit, eliminating operating system scheduling delays or software interrupt response uncertainties. Through theoretical analysis and calculation, the complete cycle from the temperature sensor reading request to the data being written to the NAND Flash is in the microsecond range, which is tens of times faster than the software implementation scheme, which is in the hundreds of microsecond range. 6. Improved anti-interference and reliability: The VME bus driver circuit of this invention adopts the domestic MS8T245TP-I bus transceiver. Its input terminal and FPGA IO BANK are connected by a series damping resistor and a parallel clamping diode to form a hardware protection network. It has been tested and can withstand ±8kV contact discharge and ±15kV air discharge, meeting the electromagnetic compatibility requirements of GJB151B Army ground equipment. Attached Figure Description

[0018] Figure 1 This is a circuit connection topology diagram of the dedicated protocol conversion hardware device of the present invention; Figure 2 This is a block diagram of the internal functional modules of the JFM7K325T. Figure 3 This is a diagram showing the physical connection of the I2C bus in the hardware monitoring circuit. Figure 4 A flowchart of the logic for generating hardware addresses; Figure 5 This is a hardware topology diagram of the main control computer module. Detailed Implementation

[0019] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0020] Example 1: Hardware execution process of VME bus read operation Reference Figure 1The circuit connection relationship of the dedicated protocol conversion hardware device of the present invention is as follows: the PCIe controller pin of the Loongson 2K1000 processor 1 is directly connected to the PCIe hard core IP input pin of the JFM7K325T FPGA chip 2 through the PCIe x4 differential signal line; the VME bus signal output pin of the FPGA (including 32-bit address lines, 32-bit data lines and control signal lines) is connected to the 3.3V level side A terminal of the MS8T245TP-I 8-channel bus transceiver 3; the 5V level side B terminal of the MS8T245TP-I 8-channel bus transceiver 3 is connected to the backplane connector 4 conforming to the VME64 specification, forming a complete signal link.

[0021] Reference Figure 2 The FPGA2, model JFM7K325T, integrates a PCIe hard core IP5, an address decoder 6, a data buffer FIFO 7, a VME bus controller state machine 8, an interrupt management logic 9, an I2C bus controller 10, a hardware timer 11, a hardware address generation logic 12, and a NAND Flash controller 13. These modules are fixedly connected through internal hardwires, forming the hardware core for protocol conversion and system monitoring.

[0022] When the Loongson 2K1000 processor 1 initiates a 16-bit data read operation on the VME bus, the hardware circuit executes according to the following fixed path: (1) The PCIe controller of Loongson 2K1000 processor 1 issues a memory read transaction, and the transaction layer data packet is transmitted to the PCIe hard core IP5 of the FPGA via the PCIe differential line; (2) The PCIe hard core IP5 sends the address phase information to the address decoder 6. The hard-wired logic of the address decoder 6 captures the 32-bit address and outputs the lower 16 bits to the address bus pin through a dedicated register. At the same time, the hard-wired logic of the VME bus controller state machine 8 automatically sets the VME_AS and VME_DS signals and sends a wait detection signal to the VME_DTACK signal line. (3) When the slave device connected to the backplane pulls the VME_DTACK signal low, the 16-bit data on the data bus is converted by the MS8T245TP-I bus transceiver 3 level and then latched by the FPGA internal data buffer FIFO7. (4) The data in the data buffer FIFO7 is encapsulated into a complete data packet through the PCIe hard core IP5 and returned to the Loongson 2K1000 processor along the original path.

[0023] In a VME bus system, a slave device may request services from a master device via an interrupt. When a VME slave device on the backplane generates an interrupt request, the request signal is transmitted to FPGA2 via the VME interrupt line, where it is captured and parsed by interrupt management logic 9. Interrupt management logic 9 submits the interrupt request to Loongson 2K1000 processor 1 via PCIe hard core IP5 based on the interrupt priority and configuration information. After responding to the interrupt, Loongson 2K1000 processor 1 can read the interrupt status register through the standard PCIe interrupt handling procedure and then execute the corresponding service routine. In the synchronous read operation of this embodiment, interrupt management logic 9 is in a standby state and does not participate in data transmission, but as a fixed hardware module inside the FPGA, it provides asynchronous event processing capabilities for the system.

[0024] Example 2: Physical Implementation and Automatic Recording Process of Hardware Log Recording Circuit Reference Figure 3 The physical connection relationship of the I2C bus of the embedded system hardware monitoring circuit is as follows: GPIO[0] pin 14 of JFM7K325TFPGA2 is connected to the SDA pin of INS5902B RTC chip 20 through a pull-up resistor; GPIO[1] pin 15 is connected to the SCL pin of INS5902B RTC chip 20 through a pull-up resistor; GPIO[2] pin 16 is connected to the SDA pin of CT75 temperature sensor chip 21 through a pull-up resistor; GPIO[3] pin 17 is connected to the SCL pin of CT75 temperature sensor chip 21 through a pull-up resistor; GPIO[4] pin 18 is connected to the SDA pin of AT24C64 EEPROM chip 22 through a pull-up resistor; GPIO[5] pin 19 is connected to the SCL pin of AT24C64 EEPROM chip 22 through a pull-up resistor. All pull-up resistors are connected to a 3.3V power supply, forming a standard I2C bus hardware topology.

[0025] Reference Figure 2 The FPGA2 integrates a hardware timer 11, an I2C bus controller 10, hardware address generation logic 12, and a NAND Flash controller 13. The hardware timer 11 is composed of a 50MHz temperature-compensated crystal oscillator connected to a 16-bit counter via a frequency divider. The counter overflow bit is connected to the start trigger input of the I2C bus controller 10.

[0026] Reference Figure 4The hardware address generation logic includes hardware circuit modules such as year register 23, month register 24, date register 25, base year constant 2020 26, subtractor 27, block address generation 28, page address generation 29, page offset generation 30, address concatenation logic 31, physical address output 32, column address latch 33, and row address latch 34. These modules are connected via a fixed data bus. Its workflow is as follows: (1) Hardware timer 11 generates an overflow pulse every 3 minutes. This pulse is hardwired to trigger the I2C bus controller physical layer to start a bus transaction. (2) The physical layer of the I2C bus controller reads 7 bytes of time data (year, month, day, week, hour, minute, second) sequentially from the second register address (0x00) of the INS5902B RTC chip through the I2C bus according to the timing preset by the hardware state machine, and stores them in parallel into the internal register group of FPGA2. (3) The I2C bus controller physical layer continues to send a read command to the temperature register address (0x00) of the CT75 temperature sensor chip 21, reads 2 bytes of temperature digital value, and the hardware logic unit converts it into a single-precision floating-point number format conforming to the IEEE 754 standard and stores it in the temperature data register. (4) The 8-bit subtractor 27 in the hardware address generation logic subtracts the base year constant 2020 26 from the value of the year register 23 to obtain the 8-bit block address 28; the 4-bit value of the month register 24 is directly used as the page address 29; the 5-bit value of the date register 25 is directly used as the page offset 30; the address concatenation logic 31 combines the three into a 17-bit physical address, in the format {block address [7:0], page address [3:0], offset [4:0]}; (5) The physical address is sent to the column address latch 33 and row address latch 34 of the NAND Flash controller 13 via hardwire 32; at the same time, the time data, temperature data and system status word (32 bytes in total) are written to the write buffer of the NAND Flash controller 13 through the DMA engine. (6) The physical layer of the NAND Flash controller 13 writes 32 bytes of log data to the storage unit corresponding to the above physical address according to the ONFI 4.0 standard timing.

[0027] The entire logging process is completed independently by the hardware circuitry without processor intervention, and the logging cycle is free of jitter.

[0028] Example 3: Overall Hardware Architecture of the Main Control Computer Module Reference Figure 5 A domestically produced main control computer module including the aforementioned dedicated protocol conversion hardware device has the following hardware topology: The Loongson 2K1000 processor 1 serves as the system's main controller. Its PCIe controller pins are directly connected to the PCIe hard core IP pins of the JFM7K325T FPGA2 via PCIex4 differential signal lines, forming a high-speed data channel between the processor and the protocol conversion core.

[0029] The VME bus signal output pins (including 32-bit address lines, 32-bit data lines, and control signal lines) of the JFM7K325T FPGA2 are connected to the 3.3V level side A terminal of the MS8T245TP-I type 8-channel bus transceiver 3. The 5V level side B terminal of the bus transceiver is connected to the backplane connector 4 conforming to the VME64 specification, realizing electrical interconnection with other VME boards in the chassis.

[0030] GPIO[0:1] pins 14 and 15 of the FPGA are connected to the I2C interface of the INS5902B RTC chip 20 through independent pull-up resistors; GPIO[2:3] pins 16 and 17 are connected to the I2C interface of the CT75 temperature sensor chip 21 through independent pull-up resistors; GPIO[4:5] pins 18 and 19 are connected to the I2C interface of the AT24C64 EEPROM chip 22 through independent pull-up resistors, forming a complete embedded system hardware monitoring network.

[0031] The FPGA's dedicated storage interface pins (data lines, address lines, control lines) are connected to the NAND Flash memory 35 via series termination resistors for automatic storage of hardware logs.

[0032] All the chips mentioned above use domestically produced components, and their electrical connections are fixed by the PCB layout and routing. The PCB board adopts a ten-layer stack-up structure design, where the third layer is a complete ground plane, the fifth layer is the VME bus signal layer, and the length error of all differential signal lines is controlled within ±5mil, while the length error within the address and data line groups is controlled within ±10mil, ensuring signal integrity and timing matching.

[0033] This module is fully compatible with the original imported main control computer module in terms of installation interface, connector definition, and electrical characteristics, allowing for in-situ replacement. Testing has shown that this module operates stably within a temperature range of -40℃ to +85℃, with a 42% improvement in VME bus read / write timing margin compared to the original solution, and overall power consumption reduced from 30W to 16W, achieving the dual goals of performance improvement and independent controllability.

Claims

1. A dedicated protocol conversion device for the VME bus, characterized in that, include: The physical layer is a PCIe interface circuit that conforms to the PCIe 2.0 specification. The PCIe interface circuit is directly connected to the PCIe controller pins of the Loongson 2K1000 processor through differential signal lines. The core circuit for protocol conversion uses a JFM7K325T FPGA chip from Fudan Microelectronics. The PCIe hard core IP pins of the FPGA chip are directly connected to the output of the PCIe interface circuit through dedicated differential traces, forming a fixed electrical path. The FPGA chip is internally configured with an address decoder, a data buffer, and a control state machine with fixed connection states. The output of the address decoder is mapped to the VME address bus. The bidirectional ports of the data buffer are connected to the PCIe data channel and the VME data channel, respectively. The output of the control state machine is connected to the VME bus control signal line. The VME bus driver circuit uses an MS8T245TP-I type 8-channel bus transceiver. The A terminal of the MS8T245TP-I type 8-channel bus transceiver is connected to the 3.3V IO BANK pin of the protocol conversion core circuit, and the B terminal is connected to the 5V level domain of the backplane VME bus. The VME backplane connector includes 32 address lines, 32 data lines, interrupt lines, clock lines, DTACK acknowledge lines, AS address strobe lines, and DS data strobe lines. All signal lines are led out through the VME bus driver circuit to a European connector conforming to the VME64 standard.

2. The dedicated protocol conversion device for VME bus as described in claim 1, characterized in that, The protocol conversion core circuit also integrates an interrupt management logic circuit. The interrupt request input terminal of the interrupt management logic circuit is connected to the VME bus interrupt line, and the interrupt output terminal is connected to the PCIe interrupt pin of the Loongson 2K1000 processor. The interrupt management logic circuit is fixedly implemented inside the FPGA chip through register transfer cascade wiring.

3. The dedicated protocol conversion device for VME bus as described in claim 1, characterized in that, The dedicated protocol conversion device also includes an embedded system hardware monitoring circuit, which is fixedly connected to the general-purpose input / output pins of the protocol conversion core circuit through an I2C bus physical interface.

4. A dedicated protocol conversion device for VME bus as described in claim 3, characterized in that, The embedded system hardware monitoring circuit includes: an INS5902B RTC clock chip, whose I2C data line is fixedly connected to the first GPIO pin of the protocol conversion core circuit via a pull-up resistor, and whose clock line is fixedly connected to the second GPIO pin; a CT75 temperature sensor chip, whose I2C data line is fixedly connected to the third GPIO pin of the protocol conversion core circuit, and whose clock line is fixedly connected to the fourth GPIO pin; and an AT24C64 EEPROM chip, whose I2C data line is fixedly connected to the fifth GPIO pin of the protocol conversion core circuit, and whose clock line is fixedly connected to the sixth GPIO pin.

5. A dedicated protocol conversion device for VME bus as described in claim 4, characterized in that, The protocol conversion device further includes a log storage hardware interface circuit, which includes a NAND Flash controller physical layer. Its data lines are fixedly connected to the dedicated storage interface pins of the protocol conversion core circuit through series termination resistors, and its address lines are fixedly connected to the general-purpose I / O pins of the protocol conversion core circuit.

6. A dedicated protocol conversion device for VME bus as described in claim 5, characterized in that, The embedded system hardware monitoring circuit further includes: a hardware timer configured to generate periodic trigger pulses, the pulse signals triggering the I2C bus controller physical layer to start bus transactions via hardwired connections; the I2C bus controller physical layer configured to read time data from the RTC chip according to the timing preset by the hardware state machine, and store it in parallel into the FPGA internal register group; the I2C bus controller physical layer configured to read temperature digital values ​​from the temperature sensor chip according to the timing preset by the hardware state machine, converting them into floating-point format by the hardware logic unit and storing them in the data register; the time data and temperature data in the FPGA internal register group are written to the write buffer of the NAND Flash controller through the PCIe bus direct memory access engine; the NAND Flash controller physical layer is configured to automatically calculate the file system directory offset based on the year, month, and day information in the time data using hardware address generation logic, and write the temperature data and system status word to the corresponding physical page address.

7. An embedded system hardware monitoring method based on the dedicated protocol conversion device of claim 6, characterized in that, The following hardware execution steps are included: Step A: The hardware timer generates periodic trigger pulses, and the pulse signals trigger the I2C bus controller physical layer to start bus transactions through the hardwired internal wiring of the FPGA chip; Step B: The physical layer of the I2C bus controller sends a read command to the second register address of the RTC chip according to the timing preset by the hardware state machine, and reads the BCD format time data bit by bit from the data line and stores it in parallel into the pre-allocated register group inside the FPGA chip. Step C: The physical layer of the I2C bus controller sends a read command to the temperature register address of the temperature sensor chip according to the timing preset by the hardware state machine, reads the 16-bit temperature digital value, converts it into a single-precision floating-point number format conforming to the IEEE 754 standard by the hardware logic unit, and stores it in the data register. Step D: The time and temperature data in the FPGA's internal register group are written to the write buffer of the NAND Flash controller via the PCIe bus direct memory access hardware logic. Step E: The physical layer of the NAND Flash controller automatically calculates the file system directory offset based on the year, month, and day information in the time data using the hardware address generation logic, and writes the temperature data and system status word as a log record to the corresponding physical page address.

8. The embedded system hardware monitoring method as described in claim 7, characterized in that, The specific circuit connection relationship of the hardware address generation logic in step E is as follows: the 8-bit binary number of the year register output by the RTC chip is added to the reference year constant 2020 by the adder circuit to form the high-order address, and the month and date register values ​​are concatenated by combinational logic to form the low-order address. This address bus is directly connected to the column address latch input terminal of the NAND Flash controller.

9. An embedded system management circuit comprising the dedicated protocol conversion device according to any one of claims 1 to 6, characterized in that, The embedded system management circuit's printed circuit board integrates the following fixed electrical connections between chips: the PCIe controller pin of the Loongson 2K1000 processor is connected to the PCIe hard core pin of the JFM7K325T FPGA chip via differential traces; the VME bus output pin of the JFM7K325T FPGA chip is connected to the VME backplane connector via the MS8T245TP-I 8-channel bus transceiver; the I2C bus pins of the INS5902B RTC clock chip, the CT75 temperature sensor chip, and the AT24C64 EEPROM chip are connected to the GPIO pins of the JFM7K325T FPGA chip via pull-up resistors; all connections are fixed by PCB layout and routing, forming an unchangeable hardware topology.

10. The embedded system management circuit as described in claim 9, characterized in that, The PCB board adopts a ten-layer stacked structure, where the third layer is a complete ground plane, the fifth layer is the VME bus signal layer, the length error of differential signal lines is controlled within ±5mil, and the length error of address lines and data lines within the same group is controlled within ±10mil.

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