An all-digital phase-locked loop and a locking method thereof

Abstract

This invention provides a fully digital phase-locked loop (PLL) and its locking method, comprising: dividing the output frequency of a numerically controlled oscillator (CNC) into N frequency bands through pre-calibration, and obtaining the input control word range corresponding to each frequency band, where N is a natural number greater than 1; setting the input control word of the CNC oscillator according to the locking frequency; inputting a reference signal and a feedback signal to a time-to-digital converter (TD-SCDC); and switching the loop state of the fully digital PLL from open-loop to closed-loop when the value of the phase digital signal output by the TD-SCDC meets a preset condition. By setting the input control word of the CNC oscillator according to the locking frequency, the phase of the feedback signal output by the CNC oscillator is made close to the phase of the reference signal, thereby making the value of the phase digital signal output by the TD-SCDC close to 0, thus enabling the loop state of the fully digital PLL to be quickly switched to closed-loop, solving the problem of how to shorten the locking time of the fully digital PLL.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a fully digital phase-locked loop and its locking method. Background Technology

[0002] All-digital phase-locked loops (ADPLLs) offer advantages over traditional charge-pumped phase-locked loops (CPPLLs) in terms of adaptability to low power supply voltages and smaller filter area, leading to their increasing adoption. Unlike traditional CPPLLs where a phase-frequency detector (PFD) converts the input reference and feedback signals into analog signals, ADPLLs use a time-to-digital converter (TDC) instead of a PFD. The TDC works by converting the phase difference between the input reference and feedback signals into a digital signal, which is then filtered by a subsequent digital filter (DLF).

[0003] However, existing TDCs only have phase detection capabilities and not frequency detection. Therefore, it is generally necessary to pre-calibrate the digitally controlled oscillator (DCO) output frequency into N frequency bands, and pre-set the DCO output frequency at the midpoint of the band containing the desired locked frequency. Then, the phase-locked loop (PLL) is changed from an open-loop to a closed-loop state, causing the DCO to gradually move from the midpoint of the same frequency band towards the vicinity of the locked frequency until it locks. In this process, the phase difference between the DCO output feedback signal and the reference signal at the initial moment is crucial. If the phase difference between the reference and feedback signals is 0 when their frequencies are close, the PLL can lock quickly. If the phase difference reaches a maximum of π, the PLL output frequency will oscillate around the desired locked frequency before finally locking after a long time. That is, the initial phase difference between the reference and feedback signals causes the locking time of the all-digital PLL to be too long. Summary of the Invention

[0004] The purpose of this invention is to provide a fully digital phase-locked loop and its locking method to solve the problem of how to shorten the locking time of the fully digital phase-locked loop.

[0005] To solve the above-mentioned technical problems, the present invention provides a locking method for a fully digital phase-locked loop, comprising: Through pre-calibration, the output frequency of the numerically controlled oscillator is divided into N frequency bands, and the input control word range corresponding to each frequency band is obtained, where N is a natural number greater than 1; Set the input control word of the numerically controlled oscillator according to the locking frequency; The reference signal and feedback signal are input to the time-to-digital converter; When the value of the phase digital signal output by the time-to-digital converter meets the preset conditions, the loop state of the all-digital phase-locked loop is switched from open loop to closed loop.

[0006] Optionally, in the locking method of the all-digital phase-locked loop, the method of dividing the output frequency of the numerically controlled oscillator into N frequency bands through pre-calibration and obtaining the input control word range corresponding to each frequency band includes: Obtain the maximum and minimum values ​​of the output frequency of the numerically controlled oscillator, as well as the range of the input control word; Based on the maximum and minimum values ​​of the output frequency of the numerically controlled oscillator and the number of frequency bands N, the output frequency of the numerically controlled oscillator is divided into N consecutive frequency bands. Based on the number of frequency bands N, the input control word range is divided into N input control word sub-ranges. According to the preset method, the frequency bands are matched one-to-one with the input control word range.

[0007] Optionally, in the locking method of the all-digital phase-locked loop, the method for determining the input control word of the numerically controlled oscillator based on the locking frequency includes: Arrange all frequency bands in order of frequency magnitude to obtain the sequence number of each frequency band; If the frequency band where the locked frequency is located is number k, and k is less than the number threshold, then the input control word of the numerically controlled oscillator is set to the input control word corresponding to the midpoint of the (k+2)th frequency band; otherwise, the input control word of the numerically controlled oscillator is set to the input control word corresponding to the midpoint of the (k-2)th frequency band, where k = 1, 2, ..., N, and the value range of the number threshold is 3 to N-2.

[0008] Optionally, in the locking method of the all-digital phase-locked loop, the method of inputting the reference signal and feedback signal to the time-to-digital converter includes: The reference signal is input to the time-to-digital converter, and the signal output from the numerically controlled oscillator is used as the feedback signal and input to the time-to-digital converter.

[0009] Optionally, in the locking method of the all-digital phase-locked loop, after inputting the reference signal and feedback signal to the time-to-digital converter, the locking method of the all-digital phase-locked loop further includes: If the phase difference between the reference signal and the feedback signal is greater than the first phase difference threshold, the value of the phase digital signal output by the time-to-digital converter reaches its upper or lower limit. If the phase difference between the reference signal and the feedback signal is less than the second phase difference threshold, then the value of the phase digital signal output by the time-to-digital converter is less than the lockout threshold.

[0010] Optionally, in the locking method of the all-digital phase-locked loop, the method of switching the loop state of the all-digital phase-locked loop from open loop to closed loop when the value of the phase digital signal output by the time-to-digital converter meets a preset condition includes: When the value of the phase digital signal output by the time-to-digital converter is less than the locking threshold, the loop state of the all-digital phase-locked loop is switched from open loop to closed loop.

[0011] Optionally, in the locking method of the all-digital phase-locked loop, the method of switching the loop state of the all-digital phase-locked loop from open loop to closed loop when the value of the phase digital signal output by the time-to-digital converter meets the preset condition further includes: When the value of the phase digital signal output by the time-to-digital converter meets the preset conditions, the input control word of the numerically controlled oscillator is switched to the input control word corresponding to the midpoint of the frequency band where the locked frequency is located.

[0012] To address the aforementioned technical problems, the present invention also provides a fully digital phase-locked loop (PLL) for implementing the locking method of the fully digital PLL as described in any of the preceding claims. The fully digital PLL includes a time-to-digital converter (TDD) and a numerically controlled oscillator (NCO). The TDD is used to receive a reference signal and a feedback signal, and generate a phase digital signal based on the reference signal and the feedback signal. The NCO is used to receive the phase digital signal and output a frequency signal.

[0013] Optionally, in the all-digital phase-locked loop, the all-digital phase-locked loop further includes a digital filter, which is used to record the value of the phase digital signal output by the time-to-digital converter in the open-loop state.

[0014] Optionally, in the all-digital phase-locked loop, the all-digital phase-locked loop further includes a frequency divider, which is used to receive frequency signals and output feedback signals.

[0015] The present invention provides a fully digital phase-locked loop and its locking method, comprising: dividing the output frequency of a numerically controlled oscillator into N frequency bands through pre-calibration, and obtaining the input control word range corresponding to each frequency band, where N is a natural number greater than 1; setting the input control word of the numerically controlled oscillator according to the locking frequency; inputting a reference signal and a feedback signal to a time-to-digital converter; and switching the loop state of the fully digital phase-locked loop from open loop to closed loop when the value of the phase digital signal output by the time-to-digital converter meets a preset condition. By setting the input control word of the numerically controlled oscillator according to the locking frequency, the phase of the feedback signal output by the numerically controlled oscillator is made close to the phase of the reference signal, thereby making the value of the phase digital signal output by the time-to-digital converter close to 0, thus enabling the loop state of the fully digital phase-locked loop to be quickly switched to closed loop, solving the problem of how to shorten the locking time of the fully digital phase-locked loop. Attached Figure Description

[0016] Figure 1 A flowchart of the locking method for the all-digital phase-locked loop provided in this embodiment; Figure 2 This is a block diagram of the basic circuit structure of the all-digital phase-locked loop provided in this embodiment; Figure 3 This embodiment provides a basic circuit structure block diagram of an all-digital phase-locked loop with a digital filter. Figure 4 The basic circuit structure block diagram of the all-digital phase-locked loop with a frequency divider is provided for this embodiment. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the all-digital phase-locked loop and its locking method proposed in this invention. It should be noted that the drawings are all in a very simplified form and use non-precise scales, intended only to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0018] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] A digitally controlled oscillator (DCO) operates based on digital frequency synthesis technology. Its core components include a phase accumulator, a waveform memory, and a digital-to-analog converter (DAC). The phase accumulator performs accumulation operations based on the input control word (FCW). Within each clock cycle, the phase accumulator adds the FCW to the current phase value to obtain a new phase value. Simply put, the role of the input control word in the DCO is to control the frequency and phase of its output signal; that is, by changing the value of the input control word, the accumulation step size of the phase accumulator can be adjusted, thereby changing the frequency and phase of the output signal.

[0020] Based on this, this embodiment provides a locking method for a fully digital phase-locked loop, such as... Figure 1 As shown, it includes: S1, through pre-calibration, divide the output frequency of the numerically controlled oscillator into N frequency bands, and obtain the input control word range corresponding to each frequency band, where N is a natural number greater than 1; S2, Set the input control word of the numerically controlled oscillator according to the locking frequency; S3 inputs the reference signal and feedback signal to the time-to-digital converter; S4, when the value of the phase digital signal output by the time-to-digital converter meets the preset conditions, the loop state of the all-digital phase-locked loop is switched from open loop to closed loop.

[0021] The locking method of the all-digital phase-locked loop provided in this embodiment sets the input control word of the numerically controlled oscillator according to the locking frequency, so that the phase of the feedback signal output by the numerically controlled oscillator is close to the phase of the reference signal, thereby making the value of the phase digital signal output by the time-to-digital converter close to 0, and thus enabling the loop state of the all-digital phase-locked loop to be quickly switched to closed loop, solving the problem of how to shorten the locking time of the all-digital phase-locked loop.

[0022] Specifically, in this embodiment, step S1, which involves dividing the output frequency of the numerically controlled oscillator into N frequency bands through pre-calibration and obtaining the input control word range corresponding to each frequency band, includes: S11, obtain the maximum and minimum values ​​of the output frequency of the numerically controlled oscillator, as well as the range of input control words.

[0023] In this embodiment, the maximum value of the output frequency of the numerically controlled oscillator can be denoted as Fh, the minimum value as Fl, and the input control word range can be set to 0~Wn, wherein the input control word and the frequency satisfy the following relationship:

[0024] Where f represents the output frequency of the numerically controlled oscillator, Wi represents the input control word, the value of Wi ranges from 0 to Wn, and F() represents the nonlinear function of the output frequency of the numerically controlled oscillator with respect to the input control word.

[0025] Of course, in practical applications, the maximum value Fh and the minimum value Fl of the output frequency, as well as the range of the input control word, can be set according to actual needs, and this application does not impose any restrictions on this.

[0026] S12, based on the maximum and minimum values ​​of the output frequency of the numerically controlled oscillator and the number of frequency bands N, divide the output frequency of the numerically controlled oscillator into N consecutive frequency bands.

[0027] In this embodiment, the frequency range of each frequency band is (Fh-Fl) / N. For example, if the maximum value Fh of the output frequency of the numerically controlled oscillator is 10GHz and the minimum value Fl is 0, and it is to be divided into 250 frequency bands, i.e., N=250, then the frequency range of each frequency band is 40MHz. That is, the first frequency band covers a frequency of 0~40MHz, the second frequency band covers a frequency of 40~80MHz, ..., the 249th frequency band covers a frequency of 9.92~9.96GHz, and the 250th frequency band covers a frequency of 9.96~10GHz.

[0028] Of course, in practical applications, the value of the number of frequency bands N needs to be reasonably determined based on the maximum and minimum values ​​of the output frequency of the numerically controlled oscillator.

[0029] S13, based on the number of frequency bands N, divide the input control word range into N input control word sub-ranges.

[0030] In this embodiment, similar to the division of frequency bands, the input control word range is also divided into the same number of input control word sub-ranges.

[0031] S14, according to the preset method, the frequency bands are matched one by one with the input control word range.

[0032] For example, the range of input control words corresponding to the kth frequency band can be expressed as Wk = k / N × Wn.

[0033] Furthermore, in this embodiment, step S2, the method of setting the input control word of the numerically controlled oscillator according to the locking frequency, includes: S21, arrange all frequency bands in order of frequency magnitude to obtain the sequence number of each frequency band.

[0034] Specifically, taking the above example, the frequency band covered is 0~40MHz, and its number is 1; the frequency band covered is 40~80MHz, and its number is 2; ... the frequency band covered is 9.92~9.96GHz, and its number is 249; the frequency band covered is 9.96~10GHz, and its number is 250.

[0035] S22, if the sequence number of the frequency band where the locked frequency is located is k, and k is less than the sequence number threshold, then the input control word of the numerically controlled oscillator is set to the input control word corresponding to the midpoint of the (k+2)th frequency band; otherwise, the input control word of the numerically controlled oscillator is set to the input control word corresponding to the midpoint of the (k-2)th frequency band, where k = 1, 2, ..., N, and the value range of the sequence number threshold is 3 to N-2.

[0036] In this way, it can be ensured that when the locked frequency is in a higher frequency band, the input control word of the frequency band following it can be used as the input control word of the numerically controlled oscillator; and when the locked frequency is in a lower frequency band, the input control word of the frequency band preceding it can be used as the input control word of the numerically controlled oscillator.

[0037] In this embodiment, the sequence number threshold can be set to 3 to ensure that frequency bands with sequence numbers less than the threshold can effectively select the last two digits of their sequence number as the input control word for the numerically controlled oscillator, while frequency bands with sequence numbers greater than or equal to the threshold can effectively select the first two digits of their sequence number as the input control word for the numerically controlled oscillator. Of course, in practical applications, the sequence number threshold can be set according to actual needs to ensure that there are a sufficient number of frequency bands available for selection before and after the k-th frequency band.

[0038] Furthermore, in this embodiment, when setting the input control word of the numerically controlled oscillator, the input control word is selected from the last two or the first two frequency bands of the current frequency band. This is to ensure that while there is a significant frequency difference between the reference signal and the feedback signal output by the numerically controlled oscillator, the frequency difference between the two is not too large, so as to ensure that the feedback signal can match the frequency and phase of the reference signal in a short time. Of course, in practical applications, the frequency band selected for the input control word is not limited to two frequency bands different from the current k-th frequency band; it can also be other frequency bands.

[0039] Furthermore, in practical applications, if a frequency band corresponds to multiple input control words, the frequency band can be further divided equally according to the number of input control words, so that each input control word corresponds to a certain frequency range. When setting the input control words of the numerically controlled oscillator, the input control word corresponding to the frequency at the midpoint of the frequency band can be selected as the input control word of the numerically controlled oscillator.

[0040] Furthermore, in this embodiment, step S3, the method of inputting the reference signal and the feedback signal to the time-to-digital converter, includes: inputting the reference signal to the time-to-digital converter, and inputting the signal output by the numerically controlled oscillator as the feedback signal to the time-to-digital converter.

[0041] In practical applications, a frequency divider can be used to divide the signal (frequency signal) output by the numerically controlled oscillator and then use it as a feedback signal to input to the time-to-digital converter.

[0042] After the time-to-digital converter (TD-SCDMA) receives a reference signal and a feedback signal, if the phase difference between the reference signal and the feedback signal is greater than a first phase difference threshold, the value of the phase digital signal output by the TD-SCDMA reaches its upper or lower limit. If the phase difference between the reference signal and the feedback signal is less than a second phase difference threshold, the value of the phase digital signal output by the TD-SCDMA is less than a locking threshold. The first phase difference threshold is greater than the second phase difference threshold.

[0043] In practical applications, the first phase difference threshold can be close to π, and the second phase difference threshold can be close to 0. In this case, the lock-in threshold can also be close to 0. That is, if the phase difference between the reference signal and the feedback signal is about π, the value of the phase digital signal output by the time-to-digital converter will reach its upper or lower limit; if the phase difference between the reference signal and the feedback signal is close to 0, the value of the phase digital signal output by the time-to-digital converter will be close to 0.

[0044] Of course, in practical applications, the specific values ​​of the first phase difference threshold, the second phase difference threshold, and the locking threshold can be reasonably set according to the actual required accuracy.

[0045] Using the example above, if the frequency of the reference signal is 100MHz and the frequency of the digitally controlled oscillator is 10GHz, the frequency range of each band is 40MHz. If the initial phase difference between the reference signal and the feedback signal is π, then after 625ns, the phases of the reference signal and the feedback signal will align, making the value of the phase digital signal output by the time-to-digital converter close to 0.

[0046] Furthermore, in this embodiment, step S4, the method of switching the loop state of the all-digital phase-locked loop from open loop to closed loop when the value of the phase digital signal output by the time-to-digital converter meets the preset condition, includes: when the value of the phase digital signal output by the time-to-digital converter is less than the locking threshold, switching the loop state of the all-digital phase-locked loop from open loop to closed loop. That is, when the value of the phase digital signal output by the time-to-digital converter is close to 0, switching the loop state of the all-digital phase-locked loop from open loop to closed loop.

[0047] Furthermore, in this embodiment, step S4, the method of switching the loop state of the all-digital phase-locked loop from open-loop to closed-loop when the value of the phase digital signal output by the time-to-digital converter meets the preset condition, further includes: when the value of the phase digital signal output by the time-to-digital converter meets the preset condition, switching the input control word of the numerically controlled oscillator to the input control word corresponding to the midpoint of the frequency band where the locked frequency is located. That is, when the value of the phase digital signal output by the time-to-digital converter is close to 0, switching the input control word of the numerically controlled oscillator to the input control word corresponding to the midpoint of the frequency band where the locked frequency is located.

[0048] Thus, the all-digital phase-locked loop can reach the locked state after a sub-microsecond period. Compared to the locking time of tens of microseconds in existing technologies, the locking method of the all-digital phase-locked loop provided in this embodiment can effectively shorten the locking time of the all-digital phase-locked loop.

[0049] This embodiment also provides a fully digital phase-locked loop (PLL) for implementing the locking method of the fully digital PLL as described above, such as... Figure 2 As shown, the all-digital phase-locked loop includes a time-to-digital converter and a numerically controlled oscillator; the time-to-digital converter is used to receive a reference signal and a feedback signal, and generate a phase digital signal based on the reference signal and the feedback signal; the numerically controlled oscillator is used to receive the phase digital signal and output a frequency signal.

[0050] Preferably, in order to record the value of the phase digital signal output by the time-to-digital converter and to determine the closing-loop switching timing of the all-digital phase-locked loop in a timely manner, in this embodiment, as follows: Figure 3 As shown, the all-digital phase-locked loop also includes a digital filter, which is used to record the value of the phase digital signal output by the time-to-digital converter in the open-loop state. Furthermore, the digital filter can also be used to filter the phase digital signal generated by the time-to-digital converter, thereby improving the quality of the signal input to the numerically controlled oscillator.

[0051] More preferably, in order to obtain a feedback signal that matches the frequency signal output by the numerically controlled oscillator, in this embodiment, as follows: Figure 4 As shown, the all-digital phase-locked loop also includes a frequency divider, which is used to receive frequency signals and output feedback signals.

[0052] In practical applications, those skilled in the art can obtain circuit connection schemes between time-to-digital converters, numerically controlled oscillators, digital filters, frequency dividers, and even other functional devices based on the technical solutions disclosed in this application and in combination with existing technologies. This application will not elaborate on these schemes further.

[0053] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0054] The all-digital phase-locked loop and its locking method provided in this embodiment include: dividing the output frequency of a numerically controlled oscillator into N frequency bands through pre-calibration, and obtaining the input control word range corresponding to each frequency band, where N is a natural number greater than 1; setting the input control word of the numerically controlled oscillator according to the locking frequency; inputting a reference signal and a feedback signal to a time-to-digital converter; and switching the loop state of the all-digital phase-locked loop from open-loop to closed-loop when the value of the phase digital signal output by the time-to-digital converter meets a preset condition. By setting the input control word of the numerically controlled oscillator according to the locking frequency, the phase of the feedback signal output by the numerically controlled oscillator is made close to the phase of the reference signal, thereby making the value of the phase digital signal output by the time-to-digital converter close to 0, thus enabling the loop state of the all-digital phase-locked loop to be quickly switched to closed-loop, solving the problem of how to shorten the locking time of the all-digital phase-locked loop.

[0055] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A locking method for a fully digital phase-locked loop, characterized in that, include: Through pre-calibration, the output frequency of the numerically controlled oscillator is divided into N frequency bands, and the input control word range corresponding to each frequency band is obtained, where N is a natural number greater than 1; Set the input control word of the numerically controlled oscillator according to the locking frequency; The reference signal and feedback signal are input to the time-to-digital converter; When the value of the phase digital signal output by the time-to-digital converter meets the preset conditions, the loop state of the all-digital phase-locked loop is switched from open loop to closed loop.

2. The locking method of the all-digital phase-locked loop according to claim 1, characterized in that, The method for dividing the output frequency of a numerically controlled oscillator into N frequency bands through pre-calibration and obtaining the input control word range corresponding to each frequency band includes: Obtain the maximum and minimum values ​​of the output frequency of the numerically controlled oscillator, as well as the range of the input control word; Based on the maximum and minimum values ​​of the output frequency of the numerically controlled oscillator and the number of frequency bands N, the output frequency of the numerically controlled oscillator is divided into N consecutive frequency bands. Based on the number of frequency bands N, the input control word range is divided into N input control word sub-ranges. According to the preset method, the frequency bands are matched one-to-one with the input control word range.

3. The locking method of the all-digital phase-locked loop according to claim 1, characterized in that, The method for determining the input control word of the numerically controlled oscillator based on the locking frequency includes: Arrange all frequency bands in order of frequency magnitude to obtain the sequence number of each frequency band; If the frequency band where the locked frequency is located is number k, and k is less than the number threshold, then the input control word of the numerically controlled oscillator is set to the input control word corresponding to the midpoint of the (k+2)th frequency band; otherwise, the input control word of the numerically controlled oscillator is set to the input control word corresponding to the midpoint of the (k-2)th frequency band, where k = 1, 2, ..., N, and the value range of the number threshold is 3 to N-2.

4. The locking method of the all-digital phase-locked loop according to claim 1, characterized in that, The method of inputting the reference signal and the feedback signal to the time-to-digital converter includes: The reference signal is input to the time-to-digital converter, and the signal output from the numerically controlled oscillator is used as the feedback signal and input to the time-to-digital converter.

5. The locking method of the all-digital phase-locked loop according to claim 1, characterized in that, After the reference signal and feedback signal are input to the time-to-digital converter, the locking method of the all-digital phase-locked loop further includes: If the phase difference between the reference signal and the feedback signal is greater than the first phase difference threshold, the value of the phase digital signal output by the time-to-digital converter reaches its upper or lower limit. If the phase difference between the reference signal and the feedback signal is less than the second phase difference threshold, then the value of the phase digital signal output by the time-to-digital converter is less than the lockout threshold.

6. The locking method of the all-digital phase-locked loop according to claim 1, characterized in that, The method for switching the loop state of the all-digital phase-locked loop from open-loop to closed-loop when the value of the phase digital signal output by the time-to-digital converter meets a preset condition includes: When the value of the phase digital signal output by the time-to-digital converter is less than the locking threshold, the loop state of the all-digital phase-locked loop is switched from open loop to closed loop.

7. The locking method of the all-digital phase-locked loop according to claim 1, characterized in that, The method for switching the loop state of the all-digital phase-locked loop from open-loop to closed-loop when the value of the phase digital signal output by the time-to-digital converter meets a preset condition further includes: When the value of the phase digital signal output by the time-to-digital converter meets the preset conditions, the input control word of the numerically controlled oscillator is switched to the input control word corresponding to the midpoint of the frequency band where the locked frequency is located.

8. A fully digital phase-locked loop (PLL) for implementing the locking method of the fully digital PLL as described in any one of claims 1 to 7, characterized in that, The all-digital phase-locked loop includes a time-to-digital converter and a numerically controlled oscillator; the time-to-digital converter is used to receive a reference signal and a feedback signal, and generate a phase digital signal based on the reference signal and the feedback signal; the numerically controlled oscillator is used to receive the phase digital signal and output a frequency signal.

9. The all-digital phase-locked loop according to claim 8, characterized in that, The all-digital phase-locked loop also includes a digital filter, which is used to record the value of the phase digital signal output by the time-to-digital converter in the open-loop state.

10. The all-digital phase-locked loop according to claim 8, characterized in that, The all-digital phase-locked loop also includes a frequency divider, which is used to receive frequency signals and output feedback signals.

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