Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: a bit line extending in a vertical direction; and a 2-transistor (2T) memory cell including a first transistor and a second transistor on the first transistor. The first transistor includes: an active pattern contacting the bit line, the active pattern including: a first source / drain region and a second source / drain region and a channel region; and a first gate structure including a first gate electrode layer overlapping the channel region. The second transistor includes: a second gate structure including a second gate electrode layer; a channel structure contacting the bit line, the channel structure including: a first horizontal portion extending away from the bit line in a first horizontal direction, and a vertical portion extending vertically from one end of the first horizontal portion; and a memory node between the first gate electrode layer and the second gate electrode layer, and the memory node being connected to the channel structure.

Description

Cross-reference to related applications

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0195251, filed with the Korean Intellectual Property Office on December 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The exemplary embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0003] For semiconductor devices mounted in electronic devices, miniaturization, as well as higher performance and higher capacity, can be advantageous. To achieve these characteristics, semiconductor devices in which each memory cell includes two transistors are being developed. Summary of the Invention

[0004] Some exemplary embodiments of the present invention are intended to provide a semiconductor device with improved reliability.

[0005] According to some exemplary embodiments of the present invention, a semiconductor device includes: a bit line extending in a vertical direction; and a 2-transistor (2T) memory cell on at least one side of the bit line, the 2-transistor (2T) memory cell including a first transistor and a second transistor on the first transistor. The first transistor includes: an active pattern contacting the bit line, the active pattern including: a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region; and a first gate structure including a first gate electrode layer overlapping at least a portion of the channel region of the active pattern. The second transistor includes: a second gate structure including a second gate electrode layer; a channel structure contacting the bit line, the channel structure including: a first horizontal portion extending away from the bit line in a first horizontal direction from the portion contacting the bit line, and a vertical portion extending vertically from one end of the first horizontal portion; and a memory node between the first gate electrode layer and the second gate electrode layer, the memory node being connected to the channel structure.

[0006] According to some exemplary embodiments of the present invention, a semiconductor device includes: a plurality of 2-transistor (2T) memory cells arranged vertically on a substrate. Each of the plurality of 2-transistor (2T) memory cells includes: a first transistor, a second transistor, and an insulating material layer between the first transistor and the second transistor. The first transistor includes: an active pattern extending in a first horizontal direction, the active pattern including: a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region; and a first gate electrode overlapping at least a portion of the channel region of the active pattern. The second transistor includes: a second gate electrode layer; a channel structure including: a horizontal portion extending horizontally, and a vertical portion extending vertically from one end of the horizontal portion on the second gate electrode layer; and a memory node having at least a portion vertically overlapping the channel region and connected to the channel structure.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device includes: a bit line extending in a vertical direction; a first transistor including: a first active pattern including a first channel region extending in a first horizontal direction on at least one side of the bit line, and a first gate electrode overlapping at least a portion of the first channel region; and a second transistor including: a second active pattern on the first transistor and including a second channel region having a horizontal portion and a vertical portion, a second gate electrode overlapping at least a portion of the second channel region, and a storage node contacting the second active pattern and having at least a portion vertically overlapping the first channel region.

[0008] According to some exemplary embodiments of the present invention, a method for manufacturing a semiconductor device includes: forming a substrate; and forming a plurality of memory cells and bit lines on the substrate, the plurality of memory cells each including a 2-transistor (2T) memory cell, the 2-transistor memory cell including a first transistor and a second transistor, wherein forming the plurality of memory cells and bit lines includes forming a first molding structure and a second molding structure on the substrate, wherein each of the first molding structure and the second molding structure includes a first sacrificial layer, a channel material layer, a second sacrificial layer, a channel material layer, a second sacrificial layer, a first sacrificial layer, a second sacrificial layer, and a channel material layer stacked sequentially; removing the first sacrificial layer to fill a molding insulating layer; forming a first trench penetrating the first molding structure, the second molding structure, and the molding insulating layer; removing the second sacrificial layer to form a first open region, wherein the first open region extends horizontally from the first trench; forming a second transistor in the first open region; filling the first trench with a conductive material to form a bit line; removing the molding insulating layer to form the second open region; and forming a first transistor in the second open region.

[0009] Alternatively, a method may be provided in which the channel material layer comprises silicon (Si), and the first sacrificial layer and the second sacrificial layer comprise different materials.

[0010] Alternatively, a method may be provided in which a channel material layer is exposed through a first open area, and after the first open area is formed, an insulating material layer is formed on the channel material layer exposed within the first open area.

[0011] Alternatively, a method may be provided in which forming the second open region includes performing the following steps in sequence: forming a channel structure including a horizontal portion and a vertical portion in the first open region, forming a gate dielectric layer on the channel structure, and forming a gate electrode layer on the gate dielectric layer.

[0012] Alternatively, a method may be provided in which forming a channel structure includes: depositing a first conductive material on the inner surface of a first open region to form a preliminary channel structure; after forming a gate dielectric layer, recessing a horizontally extending portion of the preliminary channel structure to form a plurality of openings; and filling one of the plurality of openings with the first conductive material to form a horizontal portion of the channel structure.

[0013] Alternatively, a method may be provided in which the first conductive material comprises an oxide semiconductor.

[0014] Alternatively, a method may be provided in which forming the second transistor further includes filling the remaining portion of the plurality of openings with a second conductive material after forming the horizontal portion of the channel structure to form a storage node.

[0015] Alternatively, a method can be provided in which the storage node contacts the vertical portion of the trench structure.

[0016] Alternatively, a method may be provided in which the second conductive material comprises a metallic material or an oxide semiconductor.

[0017] Alternatively, a method may be provided in which forming a first transistor by exposing a channel material layer by a second open region includes: sequentially forming a gate dielectric layer on the channel material layer exposed in the second open region, and forming a gate electrode layer on the gate dielectric layer.

[0018] According to some exemplary embodiments of the present invention, a method is provided for operating a semiconductor device including a 2-transistor (2T) memory cell, the 2-transistor (2T) memory cell including a first transistor and a second transistor on the first transistor and a storage node therebetween, the method including performing a write operation on the memory cell, the operation including applying a voltage to the gate electrode of the second transistor, causing current to flow through the channel structure of the second transistor, and accumulating or reducing charge in the storage node between the first transistor and the second transistor.

[0019] In addition, when performing a write operation on a memory cell, the write operation also includes applying a lower voltage to a bit line connected to the first electrode of the second transistor during the write operation to reduce the charge on the memory node, or applying a higher voltage to the bit line during the write operation to accumulate charge on the memory node. Attached Figure Description

[0020] The above-described exemplary embodiments and other aspects, features, and advantages of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a plan view illustrating a semiconductor device according to some example embodiments.

[0021] Figure 2A yes Figure 1 A partial enlarged view of the semiconductor device shown. Figure 2A This is a circuit diagram of a memory cell in a memory cell region according to some example embodiments.

[0022] Figure 2B These are timing diagrams of memory cells according to some example embodiments.

[0023] Figure 3A yes Figure 1 The image shows a vertical cross-sectional view of the memory cell region along line I-I'.

[0024] Figure 3B yes Figure 1 The image shows a vertical cross-sectional view of the memory cell region along line II-II'.

[0025] Figure 3C This is a perspective view showing a semiconductor device according to some example embodiments.

[0026] Figure 4 This is a partial enlarged view of a semiconductor element according to some example embodiments.

[0027] Figures 5 to 8 This is a partial enlarged view of a semiconductor element according to some example embodiments.

[0028] Figure 9 , Figure 11 , Figure 14 , Figure 16 , Figure 21 , Figure 23 , Figure 26 , Figure 32 and Figure 34 It is a plan view illustrating the process sequence of a method for manufacturing a semiconductor device according to some example embodiments.

[0029] Figure 10A , Figure 10B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 22A , Figure 22B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 31A , Figure 31B , Figure 33A , Figure 33B , Figure 35A , Figure 35B , Figure 36A , Figure 36B , Figure 37A and 37B It is a vertical cross-sectional view illustrating the process sequence of a method for manufacturing a semiconductor device according to some example embodiments. Detailed Implementation

[0030] In the following text, terms such as “on,” “above,” “upper part,” “upper surface,” “below,” “lower part,” “lower surface,” “side surface,” “upper end,” and “lower end” may be understood to refer to the accompanying drawings unless otherwise indicated by the reference numerals. Terms such as “above,” “upper part,” “middle,” “lower,” and “lower part” may be replaced by other terms such as “first,” “second,” and “third” and are used to describe components of the specification. Terms such as “first,” “second,” and “third” may be used to describe various components, but components are not limited by the terms, and “first component” may be referred to as “second component.”

[0031] In the following description, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0032] Figure 1 This is a plan view illustrating a semiconductor device according to some example embodiments.

[0033] Figure 2A yes Figure 1 A partial enlarged view of the semiconductor device shown. Figure 2A Based on some example embodiments Figure 1 A partial enlarged view of "A" and a circuit diagram of the memory cells in the memory cell area.

[0034] Figure 2B These are timing diagrams of memory cells according to some example embodiments.

[0035] Figure 3A yes Figure 1 The image shows a vertical cross-sectional view of the memory cell region along line I-I'.

[0036] Figure 3B yes Figure 1 The image shows a vertical cross-sectional view of the memory cell region along line II-II'.

[0037] Figure 3C This is a perspective view showing a semiconductor device according to some example embodiments.

[0038] Figure 4 This is a partial enlarged view of a semiconductor element according to some example embodiments. Figure 4 yes Figure 3A A magnified view of part "B".

[0039] Reference Figures 1 to 4 A semiconductor device 100 according to some exemplary embodiments of the present invention may include a cell region CA and a peripheral circuit region PA. The peripheral circuit region PA may be configured to surround the cell region CA. An interface region (not shown) may be disposed between the cell region CA and the peripheral circuit region PA. The cell region CA may refer to the region in which memory cells of a dynamic random access memory (DRAM) device are disposed, and the peripheral circuit region PA may be the region in which word line drivers, sense amplifiers, row decoders and column decoders, and control circuitry are disposed. The interface region (not shown) may be the region for electrically connecting the cell region CA to the peripheral circuit region PA.

[0040] Semiconductor device 100 according to some exemplary embodiments of the present invention may include a substrate 101, a plurality of memory cells (e.g., MC1 and MC2), bit lines BL, and plate electrode layers PP in a cell region CA. For example, semiconductor device 100 may be applied to a cell array of dynamic random access memory (DRAM), but the exemplary embodiments are not limited thereto.

[0041] Substrate 101 may include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 101 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer. However, the exemplary embodiments are not limited thereto.

[0042] Multiple memory cells MC1 and MC2 may be vertically arranged on substrate 101 at multiple levels. The multiple memory cells MC1 and MC2 may, for example, be vertically stacked repeatedly on substrate 101. The multiple memory cells MC1 and MC2 may include a first memory cell MC1 and a second memory cell MC2 arranged vertically. Each of the multiple memory cells MC1 and MC2 may include a first transistor T1 and a second transistor T2. In some example embodiments, the first transistor T1 and the second transistor T2 may be collectively referred to as 2 transistors (2T), and therefore, each of the multiple memory cells MC1 and MC2 may be referred to as a 2-transistor (2T) memory cell. In some example embodiments, the first transistor T1 may be referred to as a read transistor, and the second transistor T2 may be referred to as a write transistor.

[0043] The first transistor T1 may include an active pattern 120 and a first gate structure GS1.

[0044] Active patterns 120 may be disposed on substrate 101 and may extend horizontally in a first horizontal direction (e.g., the X direction). Active patterns 120 may be spaced apart from each other in a second horizontal direction (e.g., the Y direction) by molding insulating structures 177. Active patterns 120 may be configured to be spaced apart from each other in a vertical direction. In some example embodiments, active patterns 120 may comprise semiconductor materials, such as silicon, germanium, or silicon-germanium. However, the example embodiments are not limited thereto.

[0045] The active pattern 120 may include a first source / drain region SD1, a second source / drain region SD2, and a channel region CH. Each of the first source / drain region SD1 and the second source / drain region SD2 may be referred to as a first impurity region and a second impurity region. The first source / drain region SD1 and the second source / drain region SD2 may be located at both ends of a first horizontal direction (e.g., the X direction) of the active pattern 120, and the channel region CH may be located between the first source / drain region SD1 and the second source / drain region SD2.

[0046] The first source / drain region SD1 may, for example, be adjacent to and in contact with the bit line BL. The second source / drain region SD2 may, for example, be adjacent to and in contact with the plate electrode layer PP.

[0047] The boundary between the first source / drain region SD1 and the channel region CH may be aligned with the first side surface of the portion of the first gate electrode 140 adjacent to the bit line BL, but the example embodiment is not limited thereto. For example, the boundary between the first source / drain region SD1 and the channel region CH may not be aligned with the first side surface of the first gate electrode 140.

[0048] The boundary between the second source / drain region SD2 and the channel region CH can be aligned with the second side surface of the portion of the first gate electrode 140 adjacent to the plate electrode layer PP, but the example embodiment is not limited thereto. For example, the boundary between the second source / drain region SD2 and the channel region CH may not be aligned with the second side surface of the first gate electrode 140.

[0049] The active pattern 120 may include a semiconductor material such as silicon. The active pattern 120 may include, for example, monocrystalline silicon or polycrystalline silicon.

[0050] In some example embodiments, it can be understood that a first channel material layer is formed of monocrystalline silicon ( Figure 10A The advantage that the active pattern 120 of the semiconductor device 100 includes single-crystal silicon is that the first channel material layer 120p is retained and not removed from the molded structures MS1 and MS2.

[0051] In some example embodiments, the active pattern 120 may include an oxide semiconductor layer. In this case, the active pattern 120 may not include a separate first source / drain region SD1 and a second source / drain region SD2.

[0052] The oxide semiconductor layer may include, for example, indium gallium zinc oxide (IGZO), but the exemplary embodiments are not limited thereto. For example, the oxide semiconductor layer may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), indium zinc oxide (InZnO), and oxygen. At least one of indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO). However, the exemplary embodiments are not limited thereto.

[0053] The first gate structure GS1 may include a first gate electrode 140 and a first gate dielectric layer 142.

[0054] The first gate electrode 140 may extend in a first horizontal direction (e.g., the X direction) and may vertically overlap with the channel region CH of the active pattern 120. The first gate electrode 140 may extend in a second horizontal direction (e.g., the Y direction). In some example embodiments, the first gate electrode 140 may be referred to as a first gate electrode layer.

[0055] The first gate dielectric layer 142 may include a first portion 142a extending in a first horizontal direction (e.g., the X direction) between the active pattern 120 and the first gate electrode 140, and a second portion 142b connected to the end of the first portion 142a and extending vertically between the first gate electrode 140 and the bit line BL.

[0056] The first gate dielectric layer 142 may include at least one of silicon oxide, silicon nitride, a low-κ material, and a high-κ material. However, the exemplary embodiments are not limited thereto. A high-κ material may represent a dielectric material having a higher dielectric constant than silicon oxide, and a low-κ material may represent a dielectric material having a lower dielectric constant than silicon oxide. A high-κ material may be, for example, a metal oxide or a metal nitride. A high-κ material may be, for example, aluminum oxide (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y The first gate dielectric layer 142 may be formed of any one of the above-described materials, such as praseodymium oxide (Pr₂O₃). However, the example embodiment is not limited thereto.

[0057] In some example embodiments, the first gate structure GS1 may further include an insulating liner 142' covering the first gate electrode 140 between the first molded insulating layer MD1 and the first gate electrode 140. The insulating liner 142' may be located on the opposite side of the first gate dielectric layer 142 relative to the first gate electrode 140. The insulating liner 142' may include a first portion extending in a first horizontal direction (e.g., the X direction) between the first molded insulating layer MD1 and the first gate electrode 140, and a second portion connected to the end of the first portion and extending vertically between the first molded insulating layer MD1 and the first gate capping layer 144.

[0058] In some example embodiments, the semiconductor device 100 may further include a plurality of gate capping layers 144 and 146. The plurality of gate capping layers 144 and 146 may include a first gate capping layer 144 between the first gate electrode 140 and the bit line BL, and a second gate capping layer 146 between the first gate electrode 140 and the plate electrode layer PP. In some example embodiments, the first gate capping layer 144 and the second gate capping layer 146 may be collectively referred to as the first gate capping layer.

[0059] The first gate capping layer 144 and the second gate capping layer 146 may comprise at least one insulating material selected from, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. However, the exemplary embodiments are not limited thereto. For example, the first gate capping layer 144 may comprise silicon nitride, and the second gate capping layer 146 may comprise silicon oxide.

[0060] The second transistor T2 may include a second gate structure GS2, a channel structure 220, and a memory node SN.

[0061] The second gate structure GS2 may include a second gate electrode 240 and a second gate dielectric layer 242.

[0062] The second gate electrode 240 may include a portion extending in a first horizontal direction (e.g., the X direction). The second gate electrode 240 may extend in a second horizontal direction (e.g., the Y direction). In some example embodiments, the second gate electrode 240 may be referred to as a second gate electrode layer.

[0063] In the vertical direction (e.g., the Z direction), the second gate electrode 240 may include a first portion p1 overlapping with the storage node SN and a second portion p2 overlapping with the molded insulating structure 177 (see [link to documentation]). Figure 3B The first portion p1 may be spaced apart in a second horizontal direction (e.g., the Y direction), and the second portion p2 may be spaced apart in the second horizontal direction. For example, the first portion p1 and the second portion p2 may be alternately arranged in the second horizontal direction.

[0064] The second gate electrode 240 may have a different shape than the first gate electrode 140. For example, the maximum thickness of the first portion p1 in the vertical direction may be less than the maximum thickness of the second portion p2 in the vertical direction.

[0065] The second gate dielectric layer 242 may surround the upper, lower and side portions of the second gate electrode 240 between the channel structure 220 and the second gate electrode 240.

[0066] The second gate dielectric layer 242 may include at least one of silicon oxide, silicon nitride, a low-κ material, and a high-κ material. However, the exemplary embodiments are not limited thereto. A high-κ material may represent a dielectric material having a higher dielectric constant than silicon oxide, and a low-κ material may represent a dielectric material having a lower dielectric constant than silicon oxide. The high-κ dielectric material may be, for example, a metal oxide or a metal nitride. The high-κ dielectric material may be, for example, alumina (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y The second gate dielectric layer 242 may be formed of any one of the above-described materials, such as praseodymium oxide (Pr₂O₃). However, the example embodiment is not limited thereto.

[0067] In some example embodiments, the semiconductor device 100 may further include a second gate capping layer 244. The second gate capping layer 244 may be disposed between the second gate electrode 240 and the bit line BL. The second gate capping layer 244 may include at least one of an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. However, the example embodiments are not limited thereto.

[0068] The channel structure 220 may include a horizontal portion 220a extending away from the contact bit line BL along a first horizontal direction (e.g., the X direction) and a vertical portion 220b connected to the end of the horizontal portion 220a and extending vertically between the second gate electrode 240 and the plate electrode layer PP.

[0069] In adjacent second transistors T2 in the vertical direction (e.g., the Z direction), the channel structures 220 may be vertically spaced apart by a second molded insulating layer MD2 located therebetween. For example, the horizontal portions 220a of the upper and lower channel structures 220 may face each other, with the second molded insulating layer MD2 located between them. Furthermore, the vertical portions 220b of the upper and lower channel structures 220 may extend away from each other, with the second molded insulating layer MD2 located between them. On the other hand, in adjacent second transistors T2 in the vertical direction (e.g., the Z direction), the channel structures 220 may be symmetrical with respect to the second molded insulating layer MD2.

[0070] In some example embodiments, the channel structure 220 may include an oxide semiconductor layer.

[0071] The oxide semiconductor layer may include indium gallium zinc oxide (IGZO). For example, the oxide semiconductor layer may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), indium zinc oxide (InZnO), and oxygen. At least one of indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO). However, the exemplary embodiments are not limited thereto.

[0072] The storage node SN can be disposed between the first gate electrode 140 and the second gate electrode 240, and can be connected to the channel structure 220. The end of the storage node SN can, for example, contact the side surface of the vertical portion 220b.

[0073] The memory node SN may include a portion that overlaps with at least a portion of each of the first gate electrode 140 and the active pattern 120 of the first transistor T1. For example, the memory node SN may include a portion that overlaps with at least a portion of the first gate electrode 140 in a vertical direction (e.g., the Z direction). The memory node SN may also include a portion that overlaps with at least a portion of the channel region CH of the active pattern 120 in a vertical direction (e.g., the Z direction).

[0074] Storage node SN may include metal or metal nitride. For example, storage node SN may include titanium nitride, tungsten, ruthenium, molybdenum, etc. However, the example embodiments are not limited thereto.

[0075] An insulating capping layer 254 may be disposed between the memory node SN and the bit line BL. The insulating capping layer 254 may be configured to separate the memory node SN from the bit line BL. The insulating capping layer 254 may include an insulating material, such as at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. However, the exemplary embodiments are not limited thereto.

[0076] According to some exemplary embodiments of the present invention, the semiconductor device 100 may include transistors that can operate in a complementary MOSFET (CMOS) circuit. For example, the first transistor T1 and the second transistor T2 of the semiconductor device 100 may be transistors with different doping characteristics.

[0077] According to some exemplary embodiments of the present invention, the first transistor T1 may be a PMOS transistor, and the second transistor T2 may be an NMOS transistor. In this case, the channel region CH may be formed as P-type, and the channel structure 220 may be formed as N-type. In this case, the channel region CH may be referred to as a P-type channel, and the channel structure 220 may be referred to as an N-type channel.

[0078] However, some example embodiments are not limited to this. For example, the first transistor T1 can be an NMOS transistor, and the second transistor T2 can be a PMOS transistor. In this case, the channel region CH can be formed as N-type, and the channel structure 220 can be formed as P-type. In this case, the channel region CH can be referred to as an N-type channel, and the channel structure 220 can be referred to as a P-type channel.

[0079] The semiconductor device 100 may further include an insulating material layer EL between the first transistor T1 and the second transistor T2. The insulating material layer EL may be configured to allow each of the first transistor T1 and the second transistor T2 to operate independently.

[0080] The insulating material layers EL may extend in a first horizontal direction (e.g., the X direction), and one end of the insulating material layer EL may contact the bit line BL. The insulating material layers EL may be spaced apart from each other in a second horizontal direction (e.g., the Y direction) by molding the insulating structure 177. The insulating material layers EL may be configured to be spaced apart from each other in the vertical direction.

[0081] An insulating material layer EL may contact the channel portion of each of transistors T1 and T2. For example, the insulating material layer EL may contact the active pattern 120 of the first transistor T1. The insulating material layer EL may contact the channel structure 220 and the memory node SN of the second transistor T2. The memory node SN may face the active pattern 120, and the insulating material layer EL is located between the memory node SN and the active pattern 120. The memory node SN may include, for example, a portion that overlaps with the channel region CH of the active pattern 120 in the vertical direction (e.g., the Z direction), and the insulating material layer EL is located between the two.

[0082] The insulating material layer EL may include a high-κ material. High-κ materials may be, for example, alumina (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), or zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y The example can be any of praseodymium oxide (Pr2O3) or praseodymium oxide (Pr2O3). However, the example is not limited thereto.

[0083] The semiconductor device 100 may further include molded insulating layers MD1 and MD2 covering each of transistors T1 and T2. A first molded insulating layer MD1 may cover the first transistor T1, and a second molded insulating layer MD2 may cover the second transistor T2. The first molded insulating layer MD1 may cover the first transistor T1, which is vertically adjacent to each other, on one side of the plate electrode layer PP. The second molded insulating layer MD2 may cover the second transistor T2, which is vertically adjacent to each other, between the plate electrode layer PP and the bit line BL. The second molded insulating layer MD2 may contact the source / drain region (e.g., SD2) of the active pattern 120 of the first transistor T1 and may contact the channel structure 220 of the second transistor T2. The second molded insulating layer MD2 may contact the insulating material layer EL.

[0084] The first transistors T1 can be vertically adjacent to each other, and the second transistors T2 can be vertically adjacent to each other. For example, the first transistors T1 of the first memory cell MC1 and the first transistors T1 of the second memory cell MC2 can be vertically adjacent to each other. The second transistors T2 of the first memory cell MC1 and the second transistors T2 of the memory cell located above the first memory cell MC1 can be vertically adjacent to each other.

[0085] Reference Figure 3B Adjacent first memory cells MC1 in the second horizontal direction (e.g., the Y direction) may share the same gate electrode. For example, first memory cells MC1 may share the first gate electrode 140 and the second gate electrode 240. Alternatively, first memory cells MC1 may share the same word line. Similarly, adjacent second memory cells MC2 in the second horizontal direction (e.g., the Y direction) may share the same word line.

[0086] The first gate electrode 140 and the second gate electrode 240 can be electrically connected to each other (see...). Figure 3C For example, the first gate electrode 140 and the second gate electrode 240 may share a gate interconnect GC. The first gate electrode 140 may be connected, for example, by the gate interconnect GC and a first contact structure CA1, and the second gate electrode 240 may be connected, for example, by the gate interconnect GC and a second contact structure CA2. In this case, the gate interconnect GC may correspond to Figure 1 and Figure 2A The letter line WL.

[0087] Bit lines BL may extend on substrate 101 in a second horizontal direction (e.g., the Y direction) and a vertical direction. Bit lines BL may be spaced apart from each other in the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction). Active pattern 120 may be electrically connected to a bit line BL. For example, bit line BL may be electrically connected to the first source / drain region SD1 of active pattern 120. Channel structure 220 may be electrically connected to a bit line BL. For example, bit line BL may be electrically connected to the horizontal portion 220a of channel structure 220.

[0088] The semiconductor device 100 may be symmetrical with respect to the bit line BL. For example, the first memory cell MC1 may be arranged symmetrically with respect to the bit line BL, and the second memory cell MC2 may be arranged symmetrically with respect to the bit line BL.

[0089] Bit line BL may include at least one of doped semiconductor material, conductive metal nitride, metal, and metal semiconductor compound. For example, bit line BL may include doped polysilicon.

[0090] The plate electrode layer PP may extend on the substrate 101 in a second horizontal direction (e.g., the Y direction) and a vertical direction. The plate electrode layer PP may be configured to be spaced apart from each other in the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction). The plate electrode layer PP may, for example, face the bit line BL in the first horizontal direction (e.g., the X direction).

[0091] The plate electrode layer PP may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. In some example embodiments, the plate electrode layer PP may include silicon-germanium. However, the example embodiments are not limited thereto.

[0092] In the operation performed by the second transistor T2, a voltage can be applied to the second gate electrode 240, and current can flow through the channel structure 220 and the memory node SN. In this case, the operation performed by the second transistor T2 can be, for example, a write operation. Figure 2B The "write 0" segment and the "write 1" segment), and the current caused by the write operation can be called the write current. Figure 2B As can be seen, when a voltage is applied to the gate electrode 240 connected to the word line, and when the reference potential Vdd of the bit line BL decreases, the charge in the memory node decreases ("Write 0"). Alternatively, when a voltage is applied to the gate electrode 240 connected to the word line, and when the reference potential Vdd of the bit line BL increases, the charge in the memory node increases ("Write 1").

[0093] The second gate electrode 240, the second gate dielectric layer 242, and the storage node SN can be considered as a first capacitor C1, and the channel region CH, the insulating material layer EL, and the storage node SN can be considered as a second capacitor C2. In this state, through the operation of the first transistor T1 and the second transistor T2, charge can accumulate in the storage node SN, and data can be stored in the memory cell MC.

[0094] The amount of charge accumulated in the storage node SN can affect the threshold voltage Vt of the first transistor T1. For example, the amount of charge accumulated in the storage node SN can cause a change of ΔV in the threshold voltage Vt of the first transistor T1. Compared to the reference potential Vdd of the bit line BL, the potential of the bit line BL can change by ΔV. Whether ΔV is greater than or less than the bias voltage of the bit line sense amplifier can distinguish data 0 (or "binary 0"). Figure 2B D0) or data 1 (or "binary 1") Figure 2B D1).

[0095] Figures 5 to 8 This is a partial enlarged view of a semiconductor element according to some example embodiments.

[0096] Reference Figure 5 In addition to including a memory node SN' containing a material substantially the same as that of the channel structure 220, the semiconductor device 100A can be compared with a reference. Figures 1 to 4 The semiconductor devices described are the same or similar.

[0097] Storage node SN' may include an oxide semiconductor layer.

[0098] The oxide semiconductor layer may include, for example, indium gallium zinc oxide (IGZO). For instance, the oxide semiconductor layer may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), indium zinc oxide (InZnO), and oxygen... At least one of indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO). However, the exemplary embodiments are not limited thereto.

[0099] In some example embodiments, the concentration of the oxide semiconductor included in the storage node SN' may differ from the concentration of the oxide semiconductor included in the channel structure 220. In this case, the concentration of the oxide semiconductor may be the carrier concentration of the oxide semiconductor, and the carrier concentration may be appropriately controlled by doping.

[0100] Reference Figure 6 In addition to including a memory node SN having a convex shape in the direction toward the channel structure 220, the semiconductor device 100B can be compared with a reference. Figures 1 to 5 The semiconductor devices described are the same or similar.

[0101] The storage node SN” may have a convex shape in the direction toward the channel structure 220. For example, the end of the storage node SN” may have a convex shape toward the vertical portion 220b of the channel structure 220. Therefore, at least a portion of the side surface of the vertical portion 220b may have a concave shape toward the plate electrode layer PP.

[0102] Reference Figure 7 In addition to including a channel structure 220 having multiple horizontal portions 220a_1 and 220a_2, the semiconductor device 100C can be compared with a reference. Figures 1 to 6 The semiconductor devices described are the same or similar.

[0103] The channel structure 220 may include: a first horizontal portion 220a_1 that extends horizontally away from the bit line BL from a portion that contacts the bit line BL; a vertical portion 220b that is connected to the end of the first horizontal portion 220a_1 and extends vertically between the second gate electrode 240 and the plate electrode layer PP; and a second horizontal portion 220a_2 that is connected to the end of the vertical portion 220b and extends horizontally close to the bit line BL.

[0104] The second horizontal portion 220a_2 may have a shorter horizontal length than the first horizontal portion 220a_1. A storage node SN may be connected to the second horizontal portion 220a_2. For example, the storage node SN may contact an end of the second horizontal portion 220a_2. Unlike the first horizontal portion 220a_1, the second horizontal portion 220a_2 may not contact the bit line BL.

[0105] Reference Figure 8 In addition to the gate electrode layers 140' and 240', which include side surfaces with concave profiles, the semiconductor device 100D can be compared with a reference. Figures 1 to 7 The semiconductor devices described are the same or similar.

[0106] The end of the first gate electrode layer 140' may have a concave profile. For example, the side surface of the portion of the first gate electrode layer 140' adjacent to the plate electrode layer PP may have a concave shape facing the bit line BL.

[0107] The end of the second gate electrode layer 240' may have a concave profile. For example, the side surface of the portion of the second gate electrode layer 240' adjacent to the bit line BL may have a concave shape facing the plate electrode layer PP.

[0108] Figure 9 , Figure 11 , Figure 14 , Figure 16 , Figure 21 , Figure 23 , Figure 26 , Figure 32 and Figure 34 It is a plan view illustrating the process sequence of a method for manufacturing a semiconductor device according to some example embodiments.

[0109] Figure 10A , Figure 10B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 22A , Figure 22B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 31A , Figure 31B , Figure 33A , Figure 33B , Figure 35A , Figure 35B , Figure 36A , Figure 36B , Figure 37A and Figure 37B It is a vertical cross-sectional view illustrating the process sequence of a method for manufacturing a semiconductor device according to some example embodiments.

[0110] Figure 10A and Figure 10B It is along Figure 9 The vertical cross-sectional view of lines I-I' and II-II' of the memory cell region shown.

[0111] Reference Figure 9 , Figure 10A and Figure 10B A first molding structure MS1 and a second molding structure MS2 can be formed on the substrate 101. For convenience, the first molding structure MS1 and the second molding structure MS2 can be collectively referred to as molding structures.

[0112] Each of the first molding structure MS1 and the second molding structure MS2 may include alternately stacked first channel material layers 120p and a plurality of sacrificial layers 121 and 122. For example, each of the first molding structure MS1 and the second molding structure MS2 may be a structure in which the first sacrificial layer 121, the first channel material layer 120p, the second sacrificial layer 122, the first sacrificial layer 121, the second sacrificial layer 122, and the first channel material layer 120p are stacked sequentially. The thickness of the first sacrificial layer 121 of the first molding structure MS1 may be less than the thickness of the second sacrificial layer 122 of the second molding structure MS2. The arrangement, combination, and thickness of each of the first channel material layer 120p and the plurality of sacrificial layers 121 and 122 are not limited to those described above and can be modified in various ways.

[0113] At least one separate second molded structure MS2 can be stacked vertically on the second molded structure MS2 (not shown).

[0114] Each of the first channel material layer 120p and the plurality of sacrificial layers 121 and 122 may have different etch selectivity. For example, the first channel material layer 120p may include silicon (Si), the first sacrificial layer 121 may include silicon germanium carbon (SiGeC), and the second sacrificial layer 122 may include silicon germanium (SiGe). However, the example embodiment is not limited thereto.

[0115] Figure 12A and Figure 12B It is along Figure 11 The image shows a vertical cross-sectional view of the memory cell region shown, taken from lines I-I' and II-II'.

[0116] Reference Figure 11 , Figure 12A and Figure 12B This can form a through-molded structure and expose multiple openings OP1 and OP2 on the substrate 101.

[0117] The plurality of opening portions OP1 and OP2 may include a first opening portion OP1 extending in a second horizontal direction (e.g., the Y direction) and a second opening portion OP2 extending in a first horizontal direction (e.g., the X direction). The first opening portion OP1 may be formed to be spaced apart in the first horizontal direction (e.g., the X direction), and the second opening portion OP2 may be formed to be spaced apart in the second horizontal direction (e.g., the Y direction).

[0118] Reference Figure 13A and Figure 13B This can remove the first sacrificial layer 121.

[0119] The first sacrificial layer 121 exposed by the multiple openings OP1 and OP2 can be selectively removed. The first sacrificial layer 121 can be removed by an etching process in the lateral direction (e.g., the X and / or Y directions).

[0120] Figure 15A and Figure 15B It is along Figure 14 The vertical cross-sectional view of lines I-I' and II-II' of the memory cell region shown.

[0121] Reference Figure 14 , Figure 15A and Figure 15B Multiple openings OP1 and OP2 can be filled with insulating material to form a molded insulating layer 171.

[0122] Multiple openings OP1 and OP2 can be filled with an insulating material. The insulating material can completely fill the space between adjacent second sacrificial layers 122 in the vertical direction. The insulating material may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The molded insulating layer 171 may include, for example, silicon nitride. However, the exemplary embodiments are not limited thereto.

[0123] Figure 17A and Figure 17B It is along Figure 16 The vertical cross-sectional view of lines I-I' and II-II' of the memory cell region shown.

[0124] Reference Figure 16 , Figure 17A and Figure 17B A first trench TR1 can be formed that penetrates the first channel material layer 120p and the second sacrificial layer 122 and exposes the substrate 101.

[0125] The first groove TR1 may extend along a second horizontal direction (e.g., the Y direction). The first groove TR1 may be spaced apart in a first horizontal direction (e.g., the X direction).

[0126] Reference Figure 18A and Figure 18B This can remove the second sacrificial layer 122.

[0127] The second sacrificial layer 122 exposed by the first trench TR1 can be selectively removed. The second sacrificial layer 122 can be removed by an etching process in the lateral direction (e.g., the X and / or Y directions). Thus, a first open region OR1 extending horizontally from the first trench TR1 can be defined.

[0128] Reference Figure 19A and Figure 19B It can form an insulating lining 173.

[0129] An insulating material may be deposited on the surface of the molded insulating layer 171 exposed by the first open region OR1, and a portion of the insulating material may be recessed to form an insulating liner 173 (which is part of the second molded insulating layer MD2). The recessed portion of the insulating material may include a portion extending horizontally on the molded insulating layer 171. Thus, the insulating liner 173 may extend vertically.

[0130] The insulating material may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The insulating liner 173 may include, for example, silicon oxide. However, the example embodiments are not limited thereto.

[0131] Reference Figure 20A and Figure 20B It can form an insulating material layer EL.

[0132] Using area-selective deposition (ASD), an insulating material layer EL can be selectively deposited on the first trench material layer 120p exposed by the first open region OR1. The insulating material layer EL may include a high-κ material.

[0133] Figure 22A and Figure 22B It is along Figure 21 The image shows a vertical cross-sectional view of the memory cell region shown, taken from lines I-I' and II-II'.

[0134] Reference Figure 21 , Figure 22A and Figure 22B This can form a second channel material layer 220p.

[0135] The second channel material layer 220p can be formed in the first open region OR1. The second channel material layer 220p can be formed in the trench TR1 and the first open region OR1 using atomic layer deposition (ALD) technology. The second channel material layer 220p can be formed on the surface of the insulating material layer EL, the surface of the insulating liner 173, and the surface of the molded insulating layer 171.

[0136] The second channel material layer 220p may include an oxide semiconductor. In some exemplary embodiments of the present invention, the second channel material layer 220p may include indium gallium zinc oxide (IGZO). However, the exemplary embodiments are not limited thereto.

[0137] Figure 24A and Figure 24B It is along Figure 23 The image shows a vertical cross-sectional view of the memory cell region shown, taken from lines I-I' and II-II'.

[0138] Reference Figure 23 , Figure 24A and Figure 24B , can Figure 22A and Figure 22B The first open area OR1 and the first trench TR1 are filled with insulating material to form a molded insulating layer 175.

[0139] Refer to together Figure 22A and Figure 22B The insulating material can be filled in the first open region OR1. The insulating material can fill not only the first open region OR1, but also the first trench TR1. In this case, a second trench TR2 can be formed again to expose the substrate 101.

[0140] The insulating material may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. The molded insulating layer 175 may include, for example, silicon oxide. However, the example embodiments are not limited thereto.

[0141] Reference Figure 25A and Figure 25B This allows for the removal of a portion of the second channel material layer 220p.

[0142] The portion of the second channel material layer 220p that extends vertically and is spaced apart in the second horizontal direction (e.g., the Y direction) can be removed. Therefore, the surface of the molded insulating layer 175 can be exposed in the second horizontal direction (e.g., the Y direction).

[0143] Figure 27A and Figure 27B It is along Figure 26 The image shows a vertical cross-sectional view of the memory cell region shown, taken from lines I-I' and II-II'.

[0144] Reference Figure 26 , Figure 27A and Figure 27B , can Figure 25A and Figure 25B The second trench TR2 is filled with insulating material, and a portion of the insulating material can be removed to form a molded insulating structure 177. In this case, the molded insulating layer 175 can be removed.

[0145] Insulating material can be filled into the second trench TR2, and a portion of the insulating material can be removed by an etching process in the lateral direction (e.g., in the X and / or Y directions). Therefore, the molded insulating structure 177 can be partially retained in the second trench TR2, extending in the second horizontal direction (e.g., in the Y direction) (see...). Figure 27B In “TR2”).

[0146] Reference Figure 28A and Figure 28B A second gate dielectric layer 242, a second gate electrode layer 240, and a second gate capping layer 244 can be formed.

[0147] An insulating material can be deposited on the second channel material layer 220p to form a second gate dielectric layer 242. The second gate dielectric layer 242 may extend in a second horizontal direction (e.g., in the Y direction).

[0148] A conductive material may be formed on the second gate dielectric layer 242 to form the second gate electrode layer 240. The second gate electrode layer 240 may extend in a second horizontal direction (e.g., the Y direction).

[0149] A portion of the side surface of the second gate dielectric layer 242 may be recessed and filled with an insulating material to form a second gate capping layer 244. The insulating material may include silicon oxide. The second gate dielectric layer 242 and the second gate electrode layer 240 may be defined as a second gate structure. Figure 3A (GS2).

[0150] Reference Figure 29A and Figure 29B , Figure 28A and Figure 28B A portion of the second channel material layer 220p can be recessed and removed.

[0151] A portion of the second channel material layer 220p can be removed using an etching process in the lateral direction (e.g., the X and Y directions). Therefore, the inner surface of the insulating material layer EL can be exposed, and the vertical portion 220b of the second channel material layer 220p can be retained.

[0152] Reference Figure 30A and Figure 30B This can form a storage node SN.

[0153] Using area-selective deposition (ASD), a storage node SN can be formed on the exposed inner surface of the insulating material layer EL. The storage node SN can include a metal or a metal nitride. For example, the storage node SN can include titanium nitride, tungsten, ruthenium, molybdenum, etc. However, the example embodiments are not limited thereto.

[0154] Reference Figure 31A and Figure 31B A second channel material layer (or "horizontal portion 220a") may be formed on the opposite side of the storage node SN, thereby forming a channel structure 220. Next, a portion of the side of the storage node SN may be recessed and filled with insulating material to form an insulating capping layer 254.

[0155] Figure 33A and Figure 33B It is along Figure 32 The vertical cross-sectional view of lines I-I' and II-II' of the memory cell region shown.

[0156] Reference Figure 32 , Figure 33A and Figure 33B This can form a bit line BL.

[0157] Conductive material can be filled into the second trench TR2 to form bit lines BL. Bit lines BL can extend in a vertical direction and can be spaced apart in a first horizontal direction (e.g., the X direction).

[0158] Figure 35A and Figure 35B It is along Figure 34 The vertical cross-sectional view of lines I-I' and II-II' of the memory cell region shown.

[0159] Reference Figure 34 , Figure 35A and Figure 35B It can remove the molded insulating layer 171 and form an insulating structure 179 between vertically adjacent channel structures 220.

[0160] The molded insulating layer 171 can be removed, defining a second open region OR2. Thereafter, insulating material can be deposited on the insulating liner 173, the first channel material layer 120p (i.e., the active pattern 120), and the bit line BL to form an insulating liner. The insulating material can fill the spaces between vertically adjacent channel structures 220. Thereafter, a portion of the insulating liner can be removed to form an insulating structure 179 (which is part of the second molded insulating layer MD2).

[0161] Reference Figure 36A and Figure 36B A first gate dielectric layer 142, an insulating material layer 144p, an insulating liner 142', and a first molded insulating layer MD1 can be sequentially formed on the side of the bit line BL.

[0162] Reference Figure 37A and Figure 37B A first gate electrode layer 140 and a second gate capping layer 146 can be formed.

[0163] The insulating material layer can be removed. Figure 36A A portion of 144p) can be filled with a conductive material to form the first gate electrode layer 140. Therefore, a first gate structure including the first gate electrode layer 140 and the first gate dielectric layer 142 ( Figure 3A GS1) can be limited to reference Figure 35A and Figure 35B The second open region OR2 is described. Furthermore, by removing a portion of the insulating material layer, a first gate capping layer 144 can be defined.

[0164] A portion of the side surface of the first gate electrode layer 140 may be recessed and filled with an insulating material to form a second gate capping layer 146. The insulating material may include silicon oxide. Thereafter, a plate electrode layer PP may be formed, and a semiconductor device 100 (see [link to documentation]) may be provided. Figure 3A ).

[0165] According to some exemplary embodiments of the present invention, semiconductor devices with improved reliability and methods of manufacturing thereof can be provided.

[0166] Specifically, according to some exemplary embodiments of the present invention, a semiconductor device comprising a 2-transistor (2T) memory cell can be provided, the 2-transistor memory cell comprising a first transistor and a second transistor respectively.

[0167] More specifically, one of the first transistor and the second transistor may include a channel structure and a storage node connected to the channel structure to provide a semiconductor device that does not include a separate capacitor.

[0168] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the associated numerical value includes manufacturing or operational tolerances (e.g., ±10%) around said numerical value. Furthermore, when the terms “approximately” and “substantially” are used in conjunction with geometry, it is intended that the geometry is not required to be precise, but that the degrees of freedom of shape are within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said numerical value or shape. When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0169] The various advantages and effects of the present invention are not limited to those described above, and will be more readily understood in the process of describing specific embodiments of the present invention.

[0170] Although some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The position line extends in the vertical direction; as well as A two-transistor memory cell is located on at least one side of the bit line, the two-transistor memory cell comprising a first transistor and a second transistor on the first transistor. in, The first transistor includes: An active pattern, which contacts the bit line, the active pattern comprising: First source / drain region The second source / drain region, and The channel region, which lies between the first source / drain region and the second source / drain region, and A first gate structure includes a first gate electrode layer that overlaps with at least a portion of the channel region of the active pattern, and The second transistor includes: The second gate structure includes a second gate electrode layer. The channel structure that contacts the bit line includes: A first horizontal portion, which extends away from the bit line in a first horizontal direction from the portion that contacts the bit line, and The vertical portion extends vertically from one end of the first horizontal portion, and A storage node is located between the first gate electrode layer and the second gate electrode layer, and the storage node is connected to the channel structure.

2. The semiconductor device according to claim 1, wherein, The storage node is in contact with the vertical portion of the trench structure.

3. The semiconductor device according to claim 1, wherein, The end of the storage node has a convex shape facing the vertical portion of the channel structure.

4. The semiconductor device according to claim 1, wherein, The channel structure of the second transistor further includes a second horizontal portion connected to the vertical portion and extending toward the bit line in the first horizontal direction.

5. The semiconductor device according to claim 4, wherein, The storage node is in contact with the second horizontal portion of the channel structure.

6. The semiconductor device according to claim 4, wherein, The second horizontal portion of the channel structure is at the same level as the storage node.

7. The semiconductor device according to claim 1, wherein, The storage node comprises a metallic material or an oxide semiconductor, and The channel structure includes an oxide semiconductor.

8. The semiconductor device according to claim 1, wherein, The channel region of the active pattern comprises silicon (Si), and The channel structure includes an oxide semiconductor.

9. The semiconductor device according to claim 1, wherein, The storage node includes a first oxide semiconductor, and The channel structure includes a second oxide semiconductor having a carrier concentration different from that of the first oxide semiconductor.

10. The semiconductor device according to claim 1, wherein, The first gate electrode layer extends at the same level in a second horizontal direction, which intersects with the first horizontal direction.

11. The semiconductor device according to claim 1, wherein, The second gate electrode layer includes: The first part, which vertically overlaps with the storage node; and The second part is connected to the first part, and the second part has a thickness greater than that of the first part.

12. The semiconductor device according to claim 1, further comprising: A plate electrode layer, which is opposite to the bit line and in contact with at least one of the first source / drain region and the second source / drain region. The first gate structure further includes: A first gate dielectric layer, located between the active pattern and the first gate electrode layer, and A first gate capping layer is located between the first gate electrode layer and the plate electrode layer.

13. The semiconductor device according to claim 12, wherein, The side surface of the first gate electrode layer adjacent to the plate electrode layer has a concave profile.

14. The semiconductor device according to claim 1, wherein, The second gate structure further includes: A second gate dielectric layer is disposed between the channel structure and the second gate electrode layer, and the second gate dielectric layer is disposed between the memory node and the second gate electrode layer; and A second gate capping layer is located between the second gate electrode layer and the bit line.

15. The semiconductor device according to claim 14, wherein, The side surface of the second gate electrode layer adjacent to the bit line has a concave profile.

16. A semiconductor device, comprising: Multiple 2-transistor memory cells are arranged vertically on a substrate. in, Each of the plurality of 2-transistor memory cells includes: First transistor, The second transistor, and An insulating material layer is disposed between the first transistor and the second transistor. The first transistor includes: An active pattern that extends in the first horizontal direction. The active pattern includes: First source / drain region The second source / drain region, and The channel region, which lies between the first source / drain region and the second source / drain region, and The first gate electrode overlaps with at least a portion of the channel region of the active pattern, and The second transistor includes: Second gate electrode layer, The channel structure includes: The horizontal portion, which extends horizontally, and The vertical portion extends vertically from one end of the horizontal portion on the second gate electrode layer, and A storage node having at least a portion that vertically overlaps with the channel region and is connected to the channel structure.

17. The semiconductor device according to claim 16, wherein, The storage node overlaps with at least a portion of the first gate electrode in the first transistor and at least a portion of the active pattern.

18. The semiconductor device according to claim 16, wherein, The insulating material layer is located between the channel region of the first transistor and the memory node of the second transistor.

19. A semiconductor device, comprising: The position line extends in the vertical direction; The first transistor includes: The first active pattern includes a first channel region extending in a first horizontal direction on at least one side of the bit line, and A first gate electrode, which overlaps at least a portion of the first channel region; and The second transistor includes: The second active pattern is on the first transistor and includes a second channel region having horizontal and vertical portions. The second gate electrode overlaps with at least a portion of the second channel region, and A storage node that contacts the second active pattern and has at least a portion that vertically overlaps with the first channel region.

20. The semiconductor device of claim 19, further comprising: An insulating material layer is located between the first active pattern of the first transistor and the memory node of the second transistor.

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