Display panel

Abstract

A display panel is provided. The display panel includes a substrate, which includes an active region and an inactive region. A sub-pixel in the active region includes a light-emitting device, a driving transistor configured to supply driving current to the light-emitting device, and a switching transistor electrically connected to the driving transistor. Each of the driving transistor and the switching transistor includes a gate electrode and a semiconductor layer comprising oxide. A first interlayer insulating layer is located on the semiconductor layer of each transistor, and a second interlayer insulating layer is located on the first interlayer insulating layer. The thickness of the first interlayer insulating layer located on the semiconductor layer of the switching transistor is different from the thickness of the first interlayer insulating layer located on the semiconductor layer of the driving transistor. This structure allows the display panel to accommodate the different electrical characteristics required by the switching and driving transistors in each sub-pixel.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0196086, filed on December 24, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to a display panel. Background Technology

[0004] Display devices for displaying images are being used in various modes and types in televisions (TVs), monitors, smartphones, tablet PCs, and laptops.

[0005] The display device includes a display panel, which includes a plurality of light-emitting devices for realizing an image and a transistor for controlling the operation of each of the light-emitting devices or the operation of a liquid crystal, and displays an image to be displayed by the plurality of light-emitting devices or the liquid crystal.

[0006] The display device includes a plurality of pixels, each pixel including a light-emitting device, and further includes a plurality of driving and switching elements for driving and controlling the light-emitting device included in each pixel. The driving and switching elements may each be configured as transistors.

[0007] Recently, various research and developments have been conducted to improve the performance and reliability of transistors. Summary of the Invention

[0008] This disclosure relates to a display panel that uses a differentiated interlayer structure to optimize transistor performance based on transistor function and subpixel color. By adjusting the thickness and material composition of the upper interlayer insulating layers (such as silicon oxide and silicon nitride), this structure controls hydrogen diffusion into the oxide semiconductor layer. This approach allows the switching transistors to maintain longer channel lengths and stable threshold voltages, while the driving transistors for blue subpixels achieve higher on-current characteristics, and the driving transistors for green subpixels exhibit improved grayscale control through enhanced subthreshold oscillation.

[0009] The structure also includes a multi-layer buffer layer beneath the transistor, composed of dielectric materials with different properties, used to adjust capacitance and also support desired electrical characteristics. These targeted modifications across sub-pixel regions enable consistent and reliable transistor behavior, reducing power consumption, improving energy efficiency, and extending device durability.

[0010] For example, embodiments of this disclosure provide a display panel in which the interlayer structure is enhanced to suit the desired characteristics of each transistor.

[0011] For example, embodiments of this disclosure provide a display panel in which the interlayer structure is enhanced to suit the desired characteristics of each transistor.

[0012] Embodiments of this disclosure provide a display panel suitable for the desired characteristics of each switching transistor and driving transistor.

[0013] Embodiments of this disclosure provide a display panel suitable for the desired characteristics of the switching transistors in each sub-pixel.

[0014] Embodiments of this disclosure provide a display panel suitable for the desired characteristics of driving transistors that require relatively stable grayscale in each sub-pixel.

[0015] Embodiments of this disclosure provide a display panel suitable for the desired characteristics of drive transistors that require relatively high on-current (Ion) characteristics in each sub-pixel.

[0016] The embodiments disclosed herein can improve the reliability of transistors and display panels and reduce power consumption, thereby achieving environmental, social and governance (ESG) goals.

[0017] The display panel according to an embodiment of the present disclosure includes a substrate including an effective area and an ineffective area, a driving transistor configured to provide driving current to a light-emitting device disposed in a sub-pixel in the effective area and including a gate electrode and a semiconductor layer including an oxide layer, a switching transistor disposed in the sub-pixel and electrically connected to the driving transistor and including a gate electrode and a semiconductor layer including an oxide layer, a first upper interlayer insulating layer disposed on the semiconductor layer of each of the driving transistor and the switching transistor, and a second upper interlayer insulating layer disposed on the first upper interlayer insulating layer, wherein the thickness of the first upper interlayer insulating layer disposed on the semiconductor layer of the switching transistor is different from the thickness of the first upper interlayer insulating layer disposed on the semiconductor layer of the driving transistor. Attached Figure Description

[0018] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated in and constituting a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0019] Figure 1 These are diagrams used to describe embodiments of display devices applicable to this disclosure;

[0020] Figure 2 This is a diagram illustrating an embodiment of a pixel equivalent circuit suitable for a sub-pixel of a display device according to the present disclosure;

[0021] Figure 3This is a diagram illustrating an embodiment of the interlayer structure of a display panel including switching transistors and driving transistors according to a first embodiment of the present disclosure;

[0022] Figure 4 It is used to describe Figure 3 A graph showing the hydrogen concentration in the semiconductor layer of each of the switching transistors and the first and second driving transistors.

[0023] Figure 5 This is a diagram used to illustrate the difference in effective channel length and threshold voltage (Vth) between the switching transistor and the first driving transistor and the second driving transistor according to a second embodiment of the present disclosure;

[0024] Figure 6 It is a graph used to describe the S-factor and characteristic curves of the improved driving transistor according to the first embodiment of the present disclosure;

[0025] Figure 7 and Figure 8 This is a diagram illustrating an embodiment of the interlayer structure of a display panel including switching transistors and driving transistors according to a second embodiment of the present disclosure;

[0026] Figure 9 This is a diagram illustrating an embodiment of the interlayer structure of a display panel according to a first embodiment of the present disclosure, the display panel including transistors disposed in ineffective regions compared to transistors disposed in ineffective regions; and

[0027] Figure 10 This is a diagram illustrating an embodiment of the interlayer structure of a display panel according to an embodiment of the present disclosure, the display panel including low-temperature polycrystalline silicon (LTPS) transistors that can be further disposed in non-active regions. Detailed Implementation

[0028] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0029] The same reference numerals denote the same elements. The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, etc. shown in the drawings used to describe embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

[0030] For ease of description, dimensions including the size and thickness of each component shown in the figures are shown, and this disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions of the relative size, position and thickness of the components shown in the various figures submitted herein are part of this disclosure.

[0031] In this disclosure, when any element (or region, layer, part, etc.) is described as “conductive,” “connected,” or “coupled,” this may mean that the arbitrary element can be directly connected to / coupled to another element, or that a third element can be placed therein.

[0032] For clarity, the term “connection” as used herein is intended to have the broadest possible meaning. Specifically, the phrase “A connected to B” includes both direct connections (where no intermediate components or elements exist) and indirect connections (where one or more intermediate components or elements exist between A and B). In other words, “A connected to B” includes both direct physical or electrical coupling and indirect coupling via one or more intermediate components. Unless otherwise explicitly stated, these terms do not require direct physical or electrical contact. The terms “coupling” and “contact” should be interpreted in the same manner.

[0033] The term "and / or" can include all combinations that can be defined by the relevant elements.

[0034] Terms such as "first" and "second" may be used to describe various elements, but these elements should not be limited by these terms. These terms may be used only for the purpose of distinguishing one element from another. For example, without departing from the spirit and scope of the inventive concept, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless otherwise stated, singular terms may include plural forms.

[0035] The terms “down,” “below,” “up,” and “above” are used to describe the relationship between elements shown in the accompanying drawings. These terms can be relative concepts and can be described relative to the directions shown in the drawings. For example, one or more other elements may be placed between two elements unless “only” or “directly” is used. The spatially relative terms “down,” “below,” and “below,” “up,” and “above” can be used to readily describe the relationship between one device or element and other devices or elements shown in the figures. Thus, for example, for the first element, “down” and “below” can be the opposite of “up” and “above.”

[0036] It should be understood that, in addition to the orientations shown in the accompanying drawings, spatial relative terms also include terms that encompass different orientations of elements in use or operation. For example, if the device in the accompanying drawings is flipped, an element described as being located "below" or "below" to other elements can be placed "above" to other elements. Thus, the exemplary term "below" can include both "below" and "above" orientations. Similarly, the exemplary term "above" or "above" can include both "up" and "down" orientations.

[0037] It should be understood that "includes", "contains", "includes" or "contains" specifies an attribute, region, fixed number, step, process, element and / or component, but does not exclude other attributes, regions, fixed numbers, steps, processes, elements and / or components.

[0038] Those skilled in the art will fully understand that the features of the various embodiments of this disclosure may be partially or wholly coupled or combined with each other, and may interoperate and be technology-driven with each other in various ways. The embodiments of this disclosure may be performed independently of each other or together in an interdependent relationship.

[0039] In the following description, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0040] Figure 1 These are diagrams used to describe embodiments of display devices applicable to this disclosure. Figure 2 This is a diagram illustrating an embodiment of a pixel equivalent circuit for a sub-pixel SP suitable for a display device according to the present disclosure.

[0041] refer to Figure 1 and Figure 2 The display device according to the embodiments of the present disclosure may include a display panel 10, and the display panel 10 may include an effective area AA and an ineffective area NA.

[0042] The effective area AA can be the area for displaying an image. Multiple sub-pixels SP can be disposed at the intersections of the gate line GL and the data line DL in the effective area AA of the display panel 10, and the effective area AA can display an image using multiple sub-pixels SP. Figure 1 The effective area AA shows one sub-pixel SP, but multiple sub-pixels SP, including one sub-pixel SP, can be set in the effective area AA.

[0043] Multiple subpixels SP can include subpixel SPs that emit light of different colors. For example, subpixel SPs that emit red (R) light, subpixel SPs that emit green (G) light, and subpixel SPs that emit blue (B) light can be grouped to configure a unit pixel, and each unit pixel can achieve various colors by mixing the different colors of light emitted from the subpixel SPs.

[0044] The area where multiple sub-pixels SP are set can be a valid area AA, and the area other than the valid area AA can be a non-valid area NA.

[0045] The inactive area NA can be located in the edge region surrounding the active area AA of the displayed image. At least one driver for driving multiple sub-pixels SP can be located in the inactive area NA. The driver can be of the gate in panel (GIP) type.

[0046] Various additional elements used to drive the sub-pixel SP of the effective region AA can be further set in the ineffective region NA.

[0047] For example, such as Figure 2 As shown in part (a) or (b), at least one of the plurality of sub-pixels SP may include a first switching transistor ST1, a driving transistor DT, a capacitor Cst, and a light-emitting device OLED.

[0048] The first electrode (e.g., drain electrode) of the first switching transistor ST1 can be electrically connected to the data line DL, its second electrode (e.g., source electrode) can be electrically connected to the first node N1, and the gate electrode of the first switching transistor ST1 can be electrically connected to the gate line GL. The first switching transistor ST1 can transmit the data signal supplied through the data line DL to the first node N1 in response to the scan signal supplied through the gate line GL.

[0049] The capacitor Cst can be electrically connected to the first node N1 and can be charged with the voltage applied to the first node N1.

[0050] The first electrode (e.g., drain electrode) of the driving transistor DT can be supplied with a high-level driving voltage EVDD, and its second electrode (e.g., source electrode) can be electrically connected to the first electrode (e.g., anode electrode) of the light-emitting device OLED. The driving transistor DT can control the amplitude of the driving current flowing in the light-emitting device OLED based on the voltage applied to the gate electrode of the driving transistor DT.

[0051] The semiconductor layer of the first switching transistor ST1 and / or the driving transistor DT may include, but is not limited to, a semiconductor oxide such as indium gallium zinc oxide (IGZO).

[0052] OLEDs (Optical Display Panels) can emit light corresponding to the driving current. OLEDs can emit light corresponding to one of the colors red (R), green (G), blue (B), and white.

[0053] An OLED (Optical Display Panel) device may include an anode electrode, an emitter layer disposed on the anode electrode, and a cathode electrode that supplies a common voltage (such as a low-level drive voltage EVSS). The emitter layer may be configured to emit the same color of light, such as white light, for each pixel, or it may be configured to emit different colors of light, such as red (R), green (G), or blue (B), for each sub-pixel SP.

[0054] The light-emitting device OLED can be a top-emitting type diode or a bottom-emitting type diode.

[0055] exist Figure 2 In part (a), for example, a case is shown where the driving transistor DT is directly connected to the light-emitting device OLED, but this disclosure is not limited thereto, and as... Figure 2 As shown in part (b), the driving transistor DT can be connected to the light-emitting device OLED via the second switching transistor ST2.

[0056] In detail, such as Figure 2 As shown in part (b), a second switching transistor ST2 can be disposed between the driving transistor DT and the light-emitting device OLED. The first electrode of the second switching transistor ST2 can be connected to the driving transistor DT, and the second electrode of the second switching transistor ST2 can be electrically connected to the light-emitting device OLED. In response to an emission signal EM applied to the gate electrode of the second switching transistor ST2, the second switching transistor ST2 can control the on / off state of the driving current applied from the driving transistor DT to the light-emitting device OLED.

[0057] In addition, although not in Figure 2 As shown in sections (a) and (b), however, a compensation circuit (not shown) for compensating the threshold voltage of the driving transistor DT may be further included in the sub-pixel SP. The compensation circuit may include at least one transistor connected to the driving transistor DT and may be disposed in the sub-pixel SP.

[0058] Depending on the configuration type, the compensation circuit can have a 3T1C structure, in which three transistors and one capacitor Cst are included in the sub-pixel SP, or a 4T2C structure, in which four transistors and two capacitors Cst are included in the sub-pixel SP, or various structures such as 5T2C, 6T1C, 6T2C, 7T1C and 7T2C.

[0059] In addition, Figure 1 and Figure 2 In each sub-pixel SP shown, based on the narrow layout area, the first and second switching transistors may require relatively short channels compared to the driving transistors.

[0060] When a transistor has a relatively short channel, a roll-off phenomenon may occur where the transistor's threshold voltage Vth has a negative (-) value. In this case, the driving of the display panel 10 may be unstable.

[0061] Embodiments of this disclosure can improve the interlayer structure of the insulating layer disposed on each transistor to maximize the channel length of the switching transistor, and thus improve the reliability of the transistor and the display panel 10, and reduce power consumption.

[0062] Furthermore, each sub-pixel SP can change the characteristics of its driving transistor based on the color of the light emitted from it.

[0063] For example, green (G) may have a relatively larger impact on the color of light emitted from a unit pixel compared to red (R) or blue (B). Based on this, in embodiments of this disclosure, the interlayer structure of the insulating layer disposed beneath the driving transistor of the green (G) sub-pixel SP may differ from the interlayer structure of the insulating layer disposed beneath the driving transistor of the red (R) or blue (B) sub-pixel SP, in order to increase the subthreshold swing (S-factor) of the driving transistor included in the green (G) sub-pixel SP.

[0064] Furthermore, in each sub-pixel SP, the driving transistor of the blue (B) sub-pixel SP may require a relatively high on-state current (Ion) characteristic compared to the driving transistor of the green (G) sub-pixel SP. Based on this, in embodiments of this disclosure, the interlayer structure of the insulating layer disposed on the driving transistor of the blue (B) sub-pixel SP may differ from the interlayer structure of the insulating layer disposed on the driving transistor of the green (G) sub-pixel SP.

[0065] In the following, as described above, detailed embodiments of improving the interlayer structure of the insulating layer to improve the characteristics of the switching transistor and the driving transistor will be described.

[0066] Figure 3 This is a diagram illustrating an embodiment of the interlayer structure of a display panel including switching transistors and driving transistors according to a first embodiment of the present disclosure.

[0067] Figure 3 The interlayer structure of the display panel 10 shown according to an embodiment of the present disclosure represents the interlayer structure of each of the first sub-pixel SP1 and the second sub-pixel SP2 that emits light of different colors. For example... Figure 2 As shown in part (a), Figure 3 The illustration shows driving transistors DT1 and DT2, included in the first sub-pixel SP1 and the second sub-pixel SP2, electrically connected to the light-emitting device OLED; however, this disclosure is not limited thereto. For example, as... Figure 2 As shown in part (b), driving transistors DT1 and DT2 can be electrically connected to the light-emitting device OLED via switching transistor ST.

[0068] exist Figure 3 In the diagram, the switching transistor ST, which is included in both the first sub-pixel SP1 and the second sub-pixel SP2, is shown as a single transistor. Figure 3 The switching transistor ST shown can be Figure 2 One of the first switching transistor ST1 and the second switching transistor ST2. Figure 3 For example, it is shown that the switching transistor ST is... Figure 2 The situation of ST1 is described, but this disclosure is not limited to this, and Figure 3The switching transistor ST can be Figure 2 ST2.

[0069] Figure 3 The first sub-pixel SP1 and the second sub-pixel SP2 shown can be sub-pixels SP that emit light of different colors. For example, the first sub-pixel SP1 can be a sub-pixel SP that emits green (G) light, and the second sub-pixel SP2 can be a sub-pixel SP that emits blue (B) or red (R) light.

[0070] Therefore, in Figure 3 In the above, the first driving transistor DT1 can be a transistor that controls the amplitude of the driving current supplied to the green (G) light-emitting device OLED, and the second driving transistor DT2 can be a transistor that controls the amplitude of the driving current supplied to the blue (B) or red (R) light-emitting device OLED.

[0071] exist Figure 3 In this case, since green (G) has a relatively greater influence on the color of light emitted from a unit pixel than blue (B) or red (R), the case in which the first driving transistor DT1 is the transistor of the first sub-pixel SP1 that emits green (G) light and the second driving transistor DT2 is the transistor of the second sub-pixel SP2 that emits blue (B) or red (R) light is shown, but this disclosure is not limited thereto.

[0072] Figure 3 The display panel 10 shown according to an embodiment of the present disclosure may include a substrate 100, a substrate buffer layer 110, a first gate insulating layer 120, a lower interlayer insulating layer 130, a device buffer layer 140, a second gate insulating layer 150, an upper interlayer insulating layer 200, a planarization layer 300, a light-emitting device OLED, an encapsulation layer 500, a switching transistor ST, a first driving transistor DT1, and a second driving transistor DT2.

[0073] The substrate 100 may include a flexible plastic material and may also include a glass material with a flexible thickness. The substrate 100 may be disposed in the effective area AA and the ineffective area NA of the display panel 10.

[0074] The substrate 100 may have a multilayer structure including an insulating material. For example, the substrate 100 may include an insulating material and a polymeric material such as polyimide (PI).

[0075] The substrate buffer layer 110 can be disposed in the effective area AA and the ineffective area NA of the substrate 100. The substrate buffer layer 110 can protect the structure on the substrate 100 that is easily permeable by external water, and can planarize the surface of the substrate 100.

[0076] The substrate buffer layer 110 may include an insulating material, and may include, for example, inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx), and may include a multilayer structure comprising the same or different materials.

[0077] For example, the substrate buffer layer 110 may include multiple buffer layers 111a and 111b and an active buffer layer 112, which include different insulating materials and are stacked.

[0078] For example, multiple buffer layers 111a and 111b may include a first multiple buffer layer 111a and a second multiple buffer layer 111b. The first multiple buffer layer 111a may be disposed on the substrate 100 and may include silicon oxide (SiOx), and the second multiple buffer layer 111b may be disposed on the first multiple buffer layer 111a and may include silicon nitride (SiNx). An active buffer layer 112 may be disposed on the second multiple buffer layer 111b and may include SiOx.

[0079] The first gate insulating layer 120 may be disposed on the active buffer layer 112 of the substrate buffer layer 110. The first gate insulating layer 120 may include at least one inorganic insulating material selected from SiOx, SiNx, and silicon oxynitride (SiOxNy). The first gate insulating layer 120 may include SiOx.

[0080] The lower interlayer insulating layer 130 may be disposed on the first gate insulating layer 120 and may completely cover the effective area AA of the substrate 100. The lower interlayer insulating layer 130 may include an inorganic insulating material, and may include, for example, at least one inorganic layer selected from SiOx, SiNx, and SiOxNy. For example, the lower interlayer insulating layer 130 may include SiNx.

[0081] Device buffer layer 140 may be disposed on the underlying interlayer insulating layer 130. Device buffer layer 140 may include an inorganic insulating material. For example, device buffer layer 140 may include an inorganic insulating material such as SiOx or SiNx.

[0082] The device buffer layer 140 may have a multilayer structure comprising different materials. For example, the device buffer layer 140 may include a first device buffer layer 141, a second device buffer layer 142, and a third device buffer layer 143.

[0083] The third device buffer layer 143 may be disposed on the lower interlayer insulating layer 130, and may include, for example, SiOx. The second device buffer layer 142 may be disposed on the third device buffer layer 143, and may include, for example, SiNx. The first device buffer layer 141 may be disposed on the second device buffer layer 142, and may include, for example, SiOx.

[0084] The first device buffer layer 141 can be deposited on the second device buffer layer 142, and then a chemical mechanical polishing (CMP) process can be performed on the upper surface of the first device buffer layer 141 to planarize the surface.

[0085] Based on the CMP process on the first device buffer layer 141, the step height on the first device buffer layer 141 can be removed, and the first device buffer layer 141 can have a different thickness for each location. For example, the thickness of the first device buffer layer 141 disposed under the first driving transistor DT1 can be different from the thickness of the first device buffer layer 141 disposed under the switching transistor ST or the second driving transistor DT2.

[0086] The dielectric constants of the first device buffer layer 141 and the second device buffer layer 142 may be different. Due to the difference in dielectric constants between the first device buffer layer 141 and the second device buffer layer 142, the capacitance formed by the first device buffer layer 141 and the second device buffer layer 142 may be different based on the thickness of the first device buffer layer 141 and the second device buffer layer 142.

[0087] This disclosure allows adjustment of the capacitance formed by the first device buffer layer 141 and the second device buffer layer 142 by using the thickness difference between them, and thus the S-factor can be adjusted to suit the desired characteristics of each of the first driving transistor DT1 and the second driving transistor DT2 that supply driving current to an OLED emitting light of different colors. For example, the thicknesses of the first device buffer layer 141 and the second device buffer layer 142 can be different, and thus the S-factor of the target first driving transistor DT1 can be increased. This will be described in detail after the description of another layer of the display panel 10.

[0088] In this document, examples of methods for forming the thickness of a portion of the second device buffer layer 142 in different ways can be described as follows. First, the second device buffer layer 142 can be deposited on the third device buffer layer 143 with a uniform thickness. Then, a portion of the second device buffer layer 142 other than the portion overlapping with the first driving transistor DT1 (which is the target of the first driving transistor DT1 and the second driving transistor DT2) can be selectively etched using a mask (not shown). This allows the thickness of the portion of the second device buffer layer 142 other than the target portion to be formed relatively small.

[0089] Furthermore, an example of a method for forming a different thickness of the first device buffer layer 141 for each location can be described as follows. A first device buffer layer 141 with a uniform thickness can be deposited on a second device buffer layer 142 formed by differentiating thicknesses. Then, the upper surface of the first device buffer layer 141 can be planarized by performing a CMP process on the upper surface of the first device buffer layer 141, thereby forming a portion of the first device buffer layer 141 that overlaps with the target first driving transistor DT1 with a thickness smaller than the other portion.

[0090] The second gate insulating layer 150 may be disposed on the first device buffer layer 141, and the second gate insulating layer 150 may include at least one inorganic insulating material selected from SiOx, SiNx, and SiOxNy. For example, SiOx may include silicon dioxide (SiO2).

[0091] The second gate insulating layer 150 can insulate the gate electrode and semiconductor layer of the switching transistor ST from each other, and can also insulate the gate electrode and semiconductor layer of the first driving transistor DT1 and the second driving transistor DT2 from each other.

[0092] The upper interlayer insulating layer 200 can be disposed on the second gate insulating layer 150, and can insulate the gate electrode of the switching transistor ST from the gate electrodes of the first driving transistor DT1 and the second driving transistor DT2.

[0093] The upper interlayer insulation layer 200 can be formed as a multilayer structure comprising an insulating material such as SiOx, SiNx, or SiOxNy. For example, the upper interlayer insulation layer 200 may include a first upper interlayer insulation layer 210 and a second upper interlayer insulation layer 220.

[0094] The first upper interlayer insulating layer 210 may be disposed on the second gate insulating layer 150 and may include an inorganic insulating material (e.g., SiO2), such as SiOx.

[0095] The second upper interlayer insulating layer 220 may be disposed on the first upper interlayer insulating layer 210, and may include an inorganic insulating material different from the inorganic insulating material of the first upper interlayer insulating layer 210. For example, the second upper interlayer insulating layer 220 may include SiNx.

[0096] The hydrogen (H) content of the second upper interlayer insulating layer 220 can be higher than that of the first upper interlayer insulating layer 210. This disclosure can tailor device characteristics to suit the characteristics of each of the switching transistor ST and the first driving transistor DT1 and the second driving transistor DT2 by using the difference in hydrogen content between the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220.

[0097] For example, the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 can be different for each location. Therefore, the channel length of the switching transistor ST can be maximized, and the on-current (Ion) characteristics of the first driving transistor DT1 or the second driving transistor DT2 can be adjusted. This can be described in detail after describing another layer of the display panel 10.

[0098] In this document, an example of a method for forming a first device buffer layer 141 with a different thickness for each location can be described as follows. First, a first upper interlayer insulating layer 210 can be deposited on the second gate insulating layer 150 with a uniform thickness. Then, the thickness of a target portion of the first upper interlayer insulating layer 210 can be selectively etched, whereby the thickness of the first upper interlayer insulating layer 210 can be different for each portion.

[0099] For example, the selective etching method can initially and selectively etch a portion of the first upper interlayer insulating layer 210 disposed on the semiconductor layers of the first driving transistor DT1 and the second driving transistor DT2, without etching a portion of the first upper interlayer insulating layer 210 disposed on the semiconductor layer of the switching transistor ST. Then, a portion of the first upper interlayer insulating layer 210 disposed on the semiconductor layer of the second driving transistor DT2 can be etched a second time and selectively. Thus, the thickness of the first upper interlayer insulating layer 210 can be different for each portion.

[0100] Furthermore, an example of a method for forming a second upper interlayer insulating layer 220 with a different thickness for each location can be described as follows. A second upper interlayer insulating layer 220 with a uniform thickness can be deposited on the second device buffer layer 142, and then the upper surface of the second upper interlayer insulating layer 220 can be planarized by performing a CMP process on the upper surface of the second upper interlayer insulating layer 220, thereby allowing the thickness of the second upper interlayer insulating layer 220 to be different for each location.

[0101] As described above, after forming the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220, a heat-based annealing process can be performed. When performing the annealing process, hydrogen (H) can be doped into the semiconductor layers of the switching transistor ST, the first driving transistor DT1, and the second driving transistor DT2.

[0102] In this disclosure, since the thickness of each of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 can be different for each location, the concentration of hydrogen doping (H) can be different for each semiconductor layer, and thus, transistors with desired characteristics suitable for each element can be formed.

[0103] The planarization layer 300 may be disposed on the second upper interlayer insulating layer 220 and may include an insulating material. The planarization layer 300 can eliminate step heights caused by multiple transistors disposed in each sub-pixel SP. The upper surface of the planarization layer 300 may include a flat surface and may include a material with high fluidity. For example, the planarization layer 300 may include an organic insulating material.

[0104] The planarization layer 300 may include a multi-layer structure in which multiple layers are stacked, and for example, the planarization layer 300 may include a first planarization layer 310 and a second planarization layer 320 stacked in sequence, but is not limited thereto.

[0105] The first planarization layer 310 can remove the step height caused by drive circuitry such as the switching transistor ST and the first drive transistor DT1 and the second drive transistor DT2. The upper surface of each of the first planarization layer 310 and the second planarization layer 320 can include a flat surface. For this purpose, the first planarization layer 310 and the second planarization layer 320 can include organic insulating materials having the same or different flow properties.

[0106] The center electrode CE may be disposed between the first planarization layer 310 and the second planarization layer 320. The center electrode CE may include a conductive material, and may include at least one of metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0107] The center electrode CE can electrically connect the light-emitting device OLED and the driving transistors DT1 and DT2 to each other in each sub-pixel SP. For example, the center electrode CE can pass through the first planarization layer 310 and the second planarization layer 320, and can electrically connect the first electrode E1 (anode electrode) of the light-emitting device OLED and the driving transistors DT1 and DT2 to each other in each of the first sub-pixel SP1 and the second sub-pixel SP2.

[0108] The light-emitting device (OLED) can be disposed on the planarization layer 300 and can include a first electrode E1, an emission layer EL, and a second electrode E2. The OLED can emit light of one color: red (R), green (G), and blue (B). For example, the emission layer disposed in the first sub-pixel SP1 can emit green (G) light, and the emission layer disposed in the second sub-pixel SP2 can emit blue (B) or red (R) light.

[0109] The first electrode E1 can, for example, be used as an anode electrode and can include a conductive material. The first electrode E1 can have high reflectivity. For example, the first electrode E1 can include metals such as Al and silver (Ag). The first electrode E1 can have a multilayer structure. For instance, the first electrode E1 can have a structure in which reflective electrodes, including metals, are disposed between transparent electrodes including transparent conductive materials (such as indium tin oxide (ITO) or indium zinc oxide (IZO)).

[0110] The emitting layer EL can generate light with a brightness corresponding to the voltage difference between the first electrode E1 and the second electrode E2. For example, the emitting layer EL may include an emissive material layer (EML) containing an emissive material. The emissive material may include organic materials, inorganic materials, or hybrid materials. For example, the emitting layer EL may include an emissive material layer containing an organic material.

[0111] The emitter layer EL may include at least one of a first emitter common layer (not shown) disposed between the first electrodes E1 and a second emitter common layer (not shown) disposed between the second electrodes E2. Each of the first emitter common layer (not shown) and the second emitter common layer (not shown) may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0112] For example, the second electrode E2 can be used as a cathode electrode and can include a conductive material. The second electrode E2 can include a material different from that of the first electrode E1. For example, the second electrode E2 can be a transparent electrode including a transparent conductive material such as ITO or IZO. The transmittance of the second electrode E2 can be higher than that of the first electrode E1. Therefore, in the display panel 10 according to an embodiment of the present disclosure, light generated by the emitting layer EL can be emitted through the second electrode E2.

[0113] The encapsulation layer 500 can be disposed on the light-emitting device OLED. The encapsulation layer 500 can prevent damage to the light-emitting device OLED caused by external impact and water. The encapsulation layer 500 can have a multilayer structure. For example, the encapsulation layer 500 can be provided by alternately stacking encapsulation layers 500 comprising inorganic insulating materials and encapsulation layers 500 comprising organic insulating materials.

[0114] Therefore, in the display panel 10 according to the embodiments of the present disclosure, damage to the light-emitting device OLED caused by external impact and water can be effectively prevented.

[0115] The first driving transistor DT1 can control the driving current supplied to the light-emitting device OLED that emits green (G) light to the first sub-pixel SP1, and may include a first gate electrode G1, a first semiconductor layer ACT1, a first source electrode SD1a, a first drain electrode SD1b and a first metal layer LS1.

[0116] The second driving transistor DT2 can control the driving current supplied to the light-emitting device OLED that emits red (R) or blue (B) light to the second sub-pixel SP2, and may include a second gate electrode G2, a second semiconductor layer ACT2, a second source electrode SD2a, a second drain electrode SD2b, and a second metal layer LS2.

[0117] The switching transistor ST can be electrically connected to the driving transistor in each of the first sub-pixel SP1 or the second sub-pixel SP2 to configure Figure 2 The pixel circuit shown in part (a) may include a third gate electrode G3, a third semiconductor layer ACT3, a third source electrode SD3a, a third drain electrode SD3b and a third metal layer LS3.

[0118] The first gate electrode G1 to the third gate electrode G3 may be disposed between the second gate insulating layer 150 and the first upper interlayer insulating layer 210. The first gate electrode G1 to the third gate electrode G3 may include a conductive material, and may include at least one of metals such as Al, Cr, Cu, Ti, Mo and W.

[0119] The first gate electrode G1 to the third gate electrode G3 can be controlled based on the voltage applied thereto to control the process of forming channels in the first to third semiconductor layers ACT1 to ACT3 of transistors D1, D2 and ST.

[0120] The first semiconductor layer ACT1 to the third semiconductor layer ACT3 can be disposed between the second gate insulating layer 150 and the first device buffer layer 141, and can overlap with the first gate electrode G1 to the third gate electrode G3 respectively. The first semiconductor layer ACT1 to the third semiconductor layer ACT3 can form channels therein based on the first gate electrode G1 to the third gate electrode G3.

[0121] The first active layer ACT1 to the third active layer ACT3 may comprise an oxide semiconductor material. The oxide semiconductor material may comprise at least one of the following: InZnO (IZO)-based, InGaO (IGO)-based, InSnO (ITO)-based, InGaZnO (IGZO)-based, InGaZnSnO (IGZTO)-based, GaZnSnO (GZTO)-based, GaZnO (GZO)-based, InSnZnO (ITZO)-based, and FeInZnO (FIZO)-based oxide semiconductor materials. The first active layer ACT1 to the third active layer ACT3 may each be configured as a single layer or multiple layers comprising at least one oxide semiconductor.

[0122] The first active layer ACT1 to the third active layer ACT3 may include a channel region and conductive regions disposed on both sides with the channel region located therebetween. The first to third channel regions of the first active layer ACT1 to the third active layer ACT3 ( Figure 4 CH1 to CH3 can be configured to overlap with the first gate electrode G1 to the third gate electrode G3 respectively, and the conductive region can be configured in the region of the first active layer ACT1 to the third active layer ACT3 that does not overlap with the first gate electrode G1 to the third gate electrode G3.

[0123] One of the conductive regions in the first active layer ACT1 to the third active layer ACT3 can be the first source region to the third source region. Figure 4 AS1 to AS3), and another conductive region may be the first drain region to the third drain region ( Figure 4 (AD1 to AD3). Each of the first active layers ACT1 to the third active layer ACT3 can form a conductive region by using hydrogen as a dopant. Therefore, the conductive region in each of the first active layers ACT1 to the third active layer ACT3 can be doped with a high concentration of hydrogen (H), and the channel region can be doped with hydrogen (H) at a lower concentration than that in the conductive region.

[0124] In this disclosure, the concentration of hydrogen doped in the conductive regions of the first active layer ACT1 to the third active layer ACT3 can be different. This will be referred to below. Figure 4 Describe it.

[0125] Each of the first source electrode SD1a to the third source electrode SD3a and the first drain electrode SD1b to the third drain electrode SD3b can be disposed between the second upper interlayer insulating layer 220 and the first planarization layer 310, and can contact the conductive region of each of the first active layers ACT1 to the third active layers ACT3. For example, each of the first source electrode SD1a to the third source electrode SD3a and the first drain electrode SD1b to the third drain electrode SD3b can pass through the second upper interlayer insulating layer 220 and the second gate insulating layer 150, and can contact the conductive region of each of the first active layers ACT1 to the third active layers ACT3.

[0126] The first source electrode SD1a to the third source electrode SD3a and the first drain electrode SD1b to the third drain electrode SD3b may comprise the same material, and may comprise, for example, at least one of metals such as Al, Cr, Cu, Ti, Mo and W.

[0127] A first metal layer LS1 and a second metal layer LS2 can be disposed between a second device buffer layer 142 and a third device buffer layer 143. The first metal layer LS1 can overlap with the first semiconductor layer ACT1, and the second metal layer LS2 can overlap with the second semiconductor layer ACT2. The first metal layer LS1 and the second metal layer LS2 can block external light incident on the first semiconductor layer ACT1 and the second semiconductor layer ACT2.

[0128] The first metal layer LS1 and the second metal layer LS2 can pass through the upper interlayer insulating layer 200, the second gate insulating layer 150, and the first device buffer layer 141 and the second device buffer layer 142, and can respectively contact the first drain electrode SD1b and the second drain electrode SD2b. The first metal layer LS1 and the second metal layer LS2 can include the same conductive material.

[0129] A third metal layer LS3 may be disposed between the first gate insulating layer 120 and the lower interlayer insulating layer 130, and may overlap with the third semiconductor layer ACT3. The third metal layer LS3 may block external light incident on the third semiconductor layer ACT3, and although not shown, may be electrically connected to the third gate electrode G3. Therefore, the third metal layer LS3 may serve as the bottom gate electrode. The third metal layer LS3 may comprise a conductive material different from the conductive material of each of the first metal layer LS1 and the second metal layer LS2.

[0130] In this interlayer structure of the display panel 10, the present disclosure can form conductive regions of the first semiconductor layer ACT1 to the third semiconductor layer ACT3 by hydrogen doping, and can allow different hydrogen contents and movement distances in the layers disposed above or below the first semiconductor layer ACT1 to the third semiconductor layer ACT3, and thus can ensure device performance based on the desired characteristics of each transistor.

[0131] In the following text, for ease of description, an upper interlayer insulating layer or device buffer layer configured to overlap on or under the semiconductor layer of a particular transistor may be referred to as "the upper interlayer insulating layer or device buffer layer of a particular transistor".

[0132] In this disclosure, the thickness TSL1 of the first upper interlayer insulating layer 210 disposed on the semiconductor layer of the switching transistor ST may be different from the thicknesses TGL1 and TBL1 of the first upper interlayer insulating layer 210 disposed on the semiconductor layers of the driving transistors DT1 and DT2.

[0133] The thickness TSL1 of the first upper interlayer insulating layer 210 of the switching transistor ST can be greater than the thicknesses TGL1 and TBL1 of the first upper interlayer insulating layer 210 of the driving transistors DT1 and DT2.

[0134] Therefore, in the process of depositing the second upper interlayer insulating layer 220, the distance that hydrogen travels from the second upper interlayer insulating layer 220 of the switching transistor ST to the third semiconductor layer ACT3 can be relatively longer than the distance that hydrogen travels from the second upper interlayer insulating layer 220 of the driving transistors DT1 and DT2 to the first semiconductor layer ACT1 and the second semiconductor layer ACT2. Furthermore, the concentration of hydrogen doped in the conductive region of the third semiconductor layer ACT3 of the switching transistor ST can be less than the concentration of hydrogen doped in the conductive regions of the first semiconductor layer ACT1 and the second semiconductor layer ACT2.

[0135] Therefore, the amount of hydrogen diffused into the interior of the third gate electrode G3 in the third semiconductor layer ACT3 of the switching transistor ST can be relatively small, thus maximizing the channel region formed in the third semiconductor layer ACT3.

[0136] Furthermore, in this disclosure, the thickness TSL2 of the second upper interlayer insulating layer 220 of the switching transistor ST can be different from the thicknesses TGL2 and TBL2 of the second upper interlayer insulating layer 220 of the first driving transistor DT1 and the second driving transistor DT2. For example, the thickness TSL2 of the second upper interlayer insulating layer 220 of the switching transistor ST can be less than the thicknesses TGL2 and TBL2 of the second upper interlayer insulating layer 220 of the first driving transistor DT1 and the second driving transistor DT2.

[0137] Furthermore, in the switching transistor ST, the thickness TSL1 of the first upper interlayer insulating layer 210 can be greater than the thickness TSL2 of the second upper interlayer insulating layer 220.

[0138] As described above, the hydrogen (H) content of the second upper interlayer insulating layer 220 can be greater than the hydrogen content of the first upper interlayer insulating layer 210. After the second upper interlayer insulating layer 220 is deposited on the first upper interlayer insulating layer 210, a CMP process can be performed on the second upper interlayer insulating layer 220, and then hydrogen can be doped by an annealing process. That is, the hydrogen included in the second upper interlayer insulating layer 220 can be doped into the first semiconductor layer ACT1 to the third semiconductor layer ACT3 during the annealing process.

[0139] The second upper interlayer insulating layer 220 of the switching transistor ST can have a relatively small thickness TSL2, and when the annealing process is performed, the amount of hydrogen doped in the third semiconductor layer ACT3 of the switching transistor ST can be less than the amount of hydrogen doped in the first semiconductor layer ACT1 and the second semiconductor layer ACT2 of the first driving transistor DT1 and the second driving transistor DT2.

[0140] Therefore, the amount of hydrogen diffused into the third semiconductor layer ACT3 of the switching transistor ST can be relatively small, and the diffusion of hydrogen into the lower part of the third gate electrode G3 in the third semiconductor layer ACT3 can be minimized.

[0141] Therefore, the reduction of the channel region CH3 in the third semiconductor layer ACT3 can be minimized, and the channel length of the switching transistor ST with a relatively short channel can be maximized.

[0142] The first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 may include different materials, and for example, the first upper interlayer insulating layer 210 may include SiOx and the second upper interlayer insulating layer 220 may include SiNx.

[0143] Furthermore, the thickness TGL1 of the first upper interlayer insulating layer 210 of the first driving transistor DT1 may be different from the thickness TBL1 of the first upper interlayer insulating layer 210 of the second driving transistor DT2, and the thickness TGL2 of the second upper interlayer insulating layer 220 of the first driving transistor DT1 may be different from the thickness TBL2 of the second upper interlayer insulating layer 220 of the second driving transistor DT2.

[0144] For example, the thickness TBL1 of the first upper interlayer insulating layer 210 of the second driving transistor DT2 can be less than the thickness TGL1 of the first upper interlayer insulating layer 210 of the first driving transistor DT1, and the thickness TBL2 of the second upper interlayer insulating layer 220 of the second driving transistor DT2 can be greater than the thickness TGL2 of the second upper interlayer insulating layer 220 of the first driving transistor DT1.

[0145] Furthermore, in the second driving transistor DT2, the thickness TBL2 of the second upper interlayer insulating layer 220 can be greater than the thickness TBL1 of the first upper interlayer insulating layer 210.

[0146] When the second driving transistor DT2 of the second sub-pixel SP2 controls the driving current of the OLED that emits blue (B) light, the second driving transistor DT2 may require a higher on-current (Ion) characteristic than the OLED that emits green (G) light.

[0147] Based on this, in the present disclosure, the thickness TBL2 of the second upper interlayer insulating layer 220 in the second driving transistor DT2 can be relatively large, and the thickness TBL1 of the first upper interlayer insulating layer 210 can be relatively small. Therefore, a relatively large amount of hydrogen can be doped in the second semiconductor layer ACT2, thereby responding to the relatively high on-current (Ion) characteristics of the second driving transistor DT2.

[0148] In this disclosure, as described above, based on the thickness of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220, a CMP process can be performed on the second upper interlayer insulating layer 220, and therefore, in each of the switching transistor ST and the first driving transistor DT1 and the second driving transistor DT2, the second upper interlayer insulating layer 220 may have the same height level (or in other words, "in a common plane", or "have a top surface at a uniform height", or "have a coplanar top surface"), and may each include a planarized upper surface.

[0149] Therefore, in each region where the switching transistor ST, the first driving transistor DT1, and the second driving transistor DT2 are configured, the thickness T1 from the upper surface of the first device buffer layer 141 to the upper surface of the second upper interlayer insulating layer 220 can be uniform and equal.

[0150] The first device buffer layer 141 and the second device buffer layer 142 may have different dielectric constants and may comprise different inorganic insulating materials. For example, the first device buffer layer 141 may comprise SiOx, and the second device buffer layer 142 may comprise SiNx.

[0151] In this disclosure, the thicknesses of the first device buffer layer 141 and the second device buffer layer 142 may be different based on the dielectric constant characteristics of each of the first device buffer layer 141 and the second device buffer layer 142, in order to suit the desired characteristics of each of the first driving transistor DT1 and the second driving transistor DT2.

[0152] In detail, in this disclosure, in order to further increase the S factor of the first driving transistor DT1, the thickness TGB1 of the first device buffer layer 141 of the first driving transistor DT1 may be different from the thickness TBB1 of the first device buffer layer 141 of the second driving transistor DT2, and the thickness TGB2 of the second device buffer layer 142 of the first driving transistor DT1 may be different from the thickness TBB2 of the second device buffer layer 142 of the second driving transistor DT2.

[0153] For example, the thickness TGB1 of the first device buffer layer 141 of the first driving transistor DT1 may be less than the thickness TBB1 of the first device buffer layer 141 of the second driving transistor DT2, and the thickness TGB2 of the second device buffer layer 142 of the first driving transistor DT1 may be greater than the thickness TBB2 of the second device buffer layer 142 of the second driving transistor DT2.

[0154] Furthermore, below the first driving transistor DT1, the thickness TGB1 of the first device buffer layer 141 can be less than the thickness TGB2 of the second device buffer layer 142, and the thicknesses TBB1 and TBB2 of the first device buffer layer 141 and the second device buffer layer 142 disposed below the second driving transistor DT2 can be equal to the thicknesses TSB1 and TSB2 of the first device buffer layer 141 and the second device buffer layer 142 disposed below the switching transistor ST.

[0155] In this disclosure, as described above, the thickness TGB1 of the first device buffer layer 141 below the first driving transistor DT1 can be relatively small, and the thickness TGB2 of the second device buffer layer 142 can be relatively large. Therefore, the S-factor of the first driving transistor DT1, which has a relatively large influence on the color of a unit pixel, can be increased more, and the grayscale representation of the color of the light emitted from the unit pixel can be controlled more stably.

[0156] The first device buffer layer 141 and the second device buffer layer 142 can be respectively disposed between the first semiconductor layer ACT1 and the second semiconductor layer ACT2 and the first metal layer LS1 and the second metal layer LS2, and thus can form a capacitor.

[0157] The first device buffer layer 141 and the second device buffer layer 142 may comprise different materials and therefore may differ in dielectric constant. Furthermore, even when the distances between the first semiconductor layer ACT1 and the second semiconductor layer ACT2 and the first metal layer LS1 and the second metal layer LS2 are equal to each other, capacitors C1b and C2b may be formed differently based on the thicknesses of the first device buffer layer 141 and the second device buffer layer 142.

[0158] The first device buffer layer 141, including SiOx, can increase the capacitance of the capacitor as the thickness of the capacitor decreases, and furthermore, the capacitance of the capacitor can decrease as the thickness of the capacitor increases.

[0159] The second device buffer layer 142, which includes SiNx, can increase the capacitance of the capacitor as the thickness of the capacitor increases, and furthermore, the capacitance of the capacitor can decrease as the thickness of the capacitor decreases.

[0160] Therefore, the buffer capacitances C1b and C2b of the device buffer layer 140, which includes the first device buffer layer 141 and the second device buffer layer 142, can increase as the thickness of the first device buffer layer 141 decreases, and can increase as the thickness of the second device buffer layer 142 increases.

[0161] Furthermore, the S-factor of each of the first driving transistors DT1 and DT2 can be determined based on the ratio of the first gate capacitance C1a and the second gate capacitance C2a between each gate electrode and each semiconductor layer to the first buffer capacitance C1b and the second buffer capacitance C2b between each semiconductor layer and each metal layer.

[0162] In detail, the S-factor of each of the first driving transistor DT1 and the second driving transistor DT2 can increase as the first buffer capacitor C1b and the second buffer capacitor C2b increase relative to the first gate capacitor C1a and the second gate capacitor C2a.

[0163] This disclosure allows adjustment of the thickness of each of the first device buffer layer 141 and the second device buffer layer 142 by using the relationship between the S-factor, the gate capacitor, and the buffer capacitor, and thus the S-factor of the target transistors in the first driving transistor DT1 and the second driving transistor DT2 can be adjusted.

[0164] exist Figure 3 In the example shown, with the first driving transistor DT1 as the target, the thickness TGB1 of the first device buffer layer 141 of the first driving transistor DT1 is relatively small, and the thickness TGB2 of the second device buffer layer 142 is relatively large. Therefore, the capacitance of the first buffer capacitor C1b is relatively large, and the S factor of the first driving transistor DT1 is increased.

[0165] Furthermore, an example is shown in which the thicknesses TBB1 and TBB2 of the first device buffer layer 141 and the second device buffer layer 142 of the non-targeted second driving transistor DT2 are equal to the thicknesses TSB1 and TSB2 of the first device buffer layer 141 and the second device buffer layer 142 of the switching transistor SD.

[0166] In this disclosure, as described above, based on the thickness of the first device buffer layer 141 and the second device buffer layer 142, a CMP process can be performed on the first device buffer layer 141. Therefore, the first device buffer layer 141 disposed below the switching transistor ST and the first device buffer layer 141 disposed below the first driving transistor DT1 and the second driving transistor DT2 can each include a planarized upper surface, and the semiconductor layer of the switching transistor ST and the semiconductor layer included in the first driving transistor DT1 and the second driving transistor DT2 can be disposed on the first device buffer layer 141 having the same height level.

[0167] Therefore, in each region where the switching transistor ST, the first driving transistor DT1, and the second driving transistor DT2 are disposed, the thickness T2 from the upper surface of the substrate 100 to the upper surface of the first device buffer layer 141 can be uniform and equal.

[0168] As described above, in the first embodiment of this disclosure, in the switching transistor ST which requires a relatively short channel length in each sub-pixel SP, the thickness TSL1 of the first upper interlayer insulating layer 210 can be set to be relatively large, and the thickness TSL2 of the second upper interlayer insulating layer 220 can be set to be relatively small. Therefore, the concentration of hydrogen doped in the semiconductor layer of the switching transistor ST can be reduced, thereby maximizing the channel of the switching transistor ST and allowing the threshold voltage (Vth) of the switching transistor ST to be positively offset (+offset).

[0169] Furthermore, in the first embodiment of this disclosure, in the first driving transistor DT1 that requires relatively stable grayscale performance in each sub-pixel SP, the thickness TGB1 of the first device buffer layer 141 can be set to be relatively small, and the thickness TGB2 of the second device buffer layer 142 can be set to be relatively large. Therefore, the S-factor of the first driving transistor DT1 can be increased, thereby making the grayscale performance of the unit pixel more stable.

[0170] Furthermore, in the first embodiment of this disclosure, in the second driving transistor DT2 which requires a relatively high on-current (Ion) characteristic in each sub-pixel SP, the thickness TBL1 of the first upper interlayer insulating layer 210 can be set to be relatively small, and the thickness TBL2 of the second upper interlayer insulating layer 220 can be set to be relatively large. Therefore, the concentration of hydrogen doped in the semiconductor layers of the first driving transistor DT1 and the second driving transistor DT2 can be increased, thereby responding to the high on-current (Ion) characteristic of the semiconductor layer of the second driving transistor DT2 and reducing power consumption.

[0171] The following will describe the hydrogen concentration, threshold voltage, and S-factor of the semiconductor layer of each of the switching transistor ST, the first driving transistor DT1, and the second driving transistor DT2.

[0172] Figure 4 It is used to describe Figure 3 A graph showing the hydrogen concentration in the semiconductor layer of each of the switching transistor, the first driving transistor, and the second driving transistor.

[0173] Figure 4 Part (a) is a graph showing the concentration of hydrogen (H) doped in the third semiconductor layer ACT3 of the switching transistor ST. Figure 4 Part (b) is a graph showing the concentration of hydrogen (H) doped in the first semiconductor layer ACT1 of the first driving transistor DT1, and Figure 4 Part (c) is a graph showing the concentration of hydrogen (H) doped in the second semiconductor layer ACT2 of the second driving transistor DT2.

[0174] like Figure 4 As shown in part (a), in the third semiconductor layer ACT3 of the switching transistor ST, the amount of hydrogen doped from the second upper interlayer insulating layer 220 can be relatively small. Therefore, the hydrogen concentration HS doped in the third source region AS3 and the third drain region AD3 can be less than [amount missing]. Figure 4 Part (b) of the first driving transistor DT1 hydrogen concentration HD1 and Figure 4 The hydrogen concentration HD2 of the second driving transistor DT2 in part (c).

[0175] In addition, such as Figure 4 As shown in part (c), in the second semiconductor layer ACT2 of the second driving transistor DT2, the amount of hydrogen doped from the second upper interlayer insulating layer 220 can be relatively large. Therefore, the hydrogen concentration HD2 doped in the second source region AS2 and the second drain region AD2 can be higher than that of the second semiconductor layer ACT2. Figure 4 The hydrogen concentration of the first driving transistor DT1 in part (b) is HD1.

[0176] In addition, such as Figure 4 As shown in part (b), in the first semiconductor layer ACT1 of the second driving transistor DT1, the amount of hydrogen doped from the second upper interlayer insulating layer 220 can have an intermediate value, and therefore, the hydrogen concentration HD1 doped in the first source region AS1 and the first drain region AD1 can have Figure 4 The hydrogen concentration HD1 of the first driving transistor DT1 in part (a) is related to... Figure 4 The intermediate value between the hydrogen concentration HS of the second driving transistor DT2 in part (c).

[0177] Figure 5 This is a diagram used to illustrate the difference in effective channel length and threshold voltage (Vth) between the switching transistor and the first driving transistor and the second driving transistor according to a second embodiment of the present disclosure.

[0178] Figure 5 Part (a) shows the difference in effective channel length and threshold voltage (Vth) between the switching transistor ST and the driving transistor DT in the portion where the switching transistor ST and the driving transistor DT are disposed in each sub-pixel, with the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 being equal to each other.

[0179] like Figure 5 As shown in part (a), when the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the switching transistor ST and the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the driving transistor DT are equal to each other, the effective length of the channel formed in the semiconductor layer of the switching transistor ST can have a first length L1, and the effective length of the channel formed in the semiconductor layer of the driving transistor DT can have a second length L2.

[0180] In this case, the threshold voltage Vth of the switching transistor ST can have a first voltage V1, and the threshold voltage Vth of the driving transistor DT can have a second voltage V2 that is higher than the first voltage V1.

[0181] Therefore, as Figure 5 As shown in part (a), when the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the switching transistor ST and the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the driving transistor DT are equal to each other, the effective length difference of the channel between the switching transistor ST and the driving transistor DT can be ΔL, and the difference of their threshold voltage Vth can be ΔV1.

[0182] On the other hand, as mentioned above, such as Figure 5As shown in part (b), when the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the switching transistor ST and the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the driving transistor DT are different for each location, this disclosure can increase the effective channel length of the switching transistor ST from L1 to L1', and can also increase the threshold voltage Vth from V1 to V1'.

[0183] That is, as mentioned above. Figure 3 According to the present disclosure, the thickness TSL2 of the second upper interlayer insulating layer 220 of the switching transistor ST (where the hydrogen content is high) can be relatively smaller than TGL2 and TBL2, and the thickness TSL1 of the first upper interlayer insulating layer 210 of the switching transistor ST (where the hydrogen content is lower than that of the second upper interlayer insulating layer 220) can be relatively larger than TGL1 and TBL1. Therefore, the moving distance of hydrogen from the second upper interlayer insulating layer 220 to the third semiconductor layer ACT3 of the switching transistor ST can be increased, and the hydrogen concentration can be relatively reduced.

[0184] Therefore, the amount of hydrogen doped in the third semiconductor layer ACT3 of the switching transistor ST can be less than the amount of hydrogen doped in the first semiconductor layer ACT1 and the second semiconductor layer ACT2 of the first driving transistor DT1 and the second driving transistor DT2.

[0185] Therefore, the diffusion of hydrogen doped in the third semiconductor layer ACT3 to the lower part of the third gate electrode G3 can be minimized, and the reduction of the channel region CH3 of the third semiconductor layer ACT3 can be minimized.

[0186] As a result, with Figure 5 Compare part (a), such as Figure 5 As shown in part (b), this disclosure can form the channel region CH3 of the switching transistor ST by L1' which is greater than L1, and can increase the threshold voltage Vth of the switching transistor ST from V1 to V1'.

[0187] Therefore, according to this disclosure, in the part where the switching transistor ST and the driving transistor DT are configured, the thickness of the first upper layer interlayer insulating layer 210 and the second upper layer interlayer insulating layer 220 can be different for each location, and thus, the effective length difference of the channel between the switching transistor ST and the driving transistor DT can be reduced from ΔL to ΔLp, and the difference in threshold voltage Vth between them can be reduced from ΔV1 to ΔVp.

[0188] like Figure 5As shown in part (a), when the threshold voltage difference between the switching transistor ST and the first driving transistor DT1 and the second driving transistor DT2 has a difference ΔV1, a reliability problem may occur in the pixel driving circuit when the threshold voltage Vth of each of the first driving transistor DT1 and the second driving transistor DT2 is positively offset.

[0189] Furthermore, even when the threshold voltage Vth of each of the first driving transistor DT1 and the second driving transistor DT2 is negatively offset by adjusting the drive signal to improve reliability, the threshold voltage Vth of the switching transistor ST may also shift together, leading to problems.

[0190] However, according to this disclosure, the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the switching transistor ST can be different from the thicknesses of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the first driving transistor DT1 and the second driving transistor DT2. Therefore, the difference in effective channel length ΔLp can be reduced. Thus, this disclosure can more stably ensure the reliability of the pixel driving circuit.

[0191] Figure 6 It is a graph used to describe the S-factor and characteristic curves of the improved driving transistor according to the first embodiment of the present disclosure.

[0192] Figure 6 Part (a) is a characteristic curve of a general driving transistor that does not apply to embodiments of this disclosure, and Figure 6 Part (b) is shown relative to Figure 6 Part (a) shows the characteristic curve of the driving transistor's S-factor.

[0193] like Figure 6 As shown in part (a), the characteristic diagram of a typical driving transistor represents the relationship between the driving current Ids and the gate-source voltage Vgs, and... Figure 6 In part (a), B represents the characteristic map of the driving transistor of the blue (B) sub-pixel, and G represents the characteristic map of the driving transistor of the green (G) sub-pixel.

[0194] exist Figure 6 In part (a), when the Vgs voltage has its maximum value, the value of the drive current Ids can be referred to as the on-state current Ion. In general, the on-state current (Ion) value of the drive transistor of the blue (B) sub-pixel can be Ib, and can have a value greater than Ig, which is the on-state current (Ion) value of the drive transistor of the green (G) sub-pixel.

[0195] The on-current (Ion) value of the driving transistor for the blue (B) subpixel can be a value associated with an OLED that emits blue (B) light, and can have the characteristics required for the driving transistor of the blue (B) subpixel.

[0196] According to this disclosure, based on the characteristics required for the driving transistor of the blue (B) sub-pixel, the thickness of the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the second driving transistor DT2 can be adjusted in the second sub-pixel SP2 that emits blue (B) light. Therefore, the concentration of hydrogen doped in the second semiconductor layer ACT2 of the second driving transistor DT2 can be relatively large, thereby reducing the power consumption of the second driving transistor DT2.

[0197] In detail, as referenced above Figure 3 In the second driving transistor DT2, the thickness TBL2 of the second upper interlayer insulating layer 220, which has a high hydrogen content, can be relatively large, while the thickness TBL1 of the first upper interlayer insulating layer 210, which has a low hydrogen content, can be relatively small. Therefore, a relatively large amount of hydrogen can be doped into the second semiconductor layer ACT2. Consequently, a relatively large amount of hydrogen can be doped into the second semiconductor layer ACT2 of the second driving transistor DT2, which requires relatively high on-current (Ion) characteristics, thus increasing the carrier concentration of the second semiconductor layer ACT2.

[0198] Therefore, this disclosure enables the high on-current (Ion) characteristic of the second drive transistor DT2 with relatively low power consumption.

[0199] also, Figure 6 The S-factor of the driving transistor shown in part (b) can be expressed as the reciprocal of the slope, through which the curve in the characteristic graph of the driving transistor increases near the threshold voltage Vth.

[0200] exist Figure 6 In part (a), in the driving transistor of the blue (B) sub-pixel, the slope of the curve can be relatively large near its threshold voltage Vth, and therefore, as Figure 6 As shown in part (b), the S factor SFb of the driving transistor of the blue (B) sub-pixel can have a relatively large value, and the slope of the curve can be relatively gentle.

[0201] In addition, Figure 6 In part (a), in the driving transistor of the green (G) sub-pixel, the slope of the curve can be relatively flat near its threshold voltage Vth, and therefore, as Figure 6 As shown in part (b), the S factor SFg of the driving transistor of the green (G) sub-pixel can have a relatively small value, and the slope of the curve can be relatively large.

[0202] Because the S-factor SFb of the driving transistor has a relatively large value, the slope of the curve can be relatively gentle, and the grayscale performance can be more stable.

[0203] For example, such as Figure 6 As shown in part (b), when the thicknesses of the first device buffer layer 141 of the first driving transistor DT1 and the second driving transistor DT2 are equal to each other, and the thicknesses of the second device buffer layer 142 of the first driving transistor DT1 and the second driving transistor DT2 are equal to each other, the S factor SFg of the first driving transistor DT1 of the green (G) sub-pixel can have a value that is relatively smaller than the S factor SFb of the second driving transistor DT2 of the blue (B) sub-pixel, and the slope of the curve can be relatively large.

[0204] However, according to this disclosure, as referenced above... Figure 3 In the first sub-pixel SP1 that emits green (G) light, the thickness of the first device buffer layer 141 and the second device buffer layer 142 of the first driving transistor DT1 can be adjusted, and thus the S factor SFg' of the first driving transistor DT1 can be enhanced to be higher than the S factor SFb of the second driving transistor DT2, so that the slope of the curve can be gently tilted from SFg to SFg'.

[0205] In detail, as referenced above Figure 3 The capacitance of the capacitor in the first device buffer layer 141, which includes SiOx, can increase as its thickness decreases, and the capacitance of the capacitor in the first device buffer layer 141 can decrease as its thickness increases.

[0206] In the second device buffer layer 142 including SiNx, the capacitance of the capacitor in the second device buffer layer 142 can increase with its thickness, and the capacitance of the capacitor in the second device buffer layer 142 can decrease with its thickness.

[0207] Therefore, the buffer capacitances C1b and C2b of the device buffer layer 140, which includes the first device buffer layer 141 and the second device buffer layer 142, can increase as the thickness of the first device buffer layer 141 decreases, and furthermore, they can increase as the thickness of the second device buffer layer 142 increases.

[0208] Furthermore, the S-factor of each of the first driving transistor DT1 and the second driving transistor DT2 can be determined based on the ratio of the first gate capacitance C1a and the second gate capacitance C2a between the gate electrodes G1 and G2 and the semiconductor layers ACT1 and ACT2 to the first buffer capacitance C1b and the second buffer capacitance C2b between the semiconductor layers ACT1 and ACT2 and the metal layers LS1 and LS2.

[0209] In detail, the S-factor SFg of the first driving transistor DT1 can increase as the first buffer capacitor C1b increases relative to the first gate capacitor C1a, and the S-factor SFb of the second driving transistor DT2 can increase as the second buffer capacitor C2b increases relative to the second gate capacitor C2a.

[0210] The first gate capacitance C1a and the second gate capacitance C2a can be determined based on the thickness of the gate insulating layer 150, and as... Figure 3 As shown, the thickness of the gate insulating layer 150 of the first driving transistor DT1 and the second driving transistor DT2 can be equal to each other, and therefore, the first gate capacitance C1a and the second gate capacitance C2a can have the same value.

[0211] Therefore, the S-factor SFg of the first driving transistor DT1 and the S-factor SFb of the second driving transistor DT2 can increase with the increase of the first gate capacitance C1a and the second gate capacitance C2a.

[0212] In this disclosure, below the first driving transistor DT1, the thickness TGB1 of the first device buffer layer 141 can be less than the thickness TBB1 of the first device buffer layer 141 of the second driving transistor DT2, and the thickness TGB2 of the second device buffer layer 142 can be greater than the thickness TBB2 of the second device buffer layer 142 of the second driving transistor DT2. Therefore, the first buffer capacitor C1b of the first driving transistor DT1 can be greater than the second buffer capacitor C2b of the second driving transistor DT2.

[0213] Therefore, in this disclosure, the S-factor of the first driving transistor DT1 can be enhanced to be higher than the S-factor of the second driving transistor DT2.

[0214] As described above, in this disclosure, the thickness of the first device buffer layer 141 and the second device buffer layer 142 can be adjusted by using the relationship between the S factor and each of the gate capacitor and the buffer capacitor, and thus, the target S factor SFg' of the first driving transistor DT1, which is the target of the second driving transistor DT2, can be enhanced to be higher than the S factor SFb of the second driving transistor DT2.

[0215] Therefore, the grayscale representation of the first sub-pixel SP1 can be stabilized through the first driving transistor DT1.

[0216] Figure 7 and Figure 8 This is a diagram illustrating an embodiment of the interlayer structure of a display panel including switching transistors and driving transistors according to a second embodiment of the present disclosure. Figure 8 yes Figure 7A magnified view of region K in the image.

[0217] In the following text, in the description Figure 7 In this case, the above description can be used to briefly give or replace the above description. Figures 1 to 6 The descriptions overlap, and the main focus will be on the differences between them.

[0218] The switching transistor ST may include low-concentration regions OS3a and OS3b to reduce leakage current in the off state and to help control and stabilize its threshold voltage Vth.

[0219] For example, such as Figure 8 As shown, the third semiconductor layer ACT3 of the switching transistor ST may include a third channel region CH3, a third conductive region AS3 and AD3, and low-concentration regions OS3a and OS3b.

[0220] The third channel region CH3 can have the lowest hydrogen concentration in the third semiconductor layer ACT3, or it can be almost undoped of hydrogen. The hydrogen concentration in the third conductive regions AS3 and AD3 can be higher than that in the third channel region CH3. The low-concentration regions OS3a and OS3b can have a hydrogen concentration between that in the third channel region CH3 and the third conductive regions AS3 and AD3.

[0221] Here, one of the third conductive regions AS3 and AD3 can be the third source region AS3, and the other can be the third drain region AD3.

[0222] The third channel region CH3 can overlap with the third gate electrode G3 of the switching transistor ST. The low-concentration regions OS3a and OS3b can be disposed in the region of the third semiconductor layer ACT3 of the switching transistor ST that does not overlap with the third gate electrode G3 of the switching transistor ST. The third conductive regions AS3 and AD3 can be disposed outside the low-concentration regions OS3a and OS3b in the third semiconductor layer ACT3 of the switching transistor ST.

[0223] In the second embodiment, as Figure 8 As shown, the thickness TSL1a of the portion of the first upper interlayer insulating layer 210 that overlaps with the low-concentration regions OS3a and OS3b of the switching transistor ST can be greater than the thickness TSL1b of the portion that overlaps with the third conductive regions AS3 and AD3 of the first upper interlayer insulating layer 210.

[0224] For example, such as Figure 7As shown, the thickness TSL1a of the portion of the first upper interlayer insulating layer 210 that overlaps with the low-concentration regions OS3a and OS3b of the switching transistor ST can be greater than the thicknesses TGL1 and TBL1 of the portion of the first upper interlayer insulating layer 210 disposed on the first semiconductor layer ACT1 and the second semiconductor layer ACT2 of the first driving transistor DT1 and the second driving transistor DT2.

[0225] Furthermore, for example, the thickness TSL1b of the portion of the first upper interlayer insulating layer 210 that overlaps with the third conductive regions AS3 and AD3 of the switching transistor ST can be equal to the thickness TGL1 of the portion disposed on the first semiconductor layer ACT1 of the first driving transistor DT1.

[0226] Furthermore, the thickness TSL2 of the portion of the second upper interlayer insulating layer 220 that overlaps with the low-concentration regions OS3a and OS3b of the switching transistor ST can be less than the thickness TSL2' of the portion of the second upper interlayer insulating layer 220 that overlaps with the third conductive regions AS3 and AD3.

[0227] The thickness TSL2' of the portion of the second upper interlayer insulating layer 220 that overlaps with the third conductive regions AS3 and AD3 can be equal to the thickness TSL2 of the second upper interlayer insulating layer 220 of the first driving transistor DT1.

[0228] According to this disclosure, if in Figure 7 and Figure 8 In the process, the thickness TSL1a of the portion of the first upper interlayer insulating layer 210 that overlaps with the low-concentration regions OS3a and OS3b of the switching transistor ST can be relatively large, and the thickness TSL1b of the portion of the first upper interlayer insulating layer 210 that overlaps with the third conductive regions AS3 and AD3 can be relatively small. Therefore, in the annealing process, the low-concentration regions OS3a and OS3b of the switching transistor ST can be doped with hydrogen at a lower concentration than the third conductive regions AS3 and AD3 of the switching transistor ST.

[0229] Figure 9 This is a diagram illustrating an embodiment of the interlayer structure of a display panel according to a first embodiment of the present disclosure, wherein the display panel includes transistors disposed in non-active regions, compared to transistors disposed in active regions AA.

[0230] like Figure 9 As shown, the GIP transistor GT1 can be included in the inactive area NA of the display panel 10.

[0231] The GIP transistor GT1 may include a fourth gate electrode G4, a fourth semiconductor layer ACT4, a fourth source electrode SD4a, a fourth drain electrode SD4b, and a fourth metal layer LS4.

[0232] The fourth gate electrode G4 may be disposed between the first upper interlayer insulating layer 210 and the second gate insulating layer 150, and may include the same conductive material as the first gate electrode G1 to the third gate electrode G3.

[0233] The fourth semiconductor layer ACT4 may be disposed between the second gate insulating layer 150 and the first device buffer layer 141, and may include an oxide semiconductor.

[0234] The fourth source electrode SD4a and the fourth drain electrode SD4b can be disposed between the second upper interlayer insulating layer 220 and the first planarization layer 310, and can include the same conductive material as the conductive material of each of the first to third drain electrodes SD1b, SD2b and SD3b and the first to third source electrodes SD1a, SD2a and SD3a.

[0235] A fourth metal layer LS4 may be disposed between the first gate insulating layer 120 and the lower interlayer insulating layer 130, and may overlap with the fourth semiconductor layer ACT4. The fourth metal layer LS4 may block external light incident on the fourth semiconductor layer ACT4, and although not shown, may be electrically connected to the fourth gate electrode G4. Therefore, the fourth metal layer LS4 may serve as the bottom gate electrode. The fourth metal layer LS4 may comprise the same material as the third metal layer LS3, and may comprise a conductive material different from the conductive materials of each of the first metal layer LS1 and the second metal layer LS2.

[0236] In the GIP transistor GT1, the thickness TNL1 of the first upper interlayer insulating layer 210 disposed on the fourth semiconductor layer ACT4 may be different from the thickness TSL1 of the first upper interlayer insulating layer 210 of the switching transistor ST, and the thickness TNL2 of the second upper interlayer insulating layer 220 of the GIP transistor GT1 may be different from the thickness TSL2 of the second upper interlayer insulating layer 220 of the switching transistor ST.

[0237] For example, the thickness TNL1 of the first upper interlayer insulating layer 210 of the GIP transistor GT1 can be less than the thickness TSL1 of the first upper interlayer insulating layer 210 of the switching transistor ST, and the thickness TNL2 of the second upper interlayer insulating layer 220 of the GIP transistor GT1 can be greater than the thickness TSL2 of the second upper interlayer insulating layer 220 of the switching transistor ST.

[0238] For example, the thickness TNL1 of the first upper interlayer insulating layer 210 of the GIP transistor GT1 can be equal to the thickness TBL1 of the first upper interlayer insulating layer 210 of the second driving transistor DT2 included in the second sub-pixel SP2 that emits blue or red light. Furthermore, the thickness of the second upper interlayer insulating layer 220 of the GIP transistor GT1 can be equal to the thickness TBL2 of the second upper interlayer insulating layer 220 of the second driving transistor DT2.

[0239] Furthermore, in the GIP transistor GT1, the thickness TNL2 of the second upper interlayer insulating layer 220 can be greater than the thickness TNL1 of the first upper interlayer insulating layer 210.

[0240] As described above, based on the structure including the first upper interlayer insulating layer 210 and the second upper interlayer insulating layer 220 of the GIP transistor GT1, the fourth semiconductor layer ACT4 of the GIP transistor GT1 can be doped with hydrogen at a high concentration, and the reaction speed of the GIP transistor GT1 can be enhanced.

[0241] Furthermore, the thickness TNB1 of the first device buffer layer 141 of the GIP transistor GT1 can be equal to the thickness TSB1 of the first device buffer layer 141 of the switching transistor ST, and the thickness TNB2 of the second device buffer layer 142 of the GIP transistor GT1 can be equal to the thickness TSB2 of the second device buffer layer 142 of the switching transistor ST.

[0242] Therefore, the concentration of hydrogen doped in the fourth semiconductor layer ACT4 of the GIP transistor GT1 can be relatively high, thereby improving the reaction speed of the GIP transistor GT1.

[0243] As described above, for example, the GIP transistor GT1 can be used in a buffer or scan driver for supplying scan signals to multiple sub-pixels SP.

[0244] Furthermore, depending on the circumstances, the display panel 10 according to this disclosure may also include low-temperature polycrystalline silicon (LTPS) transistors. Examples of display panels 10 according to this disclosure also including LTPS transistors will be described below.

[0245] Figure 10 This is a diagram illustrating an embodiment of the interlayer structure of a display panel including LTPS transistors that can be further disposed in non-active regions, according to an embodiment of the present disclosure.

[0246] refer to Figure 10 The display panel 10 according to embodiments of the present disclosure may further include an LTPS transistor GT2 in an inactive region NA.

[0247] In this disclosure, for ease of description, an example in which the LTPS transistor GT2 is included in the non-active region NA can be described, but this disclosure is not limited thereto, and depending on the circumstances, the LTPS transistor GT2 may be included in the sub-pixel SP of the active region AA of the display panel 10.

[0248] like Figure 10 As shown, the LTPS transistor GT2 may include a fifth gate electrode G5, a fifth semiconductor layer ACT5, a fifth source electrode SD5a, a fifth drain electrode SD5b, and a fifth metal layer LS5.

[0249] The fifth gate electrode G5 may be disposed between the first gate insulating layer 120 and the lower interlayer insulating layer 130, and may include the same conductive material as the conductive material of each of the third metal layer LS3 and the fourth metal layer LS4.

[0250] The fifth semiconductor layer ACT5 may be disposed between the first gate insulating layer 120 and the active buffer layer 112, and may include LTPS semiconductor material, and may be doped thereon with a dopant different from hydrogen.

[0251] The fifth source electrode SD5a and the fifth drain electrode SD5b may be disposed between the second upper interlayer insulating layer 220 and the first planarization layer 310, and may include the same conductive material as the conductive material of each of the first to fourth source electrodes SD1a, SD2a, SD3a and SD4a and the first to fourth drain electrodes SD1b, SD2b, SD3b and SD4b.

[0252] Each of the fifth source electrode SD5a and the fifth drain electrode SD5b can extend upwards from the upper interlayer insulating layer 200 to the first gate insulating layer 120 and can contact the fifth semiconductor layer ACT5.

[0253] The fifth metal layer LS5 can be disposed between the active buffer layer 112 and the second multi-buffer layer 111b, and can block external light incident on the fifth semiconductor layer ACT5. Depending on the circumstances, the fifth metal layer LS5 can be electrically connected to a constant voltage source.

[0254] As described above, in embodiments of this disclosure, in a switching transistor ST that requires a relatively short channel length in each sub-pixel SP, the thickness of the first upper interlayer insulating layer 210 can be set to be relatively large, and the thickness of the second upper interlayer insulating layer 220 can be set to be relatively small. Therefore, the concentration of hydrogen doped in the semiconductor layer of the switching transistor ST can be reduced, thereby maximizing the channel of the switching transistor ST and allowing the threshold voltage (Vth) of the switching transistor ST to be positively offset (+offset).

[0255] In the embodiments of this disclosure, in the first driving transistor DT1 that requires relatively stable grayscale performance in each sub-pixel SP, the thickness of the first device buffer layer 141 can be set to be relatively small, and the thickness of the second device buffer layer 142 can be set to be relatively large. Therefore, the S-factor of the first driving transistor DT1 can be increased, thereby making the grayscale performance of the unit pixel more stable.

[0256] In embodiments of this disclosure, in the second driving transistor DT2, which requires relatively high on-current (Ion) characteristics in each sub-pixel SP, the thickness of the first upper interlayer insulating layer 210 can be set to be relatively small, and the thickness of the second upper interlayer insulating layer 220 can be set to be relatively large. Therefore, the concentration of hydrogen doped in the semiconductor layers of each driving transistor DT1 and DT2 can be increased, thereby responding to the high on-current (Ion) characteristics of the semiconductor layer of the second driving transistor DT2 and reducing power consumption.

[0257] In embodiments of this disclosure, in a switching transistor requiring a relatively short channel length in each sub-pixel, the thickness of the first upper interlayer insulating layer can be set to be relatively large, and the thickness of the second upper interlayer insulating layer can be set to be relatively small. Therefore, the concentration of hydrogen doped in the semiconductor layer of the switching transistor can be reduced, thereby maximizing the channel of the switching transistor and allowing the threshold voltage (Vth) of the switching transistor to be positively offset (+offset).

[0258] In embodiments of this disclosure, in the first driving transistor that requires relatively stable grayscale performance in each sub-pixel, the thickness of the first device buffer layer can be set to be relatively small, and the thickness of the second device buffer layer can be set to be relatively large. Therefore, the S-factor of the first driving transistor can be increased, thereby making the grayscale of the unit pixel more stable.

[0259] In embodiments of this disclosure, in a second driving transistor that requires relatively high on-current (Ion) characteristics in each sub-pixel, the thickness of the first upper interlayer insulating layer can be set to be relatively small, and the thickness of the second upper interlayer insulating layer can be set to be relatively large. Therefore, the concentration of hydrogen doped in the semiconductor layer of the driving transistor can be increased, thereby responding to the high on-current (Ion) characteristics of the semiconductor layer of the second driving transistor and reducing power consumption.

[0260] The embodiments disclosed herein can improve the reliability of transistors and reduce the power consumption of display devices, thereby achieving ESG.

[0261] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0262] While this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0263] The various embodiments described above can be combined to provide further embodiments.

[0264] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents enjoyed by those claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A display panel, comprising: A substrate, the substrate comprising an effective region and an ineffective region; A driving transistor configured to supply driving current to a light-emitting device disposed in a sub-pixel of the effective region, the driving transistor including a gate electrode and a semiconductor layer including an oxide layer; A switching transistor is disposed in the sub-pixel and electrically connected to the driving transistor, the switching transistor including a gate electrode and a semiconductor layer including oxide; A first upper interlayer insulating layer is respectively disposed on the semiconductor layer of the driving transistor and the switching transistor; as well as A second interlayer insulation layer disposed on the first interlayer insulation layer. The thickness of the first upper interlayer insulating layer disposed on the semiconductor layer of the switching transistor is different from the thickness of the first upper interlayer insulating layer disposed on the semiconductor layer of the driving transistor.

2. The display panel according to claim 1, wherein the thickness of the first upper interlayer insulating layer disposed on the switching transistor is greater than the thickness of the first upper interlayer insulating layer disposed on the driving transistor.

3. The display panel according to claim 1, wherein the thickness of the second upper interlayer insulating layer disposed on the switching transistor is different from the thickness of the second upper interlayer insulating layer disposed on the driving transistor.

4. The display panel according to claim 3, wherein the thickness of the second upper interlayer insulating layer disposed on the switching transistor is less than the thickness of the second upper interlayer insulating layer disposed on the driving transistor.

5. The display panel according to claim 1, wherein the hydrogen content of the second upper interlayer insulating layer is higher than the hydrogen content of the first upper interlayer insulating layer.

6. The display panel according to claim 1, wherein the first upper interlayer insulating layer and the second upper interlayer insulating layer comprise different insulating materials, and The first upper interlayer insulating layer comprises silicon oxide, and the second upper interlayer insulating layer comprises silicon nitride.

7. The display panel according to claim 1, wherein the second upper interlayer insulating layer disposed on the switching transistor and the second upper interlayer insulating layer disposed on the driving transistor are in a common plane.

8. The display panel according to claim 1, wherein the driving transistor comprises: A first driving transistor is disposed in a first sub-pixel and configured to supply driving current to a first light-emitting device that emits light of a first color. as well as The second driving transistor is disposed in the second sub-pixel and configured to supply driving current to the second light-emitting device that emits light of a second color different from the first color. The thickness of each of the first and second upper interlayer insulating layers disposed on the first driving transistor is different from the thickness of each of the first and second upper interlayer insulating layers disposed on the second driving transistor.

9. The display panel of claim 8, wherein the first light-emitting device emits green light, and the second light-emitting device emits blue or red light, and The thickness of the first upper interlayer insulating layer disposed on the first driving transistor is greater than the thickness of the first upper interlayer insulating layer disposed on the second driving transistor.

10. The display panel according to claim 8, wherein the thickness of the second upper interlayer insulating layer disposed on the second driving transistor is greater than the thickness of the second upper interlayer insulating layer disposed on the first driving transistor.

11. The display panel according to claim 8, further comprising a device buffer layer, the device buffer layer comprising: A first device buffer layer is disposed beneath the semiconductor layer included in each of the switching transistor and the first and second driving transistors to contact the semiconductor layer; as well as A second device buffer layer is disposed below the first device buffer layer, and The first and second device buffer layers have different dielectric constants.

12. The display panel according to claim 11, wherein the thickness of the first device buffer layer disposed below the first driving transistor is different from the thickness of the first device buffer layer disposed below the second driving transistor.

13. The display panel according to claim 11, wherein the thickness of the first device buffer layer disposed below the first driving transistor is less than the thickness of the first device buffer layer disposed below the second driving transistor.

14. The display panel of claim 11, wherein the semiconductor layer of the switching transistor and the semiconductor layer included in each of the first and second driving transistors are disposed on the first device buffer layer and are in a common plane.

15. The display panel according to claim 11, wherein the thickness of the second device buffer layer disposed below the first driving transistor is different from the thickness of the second device buffer layer disposed below the second driving transistor.

16. The display panel according to claim 15, wherein the thickness of the second device buffer layer disposed below the first driving transistor is greater than the thickness of the second device buffer layer disposed below the second driving transistor.

17. The display panel of claim 11, wherein the thickness of the first device buffer layer is less than the thickness of the second device buffer layer below the first driving transistor.

18. The display panel of claim 11, wherein the first device buffer layer and the second device buffer layer comprise different insulating materials, and The first device buffer layer comprises silicon oxide, and the second device buffer layer comprises silicon nitride.

19. The display panel of claim 1, wherein the semiconductor layer of the switching transistor includes a channel region, a conductive region having a higher hydrogen concentration than the channel region, and a low-concentration region having a hydrogen concentration between the channel region and the conductive region. The channel region overlaps with the gate electrode of the switching transistor. The low-concentration region is located in a region of the semiconductor layer of the switching transistor that does not overlap with the gate electrode of the switching transistor, and The conductive region is located outside the low-concentration region in the semiconductor layer of the switching transistor.

20. The display panel of claim 19, wherein the thickness of the portion of the switching transistor in the first upper interlayer insulating layer that overlaps with the low-concentration region is greater than the thickness of the portion of the switching transistor that overlaps with the conductive region.

21. The display panel of claim 19, wherein the thickness of the portion of the switching transistor in the first upper interlayer insulating layer that overlaps with the low-concentration region is greater than the thickness of the first upper interlayer insulating layer disposed on the semiconductor layer of the driving transistor.

22. The display panel of claim 1, further comprising a gate-in-panel (GIP) transistor in the non-active region, the gate-in-panel transistor comprising a gate electrode and a semiconductor layer comprising oxide. The thickness of the first upper interlayer insulating layer disposed on the gate transistor in the panel is different from the thickness of the first upper interlayer insulating layer disposed on the switching transistor.

23. The display panel according to claim 22, wherein the thickness of the first upper interlayer insulating layer disposed on the gate transistor in the panel is less than the thickness of the first upper interlayer insulating layer disposed on the switching transistor.

24. The display panel according to claim 22, wherein the thickness of the second upper interlayer insulating layer disposed on the gate transistor in the panel is different from the thickness of the second upper interlayer insulating layer disposed on the switching transistor.

25. The display panel according to claim 22, wherein the thickness of the second upper interlayer insulating layer disposed on the gate transistor in the panel is greater than the thickness of the second upper interlayer insulating layer disposed on the switching transistor.

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