Methods, apparatus, equipment, storage media, and computer program products for generating FPGA measurement and control systems.

Abstract

This disclosure relates to methods, apparatus, devices, storage media, and computer program products for generating FPGA measurement and control systems. It generates development data describing the structure and function of the target FPGA measurement and control system based on received system configuration description text data, automatically extracts matching hardware IP cores, embedded drivers, and host computer interface templates from a preset resource library, and automatically completes logic engineering construction, constraint generation, synthesis, placement and routing, and bitstream compilation using the FPGA development environment. Then, it automatically generates embedded processor control programs, communication interface programs, system image files, software development kits, and graphical user interface programs based on the generated files, and supports system reconfiguration and automatic optimization using difference analysis. This application enables rapid construction and reconfiguration of FPGA measurement and control systems through a unified configuration description, reducing development complexity and lowering the technical threshold while improving development efficiency. It is suitable for the rapid development of automatic measurement and control equipment and software-defined hardware systems.

Description

Technical Field

[0001] This application relates to the field of FPGA measurement and control instrument technology, and more specifically to a method, apparatus, device, storage medium and computer program product for generating an FPGA measurement and control system. Background Technology

[0002] With the development of programmable logic device technology, measurement and control instruments based on field-programmable gate arrays (FPGAs) have been widely used in signal acquisition, signal processing, automatic testing, communication measurement and other fields due to their advantages such as high-speed parallel processing capability, high reconfigurability and flexible interface. In practical applications, in order to achieve different functional requirements, it is usually necessary to build a complex measurement and control architecture on the FPGA platform, including data acquisition module, signal processing module, communication interface module and control module.

[0003] In existing technologies, developing FPGA-based measurement and control instruments typically requires completing multiple interrelated development steps, including analog front-end circuit design, analog-to-digital or digital-to-analog conversion interface circuit design, FPGA logic programming, embedded processor control programming, and host computer software development. FPGA logic programs are usually written in hardware description languages, embedded control programs are typically written in C or C++, and the host computer software requires the development of graphical user interfaces and communication interface programs depending on the specific application. Due to the close interface dependencies between these parts, developers need expertise in digital circuit design, embedded system development, and software engineering, resulting in a lengthy development cycle and a high risk of errors.

[0004] Furthermore, although some development tools can provide IP core calling or graphical design functions, they are usually only for FPGA logic design itself and cannot realize the automatic generation of the whole system from system structure description to FPGA logic, embedded program and host computer software. When it is necessary to build measurement and control instruments with different functions, developers still need to manually select IP cores, write drivers, configure communication interfaces and design user interfaces, which makes it difficult to achieve rapid construction and reconstruction of the whole system, resulting in low development efficiency and high maintenance costs. Summary of the Invention

[0005] This application provides a method, apparatus, device, storage medium, and computer program product for generating an FPGA measurement and control system. It can automatically generate FPGA logic engineering, embedded control programs, and host computer software using system configuration description text data. It can also achieve rapid reconfiguration when the system structure changes, thereby improving development efficiency and reducing maintenance costs.

[0006] In a first aspect, this application provides a method for generating an FPGA measurement and control system, comprising: generating development data describing the structure and function of a target FPGA measurement and control system based on received system configuration description text data, wherein the development data includes at least functional module information, performance parameters, hardware slot locations, and module connection information; extracting matching standardized components from a preset resource library based on the development data and integrating all extracted standardized components using an FPGA development environment to generate an FPGA logic project and compile it to generate a corresponding bitstream file, wherein the preset resource library includes at least a hardware IP core resource library, an embedded software driver library, and a host computer interface library; and generating a matching system image file, a software development kit, and a graphical user interface program, including an embedded processor control program, a driver interface program, and a communication interface configuration, based on the FPGA logic project and the bitstream file, to achieve automatic construction or reconstruction of the target FPGA measurement and control system.

[0007] In one alternative embodiment of the first aspect, development data describing the structure and function of the target FPGA measurement and control system is generated based on the received system configuration description text data. This includes: defining configuration syntax rules describing various modules, hardware resources, and module connection relationships in the target FPGA measurement and control system, wherein the syntax rules include at least a module type field, a performance parameter field, a physical slot field, a signal interface field, and an interconnection relationship field; defining corresponding functional module instances in the configuration file according to the configuration syntax rules and setting module type fields, performance parameter fields, and physical slot fields for each functional module instance, and defining the signal connection relationships and hardware slot locations for each functional module instance, wherein the signal connection relationships include at least data flow direction, control signal connection, synchronization clock connection, and trigger signal connection; and outputting the configuration file as the system configuration description text data and parsing the system configuration description text data to generate development data.

[0008] In one alternative embodiment of the first aspect, the step of integrating all extracted standardized components using the FPGA development environment to generate an FPGA logic project and compile it into a corresponding bitstream file includes: retrieving candidate IP cores that meet performance constraints from a constructed hardware IP core resource library containing various standardized FPGAs, based on the functional module information and performance parameters in the development data. The hardware IP core resource library stores various reusable IP cores, including at least analog-to-digital conversion control IP cores, digital-to-analog conversion control IP cores, digital signal processing IP cores, direct digital frequency synthesis IP cores, lock-in amplifier IP cores, communication interface IP cores, and clock management IP cores; selecting the optimal IP core from the candidate IP cores according to priority rules, including at least the principles of minimum resource consumption, maximum timing margin, and interface compatibility; generating the internal bus structure of the target FPGA measurement and control system based on the module connection information in the development data and completing the data interface connection, control interface connection, and clock interface connection of each IP core; and automatically packaging and integrating the optimal IP core using the FPGA development environment to generate an FPGA logic project, constraint file, pin allocation information, and clock configuration information, and compiling it into a corresponding bitstream file.

[0009] In one alternative embodiment of the first aspect, generating a matching system image file, including an embedded processor control program, a driver interface program, and a communication interface configuration, based on the FPGA logic project and the bitstream file, comprises: pre-configuring a programmable system architecture containing an embedded processor in the hardware platform of the target FPGA measurement and control system, wherein the embedded processor is an ARM processor or a soft-core processor and interacts with the FPGA logic project via an internal bus; retrieving corresponding driver templates from a preset embedded software driver library based on the functional module information and module connection information in the development data, and parameterizing the driver templates according to performance parameters; generating initialization programs, register configuration programs, and status reading programs for controlling each functional module based on the register mapping relationship in the FPGA logic project; generating a communication interface program between the processor and the host computer based on the communication requirements of the target FPGA measurement and control system, wherein the communication interface program includes at least one or more of a serial communication interface program, an Ethernet communication interface program, and a USB communication interface program; and compiling and linking all generated programs to generate an embedded executable program matching the bitstream file and generating a system image file based on the embedded executable program.

[0010] In one alternative embodiment of the first aspect, generating a system image file based on the embedded executable program includes: establishing image generation rules for starting the target FPGA measurement and control system, wherein the image generation rules define the storage location and loading order of FPGA configuration data, embedded program, and startup parameters; converting the bitstream file into loadable configuration data and the embedded executable program into a processor executable image according to the image generation rules; generating a startup loader program for sequentially completing FPGA configuration loading, embedded processor startup, and system initialization when the target FPGA measurement and control system is powered on, and generating a startup configuration file defining the storage medium type, loading address, and startup method according to the hardware platform type of the target FPGA measurement and control system; and packaging the configuration data, processor executable image, startup loader program, and startup configuration file to generate a system image file that can be directly written to non-volatile memory.

[0011] In one alternative of the first aspect, a software development kit is generated based on the FPGA logic project and bitstream file, including: constructing a host computer interface description model describing the control parameters, status parameters, and data access interfaces of each functional module; selecting a software interface template corresponding to each functional module from a preset host computer interface library based on the interface description model; and parameterizing the interface template based on performance parameters and module connection information; generating application programming interface functions for accessing the embedded processor communication interface and generating an interface specification document corresponding to the target FPGA measurement and control system based on the development data; and generating and outputting a software development kit for secondary development, wherein the software development kit includes at least an interface function library, sample programs, interface specification documents, and compilation configuration files.

[0012] In one alternative of the first aspect, generating a graphical user interface program based on the FPGA logic project and bitstream file includes: constructing an interface description model for describing the control interface of the target FPGA measurement and control system; retrieving interface templates corresponding to each functional module from a preset graphical interface template library based on the functional module information and performance information in the development data; and instantiating and configuring the interface templates according to module parameters; generating a data display interface for displaying data flow relationships based on the module connection information of the development data; generating a parameter control panel based on the interface description model; binding the generated interface controls to the application programming interface functions in the software development kit so that the graphical user interface can access the embedded processor control program through the application programming interface functions; and optimizing the interface layout of the generated graphical user interface and outputting an executable graphical user interface program.

[0013] In one alternative embodiment of the first aspect, when generating a matching system image file, software development kit, and graphical user interface program including an embedded processor control program and driver interface and communication interface configuration, the method further includes: when receiving new system configuration description text data, performing a difference analysis between the new system configuration description text data and the original system configuration description text data, and generating a difference analysis result; updating the development data according to the difference analysis result and re-extracting the corresponding standardized components from a preset resource library; while keeping the FPGA logic structure and driver program corresponding to the unmodified modules unchanged, updating the corresponding FPGA logic project, embedded processor control program, and graphical user interface for the modules that have changed; regenerating the bitstream file for the updated FPGA logic project and regenerating the matching system image file, software development kit, and graphical user interface program; and outputting the updated system image file, software development kit, and graphical user interface program to achieve the reconstruction of the target FPGA measurement and control system function.

[0014] In one optional embodiment of the first aspect, the automatic integration of standardized components using the FPGA development environment to generate an FPGA logic project further includes: generating FPGA resource allocation data based on the functional module information and hardware slot location information, wherein the resource allocation data describes the allocation relationship of logic units, memory units, DSP units, and IO pins; generating bus connection constraint data based on the module connection information, wherein the bus connection constraint data defines the data interface connection method and clock connection method between each functional module; automatically generating timing constraint data based on the performance information, wherein the timing constraint data defines the clock frequency, data setup time, and hold time; and performing resource conflict detection after generating the resource allocation data, connection constraint data, and timing constraint data to determine whether there is pin conflict, clock conflict, or insufficient logic resources. If so, the IP core selection result or hardware slot location is automatically adjusted according to a preset optimization strategy, and the resource allocation data, connection constraint data, and timing constraint data are regenerated. If not, the generated resource allocation data, connection constraint data, timing constraint data, and FPGA logic project are input into the FPGA development environment for synthesis, placement, and routing to generate a bitstream file that meets the performance requirements of the target FPGA measurement and control system.

[0015] Secondly, this application provides a generation apparatus for an FPGA measurement and control system implementing the generation method described in any one of the first aspects, comprising: a preset resource library, which includes at least a hardware IP core resource library, an embedded software driver library, and a host computer interface library, for storing reusable IP cores, driver templates, and software interface templates; a resource mapper, which is used to retrieve hardware resources and software resources from the hardware IP core resource library, the embedded software driver library, and the host computer interface library; an automatic generator, which includes one or more of a physical pin resolver, an FPGA project generator, an embedded project generator, and a host computer project generator; and a processing unit, which is connected to the preset resource library, the resource mapper, and the automatic generator respectively, for constructing or reconstructing the target FPGA measurement and control system; wherein, the processing unit includes: a data generation module, used to generate data based on the acquired system configuration description file. This data generates development data for the target FPGA measurement and control system to be generated. This development data includes at least functional module information, performance parameters, hardware slot locations, and module connection information. A data retrieval module extracts matching standardized components from a preset resource library based on the development data and integrates all extracted standardized components using the FPGA development environment to generate an FPGA logic project and compile it into a corresponding bitstream file. The preset resource library includes at least a hardware IP core resource library, an embedded software driver library, and a host computer interface library. A data construction module generates matching system image files, software development kits, and graphical user interface programs, including embedded processor control programs and driver and communication interface configurations, based on the FPGA logic project and bitstream file, to achieve automatic construction or reconstruction of the target FPGA measurement and control system.

[0016] Thirdly, this application provides an electronic device, comprising: a processor adapted to execute a computer program; and a computer-readable storage medium storing a computer program, wherein when executed by the processor, the computer program implements the generation method described in any one of the first aspects.

[0017] Fourthly, this application provides a computer-readable storage medium for storing a computer program that, when run on a computer, causes the computer to perform the generation method described in any one of the first aspects.

[0018] Fifthly, this application provides a computer program product, including a computer program or instructions, characterized in that, when the computer program or instructions are executed by a processor, they implement the generation method described in any one of the first aspects.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate one or more embodiments of the present application and, together with the description, serve to explain the principles of the present application and to enable those skilled in the art to make and use the present application.

[0021] Figure 1 This is a flowchart illustrating an exemplary method for generating an FPGA measurement and control system according to some embodiments of this application.

[0022] Figure 2 This is a flowchart illustrating an exemplary development data generation method according to some embodiments of this application.

[0023] Figure 3 This is a flowchart illustrating an exemplary FPGA logic engineering and bitstream file generation method according to some embodiments of this application.

[0024] Figure 4 This is a first flowchart illustrating an exemplary system image file generation method according to some embodiments of this application.

[0025] Figure 5 This is a second flowchart illustrating an exemplary system image file generation method according to some embodiments of this application.

[0026] Figure 6 This is a flowchart illustrating an exemplary software development kit (SDK) generation method according to some embodiments of this application.

[0027] Figure 7 This is a flowchart illustrating an exemplary graphical user interface program generation method according to some embodiments of this application.

[0028] Figure 8 This is a flowchart illustrating an exemplary FPGA logic engineering generation method according to some embodiments of this application.

[0029] Figure 9 This is a schematic diagram illustrating the connection relationship between an exemplary functional module and an FPGA according to some embodiments of this application.

[0030] Figure 10 This is a flowchart illustrating an exemplary method for generating a system image file, software development kit, and graphical user interface program according to some embodiments of this application.

[0031] Figure 11 This is a connection diagram of an exemplary FPGA measurement and control system generation device according to some embodiments of this application.

[0032] Figure 12This is a schematic diagram of the structure of an exemplary target FPGA measurement and control system hardware platform according to some embodiments of this application.

[0033] Figure 13 This is a schematic diagram of the structure of an exemplary processing unit according to some embodiments of this application.

[0034] Figure 14 This is a schematic diagram of the structure of an exemplary electronic device according to some embodiments of this application. Detailed Implementation

[0035] It should be noted that the terminology used in the implementation section of this application is only for explaining the embodiments of this application and is not intended to limit this application.

[0036] For example, the term "and / or" in this article simply describes the relationship between related objects, indicating that three relationships can exist. For instance, A and / or B can represent: A alone, A and B simultaneously, and B alone. The term "at least one" simply describes the combination relationship of listed objects, indicating that one or more can exist. For instance, at least one of the following: A, B, C can represent the following combinations: A alone, B alone, C alone, A and B simultaneously, A and C simultaneously, B and C simultaneously, and A, B, and C simultaneously. The term "multiple" refers to two or more. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0037] For example, the term "correspondence" can indicate a direct or indirect correspondence between two things, or an association between them, or a relationship of instruction and being instructed, configuration and being configured, etc. The term "instruction" can be direct, indirect, or indicate an association. For example, A instructing B can mean A directly instructs B, for example, B can be obtained through A; it can also mean A indirectly instructs B, for example, A instructs C, B can be obtained through C; or it can mean an association between A and B. The terms "predefined" or "preconfigured" can refer to pre-stored codes, tables, or other relevant information that can be used for instruction in the device, or it can refer to something agreed upon by a protocol. "Protocol" can refer to standard protocols in the field. The term "when..." can be interpreted as "if," "when," or "in response," etc. Similarly, depending on the context, the phrases "if determined" or "if detected (the condition or event of the statement)" can be interpreted as "when determined" or "in response to determined" or "when detected (the condition or event of the statement)" or "in response to detected (the condition or event of the statement)" and similar descriptions. The terms "first," "second," "third," "fourth," "A," "B," etc., are used to distinguish different objects, not to describe a specific order. The terms "includes" and "has," and any variations thereof, are intended to cover non-exclusive inclusion.

[0038] To facilitate understanding of the technical solutions provided in this application, the relevant terms are explained below.

[0039] Field-Programmable Gate Array (FPGA) is a reconfigurable semiconductor integrated circuit; ZYNQ SoC is a chip from Xilinx that integrates an FPGA (Xilinx calls it PL) and a CPU (Xilinx calls it PS). PL (Programmable Logic) is the FPGA integrated in ZYNQ and other SoC chips, and PS (Processing System) is the CPU system integrated in ZYNQ and other SoC chips; Intellectual Property Core (IP) is a pre-designed, reusable hardware functional module based on an FPGA (such as an ADC controller, filter, DDS, etc.); YAML (YAML Ain't Markup Language) is a human-readable data serialization standard, often used for configuration files; SDK (Software Development Kit) is a software development kit that includes callable interface functions (APIs) and some auxiliary tools; GUI (Graphical User Interface) is a graphical user interface; LLM (Large Language) Model), which is a large language model, an artificial intelligence model that can understand and generate natural language text.

[0040] FPGAs are widely used in high-performance measurement and control systems due to their parallel processing capabilities and reconfigurability. However, building a complete FPGA measurement and control system involves multiple complex steps from physical hardware to upper-level software. These steps include: modular hardware circuit construction, which involves selecting and building specific analog front-ends, ADCs / DACs, signal conditioning, and other modular hardware circuits according to measurement or control requirements and installing them onto specific physical interfaces of the hardware platform (such as FMC, high-speed connectors, and SPI interface boards). This step requires knowledge of analog and digital circuit design. FPGA hardware logic design involves designing the corresponding driver logic, data paths, and processing algorithms using Verilog / VHDL for the installed hardware modules (in ZYNQ SoC, this logic runs on PL, i.e., programmable gate arrays); embedded software development, which involves writing C / C++ programs that run on the processor (PS, CPU system in ZYNQ SoC) to initialize, control the FPGA logic, and manage data flow; and host computer application development, which involves developing PC-side applications (such as Python GUI) to provide a user interface and advanced control logic.

[0041] These steps are interconnected and require different professional skills. In the traditional development process, the physical layout and connection of the hardware circuit (such as which module is inserted into which slot) must be kept consistent with the subsequent FPGA pin constraints, driver writing, and software configuration. Any inconsistency will cause the system to fail. This results in a long development cycle (usually several months), high iteration costs, difficulty in system integration and debugging, and heavy reliance on the developer's full-stack experience.

[0042] Existing development tools (such as Xilinx Vivado IP Integrator and LabVIEW FPGA) attempt to simplify the development process, but they have significant limitations. Vivado IP Integrator allows graphical connection of IP cores to generate hardware bitstreams for the PL part, but it does not involve the mapping of physical hardware modules at all, nor does it automatically generate the corresponding PS embedded software and PC host computer program. Users must manually map FPGA pin constraints to hardware slots and manually write all software code. While LabVIEW FPGA provides a higher level of abstraction from graphical programming to FPGA implementation, its configuration file (.vi) is not machine-friendly or human-friendly. It uses binary or proprietary formats, is not directly readable by natural language, and is extremely difficult for modern large language models (AI) to understand and generate directly. This makes it highly dependent on dedicated LabVIEW software and graphical programming, resulting in a closed ecosystem and difficulty in achieving automated design based on natural language. Therefore, existing technologies not only lack a complete solution that can uniformly describe and automatically collaboratively generate the physical configuration of modular hardware circuits, FPGA hardware logic, embedded software, and host computer software, but also lack a standardized generation method that can serve as an efficient communication medium between humans and machines.

[0043] Therefore, in order to solve the above-mentioned technical problems, this application provides a method 100 for generating an FPGA measurement and control system. The core of this method 100 is to use the physical deployment information of modular hardware circuits as one of the basic inputs for system generation and describe it together with functional logic through standardized text to drive full-stack automated generation.

[0044] Figure 1 A flowchart illustrating an exemplary method 100 for generating an FPGA measurement and control system according to some embodiments of this application is shown.

[0045] refer to Figure 1 As shown. The method 100 for generating the FPGA measurement and control system includes at least the following steps 101 to 103.

[0046] 101: Based on the received system configuration description text data, generate development data to describe the structure and function of the target FPGA measurement and control system, wherein the development data includes at least functional module information, performance parameters, hardware slot locations and module connection information.

[0047] The system configuration description text data is used to uniformly describe the overall structure, hardware resource configuration, and software functional requirements of the target FPGA measurement and control system. It includes at least the following parameters: FPGA model information, peripheral type information, communication interface type, IO pin allocation information, number of data acquisition channels, data processing method, and host computer communication method. The system configuration description text data is generated by the user through manual writing or software assistance, which describes the requirements in a formatted text description file. That is, the user manually writes a YAML configuration file according to the requirements or describes the requirements to the integrated auxiliary design front end in natural language, thereby generating the corresponding system configuration description text data.

[0048] Figure 2 A flowchart illustrating an exemplary development data generation method according to some embodiments of this application is shown.

[0049] refer to Figure 2 As shown. Specifically, based on the received system configuration description text data, development data for describing the structure and function of the target FPGA measurement and control system is generated, specifically including at least the following steps 101a to 101c.

[0050] 101a: Defines the configuration syntax rules that describe the various modules, hardware resources, and module connection relationships in the target FPGA measurement and control system.

[0051] Specifically, the configuration syntax rules are used to specify the field structure and semantic meaning of system configuration description text data. It includes at least a module type field, a performance parameter field, a physical slot field, a signal interface field, and an interconnection relationship field. The module type field is used to indicate the type of functional module, the performance parameter field is used to indicate the operating parameters of the functional module, the physical slot field is used to indicate the location of the hardware physical interface where the functional module is located, the signal interface field is used to indicate the input and output ports of the module, and the interconnection relationship field is used to indicate the connection relationship between modules.

[0052] In actual implementation, the configuration syntax rules also include one or more of the following: clock parameter field, communication protocol field, and data format field, to further describe the operating characteristics of the target FPGA measurement and control system.

[0053] 101b: In the configuration file, define the corresponding functional module instances according to the configuration syntax rules and set the module type field, performance parameter field and physical slot field for each functional module instance. Then, set the performance parameters of the functional modules according to system requirements, and set the signal connection relationship and hardware slot position for each functional module instance in the configuration file.

[0054] Specifically, the performance parameters include at least one or more of the following: sampling frequency, data bit width, signal processing algorithm type, and communication rate. The signal connection relationships include at least data flow direction, control signal connection, synchronization clock connection, and trigger signal connection. These signal connection relationships can represent the connection relationships between internal logic modules of the FPGA, or the interface connection relationships between external hardware modules and the FPGA. Furthermore, when defining these signal connection relationships, interface type information and communication protocol type information can be set to automatically generate the corresponding interface control logic when generating the FPGA logic project later. The hardware slot location indicates the actual installation location of the external hardware module corresponding to this functional module in the target hardware platform.

[0055] 101c: Output the configuration file as system configuration description text data and parse the system configuration description text data to generate development data for subsequent automatic generation processes.

[0056] Specifically, the development data includes at least a list of functional modules, a set of module performance parameters, physical slot allocation information, module connection topology information, interface type information, and communication method information, so as to drive the subsequent resource mapping process and the automatic generation of FPGA logic engineering, embedded software engineering, and host computer software engineering.

[0057] 102: Based on the development data, extract matching standardized components from the preset resource library and call the FPGA development environment to integrate all the extracted standardized components, generate FPGA logic projects and compile them to generate corresponding bitstream files. The preset resource library includes at least a hardware IP core resource library, an embedded software driver library and a host computer interface library.

[0058] In this application, the FPGA development environment is referred to as an FPGA design tool that supports automated script invocation, used to perform IP core instantiation, logic connection, constraint generation, synthesis, placement and routing, and bitstream generation operations.

[0059] Figure 3 A flowchart illustrating an exemplary FPGA logic engineering and bitstream file generation method according to some embodiments of this application is shown.

[0060] refer to Figure 3As shown. Specifically, in step 102, the FPGA development environment is invoked to integrate all the extracted standardized components, generate the FPGA logic project, and compile it to generate the corresponding bitstream file, including at least the following steps 102a to 102d.

[0061] 102a: Based on the functional module information and performance parameters in the development data, retrieve candidate IP cores that meet the performance constraints from the constructed hardware IP core resource library containing various standardized FPGAs.

[0062] Specifically, the hardware IP core resource library stores a variety of reusable IP cores, including at least analog-to-digital conversion control IP cores, digital-to-analog conversion control IP cores, digital signal processing IP cores, direct digital frequency synthesis IP cores, lock-in amplifier IP cores, communication interface IP cores, clock management IP cores, data buffer IP cores, and bus interface IP cores; the performance constraints include one or more of the following: operating frequency constraints, data bit width constraints, sampling rate constraints, interface type constraints, and resource usage constraints.

[0063] 102b: Select the optimal IP core from the candidate IP cores that meets the resource constraints and performance requirements of the target FPGA system model, based on the priority rules, as the target FPGA logic component.

[0064] Specifically, the priority rules include at least one or more of the following principles: minimum resource consumption, maximum timing margin, interface compatibility, clock domain matching, and power consumption constraints.

[0065] 102c: Based on the module connection information in the development data, generate the internal bus structure of the target FPGA measurement and control system and complete the data interface connection, control interface connection, and clock interface connection of each IP core.

[0066] Specifically, the internal bus structure includes at least data interface connection relationships, control interface connection relationships, clock interface connection relationships, reset signal connection relationships, and bus interface connection relationships. When generating the internal bus structure, a bus structure for realizing module interconnection is automatically generated. This bus structure includes at least one or more of the following: AXI bus, SPI bus, I2C bus, LVDS interface, or custom high-speed interface. This completes the data interface connection, control interface connection, and clock interface connection of each IP core.

[0067] 102d: Calls the FPGA development environment to automatically package and integrate the optimal IP core, generates FPGA logic project, constraint file, pin assignment information and clock configuration information, and compiles to generate the corresponding bitstream file.

[0068] Specifically, based on the hardware physical slot location information in the development data, a pre-set hardware mapping database is queried, and pin allocation data, I / O interface constraint data, electrical standard constraint data, clock input / output constraint data, and logic resource allocation data are generated according to the query results. This data is then used to generate a constraint file for the FPGA project and imported into the FPGA development environment. Next, the FPGA development environment is invoked to execute an automatic project generation process, including automatically creating the FPGA project, automatically instantiating the optimal IP core, automatically importing the constraint file, automatically generating module connection scripts, automatically generating clock configurations, automatically generating reset logic, and automatically generating bus interconnect structures. This generates a complete FPGA logic project file through the FPGA development environment. After generating the FPGA logic project, the FPGA development environment is invoked to automatically perform logic synthesis, placement and routing, timing analysis, resource conflict detection, clock constraint checking, and pin conflict detection. When resource conflicts or timing constraints are detected, the IP core is automatically reselected or resource allocation is adjusted according to the optimization strategy pre-set by the designer, and synthesis and placement and routing are re-executed. When the constraints are met, a bitstream file for configuring the target FPGA device is generated. This bitstream file is used to implement the logic functions of the target FPGA measurement and control system on the target hardware platform.

[0069] 103: Based on the FPGA logic engineering and bitstream files, generate a system image file, software development kit, and graphical user interface program that match the target FPGA measurement and control system, including embedded processor control program, driver interface program, and communication interface configuration, so as to realize the automatic construction or reconstruction of the target FPGA measurement and control system.

[0070] Figure 4 The illustration shows a first flowchart of an exemplary system image file generation method according to some embodiments of this application.

[0071] refer to Figure 4 As shown. Specifically, in step 103, a matching system image file is generated based on the FPGA logic project and bitstream file, including the embedded processor control program, driver interface program, and communication interface configuration, including at least the following steps 103a to 103e.

[0072] 103a: A programmable system architecture containing an embedded processor is pre-configured in the hardware platform of the target FPGA measurement and control system. This programmable system architecture is used to establish register access channels and data exchange channels between the FPGA logic engineering and the embedded processor.

[0073] The embedded processor is one or more of an ARM processor, a RISC-V processor, or an FPGA soft-core processor. The embedded processor interacts with the FPGA logic through an internal bus, which includes at least one or more of an AXI bus, an AHB bus, or a custom bus.

[0074] 103b: Based on the functional module information and module connection information in the development data, retrieve the corresponding driver template from the preset embedded software driver library and parameterize the driver template according to the performance parameters.

[0075] The driver template includes at least a register access function template, a module initialization function template, a parameter configuration function template, and a status read function template. The parameterized configuration includes at least register address mapping, data bit width, communication interface type, operating frequency, and buffer size.

[0076] 103c: Based on the register mapping relationship in the FPGA logic engineering, generate initialization programs, register configuration programs, module start and stop control programs, status reading programs, interrupt handling programs and clock configuration programs for controlling each functional module.

[0077] This register mapping relationship is automatically derived by the FPGA logic engineering to ensure that the embedded program is consistent with the FPGA logic.

[0078] 103d: Generate a communication interface program between the processor and the host computer based on the communication requirements of the target FPGA measurement and control system, so as to realize the host computer parameter sending, data acquisition and uploading, and status query through the communication interface data.

[0079] The communication interface program includes at least one or more of the following: serial communication interface program, Ethernet communication interface program, USB communication interface program, PCIe communication interface program, CAN communication interface program, and custom high-speed interface program.

[0080] This generates a system startup program for starting the target FPGA measurement and control system. The system startup program includes a startup loading configuration file, storage address configuration, storage medium type configuration, and startup order configuration. This is used to load FPGA configuration data, start the embedded processor, initialize various functional modules, configure communication interfaces, and enter the system running state when the system is powered on.

[0081] 103e: Compile and link all generated programs to generate an embedded executable program that matches the bitstream file, and package the embedded executable program and the bitstream file to generate a system image file.

[0082] Figure 5The illustration shows a second flowchart of an exemplary system image file generation method according to some embodiments of this application.

[0083] refer to Figure 5 As shown. Specifically, in step 103e, generating a system image file based on the embedded executable program includes at least the following steps 1001 to 1004.

[0084] 1001: Establish image generation rules for starting the target FPGA measurement and control system.

[0085] The image generation rule is automatically generated based on the hardware platform type of the target FPGA measurement and control system. The hardware platform types include SoC FPGA platforms based on ARM processors, FPGA platforms based on soft core processors, multi-processor FPGA platforms, and external boot memory platforms. The image generation rule is used to define the FPGA configuration data storage location, embedded program storage location, boot loader storage location, boot parameter storage location, image loading order, and boot entry address.

[0086] 1002: Convert the bitstream file into loadable FPGA configuration data and the embedded executable into a processor executable image according to the image generation rules.

[0087] The FPGA configuration data is used to configure the FPGA logic during system startup and to convert the embedded executable program into a processor executable image. The processor executable image includes a code segment, a data segment, an initialization segment, an interrupt vector table, and startup entry address information, which are used to execute the system control program after the embedded processor starts up.

[0088] 1003: Generates a startup loading program that sequentially completes FPGA configuration loading, embedded processor startup, and system initialization when the target FPGA measurement and control system is powered on, and generates a startup configuration file that defines the storage medium type, image loading address, FPGA configuration data loading address, processor program loading address, startup method, and startup order according to the hardware platform type of the target FPGA measurement and control system.

[0089] The bootloader is used to execute the following operations in a preset boot order: loading FPGA configuration data, completing FPGA logic configuration, initializing the internal bus, starting the embedded processor, loading the processor executable image, executing the system initialization program, and entering the system running state. The storage medium type includes one or more of Flash memory, EEPROM, SD card, NAND memory, and QSPI memory.

[0090] 1004: Based on the image generation rules, package the configuration data, processor executable image, startup loader, and startup configuration file to generate a system image file that can be directly written to the non-volatile memory of the target FPGA measurement and control system.

[0091] The system image file can be in binary image format, partition image format, or multi-segment image format.

[0092] Figure 6 A flowchart illustrating an exemplary software development kit (SDK) generation method according to some embodiments of this application is shown.

[0093] refer to Figure 6 As shown. Specifically, in step 103, a software development kit is generated based on the FPGA logic engineering and bitstream file, including at least the following steps 103f to 103h.

[0094] 103f: Construct a host computer interface description model that describes the control parameters, status parameters, and data access interfaces of each functional module. Based on the interface description model, select the software interface template corresponding to each functional module from the preset host computer interface library. Parameterize the interface template according to the performance parameters and module connection information to generate an interface function template that matches the target FPGA measurement and control system.

[0095] The interface description model is used to uniformly describe the interface attributes of each functional module in the target FPGA measurement and control system. The interface description model includes at least control parameter description, status parameter description, register address mapping, data access interface, communication channel identifier, data type definition, and access permission definition. The interface template includes at least serial port interface template, Ethernet interface template, USB interface template, PCIe interface template, shared memory interface template, and custom communication interface template. The parameterized configuration includes at least data length setting, communication protocol type, buffer size, interface address, command word format, and data frame format.

[0096] 103g: Based on the interface function template, generate application programming interface functions for accessing the embedded processor communication interface and generate an interface specification document corresponding to the target FPGA measurement and control system based on the development data.

[0097] The application interface functions include at least an initialization function, a parameter setting function, a data reading function, a data writing function, a status query function, an interrupt callback function, and an error handling function; the interface documentation includes at least the function names, input parameter descriptions, output parameter descriptions, register address descriptions, communication protocol descriptions, calling order descriptions, and sample code.

[0098] 103h: Generates and outputs a software development kit for secondary development, enabling the rapid construction of application software compatible with the target FPGA measurement and control system.

[0099] The software development kit includes at least an interface function library, a dynamic link library or a static library, header files, sample programs, interface documentation, compilation configuration files, and project template files, which can be directly imported into the host computer development environment.

[0100] Figure 7 A flowchart illustrating an exemplary graphical user interface program generation method according to some embodiments of this application is shown.

[0101] refer to Figure 7 As shown. Specifically, in step 103, a graphical user interface program is generated based on the FPGA logic engineering and bitstream file, including at least the following steps 103i to 103l.

[0102] 103i: Construct an interface description model to describe the control interface of the target FPGA measurement and control system. Based on the functional module information and performance information in the development data, retrieve the interface template corresponding to each functional module from the preset graphical interface template library, and instantiate and configure the interface template according to the performance information to generate the interface control corresponding to the target FPGA measurement and control system.

[0103] The interface description model includes at least the module name, parameter name, parameter type, display method, control type, data refresh method, and data display format. The graphical interface template library contains a variety of interface templates pre-stored by the designers, including at least the parameter input panel template, data display panel template, waveform display template, status monitoring template, communication control template, and log display template.

[0104] 103j: Generates a data display interface to show the data flow relationship based on the module connection information of the development data, and generates a parameter control panel based on the interface description model.

[0105] The data display interface is a visual interface used to show the data transmission paths between various functional modules; the parameter control panel is used for parameter input, parameter modification, parameter saving, parameter loading, status display, and alarm prompts.

[0106] 103k: Binds the generated UI controls to the application programming interface (API) functions in the software development kit (SDK) so that the graphical user interface can access the embedded processor control program through the API functions.

[0107] This binding includes at least the binding of controls to register addresses, controls to interface functions, controls to communication channels, and controls to data refresh threads. Through this binding, the graphical user interface can realize parameter distribution, data reading, status monitoring, and remote control.

[0108] 103l: Optimize the interface layout of the generated graphical user interface and output an executable graphical user interface program.

[0109] The interface layout optimization includes at least automatic control arrangement, resolution adaptation, interface size adjustment, refresh rate optimization, and thread scheduling optimization. After the interface layout optimization, the generated interface project is compiled and an executable graphical user interface program is output. This graphical user interface program can run in the host computer operating system and interact with the target FPGA measurement and control system through the communication interface to realize the visual control of the target FPGA measurement and control system.

[0110] Specifically, the generated system image file is output to a storage device or download interface. The system image file is written to the non-volatile memory of the target FPGA measurement and control system through a preset method. This preset method includes one or more of the following: writing via JTAG interface, writing via USB interface, writing remotely via Ethernet interface, writing via SD card or Flash memory, and writing via online upgrade interface. The non-volatile memory includes one or more of NOR Flash, NAND Flash, EEPROM, SD card, and QSPI Flash. After the system image file is written, when the target FPGA measurement and control system is powered on, the startup loading program automatically completes FPGA configuration loading, embedded processor startup, system initialization, functional module initialization, and communication interface initialization.

[0111] The generated software development kit is output to the host computer development environment, and the generated graphical user interface program is output to the host computer system. After the graphical user interface program is started, a communication connection with the target FPGA measurement and control system is automatically established. This communication connection includes one or more of the following: serial port connection, Ethernet connection, USB connection, PCIe connection, and custom high-speed communication connection. In this way, users can perform operations such as system parameter configuration, data acquisition and control, real-time data monitoring, status information reading, system operation control, and function module switching through the graphical user interface program.

[0112] In some examples of this application, when new system configuration description text data is received, a difference analysis is performed between the new system configuration description text data and the current system configuration description text data to generate a difference analysis result. Then, based on the difference analysis result, the development data is updated and at least some of the steps in steps 101 to 103 are re-executed. While keeping the FPGA logic structure and driver corresponding to the unmodified module unchanged, only the functional modules that have changed are regenerated. Then, the updated system image file is rewritten to the target FPGA measurement and control system to achieve automatic reconfiguration of the target FPGA measurement and control system.

[0113] Figure 8 A flowchart illustrating an exemplary FPGA logic engineering generation method according to some embodiments of this application is shown.

[0114] refer to Figure 8 As shown. In some embodiments of this application, in step 102, the FPGA development environment is invoked to automatically integrate standardized components and generate an FPGA logic project, which includes at least the following steps 105 to 108.

[0115] 105: Generate FPGA resource allocation data based on the functional module information and hardware slot location information in the development data.

[0116] The resource allocation data describes the allocation relationship between logic units, memory units, DSP units, and I / O pins. The logic resources include at least lookup table resources, flip-flop resources, block memory resources, DSP arithmetic unit resources, high-speed transceiver resources, I / O pin resources, and clock management resources.

[0117] 106: Generate bus connection constraint data based on the module connection information in the development data.

[0118] The bus connection constraint data is used to define the data interface connection method and clock connection method between each functional module. It includes at least the data interface connection relationship, control interface connection relationship, clock signal connection relationship, reset signal connection relationship, interrupt signal connection relationship and bus arbitration relationship, thereby automatically generating the internal bus structure. The internal bus structure includes one or more of the following: AXI bus structure, AHB bus structure, SPI bus structure, I2C bus structure, LVDS interface and custom high-speed parallel interface.

[0119] 107: Automatically generate timing constraint data based on performance information.

[0120] The timing constraint data is used to limit the clock frequency, data setup time, and hold time. It includes at least system clock frequency constraints, input / output delay constraints, data setup time constraints, data hold time constraints, clock domain crossing constraints, multi-cycle path constraints, and pseudo-path constraints.

[0121] 108: After generating resource allocation data, connection constraint data, and timing constraint data, perform resource conflict detection to determine whether there are pin conflicts, clock conflicts, or insufficient logic resources. If so, automatically adjust the IP core selection result or hardware slot position according to the preset optimization strategy and regenerate the resource allocation data, connection constraint data, and timing constraint data. If not, input the generated resource allocation data, connection constraint data, timing constraint data, and FPGA logic project into the FPGA development environment for synthesis, placement, and routing to generate a bitstream file that meets the performance requirements of the target FPGA measurement and control system.

[0122] The resource conflict detection includes one or more of the following: IO pin conflict detection, logic resource overrun detection, DSP resource shortage detection, block memory shortage detection, clock resource conflict detection, timing constraint failure detection, and bus bandwidth shortage detection. The preset optimization strategy includes at least reselecting IP cores that meet the constraints, adjusting the hardware slot positions of functional modules, reducing the operating frequency, adjusting the bus structure, changing the clock allocation method, and reallocating logic resources. After optimization, resource allocation data, connection constraint data, and timing constraint data are regenerated, and resource conflict detection is performed again until there are no pin conflicts, clock conflicts, or insufficient logic resources. The synthesis, placement, and routing includes at least logic synthesis, placement and routing, timing analysis, power consumption analysis, and constraint checking.

[0123] Figure 9 A schematic diagram illustrating the connection relationship between an exemplary functional module and an FPGA is shown in some embodiments of this application.

[0124] refer to Figure 9 As shown, each functional module is connected to the FPGA core board through a slot interface. This connection includes data bus connection, control signal connection and clock signal connection. The bus connection constraint data limit diagram generated in step 106 shows the connection method between each module.

[0125] Figure 10 The diagram illustrates an exemplary method for generating system image files, software development kits, and graphical user interface programs according to some embodiments of this application.

[0126] refer to Figure 10As shown. In some embodiments of this application, step 103, when generating a matching system image file, software development kit, and graphical user interface program including an embedded processor control program and driver interface and communication interface configuration, includes at least the following steps 109 to 113.

[0127] 109: When new system configuration description text data is received, perform a difference analysis between the new system configuration description text data and the original system configuration description text data, and generate the difference analysis results.

[0128] The difference analysis is used to identify the functional modules, connections, and performance parameters that have changed in the target FPGA measurement and control system. It includes at least the detection of added functional modules, deleted functional modules, changes in functional module parameters, changes in module connections, changes in hardware slot positions, changes in communication interfaces, and changes in performance parameters. The results of the difference analysis are used to indicate the range of modules that need to be regenerated.

[0129] 110: Update the development data based on the difference analysis results and re-extract the corresponding standardized components from the preset resource library.

[0130] For functional modules, connection relationships, and performance parameters that have not changed, they will remain unchanged.

[0131] 111: While keeping the FPGA logic structure and driver for the unmodified module unchanged, update the corresponding FPGA logic project, embedded processor control program and graphical user interface for the module that has changed.

[0132] 112: Regenerate the bitstream file and the matching system image file, software development kit, and graphical user interface program for the updated FPGA logic project.

[0133] 113: Output the updated system image file, software development kit, and graphical user interface program to reconstruct the functions of the target FPGA measurement and control system.

[0134] In some embodiments of this application, after constructing or reconstructing the target FPGA measurement and control system, the generated target FPGA measurement and control system is automatically verified, corrected, and simulated to avoid the generated target FPGA measurement and control system being unable to be implemented or operate normally on the actual hardware platform.

[0135] Specifically, after generating the FPGA logic project, system image file, software development kit, and graphical user interface program, the FPGA logic project is subjected to realization verification. The realization verification includes at least resource usage detection, timing constraint detection, interface connection legality detection, and hardware slot position matching detection. When insufficient logic resources, timing constraints, pin conflicts, or interface connection errors are detected, the IP core selection results, module connection relationships, or hardware slot positions are automatically adjusted according to preset optimization rules, and the corresponding FPGA logic project and constraint data are regenerated until the preset realization conditions are met.

[0136] After passing the feasibility verification, a simulation operation verification is performed on the target FPGA measurement and control system. The simulation operation verification includes functional simulation of the generated FPGA logic project, software simulation of the embedded processor control program, and interface call testing of the graphical user interface program, in order to verify whether the data interaction relationship, control flow and communication interface between the functional modules conform to the definition in the system configuration description text data.

[0137] In some embodiments of this application, after the target FPGA measurement and control system is built or reconstructed, feedback is sent to the target terminal specified by the user so that the user can view the generated system structure and operating status.

[0138] The system allows users to modify or adjust the target FPGA measurement and control system via the target terminal after viewing it. Modifications include adjusting functional module types, modifying performance parameters, changing hardware slot positions, or modifying module connection relationships. Upon receiving user modifications, the system re-executes the processes of development data generation, standardized component extraction, FPGA logic engineering generation, system image file generation, and graphical user interface generation. Verification and simulation are then performed again until the user confirms that the generated target FPGA measurement and control system meets the usage requirements. After the user confirms that the requirements are met, the system outputs the final generated system image file, software development kit, and graphical user interface program to achieve automatic construction or reconstruction of the target FPGA measurement and control system.

[0139] The preferred embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the specific details of the embodiments described above. Within the scope of the technical concept of this application, various simple modifications can be made to the technical solutions of this application, and these simple modifications all fall within the protection scope of this application. For example, the various specific technical features described in the specific embodiments described above can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this application will not describe the various possible combinations separately. Furthermore, various different embodiments of this application can also be arbitrarily combined, as long as they do not violate the spirit of this application, they should also be considered as the content disclosed in this application.

[0140] It should also be understood that, in the various method embodiments of this application, the order of the processes mentioned above does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0141] The generation method 100 provided in the embodiments of this application has been described above. The generation apparatus 200 provided in the embodiments of this application will be described below.

[0142] This application also provides an FPGA measurement and control system generation device 200, which takes the physical deployment information of modular hardware circuits as one of the basic inputs for system generation and describes it together with functional logic through standardized text to drive full-stack automated generation.

[0143] Figure 11 A connection diagram of an exemplary FPGA measurement and control system generation apparatus 200 according to some embodiments of this application is shown.

[0144] refer to Figure 11 As shown. The generation device 200 of this application includes at least a preset resource library 201, a resource mapper 202, an automatic generator 203, and a processing unit 204, wherein the components are connected by wired or wireless means to form an overall device for automatically generating FPGA measurement and control systems.

[0145] The preset resource library 201 includes at least a hardware IP core resource library 201a, an embedded software driver library 201b, and a host computer interface library 201c, which are used to store reusable IP cores, driver templates, and software interface templates.

[0146] Specifically, the hardware IP core resource library 201a stores reusable FPGA functional IP cores, which include at least one or more of the following: analog-to-digital conversion control IP core, digital-to-analog conversion control IP core, digital signal processing IP core, direct digital frequency synthesis IP core, lock-in amplifier IP core, communication interface IP core, and clock management IP core; the embedded software driver library 201b stores driver templates for controlling the operation of the IP cores, which are used to initialize, configure, and read the status of FPGA logic modules in the embedded processor, including but not limited to initialization function templates, interrupt handling function templates, data read / write function templates, and configuration register access templates; the host computer interface library 201c stores application programming interface templates corresponding to the drivers, which are used to generate application programming interface functions in the host computer software development kit, including but not limited to serial communication interface templates, Ethernet communication interface templates, PCIe interface templates, USB interface templates, and TCP / IP communication interface templates.

[0147] The resource mapper 202 is connected to the preset resource library 201 and is used to retrieve and call up the hardware IP core, driver template and host computer interface template corresponding to the target functional module from the hardware IP core resource library 201a, embedded software driver library 201b and host computer interface library 201c, that is, to call up the relevant hardware resources and software resources.

[0148] Specifically, the resource mapper 202 parses the user-input FPGA measurement and control system configuration description text data and determines the target measurement and control system structure based on the system configuration description text data. Then, it searches for matching IP cores in the hardware IP core resource library 201a, the corresponding driver templates in the embedded software driver library 201b, and the corresponding software interface templates in the host computer interface library 201c. Then, it establishes the corresponding hardware resource mapping relationship, software driver mapping relationship, and host computer interface mapping relationship, etc., in order to obtain the hardware and software resources required by the target FPGA measurement and control system.

[0149] The automatic generator 203 includes at least a physical pin resolver 203a, an FPGA project generator 203B, an embedded project generator 203c, and a host computer project generator 203d, and is used to automatically generate FPGA measurement and control system engineering files.

[0150] Specifically, the physical pin resolver 203a reads the physical slot location (phy_slot) information of the hardware module defined in the system configuration description text data and queries the hardware mapping database to generate FPGA pin constraint data. The hardware mapping database defines the FPGA pin number, interface controller type (such as SPI, AXI), electrical standard (such as LVCMOS 3.3V), and model of the connected hardware module corresponding to each physical slot (such as SB1, J2), and generates the pin constraint file io.xdc.

[0151] The FPGA project generator 203B is used to automatically generate FPGA logic projects. Specifically, it includes automatically instantiating corresponding IP cores, automatically generating logical connection structures based on module connection relationships, automatically generating clock and timing constraints based on performance parameters, importing FPGA pin constraint data, and calling the FPGA development environment to perform synthesis, placement and routing, and bitstream generation operations, thereby generating the target FPGA logic project and its corresponding bitstream file. For example, it can read system configuration description text data to automatically generate a TCL script and call Xilinx's Vivado development tool to run the TCL script. Vivado creates the FPGA logic project based on the script, automatically instantiates the IP cores of each functional module, connects them according to connections, adds the generated io.xdc file as a pin constraint file, and finally synthesizes and generates a PL hardware description file (.xsa) containing the PL bitstream.

[0152] The embedded project generator 203c is used to automatically generate embedded software projects based on FPGA logic projects. Specifically, it includes reading register mapping relationships from the FPGA logic project, extracting corresponding driver templates from the embedded software driver library 201b, parameterizing the driver templates according to module parameters, generating processor control programs for initializing, controlling, and reading various functional modules, generating communication interface programs between the processor and external devices, and compiling and linking the control programs with bitstream files to generate a system image file for booting the target system. For example, it can automatically generate an XSCT script by reading system configuration description text data and call Xilinx's development tool Vitis to run the XSCT script. Vitis uses the XSCT script to call the description file (.xsa) to create a PS project, generating the main program main.c, which includes driver libraries for various functional modules, and finally generating a ZYNQ chip boot image (BOOT.bin) including the PL bitstream and the PS boot image.

[0153] The host computer project generator 203d is used to automatically generate host computer software development kits and graphical user interface programs. Specifically, it includes constructing an interface description model based on functional module information, extracting corresponding interface templates from the host computer interface library 201c and configuring them parametrically, generating an application programming interface function library, generating sample programs and interface documentation, generating a graphical interface description model based on functional module information, generating a parameter control interface and a data display interface based on the interface description model, binding interface controls with application programming interface functions, and generating an executable graphical user interface program. For example, it can read system configuration description text data to automatically generate PC-side SDK and GUI, where the APIs in the SDK correspond to the module instances (such as adc1, dds1) in the configuration file.

[0154] The processing unit 204 is connected to the preset resource library 201, the resource mapper 202 and the automatic generator 203203 respectively, and is used to realize the construction or reconstruction of the target FPGA measurement and control system.

[0155] Specifically, the processing unit 204 reads the received system configuration description text data and uses it as development data describing the structure and function of the target FPGA measurement and control system. Then, it calls the resource mapper 202 to obtain the corresponding resources and calls the automatic generator 203 to generate the FPGA logic project, embedded software project, and host computer software project. Then, it generates and outputs the bitstream file, system image file, software development kit, and graphical user interface program of the target FPGA measurement and control system to complete the construction of the target FPGA measurement and control system. Furthermore, when new system configuration description text data is received, the processing unit 204 is also used to perform difference analysis between the new system configuration description text data and the original system configuration description text data, and only re-execute the resource mapping and automatic generation process for the functional modules that have changed, so as to realize the rapid reconstruction of the FPGA measurement and control system.

[0156] Figure 12 A schematic diagram of the structure of an exemplary target FPGA measurement and control system hardware platform according to some embodiments of this application is shown.

[0157] refer to Figure 12 As shown, the hardware platform includes an FPGA core board mounting area, multiple functional module slot interfaces, an FPC high-speed connection interface, and power and communication interfaces. Each functional module can be installed on the hardware platform via slots. The hardware slot location information in the system configuration description text data is used to describe the installation position of each functional module on the hardware platform, so as to generate corresponding pin assignments and connection constraints when automatically generating FPGA logic projects.

[0158] In some examples of this application, Figure 13A schematic block diagram of an exemplary processing unit 204 according to some embodiments of this application is shown.

[0159] like Figure 13 As shown, the processing unit 204 may include: a data generation module 204a, used to generate development data for the target FPGA measurement and control system to be generated based on the acquired system configuration description text data, wherein the development data includes at least functional module information, performance parameters, hardware slot positions, and module connection information; a data retrieval module 204b, used to extract matching standardized components from a preset resource library based on the development data and call the FPGA development environment to integrate all extracted standardized components, generate an FPGA logic project, and compile and generate the corresponding bitstream file, wherein the preset resource library includes at least a hardware IP core resource library 201a, an embedded software driver library 201b, and a host computer interface library 201c; and a data construction module 204c, used to generate a matching system image file, software development kit, and graphical user interface program, including an embedded processor control program and driver interface and communication interface configuration, based on the FPGA logic project and the bitstream file, so as to realize the automatic construction or reconstruction of the target FPGA measurement and control system.

[0160] For example, the reference working process of this application is as follows:

[0161] Users first define their measurement and control requirements (e.g., building a lock-in amplifier system for weak signal detection). Then, users generate a formatted text description file (YAML) describing the requirements, either manually or with software assistance. In other words, users can manually write YAML configuration files based on their requirements, or describe their requirements to the integrated auxiliary design front-end in natural language, such as: "Build a lock-in amplifier, with the ADC in slot 2, the DAC in slot 5, and a 1kHz reference signal generated by the DDS." The auxiliary design front-end uses a large language model to understand the intent and automatically generate the corresponding YAML configuration file.

[0162] Regardless of the method used, users will obtain the network_analyzer.yaml configuration file shown below (this file fully describes the requirements of the FPGA measurement and control system, including the physical slots and logical connections of the hardware modules):

[0163] modules:

[0164] - name: adc1

[0165] type: AD402x

[0166] phy_slot: SB2

[0167] - name: dac1

[0168] type: AD5791

[0169] phy_slot: SB5

[0170] - name: dds1

[0171] type: DDS

[0172] phy_slot: null

[0173] - name: lockin1

[0174] type: LockIn

[0175] phy_slot: null

[0176] connections:

[0177] - from: dds1.phase_out

[0178] to: lockin1.ref_phase

[0179] - from: adc1.dataout

[0180] to: lockin1.signal_in

[0181] - from: dds1.sin_out

[0182] to: dac1.datain

[0183] The user submits the YAML configuration file to the generation device 200 of this application. After parsing the file, the generation device 200 automatically executes the following process to generate the corresponding FPGA measurement and control system:

[0184] Resource identification and mapping: Copy all logic and software resources related to AD402x, AD5791, DDS, and LockIn from the code repository for later use.

[0185] The pin constraint file (io.xdc) is generated, identifying adc1 and dac1 as physical modules, located at SB2 and SB5 respectively. The hardware mapping database is queried to find that SB2 corresponds to FPGA pins such as Pin_G7; SB5 corresponds to FPGA pins such as Pin_U14; dds1 and lockin1 are identified as pure digital IP core modules (phy_slot: null), which do not need to be bound to specific physical pins; the pin constraint file (io.xdc) is generated based on the above information.

[0186] The FPGA hardware project is generated automatically, starting Vivado and creating an FPGA project network_analyzer_pl; four IP cores are instantiated from the IP core library: AD402x, AD5791, DDS, and LockIn; physical interface binding: the pin constraints generated in the previous step (io.xdc) are imported.

[0187] The logic connection and integration automatically connects the data paths within the FPGA logic according to the connections section, connecting the phase_out port of the DDS IP core to the ref_phase input port of the LockIn IP core; connecting the dataout port of the AD402x IP core to the signal_in input port of the LockIn IP core; and connecting the sin_out port of the DDS IP core to the datain input port of the AD5791 IP core. At the same time, it automatically integrates the necessary clock, reset, and bus interconnect (such as AXI4-Lite) logic; and calls the synthesis and placement and routing tools, including the PL hardware description file (network_analyzer.xsa) containing the PL bitstream.

[0188] The embedded (PS) software project is generated automatically, Vitis is launched, and a PS project network_analyzer_ps is created based on network_analyzer.xsa. Four header files are included from the function library: AD402x.h, AD5791.h, DDS.h, and LockIn.h. The main function main.c, which calls the above header files and other necessary components, is automatically generated. main.c is compiled to generate the ZYNQ chip boot image (BOOT.bin) that includes the PL bitstream and the PS boot image.

[0189] The host computer (PC) software development kit (SDK) and graphical user interface (GUI) are generated. A Python SDK is generated, which contains control classes corresponding to the four modules (adc1, dac1, dds1, lockin1) in the configuration file, such as API functions like dds1.set_frequency(1000) and lockin1.get_R(). A basic GUI is generated, which includes panels for DDS parameter settings, LockIn result display, and real-time plotting of ADC data.

[0190] The system is packaged and output, which packages and outputs the configuration file, ZYNQ chip boot image (BOOT.bin), SDK and GUI, and delivers them to the target terminal specified by the user. The target terminal can be one or more of the following: smartphone, host computer, industrial control computer, tablet computer, laptop computer or terminal device with data processing capabilities.

[0191] Then, the user burns BOOT.bin to the hardware through the target terminal. After powering on, the user can control the entire lock-in amplifier system through the generated GUI or SDK, realizing full automation from requirement description (YAML file) to software generation.

[0192] The core configuration file is not limited to YAML; it can also use JSON, XML, TOML, or a custom text format. IP core libraries, driver libraries, etc., can be physically separated or integrated into a unified database. The mapping relationship can be hard-coded in the toolchain or managed through an external database or configuration file. In practical applications, a complete GUI may not be generated; only an SDK may be generated, or interface templates may be generated for different host computer frameworks (such as PyQt and Web).

[0193] It should be understood that the device embodiments and method embodiments can correspond to each other, and similar descriptions can be referred to the method embodiments. To avoid repetition, further details are omitted here. Specifically, the generation device 200 can correspond to the corresponding subject in the generation method 100 of the embodiments of this application, and each unit in the generation device 200 is for implementing the corresponding process in the generation method 100. For the sake of brevity, further details are omitted here.

[0194] It should also be understood that the various units in the generation apparatus 200 involved in the embodiments of this application are based on logical functional division. In practical applications, the function of one unit can also be implemented by multiple units, or the function of multiple units can be implemented by one unit. Furthermore, these functions can also be implemented with the assistance of one or more other units. For example, some or all of the generation apparatus 200 can be merged into one or more additional units. As another example, some units(s) in the generation apparatus 200 can be further divided into multiple functionally smaller units, which can achieve the same operation without affecting the technical effects of the embodiments of this application. Furthermore, the generation apparatus 200 may also include other units. In practical applications, these functions can also be implemented with the assistance of other units, and can be implemented collaboratively by multiple units.

[0195] It should also be understood that the terms "module" or "unit" used in the embodiments of this application refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0196] For example, the generation apparatus 200 involved in the embodiments of this application, and the method of the embodiments of this application, can be constructed by running a computer program (including program code) capable of executing the steps involved in the corresponding method on a general-purpose computing device including processing elements and storage elements such as a central processing unit (CPU), random access memory (RAM), and read-only memory (ROM). The computer program can be recorded on, for example, a computer-readable storage medium and loaded into an electronic device through the computer-readable storage medium. The computer program is used to implement the corresponding method of the embodiments of this application. In other words, the units mentioned above can be implemented in hardware, in software instructions, or in a combination of hardware and software. Specifically, the steps of the method embodiments in the embodiments of this application can be completed by the integrated logic circuits of the hardware in the processor and / or in software instructions. The steps of the method disclosed in the embodiments of this application can be directly embodied in the execution by a hardware decoding processor, or by the execution by a combination of hardware and software in the decoding processor. Optionally, the software can be located in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The software in the memory can be run by a processor to perform the steps described in the method embodiments above.

[0197] Figure 14 A schematic structural diagram of an exemplary electronic device 300 according to some embodiments of this application is shown.

[0198] like Figure 14As shown, the electronic device 300 includes at least a processor 310 and a computer-readable storage medium 320. The processor 310 and the computer-readable storage medium 320 can be connected via a bus or other means. The computer-readable storage medium 320 stores a computer program 321, which includes computer instructions. The processor 310 executes the computer instructions stored in the computer-readable storage medium 320. The processor 310 is the computing and control core of the electronic device 300, and is suitable for implementing one or more computer instructions, specifically for loading and executing one or more computer instructions to achieve a corresponding method flow or function.

[0199] As an example, processor 310 may also be referred to as a central processing unit (CPU). Processor 310 may include, but is not limited to: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete component gate or transistor logic devices, discrete hardware components, etc.

[0200] As an example, the computer-readable storage medium 320 may be a high-speed RAM memory or a non-volatile memory, such as at least one disk storage device; optionally, it may also be at least one computer-readable storage medium located remotely from the aforementioned processor 310. Specifically, the computer-readable storage medium 320 includes, but is not limited to, volatile memory and / or non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0201] like Figure 14 As shown, the electronic device 300 may also include a transceiver 330.

[0202] The processor 310 can control the transceiver 330 to communicate with other devices; specifically, it can send information or data to other devices or receive information or data sent by other devices. The transceiver 330 may include a transmitter and a receiver. The transceiver 330 may further include antennas, and the number of antennas may be one or more.

[0203] It should be understood that the various components in the electronic device 300 are connected via a bus system, which includes a data bus, a power bus, a control bus, and a status signal bus. It is worth noting that the electronic device 300 can be any type of electronic device with data processing capabilities; the computer-readable storage medium 320 stores first computer instructions; the processor 310 loads and executes the first computer instructions stored in the computer-readable storage medium 320 to achieve… Figure 2 The corresponding steps in the method embodiment shown; in a specific implementation, the first computer instruction in the computer-readable storage medium 320 is loaded by the processor 310 and the corresponding steps are executed. To avoid repetition, they will not be described again here.

[0204] According to another aspect of this application, embodiments of this application provide a chip. This chip can be an integrated circuit chip with signal processing capabilities, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The chip can also be referred to as a system-on-a-chip (SoC), system-on-a-chip (SoC), chip system, or system-on-chip, etc. This chip can be applied to various electronic devices capable of mounting chips, enabling the device with the chip mounted to execute the corresponding steps in the methods or logic block diagrams disclosed in the embodiments of this application. For example, the chip may be suitable for implementing one or more computer instructions, specifically suitable for loading and executing one or more computer instructions to achieve a corresponding method flow or corresponding function.

[0205] According to another aspect of this application, embodiments of this application provide a computer-readable storage medium (Memory). This computer-readable storage medium is a computer's memory device used to store programs and data. It is understood that the computer-readable storage medium here may include both built-in storage media within the computer and, of course, extended storage media supported by the computer. The computer-readable storage medium provides storage space that stores the operating system of an electronic device. This storage space contains computer instructions suitable for loading and execution by a processor. When these computer instructions are read and executed by the processor of the computer device, they cause the computer device to perform the corresponding steps in the methods or logic diagrams disclosed in the embodiments of this application.

[0206] According to another aspect of this application, embodiments of this application provide a computer program product or computer program. The computer program product or computer program includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform corresponding steps in the methods or logic block diagrams disclosed in the embodiments of this application. In other words, when the solutions provided in this application are implemented using software, they can be implemented in whole or in part as a computer program product or computer program. The computer program product or computer program includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes of the embodiments of this application are run or the functions of the embodiments of this application are implemented.

[0207] It is worth noting that the computer involved in this application can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions involved in this application can be stored in a computer-readable storage medium, or can be transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0208] Those skilled in the art will recognize that the units and process steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. In other words, those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of protection of this application.

[0209] Finally, it should be noted that the above content is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims. For example, the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. Furthermore, various different embodiments of this application can also be arbitrarily combined, as long as they do not violate the basic idea of ​​this application, and they should also be considered as the content disclosed in this application.

Claims

1. A method for generating an FPGA measurement and control system, characterized in that, include: Based on the received system configuration description text data, development data for describing the structure and function of the target FPGA measurement and control system is generated, wherein the development data includes at least functional module information, performance parameters, hardware slot locations and module connection information; Based on the development data, matching standardized components are extracted from the preset resource library and the FPGA development environment is called to integrate all the extracted standardized components, generate FPGA logic projects and compile them to generate corresponding bitstream files. The preset resource library includes at least a hardware IP core resource library, an embedded software driver library and a host computer interface library. Based on the FPGA logic project and bitstream file, a matching system image file, software development kit, and graphical user interface program, including embedded processor control program, driver interface program, and communication interface configuration, are generated to achieve automatic construction or reconstruction of the target FPGA measurement and control system.

2. The generation method according to claim 1, characterized in that... Based on the received system configuration description text data, development data is generated to describe the structure and functions of the target FPGA measurement and control system, including: Define configuration syntax rules that describe various modules, hardware resources and module connection relationships in the target FPGA measurement and control system. The syntax rules include at least module type field, performance parameter field, physical slot field, signal interface field and interconnection relationship field. According to the configuration syntax rules, define corresponding functional module instances in the configuration file, and set module type, performance parameter, and physical slot fields for each functional module instance. Also define the signal connection relationships and hardware slot locations for each functional module instance, wherein the signal connection relationships include at least data flow direction, control signal connection, synchronization clock connection, and trigger signal connection; and, The configuration file is output as the system configuration description text data, and the system configuration description text data is parsed to generate development data.

3. The generation method according to claim 1 or 2, characterized in that, The process involves integrating all extracted standardized components using the FPGA development environment, generating an FPGA logic project, and compiling it to produce the corresponding bitstream file, including: Based on the functional module information and performance parameters in the development data, candidate IP cores that meet the performance constraints are retrieved from the constructed hardware IP core resource library containing various standardized FPGAs. The hardware IP core resource library stores various reusable IP cores, and the IP cores include at least analog-to-digital conversion control IP cores, digital-to-analog conversion control IP cores, digital signal processing IP cores, direct digital frequency synthesis IP cores, lock-in amplifier IP cores, communication interface IP cores, and clock management IP cores. The optimal IP core is selected from the candidate IP cores according to the priority rules, wherein the priority rules include at least the principle of minimum resource consumption, the principle of maximum timing margin, and the principle of interface compatibility. Based on the module connection information in the development data, the internal bus structure of the target FPGA measurement and control system is generated, and the data interface connection, control interface connection, and clock interface connection of each IP core are completed; and... The optimal IP core is automatically packaged and integrated using the FPGA development environment, generating FPGA logic engineering, constraint files, pin allocation information, and clock configuration information, and then compiled to generate the corresponding bitstream file.

4. The generation method according to claim 3, characterized in that, The step of generating a matching system image file, including the embedded processor control program, driver interface program, and communication interface configuration, based on the FPGA logic project and bitstream file, includes: In the hardware platform of the target FPGA measurement and control system, a programmable system architecture containing an embedded processor is pre-configured, wherein the embedded processor is an ARM processor or a soft-core processor and interacts with the FPGA logic through an internal bus. Based on the functional module information and module connection information in the development data, the corresponding driver template is retrieved from the preset embedded software driver library and the driver template is parameterized according to the performance parameters. Based on the register mapping relationship in the FPGA logic engineering, generate initialization programs, register configuration programs, and status reading programs for controlling each functional module; Based on the communication requirements of the target FPGA measurement and control system, a communication interface program between the processor and the host computer is generated, wherein the communication interface program includes at least one or more of the following: serial communication interface program, Ethernet communication interface program, and USB communication interface program; and... All generated programs are compiled and linked to generate an embedded executable program that matches the bitstream file, and a system image file is generated based on the embedded executable program.

5. The generation method according to claim 4, characterized in that, Generate a system image file based on the embedded executable program, including: Establish image generation rules for starting the target FPGA measurement and control system, wherein the image generation rules are used to define the storage location and loading order of FPGA configuration data, embedded programs and startup parameters; According to the image generation rules, the bitstream file is converted into loadable configuration data and the embedded executable program is converted into a processor executable image; A startup loading program is generated to sequentially complete FPGA configuration loading, embedded processor startup, and system initialization when the target FPGA measurement and control system is powered on. A startup configuration file defining the storage medium type, loading address, and startup method is also generated based on the hardware platform type of the target FPGA measurement and control system. The configuration data, processor executable image, bootloader, and boot configuration file are packaged to generate a system image file that can be directly written to non-volatile memory.

6. The generation method according to claim 5, characterized in that, Based on the FPGA logic project and bitstream file, a software development kit is generated, including: Construct a host computer interface description model that describes the control parameters, status parameters and data access interfaces of each functional module, and select a software interface template corresponding to each functional module from a preset host computer interface library based on the interface description model, and parameterize the interface template according to performance parameters and module connection information. Generate application programming interface (API) functions for accessing the embedded processor's communication interface and generate an interface specification document corresponding to the target FPGA measurement and control system based on the development data; and... Generate and output a software development kit for secondary development, wherein the software development kit includes at least an interface function library, sample programs, interface documentation, and compilation configuration files.

7. The generation method according to claim 6, characterized in that, Based on the FPGA logic project and bitstream file, a graphical user interface program is generated, including: An interface description model is constructed to describe the control interface of the target FPGA measurement and control system. Based on the functional module information and performance information in the development data, an interface template corresponding to each functional module is retrieved from the preset graphical interface template library, and the interface template is instantiated and configured according to the module parameters. A data display interface for showing data flow relationships is generated based on the module connection information of the development data, and a parameter control panel is generated based on the interface description model. The generated interface controls are bound to the application programming interface (API) functions in the software development kit (SDK) so that the graphical user interface can access the embedded processor control program through the API functions; and... Optimize the layout of the generated graphical user interface and output an executable graphical user interface program.

8. The generation method according to claim 1 or 7, characterized in that, When generating matching system image files, software development kits, and graphical user interface programs, including embedded processor control programs, driver interface and communication interface configurations, the following are also included: When new system configuration description text data is received, a difference analysis is performed between the new system configuration description text data and the original system configuration description text data, and the difference analysis results are generated. The development data is updated based on the difference analysis results, and the corresponding standardized components are extracted again from the preset resource library. While keeping the FPGA logic structure and driver for the unmodified modules unchanged, update the corresponding FPGA logic project, embedded processor control program and graphical user interface for the modules that have changed. Regenerate the bitstream file and the matching system image file, software development kit, and graphical user interface program for the updated FPGA logic project; and, Output updated system image files, software development kits, and graphical user interface programs to reconstruct the functions of the target FPGA measurement and control system.

9. The generation method according to claim 3 or 7, characterized in that, The automatic integration of standardized components using the FPGA development environment to generate FPGA logic projects also includes: FPGA resource allocation data is generated based on the functional module information and hardware slot location information, wherein the resource allocation data is used to describe the allocation relationship of logic units, memory units, DSP units and IO pins; Based on the module connection information, bus connection constraint data is generated, wherein the bus connection constraint data is used to limit the data interface connection method and clock connection method between each functional module; Timing constraint data is automatically generated based on the performance information, wherein the timing constraint data is used to limit the clock frequency, data setup time, and hold time; and After generating the resource allocation data, connection constraint data, and timing constraint data, resource conflict detection is performed to determine whether there are pin conflicts, clock conflicts, or insufficient logic resources. If so, the IP core selection result or hardware slot position is automatically adjusted according to the preset optimization strategy, and the resource allocation data, connection constraint data, and timing constraint data are regenerated. If not, the generated resource allocation data, connection constraint data, timing constraint data, and FPGA logic project are input into the FPGA development environment for synthesis, placement, and routing to generate a bitstream file that meets the performance requirements of the target FPGA measurement and control system.

10. A device for generating an FPGA measurement and control system that implements the method of any one of claims 1-9, characterized in that, include: The preset resource library includes at least a hardware IP core resource library, an embedded software driver library, and a host computer interface library, which are used to store reusable IP cores, driver templates, and software interface templates. The resource mapper is used to retrieve hardware and software resources from the hardware IP core resource library, embedded software driver library, and host computer interface library. Automatic generators include one or more of the following: physical pin resolvers, FPGA project generators, embedded project generators, and host computer project generators; A processing unit, connected to the preset resource library, resource mapper, and automatic generator respectively, is used to construct or reconstruct the target FPGA measurement and control system; wherein, the processing unit includes: The data generation module is used to generate development data for the target FPGA measurement and control system to be generated based on the acquired system configuration description text data. The development data includes at least functional module information, performance parameters, hardware slot locations, and module connection information. The data retrieval module is used to extract matching standardized components from a preset resource library based on the development data, and call the FPGA development environment to integrate all the extracted standardized components, generate an FPGA logic project, and compile and generate the corresponding bitstream file. The preset resource library includes at least a hardware IP core resource library, an embedded software driver library, and a host computer interface library. The data construction module is used to generate a matching system image file, software development kit, and graphical user interface program, including embedded processor control program, driver interface and communication interface configuration, based on the FPGA logic project and bitstream file, so as to realize the automatic construction or reconstruction of the target FPGA measurement and control system.

11. An electronic device, characterized in that, include: A processor, adapted to execute computer programs; A computer-readable storage medium storing a computer program that, when executed by the processor, implements the method of any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, Used to store a computer program that, when run on a computer, causes the computer to perform the method of any one of claims 1 to 9.

13. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the method of any one of claims 1 to 9.

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