Pixel circuit and display device including the same

Abstract

An embodiment discloses a pixel circuit and a display device including the pixel circuit. The pixel circuit includes: a driving element including a first electrode to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; a first switching element that is turned on in response to a first scan signal to connect a data voltage line to a third node; a second switching element that is turned on in response to a second scan signal to connect the third node to the first node; a third switching element that is turned on in response to the second scan signal to connect a reference voltage line to a fourth node; a fourth switching element that is turned on in response to the second scan signal to connect the fourth node to the first node; a first capacitor connected between the third node and the fourth node; and a second capacitor connected between the fourth node and the second node.

Description

[0001] Cross-references to related applications This application claims priority and benefit to Korean Patent Application No. 10-0202682, filed on December 31, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a pixel circuit and a display device including the pixel circuit. Background Technology

[0003] Electroluminescent displays can be categorized into inorganic and organic electroluminescent displays based on the material of their light-emitting layers. Active-matrix organic electroluminescent displays include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs") and possess advantages such as fast response time, high luminous efficiency, high brightness, and wide viewing angles. In organic electroluminescent displays, OLEDs are formed within individual pixels. Organic electroluminescent displays not only exhibit fast response times, high luminous efficiency, high brightness, and wide viewing angles, but also can represent true black levels, thus providing excellent contrast and color reproduction.

[0004] Pixel circuitry is incorporated in each pixel of a display device to sense and compensate for the threshold voltage of the driving transistor. In a pixel circuit with a source follower structure, two capacitors are connected between the gate and source nodes of the driving transistor, and the data transmission rate is determined by their dimensions. Therefore, data transmission loss is a potential problem. Summary of the Invention

[0005] The embodiment provides a pixel circuit that improves data transmission loss caused by capacitors and a display device including the pixel circuit.

[0006] The technical problems to be solved by this disclosure are not limited to those described above. Other problems not mentioned can be clearly understood by those skilled in the art from the following description of the invention.

[0007] According to one aspect of this disclosure, a pixel circuit may include: a driving element, the driving element including a first electrode to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; a first switching element, the first switching element being turned on in response to a first scan signal to connect a data voltage line to a third node; a second switching element, the second switching element being turned on in response to a second scan signal to connect the third node to the first node; a third switching element, the third switching element being turned on in response to the second scan signal to connect a reference voltage line to a fourth node; a fourth switching element, the fourth switching element being turned on in response to the second scan signal to connect the fourth node to the first node; a first capacitor, the first capacitor being connected between the third node and the fourth node; and a second capacitor, the second capacitor being connected between the fourth node and the second node.

[0008] The pixel circuit may further include: a light-emitting element comprising an anode connected to the fifth node and a cathode to which a low-potential power supply voltage is applied; a fifth switching element that is turned on in response to an EM signal to connect the second node and the fifth node; and a sixth switching element that is turned on in response to a third scan signal to connect the fifth node and a reset voltage line.

[0009] The first and third to sixth switching elements can be n-type oxide transistors, and the second switching element and the driving element can be p-type polysilicon transistors.

[0010] The first to sixth switching elements can all be n-type oxide transistors.

[0011] The data voltage supplied to the data voltage line can be higher than the reference voltage supplied to the reference voltage line, and the reference voltage can be higher than the reset voltage supplied to the reset voltage line.

[0012] The pixel circuit can be driven in the order of initialization phase, sensing phase, data writing phase and light emission phase. In the initialization phase, the first and third to sixth switching elements can be turned on, and the second switching element can be turned off. In the sensing phase, the third, fourth and sixth switching elements can be turned on, and the remaining switching elements can be turned off. In the data writing phase, the second and sixth switching elements can be turned on, and the remaining switching elements can be turned off. In the light emission phase, the second and fifth switching elements can be turned on, and the remaining switching elements can be turned off.

[0013] During the initialization phase, the voltages of the first scan signal, second scan signal, third scan signal, and EM signal can all be gate high. During the sensing phase, the voltages of the first scan signal and EM signal can be gate low, while the voltages of the second and third scan signals can be gate high. During the data writing phase, the voltages of the first scan signal, second scan signal, and EM signal can be gate low, while the voltage of the third scan signal can be gate high. During the light emission phase, the voltages of the first to third scan signals can be gate low, while the voltage of the EM signal can be gate high.

[0014] During the initialization phase, the first switching element can be turned on, allowing the data voltage to be stored in the first capacitor.

[0015] During the initialization phase, a reset voltage can be applied to the fifth node to reset the anode of the light-emitting element.

[0016] During the sensing phase, the threshold voltage of the driving element can be stored in the second capacitor.

[0017] During the data writing phase, the second switching element can be turned on, allowing the data voltage stored in the third node to be charged into the first node.

[0018] During the light-emitting phase, the third switching element can be turned off, allowing the first capacitor and the second capacitor to be connected in series.

[0019] According to the embodiment, since the data voltage transmission rate is not determined by the capacitance ratio of the first capacitor and the second capacitor, but rather the data voltage stored in the first capacitor is applied to the gate of the driving transistor, the data voltage transmission rate can be increased to reduce the range of the data voltage. Therefore, the power consumption of the display device is reduced, thereby achieving low-power driving.

[0020] Furthermore, during the anode reset frame drive, the threshold voltage can be sensed and compensated during the anode reset interval. Therefore, accurate sensing of the threshold voltage becomes possible, thereby improving brightness uniformity.

[0021] However, the effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other effects not mentioned below based on the description of the invention below. Attached Figure Description

[0022] These and / or other aspects of this disclosure will become apparent and more readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure; Figure 2 It is shown Figure 1A cross-sectional view of the cross-sectional structure of the display panel shown; Figure 3 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure; Figure 4 This is a waveform diagram of a pixel circuit according to an embodiment of the present disclosure; Figures 5A to 5D This is a circuit diagram showing the operation of a pixel circuit according to an embodiment of the present disclosure in sequence; Figure 6 This is a diagram illustrating a pixel circuit according to another embodiment of the present disclosure; Figure 7 This is a block diagram of a gate driver according to an embodiment of the present disclosure; Figure 8 A light emission control signal driver according to an embodiment of the present disclosure is shown; Figure 9 This is a waveform diagram showing the operation of the refresh frame and anode reset frame of the pixel circuit in Figure 5; Figure 10 This is a circuit diagram illustrating the initialization phase of a pixel circuit according to an embodiment of the present disclosure; and Figure 11 This is a circuit diagram illustrating the threshold voltage sensing stage of a pixel circuit according to an embodiment of the present disclosure. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as methods for implementing them, will become clear from the following detailed description of embodiments in conjunction with the accompanying drawings. This disclosure is not limited to the following embodiments, which can be implemented in various different forms; rather, these embodiments are provided to make the disclosure of this invention complete and to enable those skilled in the art to fully understand the scope of the invention, which is limited only to the scope of the appended claims.

[0024] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings are merely examples to describe embodiments of this disclosure, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally refer to the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0025] Terms used herein such as “including,” “comprising,” “having,” and “consisting of” are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, references to the singular should be interpreted to include the plural.

[0026] When interpreting components, they are interpreted as including tolerances, even if not explicitly stated.

[0027] When describing positional relationships, such as "on," "above," "below," or "next to," one or more other components may be inserted between the two components unless "immediately adjacent" or "directly" is used.

[0028] The terms "first," "second," etc., can be used to distinguish components, but the function or structure of these components is not limited to the serial number or component name assigned to the component.

[0029] The following embodiments can be combined or associated with each other, in whole or in part, and can be technically interlocked and driven in various ways. The embodiments can be implemented independently of each other, or they can be implemented together in an associated relationship.

[0030] Each pixel is divided into multiple sub-pixels of different colors to achieve color, and each sub-pixel includes a transistor that serves as a switching element or a driving element. This transistor can be implemented as a thin-film transistor (TFT).

[0031] The driving circuit of a display device writes pixel data of an input image to the pixels. The driving circuit of a flat panel display device includes a data driver for supplying data signals to data lines and a gate driver for supplying gate signals to gate lines.

[0032] In the display device disclosed herein, the pixel circuit may include a plurality of transistors. The transistors may be implemented as oxide thin-film transistors (TFTs) including oxide semiconductors or low-temperature polycrystalline silicon TFTs (LTPS TFTs) including low-temperature polycrystalline silicon.

[0033] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. Within the transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor and reach the outside. Within the transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, the current flows from the drain to the source. In the case of a p-channel transistor, since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, the current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0034] The gate signal can swing between the gate on-state voltage and the gate off-state voltage. The gate on-state voltage is set to a voltage higher than the transistor's threshold voltage. The gate off-state voltage is set to a voltage lower than the transistor's threshold voltage.

[0035] The transistor turns on in response to a gate on-state voltage and turns off in response to a gate off-state voltage. In the case of an n-channel transistor, the gate on-state voltage can be the gate high voltage VGH and VEH, and the gate off-state voltage can be the gate low voltage VGL and VEL.

[0036] In the following description, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described with respect to an organic light-emitting display device, but the present disclosure is not limited thereto. In the description of the embodiments, the present disclosure is not intended to be limited to the names of components or signals.

[0037] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 The cross-sectional view of the display panel shown.

[0038] Reference Figure 1 and Figure 2 The display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data into pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0039] Display panel 100 may be a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. Display panel 100 may include a pixel array for displaying an input image on the screen. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. Display panel 100 may further include power lines commonly connected to the pixels. The power lines may include a power line to which a pixel drive voltage ELVDD is applied, a power line to which a reference voltage VREF is applied, and a power line to which a low-potential power supply voltage ELVSS is applied. These power lines are typically connected to the pixels.

[0040] The pixel array comprises multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln comprises a row of pixels arranged along the row direction (X direction) in the pixel array of the display panel 100. Pixels arranged in a pixel line share a gate line 103. Subpixels arranged along the column direction (Y direction) share the same data line 102. A horizontal time period (1H) is the time obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0041] The display panel 100 can be implemented as a non-transparent display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device that displays images on a screen and allows the actual objects in the background to be seen.

[0042] Display panels can be manufactured as flexible display panels. Flexible display panels can be realized as OLED panels using a plastic substrate. The pixel array and light-emitting elements of a plastic OLED panel can be disposed on an organic thin film layer adhered to a backing plate.

[0043] Each pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel may further include a white sub-pixel. Each sub-pixel includes pixel circuitry. In the following text, the term "pixel" may be interpreted as meaning a sub-pixel. Each pixel circuit is connected to a data line, a gate line, and a power line.

[0044] Pixels can be set to solid color pixels or pentile pixels. Pentile pixels can use a preset pixel rendering algorithm to drive two sub-pixels of different colors as a single pixel 101 to achieve a higher resolution than solid color pixels. The pixel rendering algorithm can compensate for insufficient color representation in each pixel by using the color of the light emitted from adjacent pixels.

[0045] The touch sensor can be disposed on the screen of the display panel 100. The touch sensor can be implemented as an on-cell or add-on type touch sensor disposed on the screen of the display panel, or as an in-cell type touch sensor embedded in the pixel array AA.

[0046] When viewed in cross-section, the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10, such as Figure 2 As shown.

[0047] Circuit layer 12 may include pixel circuitry connected to wires (such as data lines, gate lines, and power lines), gate drivers (GIPs) connected to the gate lines, a demultiplexer array 112, and circuitry for automated probe inspection (omitted in the figures). The wires and circuit elements of circuit layer 12 may include multiple insulating layers, two or more metal layers separated by insulating layers, and an active layer containing semiconductor material.

[0048] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by multiple protective layers including organic and inorganic films.

[0049] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 can be a multi-insulating film structure with alternating layers of organic and inorganic films. The inorganic film blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. If the organic and inorganic films are stacked in multiple layers, the penetration of moisture or oxygen affecting light-emitting element layer 14 can be effectively blocked because the movement path of moisture or oxygen is longer than that of a single layer.

[0050] A touch sensor layer can be formed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include a metal wire pattern forming the capacitance of the touch sensor and the insulating film. The capacitance of the touch sensor may be formed between the metal wire patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate converts the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer 12 to improve visibility and contrast. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded, or as a circular polarizing plate. A cover glass may be attached to the polarizing plate.

[0051] The display panel 100 may further include a touch sensor layer stacked on the encapsulation layer 16 and the color filter layer. The color filter layer may include a red filter, a green filter, a blue filter, and a black matrix pattern. The color filter layer can absorb a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer, replacing the function of a polarizer and enhancing color purity. In this embodiment, a color filter layer 20 with higher light transmittance than a polarizer can be applied to the display panel to improve the light transmittance of the display panel PNL and to improve the thickness and flexibility of the display panel PNL. A cover glass may be attached to the color filter layer.

[0052] Power supply 140 uses a DC-DC converter to generate the direct current (DC) power required to drive the pixel array and display panel driver of display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 140 can generate constant voltages (or DC voltages) by adjusting the level of the DC input voltage applied from the host system (not shown), such as gamma reference voltage VGMA, gate on-state voltages VGH and VEH, gate off-state voltages VGL and VEL, pixel drive voltage ELVDD, low-level supply voltage ELVSS, reference voltage VREF, and anode reset voltage VAR. The gamma reference voltage VGMA can be supplied to data driver 110. Gate on-state voltages VGH and VEH, and gate off-state voltages VGL and VEL are supplied to gate driver 120. Constant voltages such as pixel drive voltage ELVDD, low-level supply voltage ELVSS, reference voltage VREF, and anode reset voltage VAR are collectively supplied to the pixels.

[0053] Under the control of the timing controller 130, the display panel driver writes the pixel data of the input image into the pixels of the display panel 100.

[0054] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data line 102.

[0055] The demultiplexer array 112 uses multiple demultiplexers (DEMUX) to sequentially supply data voltages output from each channel of the data driver 110 to the data line 102. The demultiplexers may include multiple switching elements disposed on the display panel 100. If the demultiplexers are disposed between the output terminals of the data driver 110 and the data line 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 can be omitted.

[0056] The display panel driver may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver and touch sensor driver can be integrated into a single driver integrated circuit (IC). In mobile or wearable devices, the timing controller 130, power supply 140, data driver 110, and touch sensor driver can be integrated into a single driver IC.

[0057] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. The low-speed drive mode can be configured to reduce the power consumption of the display device by analyzing the input image and reducing the power consumption of the display device when the input image does not change within a preset time. The low-speed drive mode can reduce the power consumption of the display panel driver and the display panel 100 by reducing the pixel refresh rate when the input static image has been present for a predetermined time or longer. The low-speed drive mode is not limited to only when the input static image has been present for a predetermined time or longer. For example, the display panel drive circuit can also operate in low-speed drive mode when the display device is operating in standby mode, or when no user command or input image has been input to the display panel drive circuit for a predetermined time or longer.

[0058] The data driver 110 generates a data voltage by converting pixel data of the input image, received as a digital signal from the timing controller 130 for each frame period, into a gamma-compensated voltage using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into gamma-compensated voltages for each grayscale level by a voltage divider circuit and supplied to the DAC. The data voltage is output from each channel of the data driver 110 through an output buffer.

[0059] The gate driver 120 can be implemented together with the wires of the TFT array and pixel array as a gate-in-panel (GIP) circuit directly formed in the circuit layer 12 of the display panel 100. The GIP circuit can be disposed on the bezel area BZ, which is a non-display area of ​​the display panel 100, or it can be distributed and disposed in the pixel array that reproduces the input image. Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signals to the gate line 103. The gate driver 120 can use a shift register to shift the gate signals to sequentially supply gate signals to the gate line 103. The gate signals may include scan signals and light emission control signals (hereinafter referred to as EM signals).

[0060] The shift register of the gate driver 120 outputs a pulse of the gate signal in response to the start pulse and shift clock from the timing controller 130, and shifts the pulse synchronously with the shift clock timing.

[0061] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized with the digital video data from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of 1H for one horizontal time period.

[0062] The host system can be any of a television (TV) system, tablet computer, laptop computer, navigation system, personal computer (PC), home theater system, mobile device, wearable device, and vehicle system. The host system can scale the video signal from the video source to match the resolution of the display panel 100 and transmit the video signal along with timing signals to the timing controller 130.

[0063] The timing controller 130 can multiply the input frame frequency by i (where i is a natural number) in normal drive mode to control the operating timing of the display panel driver at a frame frequency of input frame frequency × i Hz. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) format and 50 Hz in the phase-alternating line (PAL) format. In low-speed drive mode, the timing controller 130 can reduce the frame frequency of the display panel driver to a frequency between 1 Hz and 30 Hz to reduce the pixel refresh rate.

[0064] The timing controller 130 generates, based on the timing signals Vsync, Hsync, and DE received from the host system, a data timing control signal for controlling the operating timing of the data driver 110, a control signal for controlling the operating timing of the demultiplexer array 112, and a gate timing control signal for controlling the operating timing of the gate driver 120. The timing controller 130 controls the operating timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0065] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into gate on-state voltages VGH and VEH and gate off-state voltages VGL and VEL by a level shifter (not shown), and then supplied to the gate driver 120. The level shifter can convert the low-level voltage of the gate timing control signal into the gate on-state voltages VGH and VEH, and the high-level voltage of the gate timing control signal into the gate off-state voltages VGL and VEL. The gate timing signal may include a start pulse and a shift clock.

[0066] Due to process variations and component characteristic variations in the manufacturing process of the display panel 100, differences may exist in the electrical characteristics of the driving elements between pixels, and these differences may increase over time as the pixels drive. To compensate for these differences in the electrical characteristics of the driving elements between pixels, internal or external compensation techniques can be applied to the organic electroluminescent display. Internal compensation techniques use an internal compensation circuit implemented in each pixel circuit to sample the threshold voltage of the driving element for each sub-pixel and compensate for the gate-source voltage Vgs of the driving element by measuring the threshold voltage. External compensation techniques use an external compensation circuit to sense in real time the current or voltage of the driving element that changes according to its electrical characteristics. External compensation techniques compensate for the deviation (or variation) in the electrical characteristics of the driving element of each pixel in real time by modulating the pixel data (digital data) of the input image with the sensed deviation (or variation) in the electrical characteristics of the driving element for each pixel. The display panel driver can use external or internal compensation techniques to drive the pixels.

[0067] Figure 3 This is a diagram illustrating a pixel circuit according to an embodiment of the present disclosure.

[0068] Reference Figure 3 The pixel circuit according to an embodiment includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M1 to M6, and capacitors C1 and C2. The driving element DT and the plurality of switching elements M1 to M6 can be implemented as thin-film transistors. The first switching element M1, the third switching element M3, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 can be n-type oxide transistors. The second switching transistor can be a p-type low-temperature polycrystalline silicon (LTPS) transistor. In the pixel circuit, some of the switching elements can be made of oxide thin-film transistors with excellent insulating properties, while some of the switching elements can be made of polycrystalline silicon transistors to achieve fast response characteristics.

[0069] The driving element DT generates a current for driving the light-emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate DTG connected to the first node n1, a first electrode DTD connected to the pixel driving voltage, and a second electrode DTS connected to the second node n2.

[0070] The light-emitting element (EL) can be implemented as an OLED or an inorganic LED. An OLED includes an anode, a cathode, and an organic compound layer interposed between the electrodes. The anode of the EL is electrically connected to the fifth node n5, and the cathode is supplied with a cathode voltage ELVSS.

[0071] The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When a voltage is applied to the anode and cathode of the light-emitting element (EL), holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) migrate to the emissive layer (EML) to form excitons. In this case, visible light is emitted from the emissive layer (EML). OLEDs can be implemented as tandem OLED structures with multiple emissive layers stacked on top of each other. Tandem OLED structures can improve pixel brightness and lifetime.

[0072] The first switching element M1 has a first electrode connected to the data voltage line DL to which the applied data voltage VDATA is applied, and a second electrode connected to the third node n3. The gate of the first switching element M1 can be connected to the first scan line. The gate of the first switching element M1 can be turned on in response to the gate high voltages VGH and VEH of the first scan signal SC1, and turned off in response to the gate low voltages VGL and VEL. If the first switching element M1 is turned on, the data voltage VDATA can be applied to the third node n3.

[0073] The second switching element M2 has a first electrode connected to the third node n3 and a second electrode connected to the first node n1. The gate of the second switching element M2 can be connected to the second scan line. Since the second switching element M2 is a p-type transistor, it can be turned on in response to the gate low voltages VGL and VEL of the second scan signal SC2 and turned off in response to the gate high voltages VGH and VEH. If the second switching element M2 is turned on, the voltage of the second node n2 can be applied to the first node n1.

[0074] The third switching element M3 has a first electrode connected to the reference voltage line RL1 and a second electrode connected to the fourth node n4. The gate of the third switching element M3 can be connected to the second scan line. Since the third switching element M3 is an n-type thin-film transistor, it can be turned on in response to the gate high voltages VGH and VEH of the second scan signal SC2 and turned off in response to the gate low voltages VGL and VEL. If the third switching element M3 is turned on, the reference voltage VREF can be applied to the fourth node n4.

[0075] The fourth switching element M4 has a first electrode connected to the fourth node n4 and a second electrode connected to the first node n1. The gate of the fourth switching element M4 can be connected to the second scan line. Since the fourth switching element M4 is an n-type thin-film transistor, it can be turned on in response to the gate high voltage VGH and VEH of the second scan signal SC2 and turned off in response to the gate low voltage VGL and VEL. If the fourth switching element M4 is turned on, the voltage of the fourth node n4 can be applied to the first node n1.

[0076] The fifth switching element M5 has a first electrode connected to the second node n2 and a second electrode connected to the fifth node n5. The gate of the fifth switching element M5 can be connected to the EM line. Since the fifth switching element M5 is an n-type thin-film transistor, it can be turned on in response to the gate high voltage VGH and VEH of the EM signal EM and turned off in response to the gate low voltage VGL and VEL.

[0077] The sixth switching element M6 has a first electrode connected to the reset voltage line RL2 and a second electrode connected to the fifth node n5. The gate of the sixth switching element M6 can be connected to the third scan line. Since the sixth switching element M6 is an n-type thin-film transistor, it can be turned on in response to the gate high voltages VGH and VEH of the third scan signal SC3 and turned off in response to the gate low voltages VGL and VEL. If the sixth switching element M6 is turned on, the reset voltage can be applied to the anode of the light-emitting element EL.

[0078] The first capacitor C1 and the second capacitor C2 can keep the gate-source voltage Vgs of the driving element DT constant during one frame. The first capacitor C1 can store the data voltage VDATA, and the second capacitor C2 can store the threshold voltage Vth of the driving element DT.

[0079] The first terminal of the first capacitor C1 is connected to the third node n3, and the second terminal is connected to the fourth node n4. The first terminal of the first capacitor C1 can be connected to the second electrode of the first switching element M1 and the first electrode of the second switching element M2. The second terminal of the first capacitor C1 can be connected to the second electrode of the third switching element M3, the first electrode of the fourth switching element M4, and the first terminal of the second capacitor C2.

[0080] The first terminal of the second capacitor C2 is connected to the fourth node n4, and the second terminal is connected to the second node n2. The first terminal of the second capacitor C2 can be connected to the second electrode of the third switching element M3, the first electrode of the fourth switching element M4, and the second terminal of the first capacitor C1. The second terminal of the second capacitor C2 can be connected to the second node n2.

[0081] Figure 4 This is a waveform diagram of the operation of a pixel circuit according to an embodiment of the present disclosure. Figures 5A to 5D This is a circuit diagram showing the operation of a pixel circuit according to an embodiment of the present disclosure.

[0082] The refresh frame can include an initialization phase (INI), a sampling phase (SAM), a data writing phase (DW), and an emission phase (EMI). The initialization phase (INI) is the period used to initialize the capacitor and the gate of the driving element DT; the sampling phase (SAM) is the period used to sense the threshold voltage of the driving element DT; the data writing phase (DW) is the period used to store the data voltage VDATA; and the emission phase (EMI) is the period when the light-emitting element EL is turned on.

[0083] Reference Figure 5A During the initialization phase INI, the first scan signal SC1, the second scan signal SC2, the third scan signal SC3, and the EM signal EM can all be subjected to gate high voltages VGH and VEH. Therefore, the first switching element M1 and the third to sixth switching elements M3, M4, M5, and M6 can be turned on, while the second switching element M2 can be turned off.

[0084] Because the first switching element M1 is turned on, the data voltage VDATA can be charged into the third node n3. Because the third switching element M3 is turned on, the reference voltage VREF can be applied to the fourth node n4. Because the first capacitor C1 is connected between the second node n2 and the fourth node n4, the first capacitor C1 can be initialized with the voltage VDATA - VREF. The data voltage VDATA can be higher than the reference voltage VREF.

[0085] Since the fifth switching element M5 and the sixth switching element M6 are turned on during the initialization phase INI, a reset voltage can be applied to the second node n2 and the fifth node n5. Because the reset voltage is low enough, the light-emitting element EL does not emit light during the initialization phase INI.

[0086] Since the second capacitor C2 is connected between the second node n2 and the fourth node n4, the second capacitor C2 can be initialized with the voltage of VREF - VAR.

[0087] According to this embodiment, since the reference voltage VREF is applied to the fourth node n4 located between the first capacitor C1 and the second capacitor C2, the data voltage VDATA of the third node n3 can be independent of the first capacitor C1 and the second capacitor C2. Therefore, the data voltage VDATA can be entirely stored in the first capacitor C1. Thus, during the initialization phase INI, data can be stored in the first capacitor C1.

[0088] Reference Figure 5BDuring the sampling phase SAM, the first scan signal SC1 and the EM signal EM can be supplied with low gate voltages VGL and VEL, while the second scan signal SC2 and the third scan signal SC3 can maintain high gate voltages VGH and VEH. Therefore, the third switching element M3, the fourth switching element M4, and the sixth switching element M6 can remain on, while the first switching element M1, the second switching element M2, and the fifth switching element M5 can be turned off.

[0089] Since the fifth switching element M5 is turned off and the third switching element M3 and the fourth switching element M4 remain on, the voltage of the second node n2 can be increased. As the voltage of the second node n2 increases, when the gate-source voltage Vgs of the driving element DT reaches the threshold voltage Vth, the driving element DT can be turned off, and the threshold voltage Vth can be stored in the second capacitor C2.

[0090] Reference Figure 5C During the data writing phase (DW), the first scan signal SC1, the second scan signal SC2, and the EM signal EM can be supplied with low gate voltages VGL and VEL, and the third scan signal SC3 can be supplied with high gate voltages VGH and VEH. Therefore, the second switching element M2 can be turned on, and the sixth switching element M6 can remain on. The first switching element M1, the third switching element M3, the fourth switching element M4, and the fifth switching element M5 can be turned off.

[0091] Because the second switching element M2 is turned on, the data voltage stored in the second node n2 can be transmitted to the first node n1. According to this embodiment, the first capacitor C1 and the second capacitor C2, respectively connected to the third node n3 and the second node n2, can be separated by forming a fourth node n4 between the first capacitor C1 and the second capacitor C2 and applying a reference voltage VREF to the fourth node n4. Therefore, the data voltage VDATA input to the third node n3 can be input to the first node n1 without loss, because it is not distributed by the first capacitor C1 and the second capacitor C2. Thus, during data writing, the data voltage VDATA can be applied to the first node n1 without data transmission rate loss.

[0092] According to this embodiment, since the data voltage transmission rate is not determined by the capacitance ratio of the first capacitor C1 and the second capacitor C2, the data transmission rate can be increased to reduce the range of the data voltage. Therefore, the power consumption of the display device is reduced, enabling low-power operation.

[0093] Reference Figure 5DDuring the EMI emission phase, the first scan signal SC1 to the third scan signal SC3 can be supplied with low gate voltages VGL and VEL, and the EM signal EM can be supplied with high gate voltages VGH and VEH. Therefore, the second switching element M2 can remain on, and the fifth switching element M5 can be on. The first switching element M1, the third switching element M3, the fourth switching element M4, and the sixth switching element M6 can be off.

[0094] According to this embodiment, since the third switching element M3 is turned off, the first capacitor C1 and the second capacitor C2 can be connected in series in the EMI during the light-emitting phase. Therefore, the total capacitance of the first capacitor C1 and the second capacitor C2 can be reduced, and the brightness fluctuation characteristics can be improved. If the first capacitor C1 and the second capacitor C2 are connected in series, thereby reducing the total capacitance, the voltage charging rate of the second node n2 will become faster during the light-emitting phase. That is, as the potential difference DTS - ELVSS of the light-emitting element forms in a shorter time, the time required for light emission may become relatively faster. Therefore, when exhibiting a low grayscale within a short EM duty cycle signal segment, the light emission start time becomes faster and the light emission duration within the same time period becomes longer, which can improve the brightness fluctuation characteristics.

[0095] Furthermore, according to this embodiment, since the pixel driving voltage ELVDD is not connected to a capacitor, brightness reduction due to ripple can be prevented. Additionally, the light-emitting control switch element disposed between the pixel driving voltage ELVDD and the driving element DT can be omitted.

[0096] The current generated by the gate-source voltage Vgs of the driving element DT can be supplied to the light-emitting element EL, enabling the light-emitting element EL to emit light.

[0097] In this case, the current IOLED flowing through the light-emitting element EL, the gate-source voltage Vgs of the driving element DT, and the threshold voltage Vth of the driving element DT can satisfy the following relationship 1: [Relationship 1] IOLED = k(Vgs - |Vth|) 2 =k((DATA-REF+Vth)-|Vth|) 2 =k(DATA-REF) 2 Figure 6 This is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure.

[0098] Reference Figure 6The pixel circuit according to an embodiment includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements M1 to M6, and capacitors C1 and C2. According to this embodiment, the driving element DT and the first switching elements M1 to the sixth switching elements M6 may be n-type oxide transistors.

[0099] According to this embodiment, since the switching elements constituting the pixel circuit are all oxide transistors, it has the advantage of performing the excimer laser annealing process only in the non-display area NA. If polysilicon thin-film transistors are present in the display area AA, the entire panel should be laser annealed, which increases manufacturing costs and process time. Furthermore, since polysilicon thin-film transistors and oxide thin-film transistors are disposed together in the pixel, the process complexity increases.

[0100] The driving element DT generates a current for driving the light-emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate G connected to the first node n1, a first electrode S connected to the pixel driving voltage, and a second electrode D connected to the second node n2.

[0101] The first switching element M1 has a first electrode connected to the data voltage line DL to which the applied data voltage is applied, and a second electrode connected to the third node n3. The gate of the first switching element M1 can be connected to the first scan line. The gate of the first switching element M1 can be turned on in response to the gate high voltage VGH and VEH of the first scan signal SC1 and turned off in response to the gate low voltage VGL and VEL. If the first switching element M1 is turned on, the data voltage can be applied to the third node n3.

[0102] The second switching element M2 has a first electrode connected to the third node n3 and a second electrode connected to the first node n1. The gate of the second switching element M2 can be connected to the 2-1 scan line SC2-1. Since the second switching element M2 is a p-type thin-film transistor, it can be turned on in response to the gate low voltages VGL and VEL of the 2-1 scan signal SC2-1 and turned off in response to the gate high voltages VGH and VEH. If the second switching element M2 is turned on, the voltage of the second node n2 can be applied to the first node n1.

[0103] The second-first scan signal SC2-1 can have a phase opposite to that of the second scan signal SC2. The second scan signal SC2 and the second-first scan signal SC2-1 can be output by modulating their phases differently using a single gate driver. With this configuration, a separate gate driver is not required. However, this embodiment is not limited to this. For example, a separate gate driver for outputting the fourth scan signal SC4 can be provided.

[0104] The third switching element M3 has a first electrode connected to the reference voltage line RL1 and a second electrode connected to the fourth node n4. The gate of the third switching element M3 can be connected to the second scan line. Since the third switching element M3 is an n-type thin-film transistor, it can be turned on in response to the gate high voltages VGH and VEH of the second scan signal SC2 and turned off in response to the gate low voltages VGL and VEL. If the third switching element M3 is turned on, the reference voltage can be applied to the fourth node n4.

[0105] The fourth switching element M4 has a first electrode connected to the fourth node n4 and a second electrode connected to the first node n1. The gate of the fourth switching element M4 can be connected to the second scan line. Since the fourth switching element M4 is an n-type thin-film transistor, it can be turned on in response to the gate high voltage VGH and VEH of the second scan signal SC2 and turned off in response to the gate low voltage VGL and VEL. If the fourth switching element M4 is turned on, the voltage of the fourth node n4 can be applied to the first node n1.

[0106] The fifth switching element M5 has a first electrode connected to the second node n2 and a second electrode connected to the fifth node n5. The gate of the fifth switching element M5 can be connected to the EM line. Since the fifth switching element M5 is an n-type thin-film transistor, it can be turned on in response to the gate high voltage VGH and VEH of the EM signal EM and turned off in response to the gate low voltage VGL and VEL.

[0107] The sixth switching element M6 has a first electrode connected to the reset voltage line RL2 and a second electrode connected to the fifth node n5. The gate of the sixth switching element M6 can be connected to the third scan line. Since the sixth switching element M6 is an n-type thin-film transistor, it can be turned on in response to the gate high voltages VGH and VEH of the third scan signal SC3 and turned off in response to the gate low voltages VGL and VEL. If the sixth switching element M6 is turned on, the reset voltage can be applied to the anode of the light-emitting element EL.

[0108] The first capacitor C1 and the second capacitor C2 can keep the gate-source voltage Vgs of the driving element DT constant during one frame. The first capacitor C1 can store the data voltage VDATA, and the second capacitor C2 can store the threshold voltage Vth of the driving element DT.

[0109] The first terminal of the first capacitor C1 is connected to the third node n3, and the second terminal is connected to the fourth node n4. The first terminal of the first capacitor C1 can be connected to the second electrode of the first switching element M1 and the first electrode of the second switching element M2. The second terminal of the first capacitor C1 can be connected to the second electrode of the third switching element M3, the first electrode of the fourth switching element M4, and the first terminal of the second capacitor C2.

[0110] The first terminal of the second capacitor C2 is connected to the fourth node n4, and the second terminal is connected to the second node n2. The first terminal of the second capacitor C2 can be connected to the second electrode of the third switching element M3, the first electrode of the fourth switching element M4, and the second terminal of the first capacitor C1. The second terminal of the second capacitor C2 can be connected to the second node n2.

[0111] According to this embodiment, since the pixel circuit is entirely composed of oxide thin-film transistors, it has the advantage of omitting a separate ELA process. Therefore, the ELA process can be simplified by applying it only to the gate driver.

[0112] Figure 7 This is a block diagram of a gate driver according to an embodiment of the present disclosure. Figure 8 A light emission control signal driver according to an embodiment of the present disclosure is shown.

[0113] Reference Figure 7 Relative to the display area AA, the first gate driver 121 can be located on the left side, and the second gate driver 122 can be located on the right side.

[0114] The first gate driver 121 and the second gate driver 122 can respectively apply the EM signal EM and the first scan signals SC1 to the third scan signals SC3 to the pixel circuit of the display panel. If the second switching element M2 is an n-type oxide transistor, the first gate driver and the second gate driver can apply the fourth scan signal SC4 or the second-to-first scan signal to the second switching transistor.

[0115] Reference Figure 8 The shift register of gate driver 120 includes cascaded stages ST. Stages ST1 and ST2 receive a start pulse or carry signal CAR and receive clocks VST1, CLK1, and CLK2 via clock lines. The carry signal CAR is output from the previous stage and can be input to the VST node of the next stage.

[0116] Each stage sequentially outputs gate signals and carry signals simultaneously. The first stage ST1, which outputs the gate signal to the second switching element M2, may include a first output line GOUT1 for outputting the second scan signal SC2 to the third switching element M3 and the fourth switching element M4, and a second output line GOUT2 for outputting a second-to-first scan signal SC2-1 with a phase opposite to the second scan signal SC2. The second output line GOUT2 can branch from the first output line GOUT1. The phase input by the inverter IVT can be inverted. The inverter IVT can be a NOT gate. Therefore, since the second scan signal SC2 and the second-to-first scan signal SC2-1 can be output from a single stage, an additional stage is not required.

[0117] Figure 9 This is a waveform diagram showing the operation of the refresh frame and anode reset frame of the pixel circuit in Figure 5. Figure 10 The anode reset operation of a pixel circuit according to an embodiment of the present disclosure is illustrated. (See also...) Figure 11 The diagram shows the operation of the pixel circuit during threshold voltage sensing.

[0118] Reference Figure 9 The pixel circuit can execute refresh frame RF drive and anode reset frame AF drive.

[0119] During the refresh frame RF drive, the initialization phase INI and the sampling phase SAM can be performed, thereby writing the data voltage to the sub-pixel SP during the non-emission period when the emission signal EM is applied at the off level.

[0120] During the anode reset frame (AF) drive, the anode reset phase AR-SAM, the data write phase (DW), and the emission phase EMI can be performed. The data write phase (DW) and the emission phase EMI can be the same as those in the refresh frame (RF) drive. According to an embodiment, the anode reset phase AR-SAM can perform both anode reset and threshold voltage sampling.

[0121] Reference Figure 9 and Figure 10 During the first time period t1 of the anode reset phase AR-SAM, the first scan signal SC1 and the EM signal EM can be applied with gate low voltages VGL and VEL, and the second scan signal SC2 and the third scan signal SC3 can be applied with gate high voltages VGH and VEH.

[0122] Therefore, the first switching element M1 and the second switching element M2 can be turned off, and the third to sixth switching elements M3, M4, M5 and M6 can be turned on. Since the fifth switching element M5 and the sixth switching element M6 are turned on, the anode of the light-emitting element EL can be reset by the reset voltage VAR.

[0123] Reference Figure 11 After the first time period t1 has elapsed, the EM signal can be cut off to allow the second node n2 to float. The anode reset phase can be maintained at the fifth node n5 by the sixth switching element M6. Thereafter, the threshold voltage Vth can be sensed, and the data voltage VDATA stored in the second node n2 can be applied to the gate during the data write phase DW.

[0124] In low-grayscale driving, anode reset and sampling can operate at a predetermined ratio. According to this embodiment, the advantage of low-speed driving is that anode reset and sampling can be performed multiple times during the anode reset frame segment rather than during the refresh frame segment.

[0125] The transistor turns on in response to a gate on-voltage and turns off in response to a gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be the gate high voltage VGH and VEH, and the gate off-voltage can be the gate low voltage VGL and VEH.

[0126] This disclosure is not limited to the foregoing. In the description of the embodiments, this disclosure is not intended to be limited to the names of components or signals.

[0127] [List of reference numerals] 110: Data driver; 120: Gate driver 130: Timing controller; DT: Drive element M1: First switching element

Claims

1. A pixel circuit, comprising: A driving element, the driving element including a first electrode to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; A first switching element is turned on in response to a first scan signal to connect a data voltage line to a third node; A second switching element, which is turned on in response to a second scan signal, to connect the third node to the first node; A third switching element is activated in response to the second scan signal to connect the reference voltage line to the fourth node; A fourth switching element, which is turned on in response to the second scan signal, to connect the fourth node to the first node; A first capacitor is connected between the third node and the fourth node; as well as A second capacitor is connected between the fourth node and the second node.

2. The pixel circuit according to claim 1, further comprising: A light-emitting element, the light-emitting element comprising an anode connected to a fifth node and a cathode to which a low-potential power supply voltage is applied; A fifth switching element, which is turned on in response to an EM signal, to connect the second node and the fifth node; as well as A sixth switching element, which is turned on in response to a third scan signal, to connect the fifth node to the reset voltage line.

3. The pixel circuit of claim 2, wherein, The first switching element and the third to sixth switching elements are n-type oxide transistors, and The second switching element and the driving element are p-type polysilicon transistors.

4. The pixel circuit of claim 2, wherein, The first to the sixth switching elements are n-type oxide transistors.

5. The pixel circuit of claim 2, wherein, The data voltage supplied to the data voltage line is higher than the reference voltage supplied to the reference voltage line, and The reference voltage is higher than the reset voltage supplied to the reset voltage line.

6. The pixel circuit of claim 2, wherein, The pixel circuit is driven in the order of initialization phase, sensing phase, data writing phase, and light emission phase, and... During the initialization phase, the first switching element and the third to sixth switching elements are turned on, while the second switching element is turned off. During the sensing phase, the third, fourth, and sixth switching elements are turned on, while the first, second, and fifth switching elements are turned off. During the data writing phase, the second and sixth switching elements are turned on, while the first, third, fourth, and fifth switching elements are turned off. During the light-emitting phase, the second and fifth switching elements are turned on, while the first, third, fourth, and sixth switching elements are turned off.

7. The pixel circuit of claim 2, wherein, During the initialization phase, the voltages of the first scan signal, the second scan signal, the third scan signal, and the EM signal are all gate high voltages; During the sensing phase, the voltages of the first scan signal and the EM signal are gate low voltages, and the voltages of the second scan signal and the third scan signal are gate high voltages. During the data writing phase, the voltages of the first scan signal, the second scan signal, and the EM signal are all at a gate low voltage, while the voltage of the third scan signal is at a gate high voltage; and During the light emission phase, the voltages of the first scan signal to the third scan signal are gate low voltages, and the voltage of the EM signal is gate high voltage.

8. The pixel circuit of claim 6, wherein, During the initialization phase, the first switching element is turned on so that the data voltage is stored in the first capacitor.

9. The pixel circuit of claim 6, wherein, During the initialization phase, a reset voltage is applied to the fifth node to reset the anode of the light-emitting element.

10. The pixel circuit of claim 6, wherein, During the sensing phase, the threshold voltage of the driving element is stored in the second capacitor.

11. The pixel circuit of claim 6, wherein, During the data writing phase, the second switching element is turned on so that the data voltage stored in the third node is applied to the first node.

12. The pixel circuit of claim 6, wherein, During the light-emitting phase, the third switching element is turned off, so that the first capacitor and the second capacitor are connected in series.

13. A display device, comprising: The display panel includes multiple data lines, multiple gate lines intersecting the data lines, multiple power lines to which different constant voltages are applied, and multiple sub-pixels. A data driver configured to supply a data voltage for pixel data to the data line; as well as A gate driver configured to supply a scan signal and an EM signal to the gate line; The pixel circuits of the plurality of sub-pixels include: A driving element, the driving element including a first electrode to which a pixel driving voltage is applied, a gate connected to a first node, and a second electrode connected to a second node; A first switching element is turned on in response to a first scan signal to connect a data voltage line to a third node; A second switching element, which is turned on in response to a second scan signal, to connect the third node to the first node; A third switching element is activated in response to the second scan signal to connect the reference voltage line to the fourth node; A fourth switching element, which is turned on in response to the second scan signal, to connect the fourth node to the first node; A first capacitor, the first capacitor being connected between the third node and the fourth node; and A second capacitor is connected between the fourth node and the second node.

14. The display device according to claim 13, further comprising: A light-emitting element, the light-emitting element comprising an anode connected to a fifth node and a cathode to which a low-potential power supply voltage is applied; A fifth switching element, which is turned on in response to an EM signal, to connect the second node and the fifth node; as well as A sixth switching element, which is turned on in response to a third scan signal, to connect the fifth node to the reset voltage line.

15. The display device of claim 14, wherein, The pixel circuit is driven in the order of initialization phase, sensing phase, data writing phase, and light emission phase. During the initialization phase, the first switching element and the third to sixth switching elements are turned on, and the second switching element is turned off; During the sensing phase, the third, fourth, and sixth switching elements are turned on, while the first, second, and fifth switching elements are turned off. During the data writing phase, the second and sixth switching elements are turned on, while the first, third, fourth, and fifth switching elements are turned off. and During the light-emitting phase, the second and fifth switching elements are turned on, while the first, third, fourth, and sixth switching elements are turned off.

16. The display device of claim 15, wherein, During the initialization phase, the voltages of the first scan signal, the second scan signal, the third scan signal, and the EM signal are all gate high voltages; During the sensing phase, the voltages of the first scan signal and the EM signal are gate low voltages, and the voltages of the second scan signal and the third scan signal are gate high voltages. During the data writing phase, the voltages of the first scan signal, the second scan signal, and the EM signal are all at a gate low voltage, while the voltage of the third scan signal is at a gate high voltage; and During the light emission phase, the voltages of the first scan signal to the third scan signal are gate low voltages, and the voltage of the EM signal is gate high voltage.

Images