A method for fabricating a Y-shaped gate to reduce gate resistance and its structure

Abstract

This invention relates to the field of gallium arsenide-based high-frequency device manufacturing technology, specifically a method and structure for fabricating a Y-shaped gate to reduce gate resistance. The method involves forming a first layer of negative photoresist with an inverted trapezoidal cross-section on a GaAs wafer, depositing a 30nm~80nm sacrificial passivation layer, coating a second layer of negative photoresist, and photolithographically etching out a window. A suspended region is formed through dry etching and O2 plasma etching, followed by metal evaporation and non-destructive lift-off to obtain the Y-shaped gate. This invention fundamentally eliminates the lift-off failure problem caused by the "top-heavy" effect, overcomes the process bottleneck of gate metal thickness, and achieves a significant increase in gold layer thickness, effectively reducing gate resistance. Furthermore, this invention provides a Y-shaped gate structure fabricated by this method, which has high bottom support strength and exhibits no process stress damage in its Schottky contact with the GaAs substrate, significantly improving the high-frequency performance and reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and specifically to a method for fabricating a Y-shaped gate and its structure to reduce gate resistance. Background Technology

[0002] In the fabrication of GaAs-based high-frequency devices, the Y-gate (also known as the T-gate) is the core structure for achieving high device performance. Its design focuses on maintaining a submicron or even nanometer-scale gate length (Lg) to ensure high transconductance and cutoff frequency, while simultaneously increasing the cross-sectional area at the top of the gate to reduce the gate resistance (Rg), thereby increasing the device's maximum oscillation frequency (Fmax). The transistor's cutoff frequency (Ft), a key high-frequency performance indicator, approximately satisfies the formula Ft≈1 / (2π×Rg×Cgs) (where Cgs is the gate-source capacitance). Therefore, under the premise of constant gate-source capacitance, reducing the gate resistance is a direct and effective means to increase the device's cutoff frequency.

[0003] Currently, the industry commonly uses a double-layer photoresist lift-off method to fabricate Y-shaped gates. A typical process flow is as follows: First, a first layer of positive photoresist with a thickness of 2000 Å to 6000 Å is coated on the substrate. The gate "feet" pattern is defined using high-precision photolithography methods such as electron beam lithography. The width of this pattern is the final gate length Lg. Then, a second layer of negative photoresist with a thickness of 9000 Å to 12000 Å is coated. A window wider than the first layer is then created using photolithography, forming an inverted trapezoidal profile that provides the basis for subsequent metal lift-off processes. Next, under a vacuum degree better than 5 × 10⁻⁶, the process is carried out... -6 Inside the Torr cavity, a titanium (Ti) / platinum (Pt) / gold (Au) composite metal layer is deposited sequentially using electron beam evaporation technology, with typical thicknesses of 400 Å / 500 Å / 5100 Å. Finally, the photoresist and the metal above it are removed by soaking in organic solvents such as acetone and by ultrasonic or megaphonic treatment to form a Y-shaped gate metal.

[0004] However, existing double-layer photoresist stripping methods have many technical drawbacks, which severely limit the further improvement of the performance of GaAs-based high-frequency devices: Performance improvement faces bottlenecks and is prone to peeling failure: The most direct way to reduce gate resistance is to increase the thickness of the gate metal, especially the low resistivity gold layer. However, when the gate length is fixed, simply thickening the top metal will cause the gate to form a "top-heavy" microstructure. An excessively thick continuous metal film will generate large internal stress and be too strongly bonded to the narrow gate root "feet". When dissolving the underlying photoresist, the metal "head" is very likely to pull the gate root "feet" off the substrate or cause the metal strip to break, resulting in complete device failure. This is essentially a structural instability. The device has potential reliability issues: the "top-heavy" effect caused by the thickened metal layer will generate residual stress, which will weaken the mechanical adhesion of the Schottky contact between the gate "feet" metal and the semiconductor substrate. When the device is in long-term operation or undergoes temperature cycling, it is prone to reliability deterioration. Limited reduction in gate resistance: Due to the limitation of the stripping process, the metal thickness cannot be significantly increased, and the cross-sectional area of ​​the gate metal is difficult to increase effectively. This leads to a bottleneck in the reduction of gate resistance, which cannot meet the performance requirements of high-frequency devices for lower gate resistance.

[0005] To address the shortcomings of the existing technologies, there is an urgent need to develop a new Y-shaped gate fabrication method to eliminate the "top-heavy" effect from a structural perspective, achieve reliable forming of thick metal gates, and improve the process consistency and long-term operational reliability of the devices. Summary of the Invention

[0006] To address the limitations of existing double-layer photoresist stripping methods in improving performance, such as susceptibility to stripping failure, device reliability issues, and limited reduction in gate resistance, this invention provides a Y-shaped gate fabrication method and structure to reduce gate resistance. This method fundamentally eliminates the stripping failure problem caused by the "top-heavy" effect, overcomes the process bottleneck of gate metal thickness, and achieves a significant increase in gold layer thickness, effectively reducing gate resistance. Furthermore, this invention provides a Y-shaped gate structure fabricated using this method, which exhibits high bottom support strength and exhibits no process stress damage in its Schottky contact with the GaAs substrate, resulting in significantly improved high-frequency performance and reliability of the device.

[0007] The technical solution of the present invention is as follows: A method for fabricating a Y-shaped gate to reduce gate resistance includes the following steps: Step 1: On the GaAs wafer that has completed the front-end process, a first layer of negative photoresist is coated. By controlling the spin coating speed and photoresist viscosity, the dry film thickness is controlled within the range of 2000Å~6000Å. After photolithography exposure and development, the first layer of negative photoresist in the exposed area forms an inverted trapezoidal cross-section with obvious tilt angles on the sidewalls and wider at the top and narrower at the bottom after development. The width of the bottom of the inverted trapezoidal cross-section pattern is the target gate linewidth of the device. Step 2: Deposit a sacrificial passivation layer on the photoresist pattern formed in Step 1, wherein the thickness of the sacrificial passivation layer is 30nm~80nm; Step 3: A second layer of negative photoresist with a dry film thickness of 11000Å~14000Å is coated on the GaAs wafer with the deposited sacrificial passivation layer. A window is made by photolithography. The linewidth of the window is the same as the width of the top brim of the target Y-shaped gate, and the edge of the window is aligned with the position of the inverted trapezoidal bevel formed by the first layer of negative photoresist. Then, dry etching of the sacrificial passivation layer and etch-back of the first layer of negative photoresist are performed in sequence. Dry etching is performed until the first layer of negative photoresist is completely exposed. The etch-back is performed using O2 plasma anisotropic etch-back to precisely remove the first layer of negative photoresist with a thickness of 2000Å~6000Å, forming a suspended area below the sidewall of the sacrificial passivation layer. After the etch-back, the sidewall of the photoresist remains steep. Step 4: Perform metal evaporation in an electron beam evaporation system with a base vacuum level better than 5×10⁻⁶. -7 Torr, a titanium adhesion layer, a platinum barrier layer, and a gold conductive layer are deposited sequentially; after the evaporation is completed, the sample is immersed in a heated photoresist stripping solution for metal stripping to obtain the Y-shaped gate of the GaAs-based high-frequency device.

[0008] Furthermore, in step 1, the dry film thickness of the first layer of negative photoresist is preferably 4000 Å, and the target gate linewidth at the bottom of the pattern after photolithography and development can reach below 250 nm.

[0009] Furthermore, in step 2, the sacrificial passivation layer is deposited using plasma-enhanced atomic layer deposition (PEALD) technology. The sacrificial passivation layer achieves three-dimensional coverage of the inverted trapezoidal morphology of the underlying photoresist through atomic layer deposition. The deposited sacrificial passivation layer is an aluminum oxide thin film, and the temperature of the PEALD reaction chamber is controlled between 80°C and 120°C.

[0010] Furthermore, the thickness of the aluminum oxide film is 50 nm.

[0011] Furthermore, in step 3, if the sacrificial passivation layer is aluminum oxide, the dry etching method adopts reactive ion etching (RIE) or inductively coupled plasma (ICP) etching, the etching gas is a mixture of SF6 and O2, the flow ratio of SF6 to O2 is 30:1 to 50:1, the etching RF power is 100W to 300W, and the cavity pressure is 10mTorr to 50mTorr.

[0012] Furthermore, in step 2, the sacrificial passivation layer is deposited using low-temperature plasma-enhanced chemical vapor deposition (PECVD). The deposited sacrificial passivation layer is a silicon dioxide thin film, and the deposition temperature is ≤150°C. Etching is performed using a fluorocarbon gas system, wherein the fluorocarbon gas is a mixture of CF4 and CHF3, and the flow rate ratio is controlled at CF4:CHF3 = 1:1 to 3:1. If RIE etching is used, the RF power is 100W to 300W and the cavity pressure is 10mTorr to 100mTorr; If ICP etching is used, the power of ICP etching is 300W to 800W, and the bias power is 50W to 200W.

[0013] Furthermore, in step 3, the process conditions for the O2 plasma anisotropic etching back are as follows: pure O2 gas is used, the gas flow rate is 50 sccm to 100 sccm, the radio frequency power is 200 W to 400 W, the cavity pressure is 20 mTorr to 100 mTorr, and the etching back endpoint is controlled by time. After dry etching is completed, the cavity is not replaced during the re-etching process; only the gas is switched according to process requirements.

[0014] Furthermore, the thickness of the titanium adhesion layer is 350 Å to 450 Å, the thickness of the platinum barrier layer is 450 Å to 550 Å, and the thickness of the gold conductive layer is 6000 Å to 9000 Å.

[0015] Furthermore, in step 4, the photoresist stripping solution is N-methylpyrrolidone, the temperature of the stripping solution is 60-80°C, and the immersion time of the sample is 60-90 minutes.

[0016] A Y-shaped gate structure for reducing gate resistance is prepared by the above method, comprising a GaAs substrate and a Y-shaped gate metal disposed on the GaAs substrate, wherein the Y-shaped gate metal has a gate bottom in contact with the GaAs substrate and a top cap connected to the gate bottom. The support linewidth at the bottom of the gate is Lg+2×d, where Lg is the target gate linewidth and d is the thickness of the low-temperature conformal passivation layer. The Y-shaped gate metal forms a Schottky contact with the GaAs substrate without process stress damage. The Y-shaped gate metal is a titanium, platinum, and gold composite metal layer, with a titanium layer thickness of 350 Å to 450 Å, a platinum layer thickness of 450 Å to 550 Å, and a gold layer thickness of 6000 Å to 9000 Å.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention fundamentally eliminates the "top-heavy" effect, breaks through the bottleneck of metal thickness processing, and significantly reduces gate resistance: By using an O2 plasma etching process, a suspended region is formed below the sidewall of the sacrificial passivation layer. This physically weakens the mechanical connection strength and contact area between the metal "head" and the photoresist of the gate "feet," greatly releasing peel stress. This allows the thickness of the gold conductive layer to be safely increased to 6000Å~9000Å. According to the resistance formula, the gate resistance can be reduced by more than 20%-40%. Based on the relationship Ft≈1 / (2π×Rg×Cgs), the cutoff frequency (Ft) and the maximum oscillation frequency (Fmax) of the device are effectively improved. By using a hard passivation layer as a support template, the process window is improved and the pattern fidelity is enhanced: This invention uses a sacrificial passivation layer deposited by PEALD or low-temperature PECVD as a hard film, which has excellent mechanical strength and conformability. During the metal evaporation process, it can serve as an undeformable hard sidewall template to resist the stress generated by the deposition of thick metal films and prevent photoresist pattern deformation or collapse. At the same time, the PEALD process can accurately replicate the inverted trapezoidal morphology of the initial photoresist at the atomic level. The resulting passivation layer sidewalls are smooth and steep. The metal pattern defined by this hard mask is minimally affected by subsequent process fluctuations in key dimensions such as the top brim width and gate root position, which significantly improves the consistency and repeatability of gate morphology between different batches and different wafers. Low-temperature, non-destructive process integration ensures the integrity of the underlying materials and improves device reliability: The sacrificial passivation layer deposition step of this invention is completed at a low temperature of 80°C~120°C (PEALD) or ≤150°C (PECVD), avoiding thermal damage to organic photoresist materials caused by high temperatures, ensuring that the photoresist can be completely and cleanly removed without residue during the final stripping; the photoresist etch-back adopts a pure O2 plasma dry process, which has extremely high selectivity for GaAs substrate and sidewall sacrificial passivation layer, can accurately remove target photoresist without damaging the semiconductor surface and passivation layer morphology, and provides a clean and non-destructive interface; at the same time, the low-stress stripping process protects the Schottky contact interface between the gate metal and the GaAs substrate from mechanical pulling damage, reduces interface defects caused by process stress, and improves the long-term electrical stability of the gate and the reliability of the device from the source; The process is highly modular, with good scalability and industrial application prospects: the sacrificial passivation layer of this invention is not limited to Al2O3 and PEALD processes, but can also be made using SiO2 and low-temperature PECVD processes. The depth of photoresist back etching can be flexibly adjusted according to the initial resist thickness and the aspect ratio of the target "feet". Moreover, the preparation method is based on standard photolithography, dry etching and electron beam evaporation equipment, without the need to introduce special equipment. The process module is easy to integrate into the existing GaAspHEMT / HEMT manufacturing process and adapts to the production needs of existing production lines. The Y-shaped gate structure exhibits high support strength and excellent electrical performance: The Y-shaped gate structure prepared in this invention has a support linewidth of Lg+2×d at the bottom of the gate, which significantly improves the support strength at the bottom of the gate compared to traditional structures, enhances the resistance to rinsing, and forms a Schottky contact between the gate metal and the GaAs substrate without process stress damage, effectively avoiding stress-induced contact failure; at the same time, the gold layer thickness of the composite metal layer is significantly increased, increasing the cross-sectional area of ​​the gate metal, effectively reducing the gate resistance, and ensuring the high-frequency performance of the device. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the photoresist pattern after the first layer of negative photoresist has been coated and subjected to photolithography exposure and development in an embodiment of the present invention. Figure 2 This is a schematic diagram of the deposition layer after the sacrificial passivation layer in an embodiment of the present invention; Figure 3 This is a schematic diagram of the pattern after the second layer of negative photoresist is coated in an embodiment of the present invention; Figure 4 This is a schematic diagram of the pattern after dry etching in an embodiment of the present invention; Figure 5 This is a schematic diagram of the pattern after the first layer of negative adhesive has been etched back in an embodiment of the present invention; Figure 6 This is a schematic diagram of the metal vapor deposition pattern in an embodiment of the present invention; Figure 7 This is a final graphical representation of an embodiment of the present invention; In the figure: 1-GaAs wafer, 2-first layer of negative photoresist, 3-sacrificial passivation layer, 4-second layer of negative photoresist, 5-window, 6-dangling area, 7-Y-shaped gate, 71-bottom of gate, 72-top cap. Detailed Implementation

[0019] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0020] See Figure 1-7 A method for fabricating a Y-shaped gate to reduce gate resistance includes the following steps: Step 1: On the GaAs wafer 1 that has completed the front-end process, a first layer of negative photoresist 2 is coated. By controlling the spin coating speed and photoresist viscosity, the dry film thickness is controlled within the range of 2000Å~6000Å. After photolithography exposure and development, the first layer of negative photoresist 2 in the exposed area forms an inverted trapezoidal cross-section with obvious tilt angles on the sidewalls and wider at the top and narrower at the bottom after development. The width of the bottom of the inverted trapezoidal cross-section pattern is the target gate linewidth of the device. Step 2: Deposit a sacrificial passivation layer 3 on the photoresist pattern formed in step 1, wherein the thickness of the sacrificial passivation layer 3 is 30nm~80nm; Step 3: A second layer of negative photoresist 4 is coated on the GaAs wafer 1 with the sacrificial passivation layer 3 deposited. The dry film thickness is 11000Å~14000Å. A window 5 is made by photolithography. The linewidth of the window 5 is the same as the width of the top lip 72 of the target Y-shaped gate 7, and the edge of the window 5 is aligned with the position of the inverted trapezoidal bevel formed by the first layer of negative photoresist 2. Then, the dry etching of the sacrificial passivation layer 3 and the etch back of the first layer of negative photoresist 2 are performed in sequence. The dry etching is performed until the first layer of negative photoresist 2 is completely exposed. The etch back is performed using O2 plasma anisotropic etch back, which precisely removes the first layer of negative photoresist 2 with a thickness of 2000Å~6000Å, forming a suspended region 6 below the sidewall of the sacrificial passivation layer 3. After the etch back, the photoresist sidewall remains steep. Step 4: Perform metal evaporation in an electron beam evaporation system with a base vacuum level better than 5×10⁻⁶. -7 Torr, a titanium adhesion layer, a platinum barrier layer, and a gold conductive layer are deposited sequentially; after the evaporation is completed, the sample is immersed in a heated photoresist stripping solution for metal stripping to obtain the GaAs-based high-frequency device Y-gate 7.

[0021] In step 1 of this invention, the dry film thickness of the first layer of negative photoresist 2 is preferably 4000 Å, and the target gate linewidth at the bottom of the pattern after photolithography and development can reach less than 100 nm, which meets the performance requirements of high-frequency devices for narrow gate length.

[0022] In step 2 of this invention, the sacrificial passivation layer 3 is deposited using plasma-enhanced atomic layer deposition (PEALD) technology. The sacrificial passivation layer 3 achieves three-dimensional encapsulation of the inverted trapezoidal morphology of the underlying photoresist through atomic layer deposition. The deposited sacrificial passivation layer 3 is an aluminum oxide (Al2O3) thin film. The temperature of the PEALD reaction chamber is controlled between 80°C and 120°C. The thickness of the aluminum oxide thin film is preferably 50 nm, and the PEALD reaction chamber temperature is most preferably 80°C. Low-temperature deposition can avoid thermal damage, carbonization, or cross-linking of the organic photoresist material.

[0023] As an alternative technical solution of the present invention, in step 2, the sacrificial passivation layer 3 can be deposited using low-temperature plasma-enhanced chemical vapor deposition (PECVD) technology. The deposited sacrificial passivation layer 3 is a silicon dioxide (SiO2) thin film, the deposition temperature is ≤150°C, and etching is performed using a fluorocarbon compound gas system. The fluorocarbon compound gas is a mixture of CF4 and CHF3, and the flow rate ratio is controlled at CF4:CHF3 = 1:1 to 3:1. If RIE (reactive ion etching) is used, the radio frequency power is 100W to 300W and the chamber pressure is 10mTorr to 100mTorr; If ICP etching (inductively coupled plasma) is used, the power of ICP etching is 300W to 800W, and the bias power is 50W to 200W.

[0024] This process can also meet the requirements for low-temperature and high-conformity deposition.

[0025] In step 3 of this invention, if the sacrificial passivation layer 3 is aluminum oxide, the dry etching adopts reactive ion etching (RIE) or inductively coupled plasma (ICP) etching, the etching gas is a mixture of SF6 and O2, the flow ratio of SF6 to O2 is 30:1 to 50:1, the etching RF power is 100W to 300W, and the cavity pressure is 10mTorr to 50mTorr. This process condition can achieve selective etching of aluminum oxide and avoid damage to the underlying photoresist.

[0026] In step 3 of this invention, the process conditions for the O2 plasma anisotropic etching back are as follows: pure O2 gas is used, the gas flow rate is 50 sccm to 100 sccm, the radio frequency power is 200 W to 400 W, the cavity pressure is 20 mTorr to 100 mTorr, and the etching end point is controlled by time; and after the dry etching is completed, the cavity is not changed during the etching back process, only the gas is switched according to the process requirements, which simplifies the process steps and improves the process efficiency.

[0027] In step 4 of this invention, the thickness of the titanium adhesion layer is 350 Å to 450 Å, the thickness of the platinum barrier layer is 450 Å to 550 Å, and the thickness of the gold conductive layer is 6000 Å to 9000 Å. The thickness of the gold layer is significantly increased, effectively increasing the cross-sectional area of ​​the gate metal.

[0028] In step 4 of this invention, the photoresist stripping solution is N-methylpyrrolidone, the temperature of the stripping solution is 60-80°C, and the immersion time of the sample is 60-90 minutes. These stripping conditions can achieve non-destructive stripping and prevent the gate metal from being pulled off the substrate.

[0029] On the other hand, the present invention provides a Y-shaped gate structure for reducing gate resistance, which is prepared by any of the above-described preparation methods, including a GaAs substrate and a Y-shaped gate metal disposed on the GaAs substrate. The Y-shaped gate metal has a gate bottom 71 in contact with the GaAs substrate and a top cap 72 connected to the gate bottom 71. The support linewidth of the gate bottom 71 is Lg + 2 × d, where Lg is the target gate linewidth and d is the thickness of the low-temperature conformal passivation layer. The Y-shaped gate metal forms a Schottky contact with the GaAs substrate without process stress damage. The Y-shaped gate 7 electrode metal is a titanium, platinum, and gold composite metal layer, with a titanium layer thickness of 350 Å to 450 Å, a platinum layer thickness of 450 Å to 550 Å, and a gold layer thickness of 6000 Å to 9000 Å.

[0030] The following are several embodiments to illustrate the present invention: Example 1:

[0031] This embodiment provides a method for fabricating a Y-shaped gate to reduce gate resistance, the specific steps of which are as follows: See Figure 1 Step 1: Take the GaAs wafer 1 that has completed the front-end ion implantation, epitaxial growth and other processes, and coat the surface of it with the first layer of negative photoresist 2. By adjusting the spin coating speed to 3000 r / min and matching the photoresist viscosity, the dry film thickness of the first layer of negative photoresist 2 is precisely controlled to 4000 Å. Electron beam lithography is used for exposure, and the development time is optimized to 60s. After development, the first layer of negative photoresist 2 in the exposed area forms an inverted trapezoidal cross-section with obvious tilt angle on the sidewalls and wider at the top and narrower at the bottom. The width of the bottom of the inverted trapezoidal cross-section pattern is the target gate linewidth Lg of the device. In this embodiment, Lg is 250nm, which can realize the fabrication of ultra-narrow gate lengths below 100nm. See Figure 2 Step 2: Using plasma-enhanced atomic layer deposition (PEALD) technology, a sacrificial passivation layer 3 is deposited on the photoresist pattern formed in step 1. The temperature of the PEALD reaction chamber is controlled at 80°C. Using trimethylaluminum and plasma oxygen as precursors, an aluminum oxide film is grown by atomic layer deposition to achieve three-dimensional coating of the inverted trapezoidal morphology of the underlying photoresist. The thickness of the aluminum oxide film is controlled at 50nm. See Figure 3Step 3: A second layer of negative photoresist 4 is coated on the GaAs wafer 1 with deposited aluminum oxide thin film. The dry film thickness is 12000 Å by adjusting the spin coating speed. A window 5 is created using photolithography. The linewidth of the window 5 is the same as the width of the top visor 7210 of the target Y-shaped gate 7, and the edge of the window 5 is precisely aligned with the inverted trapezoidal bevel formed by the first layer of negative photoresist 2. Then, using the second layer of negative photoresist 4 as a mask, dry etching of the aluminum oxide thin film is performed using inductively coupled plasma (ICP). The etching gas is a mixture of SF6 and O2, with an SF6 to O2 flow ratio of 40:1. The RF power of the etching is 200W, and the cavity pressure is 30mTorr. Etching continues until the first layer of negative photoresist 2 is completely exposed. Figure 4 As shown; After dry etching is completed, without changing the etching chamber, only pure O2 gas is switched to perform anisotropic etching back of the first layer of negative photoresist 2. The O2 gas flow rate is 80 sccm, the RF power is 300W, and the chamber pressure is 60 mTorr. The etching back endpoint is controlled by time, precisely removing the 4000 Å thick first layer of negative photoresist 2, forming a suspended region 6 below the sidewall of the aluminum oxide film. After etching back, the photoresist sidewall remains steep, as shown below. Figure 5 As shown.

[0032] Step 4: Place the GaAs wafer 1 from Step 3 into the electron beam evaporation system, and pump the system's base vacuum to 8 × 10⁻⁶. -8 Torr (better than 5×10) -7 Torr), sequentially depositing a titanium adhesion layer, a platinum barrier layer, and a gold conductive layer, wherein the titanium adhesion layer has a thickness of 400 Å, the platinum barrier layer has a thickness of 500 Å, and the gold conductive layer has a thickness of 8000 Å, such as Figure 6 As shown.

[0033] After metal deposition, the sample was immersed in N-methylpyrrolidone stripping solution at 70°C for 75 minutes to complete metal stripping, yielding the Y-shaped gate 7 of the GaAs-based pHEMT device, as shown. Figure 7 As shown. Example 2:

[0034] This embodiment provides a method for fabricating a Y-shaped gate to reduce gate resistance, which differs from Embodiment 1 in that: In step 2, a sacrificial passivation layer 3 is deposited using low-temperature plasma-enhanced chemical vapor deposition (PECVD) technology at a deposition temperature of 150°C. The deposited sacrificial passivation layer 3 is a silicon dioxide thin film with a thickness of 30 nm. In step 3, the dry etching uses reactive ion etching (RIE), with a mixed gas of CF4 and CHF3, the flow rate ratio of which is controlled at CF4:CHF3 = 1:1, the RF power is 200W, the cavity pressure is 20mTorr, and the first layer of negative photoresist 2 is precisely removed. In step 4, the thickness of the titanium adhesion layer is 350 Å, the thickness of the platinum barrier layer is 450 Å, and the thickness of the gold conductive layer is 6000 Å; the temperature of the stripping solution is 60°C, and the immersion time is 90 minutes.

[0035] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a Y-shaped gate to reduce gate resistance, characterized in that, Includes the following steps: Step 1: On the GaAs wafer that has completed the front-end process, a first layer of negative photoresist is coated. By controlling the spin coating speed and photoresist viscosity, the dry film thickness is controlled within the range of 2000Å~6000Å. After photolithography exposure and development, the first layer of negative photoresist in the exposed area forms an inverted trapezoidal cross-section with obvious tilt angles on the sidewalls and wider at the top and narrower at the bottom after development. The width of the bottom of the inverted trapezoidal cross-section pattern is the target gate linewidth of the device. Step 2: Deposit a sacrificial passivation layer on the photoresist pattern formed in Step 1, wherein the thickness of the sacrificial passivation layer is 30nm~80nm; Step 3: A second layer of negative photoresist with a dry film thickness of 11000Å~14000Å is coated on the GaAs wafer with the deposited sacrificial passivation layer. A window is made by photolithography. The linewidth of the window is the same as the width of the top brim of the target Y-shaped gate, and the edge of the window is aligned with the position of the inverted trapezoidal bevel formed by the first layer of negative photoresist. Then, dry etching of the sacrificial passivation layer and etch-back of the first layer of negative photoresist are performed in sequence. Dry etching is performed until the first layer of negative photoresist is completely exposed. The etch-back is performed using O2 plasma anisotropic etch-back to precisely remove the first layer of negative photoresist with a thickness of 2000Å~6000Å, forming a suspended area below the sidewall of the sacrificial passivation layer. After the etch-back, the sidewall of the photoresist remains steep. Step 4: Metal evaporation in an electron beam evaporation system with a base pressure better than 5 x 10 -7 Torr, depositing a titanium adhesion layer, a platinum barrier layer, and a gold conductive layer in sequence; After the evaporation is completed, the sample is immersed in a heated photoresist stripping solution to remove the metal, thus obtaining the Y-shaped gate of the GaAs-based high-frequency device.

2. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 1, characterized in that, In step 1, the dry film thickness of the first layer of negative photoresist is preferably 4000 Å, and the target gate linewidth at the bottom of the pattern after photolithography and development can reach below 250 nm.

3. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 1, characterized in that, In step 2, the sacrificial passivation layer is deposited using plasma-enhanced atomic layer deposition (PEALD) technology. The sacrificial passivation layer achieves three-dimensional coverage of the inverted trapezoidal morphology of the underlying photoresist through atomic layer deposition. The deposited sacrificial passivation layer is an aluminum oxide film, and the temperature of the PEALD reaction chamber is controlled between 80°C and 120°C.

4. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 3, characterized in that, The thickness of the aluminum oxide film is 50 nm.

5. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 1, characterized in that, In step 3, if the sacrificial passivation layer is aluminum oxide, the dry etching method uses reactive ion etching (RIE) or inductively coupled plasma (ICP) etching. The etching gas is a mixture of SF6 and O2, with a flow ratio of SF6 to O2 of 30:1 to 50:

1. The etching RF power is 100W to 300W, and the cavity pressure is 10mTorr to 50mTorr.

6. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 1, characterized in that, In step 2, the sacrificial passivation layer is deposited using low-temperature plasma-enhanced chemical vapor deposition (PECVD). The deposited sacrificial passivation layer is a silicon dioxide thin film, and the deposition temperature is ≤150°C. Etching is performed using a fluorocarbon gas system, wherein the fluorocarbon gas is a mixture of CF4 and CHF3, and the flow rate ratio is controlled between CF4:CHF3 = 1:1 and 3:

1. If RIE etching is used, the RF power is 100W to 300W and the cavity pressure is 10mTorr to 100mTorr; If ICP etching is used, the power of ICP etching is 300W to 800W, and the bias power is 50W to 200W.

7. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 1, characterized in that, In step 3, the process conditions for the O2 plasma anisotropic etching back are as follows: pure O2 gas is used, the gas flow rate is 50 sccm to 100 sccm, the radio frequency power is 200 W to 400 W, the cavity pressure is 20 mTorr to 100 mTorr, and the etching end point is controlled by time. After dry etching is completed, the cavity is not replaced during the re-etching process; only the gas is switched according to process requirements.

8. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 1, characterized in that, The thickness of the titanium adhesion layer is 350 Å to 450 Å, the thickness of the platinum barrier layer is 450 Å to 550 Å, and the thickness of the gold conductive layer is 6000 Å to 9000 Å.

9. The method for fabricating a Y-shaped gate to reduce gate resistance according to claim 1, characterized in that, In step 4, the photoresist stripping solution is N-methylpyrrolidone, the temperature of the stripping solution is 60-80°C, and the immersion time of the sample is 60-90 minutes.

10. A Y-shaped gate structure for reducing gate resistance, prepared by the method according to any one of claims 1-9, characterized in that, It includes a GaAs substrate and a Y-shaped gate metal disposed on the GaAs substrate, the Y-shaped gate metal having a gate bottom in contact with the GaAs substrate and a top cap connected to the gate bottom; The support linewidth at the bottom of the gate is Lg+2×d, where Lg is the target gate linewidth and d is the thickness of the low-temperature conformal passivation layer. The Y-shaped gate metal forms a Schottky contact with the GaAs substrate without process stress damage. The Y-shaped gate metal is a titanium, platinum, and gold composite metal layer, with a titanium layer thickness of 350 Å to 450 Å, a platinum layer thickness of 450 Å to 550 Å, and a gold layer thickness of 6000 Å to 9000 Å.

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