A narrow-angle polarization detection integrated chip covering communication frequency bands and a preparation method thereof

Abstract

This invention discloses a narrow-angle polarization detection integrated chip covering communication frequency bands and its fabrication method, comprising: a top-layer chip, using silicon as a substrate, wherein the silicon has an array of through-holes; an array of through-hole grooves with an insulating layer on the upper surface of the silicon; a multi-dimensional composite metasurface, disposed within the array of through-hole grooves of the insulating layer and in contact with the silicon; silicon through-hole metal connecting pillars, uniformly arrayed within the through-holes of the silicon, and connected to each other through the insulating layer; electrodes, evenly distributed above the insulating layer on the upper surface of the silicon with the array of through-hole grooves of the insulating layer as the center, and in contact with the silicon through-hole metal connecting pillars; and a bottom-layer chip, containing a readout integrated circuit module, connected to the top-layer chip via an indium tin alloy. This invention achieves chip-level ultra-narrow-angle detection, integrates the characteristics of anisotropic trench structures, and expands the detection capability of silicon-based chips across the entire communication frequency band, making it suitable for wafer-level production.

Description

Technical Field

[0001] This invention belongs to the fields of micro-nano optoelectronics, integrated photoelectric detection and advanced semiconductor manufacturing technology, and particularly relates to a narrow-angle polarization detection integrated chip covering the communication frequency band and its preparation method. Background Technology

[0002] With the exponential growth of global data traffic, optical communication systems are evolving towards higher bandwidth, denser wavelength division multiplexing, and greater intelligence. Especially in fields such as free-space optical communication, quantum key distribution, lidar, and coherent detection, the performance requirements for photodetectors have evolved from simple light intensity response to high-precision resolution of incident light angle and polarization state. Polarization state expands the information dimension from three dimensions (light intensity, spectrum, and space) to seven dimensions (light intensity, spectrum, space, degree of polarization, polarization azimuth, polarization ellipse, and direction of rotation), playing an irreplaceable role in improving target detection accuracy, reducing environmental interference, and reflecting the characteristics of different materials. The paper "Key Technologies and Applications of Polarization Information Extraction in Target Detection" (by Yang Wei, Nanjing University of Science and Technology) points out that the future development of polarization information extraction technology should focus on wideband adaptability, high polarization contrast, and the convenience and lightweight design of detection imaging devices. However, existing technologies still face significant challenges in achieving detectors with ultra-narrow angular resolution, high polarization contrast, wide spectral coverage, and CMOS compatibility in the communication band.

[0003] I. Limitations of the material system

[0004] Communication bands (especially the low-loss window of 1260 nm-1675 nm) place stringent requirements on the bandgap of detectors. Traditional silicon-based photodiodes are limited by a bandgap of 1.12 eV, with a cutoff wavelength of approximately 1100 nm, failing to cover the O, E, S, C, and L bands. To compensate for this deficiency, the industry typically uses indium gallium arsenide (IGaAs) or germanium (Germanium). However, these III-V group materials suffer from severe lattice and thermal mismatches with silicon-based CMOS processes, resulting in high epitaxial growth costs, high defect density, and low yield, making it difficult to achieve large-scale, low-cost, and high-density on-chip integration. On the other hand, while photodetectors based on two-dimensional materials show potential for polarization detection, their response bands are mostly concentrated in the visible light or short-wave near-infrared regions, making it difficult to cover the entire communication band. Furthermore, wafer-level uniform growth and CMOS compatibility issues have not yet been fundamentally resolved.

[0005] II. Engineering Challenges of Angle Detection

[0006] In angle detection, traditional methods rely on complex external optical systems. To achieve narrow field of view or angle resolution, a combination of lens groups, apertures, and precision mechanical scanning devices is typically required. For example, traditional angle detectors estimate the incident angle by coupling a microlens array with a photodiode array, but this method is bulky, has strict assembly tolerances, and the angle resolution is usually only at the degree level, which cannot meet the requirements for sub-degree-level high-precision angle demodulation. In recent years, researchers have conducted many explorations in this direction. In 2024, inspired by the compound eye structure of insects, Zhou et al. from the Hong Kong University of Science and Technology combined a 3D-printed honeycomb optical structure with a hemispherical high-density perovskite nanowire photodetector array to develop an ultra-wide field-of-view pinhole compound eye system based on a hemispherical nanowire array. This device directly guides light from an extremely narrow field of view to the nanowire light sensor through the hemispherical pinhole array, achieving an ultra-wide field of view of 140°, and was successfully mounted on a drone for real-time motion tracking testing of a quadruped robot. However, this detector has the following significant limitations: its wide-angle detection (140°) is exactly the opposite of the narrow-angle, high-precision detection requirement addressed by this invention; the 3D-printed honeycomb structure and hemispherical surface result in a large device area and complex fabrication process, making it difficult to achieve monolithic integration with modern CMOS technology, thus limiting its miniaturized deployment in practical communication and sensing systems; and its detection range is mainly limited to the visible light band, failing to cover the communication band. Therefore, developing a detector that can achieve ultra-narrow-angle response at the chip level and is compatible with CMOS technology remains an urgent need in this field.

[0007] III. Technical Bottlenecks in Polarization Detection

[0008] In polarization detection, existing technologies also have significant shortcomings. Conventional polarization detection schemes rely on external polarizers, waveplates, and beam splitters, calculating the polarization state by measuring the light intensity in different directions through rotating polarization elements. According to the classification of polarization imaging systems, time-division polarization imaging systems cannot achieve real-time detection of dynamic scenes because they require mechanical rotation of the polarizer during operation. While amplitude-division, aperture-division, and focal-plane-division systems can acquire multiple polariton images simultaneously for real-time detection of dynamic targets, their system complexity is high, often sacrificing spatial resolution or increasing the size of the optical system. These methods are not only redundant and slow in response, but also difficult to integrate into miniaturized systems. In recent years, polarization detectors based on anisotropic two-dimensional materials have made some progress, but their polarization extinction ratios are generally low (typically <100), and their response bands are limited, failing to cover the entire communication band. Furthermore, while existing semiconductor photodetectors and CMOS image sensors have matured in their detection capabilities in dimensions such as light intensity, spectrum, and space, direct on-chip detection of the physical dimension of "angle" is still in its infancy.

[0009] IV. Limitations of Existing Publicly Available Technologies

[0010] Chinese patent application CN115440828A discloses a photoelectric detection chip based on metamaterial microstructures, but its metasurface is limited to a two-dimensional planar structure, lacking a three-dimensional heterogeneous integration design, thus failing to achieve effective angle-selective response. Patent CN115117255A discloses a 1550 nm upconversion polarization detection and visualization imaging device, achieving polarization detection at 1550 nm wavelength through a self-assembled ordered composite structure; however, its polarization contrast is only about 40%-60%, and the components involve various external polarization devices, resulting in a redundant and bulky structure with low integration. Patent CN111430396A discloses a single-photon polarization detection device based on superconducting nanowires, but its detection process still relies on a complex optical system composed of polarizers, half-wave plates, and various additional sensors and polarization detectors. Furthermore, the superconducting nanowires themselves require ultra-low temperature environments to operate, posing significant limitations in practical applications. The patent with publication number CN115911152A discloses a near-infrared polarization photodetector based on a MoS2 / GeSe / MoTe2 heterojunction. Although its spectral range can cover 405-1550 nm, it is limited to the detection of linearly polarized light and cannot effectively detect circularly polarized light. Furthermore, the stacking of two-dimensional material heterojunctions cannot yet achieve large-scale integration.

[0011] V. Implications from Existing Reviews and Monographs

[0012] In the field of polarization detection, existing review articles have systematically outlined the technological development. For example, a joint research team from Taiyuan University of Technology and Xi'an University of Electronic Science and Technology published a review article titled "Research, Application and Progress of Optical Polarization Imaging Technology" in *Infrared and Laser Engineering*, pointing out that research on metasurface polarization devices in areas such as polarization conversion, optical rotation, and vector beam generation has made it possible to make polarization imaging systems portable and real-time. However, it also points out core bottlenecks such as the inability of time-division systems to detect in real time and the high complexity of amplitude-division / aperture-division / focal-plane systems. Recently, Zhang Bei's research group published a review article on polarization direction measurement technology in *IEEE Transactions on Instrumentation and Measurement*, systematically reviewing the evolution path and technological spectrum of polarization direction measurement technology since the 19th century. It points out that traditional methods generally rely on mechanical rotation, making it difficult to meet the practical needs of dynamic and wide-bandgap scenarios. Meanwhile, a review of polarization spectral imaging technology also points out that due to the limitations of the Nyquist-Shannon sampling theory, most existing polarization spectral imaging uses scanning mechanisms, which cannot acquire all information in a single exposure, making it unsuitable for high-dynamic scenarios or highly mobile platforms.

[0013] In summary, an integrated photodetector chip capable of simultaneously achieving ultra-narrow angular resolution (sub-metric), high polarization contrast (>200), full-band coverage (1260-1675 nm), and compatibility with CMOS processes in the all-optical communication band is currently unavailable. In particular, the ability to perform high-precision calculations of the incident light angle and polarization state directly at the chip level without any external lenses or polarization elements is a core bottleneck restricting the development of next-generation intelligent optoelectronic devices. Summary of the Invention

[0014] The purpose of this invention is to address the technical problems of existing photodetectors and their components, such as low integration, bulky and redundant structures, difficulty in achieving ultra-narrow angle resolution in communication bands, and poor compatibility with CMOS. This invention provides a narrow-angle polarization detection integrated chip covering communication frequency bands and its fabrication method.

[0015] To achieve the above functions, the technical feature of this invention is: a narrow-angle polarization detection integrated chip covering the communication frequency band, the chip comprising:

[0016] The top-layer chip uses silicon as a substrate, and the silicon has an array of through-holes; an insulating layer is provided on the outer surface of the silicon substrate, and the insulating layer on the upper surface of the silicon has an array of through-hole grooves.

[0017] The multidimensional composite metasurface is composed of platinum diselenide, a two-dimensional metal nanostrip metasurface, and a three-dimensional silicon nanostrip metasurface; the multidimensional composite metasurface is disposed in the array of perforated grooves of the insulating layer and is in contact with the silicon.

[0018] Silicon through-hole metal connectors are uniformly arrayed within the through-holes of the silicon, and are connected to each other through the insulating layer.

[0019] The electrodes are evenly distributed above the insulating layer on the upper surface of the silicon, with the array of perforated grooves of the insulating layer as the center, and are in contact with the silicon through-hole metal connecting post, and at the same time in contact with platinum diselenide;

[0020] The bottom chip has an indium tin alloy on its upper surface and an internal readout integrated circuit module connected to the indium tin alloy. The bottom chip is connected to the top chip through the indium tin alloy.

[0021] Furthermore, the three-dimensional silicon nanostrip metasurfaces are arranged in an array with uniform spacing, and the two-dimensional metal nanostrip metasurfaces are disposed above and in contact with the three-dimensional silicon nanostrip metasurfaces, with the same arrangement as the three-dimensional silicon nanostrip metasurfaces; the platinum diselenide is disposed around the two-dimensional metal nanostrip metasurfaces and the three-dimensional silicon nanostrip metasurfaces, thus fully encapsulating the two-dimensional metal nanostrip metasurfaces and the three-dimensional silicon nanostrip metasurfaces.

[0022] Furthermore, the multidimensional composite metasurface exhibits the following properties in the all-optical communication band (1260 nm-1675 nm): angular resolution narrow angle range ≤ ±0.5°, polarization extinction ratio ≥ 200, and tilt sensitivity ≥ 10°. 4 .

[0023] Furthermore, the first Schottky junction formed by the two-dimensional metal nanostrip metasurface and the three-dimensional silicon nanostrip metasurface, and the second Schottky junction formed by the platinum diselenide and the three-dimensional silicon nanostrip metasurface, together constitute a double Schottky junction structure. The double Schottky junction structure forms a back-to-back barrier under reverse bias conditions, which is used to suppress dark current and enhance the separation and collection efficiency of photogenerated carriers. The two-dimensional metal nanostrip metasurface generates localized surface plasmon resonance under incident light in the communication band, localizing the light field energy to the tip and sidewall region of the nanogroove, thereby enhancing the interaction between light and matter.

[0024] Furthermore, the architecture of the readout integrated circuit module comprises a pixel selector module, a digital control module, a phase-locked loop (PLL), an analog front-end (AFE), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a bandgap reference source (BGR), and decoupling capacitors. The design of this invention integrates tunable capacitors in the analog front-end, enabling the readout module to handle current signals from nanoamps to milliamps, ensuring compatibility with various devices.

[0025] Furthermore, the indium tin alloy is provided below the silicon of the top-layer chip and below the through-silicon via (TSV) metal connection pillars for ohmic contact; the bottom-layer chip is connected to the top-layer chip via the indium tin alloy to form a chip stack readout integrated module; the chip stack readout integrated module is formed by stacking the top-layer chip and the bottom-layer chip, and the stacking form of the top-layer chip and the bottom-layer chip can be any one of pyramid stacking, cantilever stacking, side-by-side stacking, or through-silicon via (TSV) stacking. The ultra-compact architecture design abandons the bulky optical design and structural redundancy of the photosensitive module and readout module in traditional photoelectric detection chip / device components. The low power consumption is due to the fact that the present invention can generate open-circuit voltage and short-circuit current by illumination without external power supply. Illumination itself can enable the chip to work, and the present invention can realize near-infrared band detection at room temperature, without the need for additional liquid nitrogen cooling as in traditional near-infrared detectors, which is a major breakthrough for near-infrared detectors.

[0026] Furthermore, the through-silicon via (TSV) metal interconnects and the indium tin alloy enable vertical interconnect stacking between chips. This vertical interconnect reduces the interconnect length and signal delay between the top-layer chip and the bottom-layer chip, and lowers capacitance and inductance.

[0027] Furthermore, the multidimensional composite metasurface pixel array on the top-level chip can be any arrangement of 2*2, 4*4, 8*8, 16*16...n*n or n*m, where n and m are positive integers.

[0028] Furthermore, the fabrication process of the insulating layer can be any one of thermal oxidation growth, PECVD furnace growth, atomic layer deposition (ALD), or electron beam evaporation deposition of silicon oxide. The metal deposition process for the two-dimensional metal nanostrip metasurface and electrodes can be any one of thermal evaporation, electron beam evaporation, or magnetron sputtering. The CMOS wafer fabrication process node of the underlying chip can be any one of 180nm, 130nm, 90nm, 65nm, 45nm, 28nm, 14nm, 7nm, 5nm, or 3nm.

[0029] Furthermore, the indium tin alloy used as the ohmic contact can be any one of indium tin alloy, metal silicide (NiSi, TiSi2, or CoSi2), gallium indium alloy, or aluminum. The indium tin alloy mentioned in this invention is just one example. The insulating layer on the upper surface of the silicon has an array of perforated grooves, which can be any one of polygonal grooves or circular grooves, such as L-shaped grooves, rectangular grooves, or triangular grooves.

[0030] Furthermore, the material of the two-dimensional metal nanostrip metasurface can be any one of gold (Au), platinum (Pt), palladium (Pd), silver (Ag), copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), or aluminum (Al). The platinum diselenide can be any one of platinum diselenide, single-element silylene, germanene, stanene, borene, black phosphorus, graphene, transition metal chalcogenides (such as MoS2, WSe2, ReS2, PtSe2, NbSe2), or main group metal chalcogenides (such as GaS, InSe, SnS, SnS2), wherein the number of layers can be single-layered or multi-layered. The platinum diselenide described in this invention is just one example.

[0031] On the other hand, the present invention also provides a method for fabricating a narrow-angle polarization detection integrated chip covering the communication frequency band, the specific fabrication process of which is as follows:

[0032] (1) Prepare the silicon substrate for the top-layer chip;

[0033] (2) Fabrication of through-silicon vias in the top-layer chip array: The required through-silicon vias are created by arraying deep silicon etching on the silicon wafer, and a metal seed layer is deposited in the through-silicon vias;

[0034] (3) Patterning of silicon windows in top-layer chip array: The cleaned silicon wafer is subjected to spin coating, photolithography, development, and etching of the oxide layer in the window area to complete the patterning of the silicon window array.

[0035] (4) Patterning of the top layer chip array electrodes: Continue the steps of spin coating-pre-baking-photolithography-development, deposit metal, and then peel off the remaining metal except for the electrode pattern. After cleaning, the complete electrode pattern is obtained.

[0036] (5) Fabrication of multidimensional composite metasurface of top chip: Two-dimensional metal nanostrip metasurface is obtained by electron beam lithography; using the two-dimensional metal nanostrip metasurface as a mask, silicon is then etched by ICP to prepare a three-dimensional silicon nanostrip metasurface; patterned platinum diselenide is prepared in the patterned silicon window of the top chip array to finally obtain a multidimensional composite metasurface.

[0037] (6) Fabricate a readout integrated circuit module for the underlying chip, which consists of a digital control module and an analog module;

[0038] (7) Fabrication of the chip stacked readout integrated module: The readout integrated circuit module of the bottom chip is stacked and flip-bonded with the silicon and silicon through-hole metal interconnect pillars of the top chip to form the chip stacked readout integrated module.

[0039] Further, in step (2), a thermal oxidation process is performed on the silicon wafer to form a through-surface insulating layer including through-silicon vias, and a metal seed layer is deposited in the through-silicon vias to obtain a top-layer chip with through-silicon via metal interconnect pillars.

[0040] Further, in step (3), the cleaned silicon wafer is spin-coated with photoresist, and then the silicon wafer after photoresist coating is photolithographically etched and developed. Then, the window area not protected by photoresist is etched in a buffer oxide etching solution, and then the wafer is cleaned and the photoresist is removed to complete the patterning of the array silicon window.

[0041] Further, in step (5), the top chip is homogenized, the design pattern is lithographically drawn using electron beam lithography, metal is deposited by electron beam evaporation, and a two-dimensional metal nanostrip metasurface is obtained by a lift-off process.

[0042] Further, in step (5), a platinum metal layer is deposited on the oxide layer by combining ion beam sputtering within the silicon window of the patterned top chip array. The top chip containing the platinum metal layer is placed in a ceramic boat containing selenium powder and patterned platinum diselenide is obtained by vacuum heating in a tube furnace, thus obtaining a multidimensional composite metasurface.

[0043] Furthermore, the fabrication process of the multidimensional composite metasurface of the top-layer chip is as follows: The top-layer chip after the above process is homogenized with a photoresist, and the designed pattern is lithographically drawn using high-resolution electron beam evaporation. Metal is then deposited via electron beam evaporation, followed by the lift-off process described above to obtain a two-dimensional metal nanostrip metasurface. Next, using the two-dimensional metal nanostrip metasurface as a mask, silicon is etched using ICP (Inductively Coupled Plasma Dry Etching System, using C4F8 and SF6 as reactive gases) to fabricate a three-dimensional silicon nanostrip metasurface. Next, a 1-15 nm thick platinum metal layer is deposited on the oxide layer within the patterned top-layer chip array silicon window using ion beam sputtering. 500 mg of selenium powder is weighed and placed in a ceramic boat. The top-layer chip containing the platinum metal layer is then placed upside down on the selenium powder in the ceramic boat, maintaining a certain distance between the platinum and the selenium powder. The ceramic boat is placed inside a quartz tube, and the quartz tube is evacuated to below 25 mTorr. Nitrogen gas is then introduced to one atmosphere. This evacuation and nitrogen introduction process is repeated three times to remove air from the quartz tube. The needle valve is adjusted to maintain the pressure inside the tube at 750 Torr, ensuring sufficient nitrogen. The airflow rate is 50 standard milliliters per minute. The ceramic boat and the tube furnace are heated simultaneously, from room temperature to 100 degrees Celsius within 10 minutes and held for 10 minutes. Then, the tube furnace is heated to 400 degrees Celsius within 60 minutes and held for 20 minutes. After this, the ceramic boat is quickly pulled out of the heating area and cooled to room temperature for 20 minutes. At the same time, the temperature of the tube furnace is lowered to 250 degrees Celsius. Then, the ceramic boat is put back into the heating area for 20 minutes. After this, the ceramic boat is quickly pulled out of the heating area and allowed to cool naturally to room temperature. The top layer chip is then removed, yielding patterned platinum diselenide with a thickness of 1-15 nanometers. The structural unit design of the two-dimensional metal nanostrip metasurface and the three-dimensional silicon nanostrip is as follows: two rectangular nanostrips with narrower sides are connected to a square nanostructure with wider sides, and the overall structure is axially symmetrical. Finally, a composite metasurface containing platinum diselenide, a two-dimensional metal nanostrip metasurface, and a low-dimensional silicon nanostrip metasurface is obtained, which is the multidimensional composite metasurface of the top layer chip.

[0044] Furthermore, the thickness of the structural units of the two-dimensional metal nanoribbon metasurface can be any range between 10 and 500 nm. The thickness of the structural units of the three-dimensional silicon nanoribbon is determined by controlling the etching process according to actual needs, and can be any range between 100 and 2000 nm.

[0045] Furthermore, the multidimensional composite metasurface is manufactured using an electron beam writing (EBL) process, or alternatively, using a multi-step photolithography process, a multi-step ion beam writing (DWL) process, or a binary-hole anodic aluminum oxide (AAO) template process. The two-dimensional metal nanostrip metasurface and the three-dimensional silicon nanostrip metasurface can achieve flexible control of the response wavelength by adjusting their different dimensions.

[0046] Furthermore, in step (6), the architecture of the readout integrated circuit includes a pixel selector module, an analog front-end (AFE), an analog-to-digital converter (ADC), a digital control module, a digital-to-analog converter (DAC), a bandgap reference source (BGR), and a phase-locked loop (PLL).

[0047] Further, in step (7), the upper surface terminals of the readout integrated circuit module of the bottom chip are coated with indium tin alloy, and the silicon underside and the silicon through-hole metal connection pillar of the top chip are respectively stacked and flip-bonded with the indium tin alloy on the bottom chip to form a chip stack readout integrated module. The top chip and the bottom chip are stacked together through the chip stack readout integrated module.

[0048] The beneficial effects of this invention are:

[0049] This invention proposes a narrow-angle polarization detection integrated chip covering the communication frequency band and its fabrication method. The chip surface is fabricated using a multidimensional composite metasurface prepared by electron beam lithography and inductively coupled plasma etching processes, and integrates a platinum / gold / silicon heterostructure fully encapsulated (HAA) stacked structure, thereby achieving ultra-narrow angle and high polarization contrast detection across the entire optical communication band. This invention employs a three-dimensional HAA stacked architecture, achieving an ultra-narrow angle detection effect (±0.5°) through an anisotropic nanogroove array. Simultaneously, the polarization extinction ratio is increased to over 200 across the entire optical communication band (1260 nm-1675 nm) through the dual Schottky junction and surface plasmon resonance effect. Furthermore, through-silicon via (TSV) technology is integrated for wafer-level fabrication, and a 0.18 μm integrated CMOS readout circuit is developed, realizing an ultra-narrow angle polarization detection chip based on HAA heterostructure stacking and three-dimensional hybrid integration. This invention not only achieves chip-level ultra-narrow angle detection, incorporating the characteristics of anisotropic trench structures, but also expands the detection capabilities of silicon-based chips across the entire communication band, making it suitable for wafer-level manufacturing. It not only reduces costs but also significantly improves compatibility with existing CMOS processes and achieves a room-temperature operating mode without external lenses or cooling. This paves the way for cutting-edge chips integrating narrow-angle, high polarization contrast detection technology, which is particularly crucial for various applications that often require complex and large-scale optoelectronic systems. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of the present invention;

[0052] Figure 2 Anisotropic electron microscope images and transmission electron microscope images of the actual multidimensional composite metasurface structure unit;

[0053] Figure 3 The images shown are physical drawings and enlarged partial views of the present invention.

[0054] Figure 4 This is a flowchart of the preparation process of the present invention;

[0055] Figure 5 These are the polarization-dependent absorption test results and simulation results of this invention;

[0056] Figure 6 This is a schematic diagram illustrating the mechanism by which the present invention achieves narrow-angle detection;

[0057] Figure 7 This is a circuit architecture diagram for reading out the present invention;

[0058] Figure 8 The figures show the test system and photoelectric imaging results of this invention.

[0059] in:

[0060] 1. Multidimensional composite metasurface; 2. Chip stacked readout integrated module; 3. Platinum diselenide; 4. Two-dimensional metal nanostrip metasurface; 5. Three-dimensional silicon nanostrip metasurface; 6. Insulating layer; 7. Electrode; 8. Silicon through-hole metal connector; 9. Silicon; 10. Indium tin alloy; 11. Readout integrated circuit module; 12. Bottom chip; 13. Top chip. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are merely illustrative and not intended to limit the invention.

[0062] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the present invention provides a narrow-angle polarization detection integrated chip covering the communication frequency band, including a multi-dimensional composite metasurface 1, a chip stacked readout integrated module 2, platinum diselenide 3, a two-dimensional metal nanostrip metasurface 4, a three-dimensional silicon nanostrip metasurface 5, an insulating layer 6, electrodes 7, silicon through-hole metal connecting pillars 8, silicon 9, indium tin alloy 10, a readout integrated circuit module 11, a bottom chip 12, a top chip 13, and other components;

[0063] The top-layer chip 13 and the bottom-layer chip 12 are vertically interconnected and stacked using through-silicon via (TSV) technology, utilizing the through-silicon via metal connectors 8 and the indium tin alloy 10. Together, they constitute the main body of the narrow-angle polarization detection integrated chip covering the communication frequency band of this invention. The vertical interconnection reduces the interconnection length and signal delay between the top-layer chip 13 and the bottom-layer chip 12, reduces capacitance and inductance, achieves low-power, high-speed communication between chips, increases bandwidth, and realizes miniaturized integration. The multidimensional composite metasurface 1, the through-silicon via metal connectors 8, the silicon 9, the electrode 7, and the insulating layer 6 together constitute the main body of the top-layer chip 13.

[0064] The silicon 9 serves as the substrate of the top-layer chip 13. The silicon 9 is provided with an array of through-holes formed by deep silicon etching. The insulating layer 6 is disposed on the outer surface of the silicon 9, including the upper and lower surfaces of the silicon 9 and the inner surface of its through-holes. The silicon through-hole metal connecting pillars 8 are uniformly arrayed within the through-holes of the silicon 9, and the two are connected by the insulating layer 6. The multidimensional composite metasurface 1 is disposed within the perforated grooves of the insulating layer 6 and contacts the silicon 9. The platinum diselenide 3, the two-dimensional metal nanoribbon metasurface 4, and the three-dimensional silicon nanoribbon metasurface 5 together constitute the multidimensional composite metasurface 1. The three-dimensional silicon nanoribbon metasurface 5 is arrayed in a uniformly spaced manner. The two-dimensional metal nanostrip metasurface 4 is disposed above the three-dimensional silicon nanostrip metasurface 5 and is in contact with the three-dimensional silicon nanostrip metasurface 5, with the same arrangement as the three-dimensional silicon nanostrip metasurface 5; the platinum diselenide 3 is disposed around the two-dimensional metal nanostrip metasurface 4 and the three-dimensional silicon nanostrip metasurface 5, fully enclosing the two-dimensional metal nanostrip metasurface 4 and the three-dimensional silicon nanostrip metasurface 5, and is in contact with the electrode 7; the electrode 7 is evenly distributed above the insulating layer 6 on the upper surface of the silicon 9 with the array of perforated grooves of the insulating layer 6 as the center, and is in contact with the silicon through-hole metal connecting posts 8 evenly distributed in the through-holes of the silicon 9;

[0065] The array arrangement of the multidimensional composite metasurface 1 constitutes the pixel array of the top chip 13; the indium tin alloy 10 is provided on the upper surface of the bottom chip 12, and the readout integrated circuit module 11 is disposed in the bottom chip 12 and connected to the indium tin alloy 10; the readout integrated circuit module 11 consists of a digital control module and an analog module, the analog module consisting of a phase-locked loop (PLL), an analog front-end (AFE), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a bandgap reference source (BGR), and a decoupling capacitor; the indium tin alloy 10 is provided below the silicon 9 and below the through-silicon via metal connection post 8 of the top chip 13 for ohmic contact, and is connected to the bottom chip 12 through the indium tin alloy 10 to form the chip stack readout integrated module 2; the overall chip architecture is composed of the pixel array of the multidimensional composite metasurface 1 disposed on the top chip 13, the chip stack readout integrated module 2, and the readout integrated circuit module 11 of the bottom chip 12;

[0066] The multidimensional composite metasurface exhibits the following properties in the all-optical communication band (1260 nm-1675 nm): angular resolution narrow angle range ≤ ±0.5°, polarization extinction ratio ≥ 200, and tilt angle sensitivity ≥ 10°. 4 ,like Figure 5 and Figure 6 As shown.

[0067] The first Schottky junction formed by the two-dimensional metal nanostrip metasurface and the three-dimensional silicon nanostrip metasurface, and the second Schottky junction formed by the platinum diselenide and the three-dimensional silicon nanostrip metasurface, together constitute a double Schottky junction structure. This double Schottky junction structure forms a back-to-back barrier under reverse bias conditions, used to suppress dark current and enhance the separation and collection efficiency of photogenerated carriers. Figure 2 As shown, the two-dimensional metallic nanostrip metasurface generates localized surface plasmon resonances under incident light in the communication band, localizing the light field energy to the tips and sidewalls of the nanogrooves, thus enhancing the interaction between light and matter. This invention can generate open-circuit voltage and short-circuit current through illumination without external power supply; the illumination itself enables the device to operate. Furthermore, this invention can achieve near-infrared detection at room temperature, eliminating the need for additional liquid nitrogen cooling as required by traditional near-infrared detectors, representing a significant breakthrough for near-infrared detectors.

[0068] This invention optimizes the core processes of carrier generation, transport, injection, and signal readout in Schottky carrier detection. The two-dimensional metal nanostrip metasurface of the three-dimensional silicon nanostrip metasurface induces surface plasmon resonance, enhancing absorption and photoelectric conversion efficiency. Hot carriers are trapped at the Schottky junctions of the two-dimensional metal nanostrip metasurface-three-dimensional silicon nanostrip metasurface and the platinum diselenide-three-dimensional silicon nanostrip metasurface, shortening the transport distance. The absorption field widens the Schottky barrier and depletion region, improving electron-hole pair collection. In the multidimensional composite metasurface, the reverse bias voltage enhances electron transport by collecting charge carriers before recombination. The heterogeneous fully enclosed structure forms a double Schottky junction, reducing the metal-semiconductor contact area to suppress dark current while increasing the contact area for better injection efficiency. Photon absorption on the two-dimensional metal nanostrip metasurface / three-dimensional silicon nanostrip metasurface generates electron-hole pairs (EHP) coupled to platinum diselenide. The Schottky barrier is matched to the communication band, reducing dark current and optimizing carrier separation, thereby improving photoelectric conversion efficiency and reducing noise. Figure 5 Experimental and simulation results of polarization-correlated absorption in the communication band are presented for this invention. Under 1550 nm polarized illumination (0.06 mW / mm²), 2 Under a bias of -2 V, the polarization extinction ratio of this invention is ≥200, which is far superior to that of traditional silicon-based photodiodes.

[0069] Figure 6 The angle-resolved response spectra of conventional metasurface devices and the present invention are demonstrated, measured under polarization conditions, covering the entire communication band. The results show that the present invention achieves ultra-narrow angle detection (±0.5°) and exceptionally high angular sensitivity (2.5 × 10⁻⁶ at 1550 nm) under parallel polarization. 4 There are no similar reports in the field of integrated chips. In contrast, traditional metasurface silicon-based devices do not exhibit angle-dependent sensitivity, and their optical response in the infrared communication band is significantly weaker than the heterogeneous fully encapsulated multidimensional composite metasurface designed in this invention. It is worth noting that... Figure 5 The significant difference between parallel and perpendicular polarized signals (polarization ratio of 215.5) shown in the diagram further supports the invention's ability to detect polarization angles across the entire communication band.

[0070] Figure 7The circuit architecture of this invention is illustrated, including a pixel selector module, a digital control module, a phase-locked loop (PLL), an analog front-end (AFE), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a bandgap reference source (BGR), and decoupling capacitors. Adjustable capacitors in the analog front-end adjust the main frequency, enabling the readout module to handle current signals from nA to mA for device compatibility. An embodiment of the readout integrated circuit module of this invention is manufactured using a 180 nm CMOS process. Its architecture integrates a selection switch, analog front-end, ADC, and digital control logic. The analog front-end employs a capacitor-transimpedance amplifier configuration, with the output voltage decreasing linearly as photogenerated charge accumulates. Due to the significant variations in photocurrent under different lighting conditions, both the integrating capacitor and integration time are designed to be adjustable. In the presence of strong photocurrent, the integrating capacitor can be configured to a larger value to prevent saturation. To suppress noise and compensate for amplifier offset, a correlated double-sampling scheme is implemented by sampling two voltages and temporarily storing them in a transfer capacitor before buffering them to the ADC. Once both samples have been converted, the digital logic calculates the difference between the two values. Finally, the processed data is transmitted to the host computer via a Universal Asynchronous Receiver / Transmitter (UART). During operation, the device array is reverse-biased, with the other end connected to the readout current input.

[0071] To verify the narrow-angle and polarization angle detection capabilities of this invention, this embodiment sets a multi-dimensional composite metasurface array (0°-385.5°, angle variation 1.5° / pixel, the last row serving as a marker line for those without metasurfaces) on each pixel of the heterogeneous fully enclosed hybrid stacked chip. The invention is connected to a field-programmable gate array (FPGA) via wire bonding, and the FPGA is then connected to a computer. By writing and compiling a program into the FPGA, various logic functions and computational acceleration are implemented on the chip, facilitating automatic signal processing through chip readout integration. The invention was tested under lensless conditions using a -2 V bias voltage and 1550 nm wavelength incident light. Figure 8 (a)). The imaging test results in this embodiment show that light emitted from a communication optical fiber with a polarization angle of 0° can be clearly distinguished and imaged by the present invention, and the same is true when the optical fiber is rotated horizontally by 90°. In addition, when the optical fiber is tilted by more than 0.5°, the present invention can detect the non-collimated state, demonstrating ultra-high tilt accuracy. Figure 8 (b) in the middle.

[0072] According to a second aspect of this specification, a method for fabricating a narrow-angle polarization detection integrated chip covering communication frequency bands is provided. This method mainly consists of three process systems: first, the fabrication of a top-layer chip; second, the fabrication of a bottom-layer chip; and third, the stacking and bonding of the top-layer and bottom-layer chips. The fabrication process includes the following steps:

[0073] (1) Preparation of silicon substrate for top-layer chip: Taking N-type lightly doped silicon wafer (silicon wafer thickness 100-500 um, resistivity 1-10 Ω·cm) as an example, cut it to the required size, perform surface cleaning treatment, and then put it into acetone, isopropanol and deionized water solution for ultrasonic cleaning in sequence, and then take it out and blow it dry with nitrogen.

[0074] (2) Fabrication of through-silicon vias in the top-layer chip array: The required through-silicon vias are created by arraying deep silicon etching process on the silicon wafer. The silicon wafer is then subjected to thermal oxidation to form a through-surface insulating layer including the through-silicon vias. Then, a metal seed layer is deposited in the through-silicon vias. The metal in the through-holes is electroplated and chemically polished to obtain a top-layer chip with metal interconnect pillars for through-silicon vias.

[0075] (3) Patterning of silicon windows in the top-layer chip array: The cleaned silicon wafer is spin-coated with photoresist to uniformly cover the surface of the wafer. It is then pre-baked at 105°C for 5 minutes, followed by photolithography. After photolithography, a developing solution is prepared by mixing developer and water in a 1:7 ratio. The wafer is then post-baked at 120°C for 20 minutes to fully cure the photoresist, protecting the oxide layer beneath it during the subsequent wet etching process. Then, the unprotected window area is etched in a buffered oxide etching (BOE) solution. The BOE solution ratio is: NH4F: HF: H2O = 60 g: 30 ml: 100 ml. This BOE solution has an etching rate of 100 nm / min. When the SiO2 layer thickness in the silicon wafer is 100 nm, etching for 1 minute is sufficient. After the device is retrieved from the BOE solution, it is washed in water and then de-adhesive is removed using acetone and isopropanol to complete the patterning fabrication of the array silicon window.

[0076] (4) Patterning of the top layer chip array electrodes: Continue to repeat the above steps of spin coating-pre-baking-photolithography-development. Metal deposition can be performed using thermal evaporation, electron beam evaporation or magnetron sputtering. Then, use acetone solution to lift off the remaining metal except for the electrode pattern, and then use isopropanol to clean the acetone to obtain the complete electrode pattern.

[0077] (5) Fabrication of multidimensional composite metasurface of top chip: The top chip after the above process is homogenized with photoresist, and the design pattern is lithographically drawn using high-resolution electron beam lithography. Metal is deposited by electron beam evaporation, and then a two-dimensional metal nanostrip metasurface is obtained by the above lift-off process. Then, using the two-dimensional metal nanostrip metasurface as a mask, silicon is etched using ICP (Inductively Coupled Plasma Dry Etching System, using C4F8 and SF6 as reactive gases) to prepare a three-dimensional silicon nanostrip metasurface. Next, a 1-15 nm thick platinum metal layer is deposited on the oxide layer within the patterned top-layer chip array silicon window using ion beam sputtering. 500 mg of selenium powder is weighed and placed in a ceramic boat. The top-layer chip containing the platinum metal layer is then placed upside down on the selenium powder in the ceramic boat, maintaining a certain distance between the platinum and the selenium powder. The ceramic boat is placed inside a quartz tube, and the quartz tube is evacuated to below 25 mTorr. Nitrogen gas is then introduced to one atmosphere. This evacuation and nitrogen introduction process is repeated three times to remove air from the quartz tube. The needle valve is adjusted to maintain the pressure inside the tube at 750 Torr, ensuring sufficient nitrogen. The gas flow rate was 50 standard milliliters per minute. The ceramic boat and the tube furnace were heated simultaneously, from room temperature to 100 degrees Celsius within 10 minutes and held for 10 minutes. Then, within 60 minutes, the tube furnace was heated to 400 degrees Celsius and held for 20 minutes. After this, the ceramic boat was quickly pulled out of the heating area and cooled to room temperature for 20 minutes. Simultaneously, the tube furnace temperature was lowered to 250 degrees Celsius. The ceramic boat was then placed back into the heating area and heated for 20 minutes. After this, the ceramic boat was quickly pulled out of the heating area and allowed to cool naturally to room temperature. The top-layer chip was then removed, yielding patterned platinum diselenide with a thickness of 1-15 nanometers. Ultimately, a composite metasurface was obtained, comprising platinum diselenide, a two-dimensional metal nanostrip metasurface, and a low-dimensional silicon nanostrip metasurface—that is, the multidimensional composite metasurface of the top-layer chip. Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown.

[0078] (6) Design and fabrication of the readout integrated circuit module for the underlying chip: The architecture of the readout integrated circuit includes a pixel selector module, an analog front-end (AFE), an analog-to-digital converter (ADC), a digital control module, a digital-to-analog converter (DAC), a bandgap reference source (BGR), and a phase-locked loop (PLL). This design integrates a decoupling capacitor in the analog front-end, enabling the readout module to accommodate current signals from nA to mA by adjusting the main frequency, thus ensuring compatibility with various devices. The chip is fabricated using a CMOS 0.18-micron process node, such as... Figure 4 and Figure 7 As shown.

[0079] (7) Fabrication of the chip stack readout integrated module (top chip and bottom chip stacking):

[0080] The upper surface terminals of the readout integrated circuit module of the bottom chip are coated with indium tin alloy using solder bump technology. Flip chip technology is used to flip-bond the silicon underside and the metal interconnect pillars of the through-silicon via (TSV) of the top chip to the indium tin alloy on the bottom chip, forming a stacked readout integrated module. The top chip and the bottom chip are stacked together through this module to form the present invention. Figure 1 , Figure 2 and Figure 3 As shown.

[0081] In summary, this invention provides a narrow-angle polarization detection integrated chip and its fabrication method covering the communication frequency band. The chip surface is fabricated using a multi-dimensional composite metasurface prepared by electron beam lithography and inductively coupled plasma etching processes, and integrates a platinum / gold / silicon heterostructure-encapsulated (HAA) stacked structure, thereby achieving ultra-narrow angle and high polarization contrast detection across the entire optical communication band. This invention employs a three-dimensional HAA stacked architecture, achieving an ultra-narrow angle detection effect (±0.5°) through an anisotropic nanogroove array. Simultaneously, the polarization extinction ratio in the entire optical communication band (1260 nm-1675 nm) is increased to over 200 through the dual Schottky junction and surface plasmon resonance effect. Furthermore, through-silicon via (TSV) technology is integrated for wafer-level fabrication, and a 0.18 μm integrated CMOS readout circuit is developed, realizing an ultra-narrow angle polarization detection chip based on HAA heterostructure stacking and three-dimensional hybrid integration. This invention not only achieves chip-level ultra-narrow angle detection, incorporating the characteristics of anisotropic trench structures, but also expands the detection capabilities of silicon-based chips across the entire communication band, making it suitable for wafer-level manufacturing. It not only reduces costs but also significantly improves compatibility with existing CMOS processes and achieves a room-temperature operating mode without external lenses or cooling. This paves the way for cutting-edge chips integrating narrow-angle, high polarization contrast detection technology, which is particularly crucial for various applications that often require complex and large-scale optoelectronic systems.

[0082] The above embodiments provide an exemplary description of the present invention. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any improvements made using the inventive concept and technical solution of the present invention, or direct application to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A narrow-angle polarization detection integrated chip covering communication frequency bands, characterized in that, The chip includes: The top-layer chip uses silicon as a substrate, and the silicon has an array of through-holes; an insulating layer is provided on the outer surface of the silicon substrate, and the insulating layer on the upper surface of the silicon has an array of through-hole grooves. The multidimensional composite metasurface is composed of platinum diselenide, a two-dimensional metal nanostrip metasurface, and a three-dimensional silicon nanostrip metasurface; the multidimensional composite metasurface is disposed in the array of perforated grooves of the insulating layer and is in contact with the silicon. Silicon through-hole metal connectors are uniformly arrayed within the through-holes of the silicon, and are connected to each other through the insulating layer. The electrodes are evenly distributed above the insulating layer on the upper surface of the silicon, with the array of perforated grooves of the insulating layer as the center, and are in contact with the silicon through-hole metal connecting post, and at the same time in contact with platinum diselenide; The bottom chip has an indium tin alloy on its upper surface and an internal readout integrated circuit module connected to the indium tin alloy. The bottom chip is connected to the top chip through the indium tin alloy.

2. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The three-dimensional silicon nanostrip metasurfaces are arranged in an array with uniform spacing. The two-dimensional metal nanostrip metasurfaces are located above and in contact with the three-dimensional silicon nanostrip metasurfaces, and their arrangement is consistent with that of the three-dimensional silicon nanostrip metasurfaces. Platinum diselenide is located on the periphery of the two-dimensional metal nanostrip metasurfaces and the three-dimensional silicon nanostrip metasurfaces, thus fully encapsulating them.

3. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The readout integrated circuit module consists of a digital control module and an analog module. The analog module is composed of a phase-locked loop (PLL), an analog front-end (AFE), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a bandgap reference source (BGR), and decoupling capacitors.

4. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The top-layer chip has an indium tin alloy below the silicon and below the through-silicon via (TSV) metal connector for ohmic contact. The bottom-layer chip is connected to the top-layer chip via the indium tin alloy to form a chip stack readout integrated module. The stacking form of the top-layer chip and the bottom-layer chip is any one of pyramid stacking, cantilever stacking, side-by-side stacking or through-silicon via (TSV) stacking.

5. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The through-silicon via (TSV) metal connectors and the indium tin alloy enable vertical interconnect stacking between chips. Vertical interconnect reduces the interconnect length and signal delay between the top-layer and bottom-layer chips, and lowers capacitance and inductance.

6. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The first Schottky junction formed by the two-dimensional metal nanostrip metasurface and the three-dimensional silicon nanostrip metasurface, and the second Schottky junction formed by the platinum diselenide and the three-dimensional silicon nanostrip metasurface, together constitute a double Schottky junction structure. The double Schottky junction structure forms a back-to-back barrier under reverse bias conditions, which is used to suppress dark current and enhance the separation and collection efficiency of photogenerated carriers. The two-dimensional metal nanostrip metasurface generates localized surface plasmon resonance under the excitation of incident light in the communication band, which localizes the light field energy to the tip and sidewall region of the nanogroove, thereby enhancing the interaction between light and matter.

7. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The array arrangement of the multidimensional composite metasurface constitutes the pixel array of the top-layer chip. The pixel array is in the form of n*n or n*m, where n and m are positive integers.

8. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The insulating layer can be prepared by any one of thermal oxidation growth, PECVD furnace growth, atomic layer deposition (ALD), or electron beam evaporation deposition of silicon oxide; the insulating layer on the upper surface of the silicon has an array of perforated grooves, which can be either polygonal grooves or circular grooves.

9. The narrow-angle polarization detection integrated chip covering the communication frequency band according to claim 1, characterized in that, The material of the two-dimensional metal nanostrip metasurface is any one of gold (Au), platinum (Pt), palladium (Pd), silver (Ag), copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), or aluminum (Al); the metal deposition process of the two-dimensional metal nanostrip metasurface and the electrode is any one of thermal evaporation, electron beam evaporation, or magnetron sputtering.

10. A method for fabricating a narrow-angle polarization detection integrated chip covering the communication frequency band according to any one of claims 1-9, characterized in that, The specific preparation process is as follows: (1) Prepare the silicon substrate for the top-layer chip; (2) Fabrication of through-silicon vias in the top-layer chip array: The required through-silicon vias are created by arraying deep silicon etching on the silicon wafer, and a metal seed layer is deposited in the through-silicon vias; (3) Patterning of silicon windows in top-layer chip array: The cleaned silicon wafer is subjected to spin coating, photolithography, development, and etching of the oxide layer in the window area to complete the patterning of the silicon window array. (4) Patterning of the top layer chip array electrodes: Continue the steps of spin coating-pre-baking-photolithography-development, deposit metal, and then peel off the remaining metal except for the electrode pattern. After cleaning, the complete electrode pattern is obtained. (5) Fabrication of multidimensional composite metasurface of top chip: Two-dimensional metal nanostrip metasurface is obtained by electron beam lithography; using the two-dimensional metal nanostrip metasurface as a mask, silicon is then etched by ICP to prepare a three-dimensional silicon nanostrip metasurface; patterned platinum diselenide is prepared in the patterned silicon window of the top chip array to finally obtain a multidimensional composite metasurface. (6) Fabricate a readout integrated circuit module for the underlying chip, which consists of a digital control module and an analog module; (7) Fabrication of the chip stacked readout integrated module: The readout integrated circuit module of the bottom chip is stacked and flip-bonded with the silicon and silicon through-hole metal interconnect pillars of the top chip to form the chip stacked readout integrated module.

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