Semiconductor structure and method of forming the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SWAYSURE TECHNOLOGY CO LTD
- Filing Date
- 2026-06-08
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies struggle to efficiently and cost-effectively form vias with a top-wide, bottom-narrow profile, leading to difficulties in controlling the etching profile and impacting the reliability of bonding pads and electrical connections.
Fluorine-containing etching gas is used to generate etching reaction deposits during the etching process of the etching reaction layer. The lateral etching rate is controlled during the etching process, and anisotropic etching is used to form upper and lower openings with different sidewall slopes. This ensures that the upper opening is larger than the lower opening, forming a through-hole structure that is wider at the top and narrower at the bottom.
This technology enables efficient and low-cost formation of vias with a top-wide and bottom-narrow shape, ensuring reliable physical contact and electrical connection of bonding pads, improving bonding strength, and reducing process costs.
Smart Images
Figure CN122349356A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the continuous improvement of semiconductor device integration, 3D (three-dimensional) stacking technology has become a key development direction for realizing high-performance, high-density integrated circuits. In a 3D stacked structure, multiple wafers are interconnected vertically via bonding pads. To meet interconnection requirements, bonding pads typically require a large top opening size to ensure reliable physical contact and electrical connection; while the bottom of the bonding pad is formed as a smaller via-like structure to connect to small metal lines or small device areas on the underlying layer. This top-wide, bottom-narrow shape requirement makes precise control of the etching profile a core challenge in process implementation. Summary of the Invention
[0003] This disclosure provides a semiconductor structure and a method for forming the same, which is advantageous for efficiently and cost-effectively forming vias with a top-wide and bottom-narrow shape.
[0004] To address the aforementioned problems, this disclosure provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein an interconnect layer is formed in the substrate and the top surface of the interconnect layer is exposed; forming an etching reaction layer covering the substrate; forming a layer to be etched covering the etching reaction layer; performing anisotropic etching on the layer to be etched and the etching reaction layer above the interconnect layer to form a via exposing the interconnect layer, wherein the via is composed of an upper opening and a lower opening with continuous sidewalls, the slope of the sidewall of the lower opening is less than the slope of the sidewall of the upper opening, such that the bottom dimension of the upper opening is larger than the bottom dimension of the lower opening, wherein the etching gas used in the etching process generates etching reaction deposits during the etching of the etching reaction layer, the material of the etching reaction layer includes metal oxide, and the etching gas used in the etching process includes a fluorine-containing etching gas.
[0005] Optionally, the thickness of the etched reactive layer is 10 nm to 100 nm.
[0006] Optionally, the metal oxide used in the etching reaction layer includes Al2O3 or a high dielectric constant material; the etching gas includes C. n F m Or C x H y F z Etching gas, where n, m, x, y, and z are all positive integers.
[0007] Optionally, the etching process includes: performing a first etching on the layer to be etched until the etching reaction layer is exposed; performing one or more etching cycles on the exposed etching reaction layer, wherein the etching cycle includes: performing a second etching on the exposed etching reaction layer, and the etching gas used in the second etching generates the etching reaction deposit during the etching process of the etching reaction layer; and cleaning the bottom and sidewalls of the via, wherein the gas used in the cleaning process can react with the etching reaction deposit, so that the cleaning process removes at least a portion of the etching reaction deposit.
[0008] Optionally, the cleaning process is plasma-assisted cleaning, and a bias voltage is applied during the plasma-assisted cleaning.
[0009] Optionally, the material of the layer to be etched includes silicon oxide or silicon nitride, and the etching gas used for the first and second etching is the same.
[0010] Optionally, the material of the etching reaction deposit includes AlF3 or HfF4, and the gas used in the cleaning process includes a mixture of Cl2 and O2 or a mixture of Cl2, O2 and BCl3.
[0011] Optionally, the angle between the sidewall of the lower opening and the horizontal direction outside the through hole is 30° to 90°; the angle between the sidewall of the upper opening and the horizontal direction outside the through hole is 50° to 90°.
[0012] Optionally, in the etching cycle process, the time percentage of the cleaning process is increased to increase the slope of the sidewall of the lower opening; or, in the etching cycle process, the time percentage of the cleaning process is decreased to decrease the slope of the sidewall of the lower opening.
[0013] Optionally, the forming method further includes: filling the vias to form an interconnect via structure electrically connected to the interconnect layer.
[0014] This disclosure also provides a semiconductor structure, including: a substrate, an interconnect layer formed therein, and the top surface of the interconnect layer exposed on the substrate; an etching reaction layer located on the substrate; a layer to be etched located on the etching reaction layer; and a via penetrating the layer to be etched and the etching reaction layer above the interconnect layer, the via exposing the interconnect layer, and the via being composed of an upper opening and a lower opening with continuous sidewalls, the sidewall slope of the lower opening being less than the sidewall slope of the upper opening, such that the bottom dimension of the upper opening is larger than the bottom dimension of the lower opening, wherein the material of the etching reaction layer can react with the etching gas forming the via to produce an etching reaction deposit.
[0015] Optionally, the material of the first material layer includes a metal oxide.
[0016] Optionally, the etching gas includes a fluorine-containing etching gas.
[0017] Optionally, the metal oxide used in the first material layer includes Al2O3 or a material with a high dielectric constant.
[0018] Optionally, the angle between the sidewall of the lower opening and the horizontal direction outside the through hole is 30° to 90°; the angle between the sidewall of the upper opening and the horizontal direction outside the through hole is 50° to 90°.
[0019] Optionally, the thickness of the first material layer is 10 nm to 100 nm.
[0020] Optionally, the semiconductor structure further includes: an interconnect via structure that fills the via and is electrically connected to the interconnect layer.
[0021] Optionally, the junction of the upper opening and the lower opening is located in the second material layer.
[0022] Compared with the prior art, the technical solution of the present disclosure has the following advantages: In the formation method provided in this embodiment, the etching gas used in the etching process generates etching reaction deposits during the etching of the etching reaction layer. Therefore, during the top-to-bottom etching process to form a via, no etching reaction deposits are generated when etching the layer to be etched. The lateral etching proceeds normally, resulting in an upper opening with a large sidewall slope. When etching reaches the etching reaction layer, etching reaction deposits are generated on the bottom sidewall of the via, obstructing the lateral etching and reducing the lateral etching rate. As the vertical etching continues, etching reaction deposits continue to accumulate on the bottom sidewall of the via. Therefore, the closer to the bottom of the via, the slower the lateral etching rate, and the corresponding lateral size of the via gradually decreases. This allows for the formation of a lower opening with a smaller sidewall slope. The sidewalls of the upper and lower openings are continuous, making the sidewall slope of the lower opening smaller than that of the upper opening. This results in the bottom size of the upper opening being larger than the bottom size of the lower opening, creating a top-wide and bottom-narrow shape. In other words, this makes the upper... The opening has a large size to ensure reliable physical contact and electrical connection of the interconnect via structure formed in the upper opening. It also ensures a large contact surface when the top of the interconnect via structure formed in the upper opening is bonded, improving the bonding strength. At the same time, the bottom of the lower opening has a small size, making the bottom size of the interconnect via structure formed in the lower opening smaller. This facilitates contact and electrical connection with the small interconnect layer below the via, and minimizes the possibility of the interconnect via structure being too large and misconnected to other interconnect layers. This results in an interconnect via structure that is wider at the top and narrower at the bottom. While ensuring precise electrical connection between the interconnect via structure and the small interconnect layer, it also ensures good electrical connection performance (e.g., low resistance). Furthermore, the larger upper opening and smaller lower opening of the via can be formed in one etching step, resulting in high process efficiency and reducing process costs. This allows for the efficient and low-cost formation of vias with a wider upper opening and narrower lower opening. Attached Figure Description
[0023] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure. Figures 6 to 7 This is a schematic diagram of the structure corresponding to each step in another method of forming a semiconductor structure; Figures 8 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure disclosed herein; Figure 13 This is a schematic diagram of one embodiment of the semiconductor structure disclosed herein. Detailed Implementation
[0024] As is known from the background technology, it is currently difficult to efficiently and cost-effectively form vias with a top-wide, bottom-narrow top profile. This paper analyzes the reasons why it is difficult to efficiently and cost-effectively form vias with a top-wide, bottom-narrow top profile using a semiconductor structure formation method.
[0025] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0026] refer to Figure 1 A substrate 10 is provided, an interconnect layer 11 is embedded in the substrate 10, the surface of the interconnect layer 11 is exposed on the substrate 10, and an etchable layer 30 is formed on the substrate 10 covering the substrate 10.
[0027] refer to Figure 2 A first via 12 is formed, penetrating the layer to be etched 30 and exposing the surface of the interconnect layer 11.
[0028] First, a first through-hole 12 with a smaller opening size is formed to expose the interconnect layer 11 more accurately.
[0029] refer to Figure 3 The first through hole 12 is filled to form a filling layer 13.
[0030] The first through-hole 12 is filled in preparation for the subsequent second etching.
[0031] refer to Figure 4 The etchable layer 30 and the fill layer 13 are patterned, and a portion of the thickness of the etchable layer 30 and the fill layer 13 is removed to form a second through hole 14 with an opening size larger than the first through hole 12.
[0032] refer to Figure 5 Remove the remaining filling layer 13 in the first through hole 12 to form a through hole 15 that exposes the surface of the interconnect layer 11, which is composed of the first through hole 12 and the second through hole 14.
[0033] To form the through-hole 15, which is wider at the top and narrower at the bottom, a dual damascus etching method is usually used, which requires multiple etching steps, resulting in higher process costs, a more complex process flow, and lower process efficiency.
[0034] Figures 6 to 7 This is a schematic diagram of the structure corresponding to each step in another method for forming a semiconductor structure.
[0035] refer to Figure 6 A substrate 10 is provided, an interconnect layer 11 is embedded in the substrate 10, the surface of the interconnect layer 11 is exposed on the substrate 10, an etchable layer 30 is formed on the substrate 10 covering the substrate 10, a mask layer 40 is formed on the etchable layer 30, and a mask opening is formed in the mask layer 40 to expose the etchable layer 30.
[0036] refer toFigure 7 Pattern the layer to be etched 30 along the mask opening to form vias 15 that expose the surface of the interconnect layer 11.
[0037] If the contact points of the interconnect layer 11 are small and the mask opening above is large, that is, the sidewall profile of the via 15 needs to be too taper, it will cause too much polymer to accumulate at the bottom of the via 15 when etching the layer to be etched 30. This will result in a small opening size at the bottom of the via 15, or even the via being closed by the polymer, thus failing to expose the interconnect layer 11.
[0038] To address the aforementioned technical problems, this disclosure provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein an interconnect layer is formed in the substrate and the top surface of the interconnect layer is exposed; forming an etching reaction layer covering the substrate; forming a layer to be etched covering the etching reaction layer; performing anisotropic etching on the layer to be etched and the etching reaction layer above the interconnect layer to form a via exposing the interconnect layer, wherein the via is composed of an upper opening and a lower opening with continuous sidewalls, the sidewall slope of the lower opening is less than the sidewall slope of the upper opening, such that the bottom dimension of the upper opening is larger than the bottom dimension of the lower opening, wherein the etching gas used in the etching process generates etching reaction deposits during the etching of the etching reaction layer.
[0039] In this embodiment, the etching gas used in the etching process generates etching reaction deposits during the etching of the etching reaction layer. Therefore, during the top-to-bottom etching process to form a via, no etching reaction deposits are generated when etching the layer to be etched. The lateral etching proceeds normally, resulting in an upper opening with a relatively large sidewall slope. When etching reaches the etching reaction layer, etching reaction deposits are generated on the bottom sidewall of the via, obstructing the lateral etching and reducing the lateral etching rate. As the vertical etching continues, etching reaction deposits continue to accumulate on the bottom sidewall of the via. Therefore, the closer to the bottom of the via, the slower the lateral etching rate, and the lateral size of the via gradually decreases. This allows for the formation of a lower opening with a smaller sidewall slope. The sidewalls of the upper and lower openings are continuous, ensuring that the sidewall slope of the lower opening is less than that of the upper opening. This results in a larger bottom size for the upper opening than the lower opening, creating a top-wide and bottom-narrow shape. In other words, this gives the upper opening a... A larger opening size ensures reliable physical contact and electrical connection for the interconnect via structure formed in the upper opening, and provides a larger contact surface for bonding at the top of the interconnect via structure formed in the upper opening, improving bonding strength. At the same time, it allows for a smaller opening size at the bottom of the lower opening, making it easier for the interconnect via structure formed in the lower opening to contact and connect with the small interconnect layer below the via for electrical connection. It also minimizes the possibility of the interconnect via structure being too large at the bottom and being misconnected to other interconnect layers. This results in an interconnect via structure that is wider at the top and narrower at the bottom. While ensuring precise electrical connection between the interconnect via structure and the small interconnect layer, it also ensures good electrical connection performance (e.g., low resistance). Furthermore, the larger upper opening and smaller lower opening of the via can be formed in one etching step, resulting in high process efficiency and reducing process costs. This allows for the efficient and low-cost formation of vias with a wider upper opening and narrower lower opening.
[0040] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0041] Figures 8 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure fabrication method disclosed herein.
[0042] refer to Figure 8 A substrate 100 is provided, an interconnect layer 110 is formed in the substrate 100, and the top surface of the interconnect layer 110 is exposed on the substrate 100.
[0043] The substrate 100 is used to provide the basis for process operations in the fabrication of semiconductor structures.
[0044] In some embodiments, an interconnect layer 110 is formed in the substrate 100, and the top surface of the interconnect layer 110 is exposed in the substrate 100.
[0045] Interconnect layer 110 is used for external electrical connection to implement basic circuitry. The substrate 100 exposes the surface of interconnect layer 110 so that interconnect layer 110 can achieve electrical connection with the outside through the exposed surface of substrate 100.
[0046] In some embodiments, the interconnect layer 110 is made of a metallic material.
[0047] As an example, in some embodiments, interconnect layer 110 is a bottom metal layer with a small lateral dimension.
[0048] As an example, in some embodiments, interconnect layer 110 includes conductive contacts or conductive wiring.
[0049] Continue to refer to Figure 8 An etching reaction layer 200 is formed covering the substrate 100.
[0050] The etching reaction layer 200 is used to react with the etching gas during subsequent etching processes to produce reaction deposits.
[0051] In some embodiments, the material of the etching reaction layer 200 includes a metal oxide.
[0052] The material of the etching reaction layer 200 includes metal oxides. By subsequently selecting an etching gas, it is easy to react with the metal oxides to form a non-volatile substance that adheres to the bottom, thereby generating a reaction deposit.
[0053] Specifically, in some embodiments, the metal oxide used in the etching reaction layer 200 includes Al2O3 or a high-k material.
[0054] When metal oxides of Al2O3 or high-k dielectric materials (e.g., HfO2, ZrO2, etc.) react with specific etching gases (e.g., fluorine-containing gases), byproducts (e.g., AlF) are generated. x HfF x (etc.) can form non-volatile etching reaction deposits, achieving the formation of a bottom-narrowed opening. These etching reaction deposits can be removed by specific cleaning gases (e.g., chlorine-containing gases), thereby enabling the control of the amount of etching reaction deposits. This allows for controllable deposition rate of bottom etching reaction deposits, precisely assisting in the formation of the desired via profile.
[0055] As an example, in some embodiments, the high dielectric constant material used in the etching reaction layer 200 includes any one of HfO2, ZrO2, Ta2O5, TiO2, La2O3, and Y2O3.
[0056] In some embodiments, the thickness of the etch reaction layer 200 is 10 nm to 100 nm.
[0057] The thickness of the etching reaction layer 200 is 10 nm to 100 nm, which ensures that the etching reaction layer 200 has sufficient thickness to react sufficiently with the etching gas during subsequent etching processes, forming sufficient reaction deposits. At the same time, it ensures that the etching reaction layer 200 is not too thick, providing sufficient space for the formation of the upper etchable layer, so that a sufficiently deep upper opening can be formed during subsequent etching processes, and that too many reaction deposits are not generated during etching of the etching reaction layer 200, thereby avoiding the situation where the bottom of the via is blocked by too many reaction deposits.
[0058] Continue to refer to Figure 8 This forms an etchable layer 300 covering the etch reaction layer 200.
[0059] The etched layer 300 serves as a platform for subsequent through-hole formation processes.
[0060] In some embodiments, the material of the layer 300 to be etched includes silicon oxide or silicon nitride.
[0061] If the material of the layer to be etched 300 includes silicon oxide or silicon nitride, then in the subsequent etching process, by selecting the etching gas that reacts with the etching reaction layer 200, no extra reactants will be generated with the layer to be etched 300. Moreover, after the vias that penetrate the layer to be etched 300 are formed, and the interconnect via structure is formed in the vias, the material of the layer to be etched 300, silicon oxide or silicon nitride, can also play an isolation role.
[0062] In some embodiments, a mask layer 400 is formed on the layer to be etched 300, and a mask opening 410 is formed in the mask layer 400 to expose the top surface of the layer to be etched 300.
[0063] The mask layer 400 is used as an etching mask for subsequent etching of the layer to be etched 300 and the etching reaction layer 200. Specifically, the layer to be etched 300 and the etching reaction layer 200 are subsequently etched along the mask opening 410.
[0064] It should be noted that the subsequently formed interconnect via structure needs to ensure reliable physical contact and electrical connection with the upper structure. Furthermore, when bonding is achieved at the top of the interconnect via structure, a large contact surface is required to improve bonding strength. Therefore, the mask opening 410 has a large lateral dimension (typically larger than the lateral dimension of the interconnect layer 110), resulting in a larger width in the upper half of the subsequently formed interconnect via structure. Specifically, the mask opening 410 corresponds to the size of the upper opening.
[0065] Reference Figures 9 to 11Anisotropic etching is performed on the layer 300 to be etched and the etching reaction layer 200 above the interconnect layer 110 to form a via 500 exposing the interconnect layer 110. The via 500 is composed of an upper opening 510 and a lower opening 520 with continuous sidewalls. The sidewall slope of the lower opening 520 is less than that of the upper opening 510, so that the bottom size of the upper opening 510 is larger than the bottom size of the lower opening 520. During the etching process, the etching gas used in the etching process generates etching reaction deposits 600.
[0066] The through-hole 500 is used to provide space for the subsequent formation of interconnect through-hole structures.
[0067] Among them, the slope of the sidewall of the lower opening 520 is less than the slope of the sidewall of the upper opening 510. The slope of the sidewall refers to the degree of inclination of the sidewall. The greater the slope, the closer the sidewall is to vertical, and thus the steeper it is. The smaller the slope, the closer the sidewall is to horizontal, and thus the gentler it is.
[0068] In some embodiments, during the etching process, the etching gas used in the etching process generates etching reaction deposits on the etching reaction layer 200. Therefore, during the etching process to form the via 500 from top to bottom, no etching reaction deposits 600 are generated when etching the layer to be etched 300, and the lateral etching proceeds normally, thus forming an upper opening 510 with a large sidewall slope. When etching reaches the etching reaction layer 200, etching reaction deposits 600 are generated on the bottom sidewall of the via 500, which somewhat obstructs the lateral etching, thus reducing the lateral etching rate. As longitudinal etching continues, the etching reaction deposits 600 continue to accumulate on the bottom sidewall of the via 500. Therefore, the closer to the bottom of the via 500, the slower the lateral etching rate, and the corresponding lateral dimension of the via 500 gradually decreases. This allows for the formation of a lower opening 520 with a smaller sidewall slope. The sidewalls of the upper opening 510 and lower opening 520 are continuous, resulting in a sidewall slope of the lower opening 520 that is smaller than that of the upper opening 510. Consequently, the bottom dimension of the upper opening 510 is larger than that of the lower opening 520, creating a top-wide and bottom-narrow shape. In other words, the upper opening 510 has a larger opening size to ensure reliable physical contact and electrical connection of the interconnect via structures subsequently formed in the upper opening 510, and to ensure a larger contact surface when the top of the interconnect via structures subsequently formed in the upper opening 510 is bonded, thereby improving the bonding strength. Simultaneously, the lower opening 520 has a smaller opening size at the bottom, making the bottom size of the interconnect via structures formed in the lower opening 520 smaller, facilitating contact and electrical connection with the small-sized interconnect layer 110 below the via 500, and minimizing... This avoids the situation where the bottom size of the interconnect via structure is too large and it is mistakenly connected to other interconnect layers 110. This allows for the formation of an interconnect via structure that is wider at the top and narrower at the bottom. While ensuring accurate electrical connection between the interconnect via structure and the small-sized interconnect layer, it also ensures good electrical connection performance (e.g., low resistance). Furthermore, the larger upper opening 510 and the smaller lower opening 520 of the via 500 can be formed in one etching step, resulting in high process efficiency and reduced process costs. This allows for the efficient and low-cost formation of the via 500 with a wider top and narrower bottom profile.
[0069] In some embodiments, the etching gas used in the etching process includes a fluorine-containing etching gas.
[0070] If the material of the etching reaction layer 200 is a metal oxide, the fluorine-containing etching gas can react with the metal oxide to produce non-volatile byproducts, thereby forming a reaction deposit.
[0071] Specifically, in some embodiments, the etching gas includes C n F m Or C x H y F zEtching gas, where n, m, x, y, and z are all positive integers.
[0072] Etching gases containing fluorine react with metal oxides to generate non-volatile metal fluoride byproducts, which then combine with polymers to form a stable reaction deposit at the bottom. This prevents the byproducts from completely volatilizing or over-reacting, thus inhibiting lateral etching. Simultaneously, the use of C... n F m Or C x H y F z Etching gases can flexibly balance the etching rate and polymer deposition by adjusting the fluorine-carbon ratio (F / C atomic ratio), resulting in a large process window. In addition, these etching gases have a high selectivity for photoresists, effectively protecting the mask layer 400. As a standard gas for etching dielectric materials, they are highly compatible with existing equipment and processes, and the industry is highly mature.
[0073] Specifically, refer to Figure 9 The etching process includes: performing a first etching on the layer to be etched 300 until the etching reaction layer 200 is exposed.
[0074] The first etching of the etch layer 300 is performed to basically form the shape of the opening 510 on the via 500 until the etching reaction layer 200 is exposed, which prepares for the subsequent reaction between the etching gas and the etching reaction layer 200. In this case, the first etching will not produce etching reaction deposits 600, so the lateral etching of the etch layer 300 is carried out normally. Thus, the first etching can first form the via 500 with a larger lateral size at the top.
[0075] refer to Figure 10 The exposed etch reaction layer 200 is subjected to one or more etching cycles. The etching cycle includes: a second etching of the exposed etch reaction layer 200, wherein the etching gas used in the second etching generates an etching reaction deposit 600 during the etching process of the etch reaction layer 200.
[0076] When the etching reaction layer 200 is exposed, the etching gas used in the second etching process reacts with the etching reaction layer 200 to produce etching reaction deposits 600, which adhere to the sidewall at the bottom of the via 500, thus inhibiting lateral etching to a certain extent.
[0077] It should be noted that although the etching gas of the second etching reacts with the etching reaction layer 200, the resulting etching reaction deposit 600 not only adheres to the etching reaction layer 200, but also adheres to the sidewall of the layer 300 to be etched at the bottom of the via 500. This reduces the lateral etching rate of the layer 300 to be etched, so that the lateral dimension of the via 500 gradually decreases from top to bottom at a depth near the bottom side.
[0078] Specifically, in some embodiments, the reaction between the etching gas of the second etching and the etching reaction layer 200 is as follows: HfO2 + 4F* → HfF4 + O2↑, Al2O3 + 6F* → 2AlF3 + 3 / 2 O2↑.
[0079] Accordingly, in some embodiments, the material of the etching reaction attachment 600 includes AlF3 or HfF4.
[0080] In some embodiments, the first etching and the second etching use the same etching gas.
[0081] The first and second etching can use the same etching gas, which is beneficial to improve etching efficiency, reduce process cost, and achieve the effect that no etching reaction deposit 600 is generated between the first etching and the etchable layer 300, and the etching reaction deposit 600 is generated between the second etching and the etch reaction layer 200.
[0082] refer to Figure 11 The etching cycle process also includes cleaning the bottom and sidewalls of the via 500, wherein the gas used for cleaning can react with the etching reaction deposits 600, thereby removing at least a portion of the etching reaction deposits 600.
[0083] The gas used in the cleaning process can react with the etching reaction deposits 600. By adding cleaning treatment to the etching cycle and adjusting the cleaning treatment parameters, the amount of etching reaction deposits 600 on the bottom and sidewalls of the via 500 can be adjusted, thereby regulating the lateral etching rate. This allows the cleaning treatment to optimize the distribution of the bottom etching reaction deposits 600, thereby adjusting the bottom morphology of the via 500. Furthermore, the cleaning treatment can reduce the amount of etching reaction deposits 600, which is beneficial for ensuring the smooth progress of the etching process that exposes the interconnect layer 110.
[0084] In some embodiments, the cleaning process is plasma-assisted cleaning, and a bias voltage is applied during plasma-assisted cleaning.
[0085] The cleaning process is plasma-assisted cleaning, in which a bias voltage is applied, and the etching reaction deposits 600 are deposited on the upward-sloping surface (bottom and lower sidewall of the via 500). The bias voltage can directionally accelerate the ions in the plasma, thereby improving the removal efficiency of the etching reaction deposits 600 on the upward-sloping surface. At the same time, the ion bombardment energy and direction can be controlled, which can reduce the damage to the sidewall of the via 500 and achieve a balance between efficient cleaning and low damage.
[0086] In some embodiments, the gas used for cleaning includes a mixture of Cl2 and O2 or a mixture of Cl2, O2 and BCl3.
[0087] A mixture of Cl2 and O2 or a mixture of Cl2, O2 and BCl3 can react with the etching reaction deposit 600 to form a substance that is easy to remove, thereby removing the etching reaction deposit 600.
[0088] Specifically, in some embodiments, the cleaning process uses a mixture of Cl2, O2, and BCl3, with BCl3 capable of removing AlF3 or HfF4 by plasma-assisted bombardment.
[0089] In some embodiments, increasing the time percentage of the cleaning process in the etching cycle process can increase the amount of etching reaction deposits 600 removed, resulting in less suppression of lateral etching. This prevents the lateral etching rate from decreasing too much, thereby increasing the slope of the sidewall of the lower opening 520, i.e., making the sidewall morphology of the lower opening 520 steeper.
[0090] In some embodiments, reducing the time ratio of the cleaning process in the etching cycle process can reduce the amount of etching reaction deposits 600 removed, thereby greatly suppressing lateral etching and reducing the lateral etching rate, which in turn reduces the slope of the sidewall of the lower opening 520, i.e., the sidewall morphology of the lower opening 520 is more gentle.
[0091] In other words, in the etching cycle process, the sidewall slope of the lower opening 520 can be adjusted by adjusting the proportion of the cleaning process time to the total cleaning process and the second etching time.
[0092] In some embodiments, the angle α between the sidewall of the lower opening 520 and the horizontal direction located outside the through hole 500 is 30° to 90°; the angle β between the sidewall of the upper opening 510 and the horizontal direction located outside the through hole 500 is 50° to 90°.
[0093] In the first etching, the etching gas does not produce etching reaction deposits 600 with the layer to be etched 300, so the lateral etching of the layer to be etched 300 proceeds normally. However, during the vertical downward etching process, the lateral etching slows down as the etching progresses, resulting in some tilt on the sidewall of the upper opening 510. However, the overall tilt is not too large, so the angle β between the sidewall of the upper opening 510 and the horizontal direction outside the via 500 is 50° to 90°. In the second etching, the etching gas reacts with the etching reaction layer 200, producing etching reaction deposits 600 on the bottom sidewall of the via 500. The adhering material 600 obstructs the lateral etching, thus reducing the lateral etching rate. As the longitudinal etching continues, the etching reaction adhering material 600 continues to accumulate on the bottom sidewall of the via 500. Therefore, the closer to the bottom of the via 500, the slower the lateral etching rate becomes, and the lateral dimension of the via 500 gradually decreases. This allows for the formation of a lower opening 520 with a smaller sidewall slope. Furthermore, by adding a cleaning process, the sidewall slope of the lower opening 520 can be adjusted, so that the angle α between the sidewall of the lower opening 520 and the horizontal direction located outside the via 500 is 30° to 90°.
[0094] It should be noted that, since the etching reaction deposit 600 is attached to the sidewall at the bottom of the through hole 500, it has a certain inhibitory effect on the transverse etching, so that the junction of the upper opening 510 and the lower opening 520 can be located in the layer 300 to be etched.
[0095] refer to Figure 12 The method of forming also includes: filling the via 500 to form an interconnect via structure 700 that is electrically connected to the interconnect layer 110.
[0096] The interconnect via structure 700 is used for electrical connection to the interconnect layer 110 and subsequently to structures above the interconnect via structure 700 (e.g., bonding pads) to achieve vertical electrical connection. The interconnect via structure 700 is made of conductive materials, such as copper or tungsten.
[0097] Specifically, the via 500 has a shape that is wider at the top and narrower at the bottom, and the corresponding interconnect via structure 700 also has a shape that is wider at the top and narrower at the bottom. This allows the interconnect via structure 700 in the upper opening 510 to make reliable physical contact and electrical connection, and ensures that when the top of the interconnect via structure 700 in the upper opening 510 is bonded, it has a large contact surface, which improves the bonding strength. At the same time, it makes the bottom size of the interconnect via structure 700 in the lower opening 520 smaller, which makes it easier to contact and connect with the small interconnect layer 110 below the via 500 for electrical connection, and avoids the situation where the bottom size of the interconnect via structure 700 is too large and is mistakenly connected to other interconnect layers 110.
[0098] Specifically, in some embodiments, before filling the via 500 to form the interconnect via structure 700 electrically connected to the interconnect layer 110, the method further includes removing the mask layer 400.
[0099] Figure 12 This is a schematic diagram of one embodiment of the semiconductor structure disclosed herein.
[0100] refer to Figure 12 The semiconductor structure includes: a substrate 100, an interconnect layer 110 formed therein, and the top surface of the interconnect layer 110 exposed on the substrate 100; a first material layer 201 on the substrate 100; a second material layer 301 on the first material layer 201; and a via 500 penetrating the first material layer 201 and the second material layer 301 above the interconnect layer 110, the via 500 exposing the interconnect layer 110, and the via 500 being composed of an upper opening 510 and a lower opening 520 with continuous sidewalls, the sidewall slope of the lower opening 520 being less than the sidewall slope of the upper opening 510, such that the bottom dimension of the upper opening 510 is larger than the bottom dimension of the lower opening 520, wherein the material of the first material layer 201 can react with the etching gas that etches the first material layer 201 when forming the via 500 to produce an etching reaction deposit.
[0101] The substrate 100 is used to provide the basis for process operations in the fabrication of semiconductor structures.
[0102] In some embodiments, an interconnect layer 110 is formed in the substrate 100, and the top surface of the interconnect layer 110 is exposed in the substrate 100.
[0103] Interconnect layer 110 is used for external electrical connection to implement basic circuitry. The substrate 100 exposes the surface of interconnect layer 110 so that interconnect layer 110 can achieve electrical connection with the outside through the exposed surface of substrate 100.
[0104] In some embodiments, the interconnect layer 110 is made of a metallic material.
[0105] As an example, in some embodiments, interconnect layer 110 is a bottom metal layer with a small lateral dimension.
[0106] The first material layer 201 is used to react with the etching gas used to etch the first material layer 201 during the etching process to produce a reaction deposit.
[0107] In some embodiments, the material of the first material layer 201 includes a metal oxide.
[0108] The material of the first material layer 201 includes metal oxides. A specific etching gas readily reacts with the metal oxides to form a non-volatile substance that adheres to the bottom, thereby generating a reactive deposit.
[0109] Specifically, in some embodiments, the metal oxide used in the first material layer 201 includes Al2O3 or a high-k material.
[0110] When metal oxides of Al2O3 or high-k dielectric materials (e.g., HfO2, ZrO2, etc.) react with specific etching gases (e.g., fluorine-containing gases), byproducts (e.g., AlF) are generated. x HfF x (etc.) can form non-volatile etching reaction deposits, achieving the formation of a bottom-narrowed opening. These etching reaction deposits can be removed by specific cleaning gases (e.g., chlorine-containing gases), thereby enabling the control of the amount of etching reaction deposits. This allows for controllable deposition rate of bottom etching reaction deposits, precisely assisting in the formation of the desired via profile.
[0111] As an example, in some embodiments, the high dielectric constant material used in the first material layer 201 includes any one of HfO2, ZrO2, Ta2O5, TiO2, La2O3, and Y2O3.
[0112] In some embodiments, the thickness of the first material layer 201 is 10 nm to 100 nm.
[0113] The thickness of the first material layer 201 is 10 nm to 100 nm, which ensures that the first material layer 201 has sufficient thickness to react sufficiently with the etching gas during the etching process to form sufficient reactive deposits. At the same time, it ensures that the first material layer 201 is not too thick, providing sufficient space for the formation of the upper second material layer. This allows for the formation of a sufficiently deep upper opening during the etching process, and prevents the generation of excessive reactive deposits when etching the first material layer 201, thereby avoiding the situation where the bottom of the via is blocked by excessive reactive deposits.
[0114] The second material layer 301 serves as a platform for subsequent processes to form through holes.
[0115] In some embodiments, the material of the second material layer 301 includes silicon oxide or silicon nitride.
[0116] The material of the second material layer 301 includes silicon oxide or silicon nitride. In the subsequent etching process, by selecting the etching gas that reacts with the etching reaction layer 200, no extra reactants will be generated with the second material layer 301. Moreover, after the vias that penetrate the second material layer 301 are formed, and the interconnect via structure is formed in the vias, the material of the second material layer 301, which is silicon oxide or silicon nitride, can also play an isolation role.
[0117] Through-hole 500 is used to provide spatial location for interconnect via structures.
[0118] Among them, the slope of the sidewall of the lower opening 520 is less than the slope of the sidewall of the upper opening 510. The slope of the sidewall refers to the degree of inclination of the sidewall. The greater the slope, the closer the sidewall is to vertical, and thus the steeper it is. The smaller the slope, the closer the sidewall is to horizontal, and thus the gentler it is.
[0119] In some embodiments, during the etching process, the etching gas used in the etching process generates etching reaction deposits on the first material layer 201. Therefore, during the etching process to form the via 500 from top to bottom, no etching reaction deposits are generated when etching the second material layer 301, and the lateral etching proceeds normally, thus forming an upper opening 510 with a large sidewall slope. When etching reaches the first material layer 201, etching reaction deposits are generated on the bottom sidewall of the via 500, which somewhat obstructs the lateral etching, thus reducing the lateral etching rate. As the longitudinal etching rate increases... As etching continues, etching residue accumulates on the bottom sidewall of the via 500. Therefore, the closer to the bottom of the via 500, the slower the lateral etching rate, and the smaller the lateral dimension of the via 500 becomes. This results in a lower opening 520 with a smaller sidewall slope, and continuous sidewalls between the upper and lower openings 510. Consequently, the sidewall slope of the lower opening 520 is smaller than that of the upper opening 510, making the bottom dimension of the upper opening 510 larger than that of the lower opening 520, creating a top-wide, bottom-narrow shape. The upper opening 510 has a large opening size to ensure reliable physical contact and electrical connection of the interconnect via structure subsequently formed in the upper opening 510. It also ensures a large contact surface when the top of the interconnect via structure subsequently formed in the upper opening 510 is bonded, thereby improving the bonding strength. At the same time, the lower opening 520 has a small opening size at the bottom, making the bottom size of the interconnect via structure formed in the lower opening 520 smaller. This facilitates contact and electrical connection with the small-sized interconnect layer 110 below the via 500, and minimizes the possibility of the interconnect via structure being too large at the bottom and being misconnected to other interconnect layers 110. This results in an interconnect via structure that is wider at the top and narrower at the bottom. While ensuring precise electrical connection between the interconnect via structure and the small-sized interconnect layer, it also ensures good electrical connection performance (e.g., low resistance) of the interconnect via structure. Furthermore, the larger upper opening 510 and the smaller lower opening 520 of the via 500 can be formed in one etching step, resulting in high process efficiency and reducing process costs. This allows for the efficient and low-cost formation of the via 500 with a wider upper opening and narrower lower opening.
[0120] In some embodiments, the etching gas used in the etching process includes a fluorine-containing etching gas.
[0121] If the material of the first material layer 201 is a metal oxide, the fluorine-containing etching gas can react with the metal oxide to produce non-volatile byproducts, thereby forming a reaction deposit.
[0122] In some embodiments, the angle α between the sidewall of the lower opening 520 and the horizontal direction located outside the through hole 500 is 30° to 90°; the angle β between the sidewall of the upper opening 510 and the horizontal direction located outside the through hole 500 is 50° to 90°.
[0123] During the etching of the second material layer 301, the etching gas does not produce etching reaction deposits with the second material layer 301, so the lateral etching of the second material layer 301 proceeds normally. However, during the vertical downward etching process, the lateral etching slows down as the etching progresses, resulting in some tilting of the sidewall of the upper opening 510. However, the overall tilt is not too large, so the angle β between the sidewall of the upper opening 510 and the horizontal direction outside the via 500 is 50° to 90°. During the etching of the first material layer 201, the etching gas reacts with the first material layer 201, and in the via 500... The formation of etching reaction deposits on the bottom sidewalls obstructs lateral etching, thus reducing the lateral etching rate. As longitudinal etching continues, the etching reaction deposits continue to accumulate on the bottom sidewalls of the via 500. Therefore, the closer to the bottom of the via 500, the slower the lateral etching rate becomes, and the lateral dimension of the via 500 gradually decreases. This allows for the formation of a lower opening 520 with a smaller sidewall slope. Furthermore, by incorporating a cleaning process, the sidewall slope of the lower opening 520 can be adjusted, resulting in an angle α between the sidewall of the lower opening 520 and the horizontal direction located outside the via 500, ranging from 30° to 90°.
[0124] Since the etching reaction deposit 600 is attached to the sidewall at the bottom of the through hole 500, it has a certain inhibitory effect on lateral etching, so that the junction of the upper opening 510 and the lower opening 520 can be located in the second material layer 301.
[0125] In some embodiments, the semiconductor structure further includes an interconnect via structure 700 that is filled in the via 500 and electrically connected to the interconnect layer 110.
[0126] The interconnect via structure 700 is used for electrical connection to the interconnect layer 110 and subsequently to structures above the interconnect via structure 700 (e.g., bonding pads) to achieve vertical electrical connection. The interconnect via structure 700 is made of conductive materials, such as copper or tungsten.
[0127] Specifically, the via 500 has a shape that is wider at the top and narrower at the bottom, and the corresponding interconnect via structure 700 also has a shape that is wider at the top and narrower at the bottom. This allows the interconnect via structure 700 in the upper opening 510 to make reliable physical contact and electrical connection, and ensures that when the top of the interconnect via structure 700 in the upper opening 510 is bonded, it has a large contact surface, which improves the bonding strength. At the same time, it makes the bottom size of the interconnect via structure 700 in the lower opening 520 smaller, which makes it easier to contact and connect with the small interconnect layer 110 below the via 500 for electrical connection, and avoids the situation where the bottom size of the interconnect via structure 700 is too large and is mistakenly connected to other interconnect layers 110.
[0128] It should be noted that the semiconductor structure in this embodiment can be formed using the formation method of the aforementioned embodiment, or it can be formed using other methods.
[0129] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided in which an interconnect layer is formed, and the substrate exposes the top surface of the interconnect layer; An etching reaction layer is formed covering the substrate; Forming a layer to be etched covering the etching reaction layer; Anisotropic etching is performed on the layer to be etched and the etching reaction layer above the interconnect layer to form a via exposing the interconnect layer. The via consists of an upper opening and a lower opening with continuous sidewalls. The sidewall slope of the lower opening is less than that of the upper opening, such that the bottom dimension of the upper opening is larger than that of the lower opening. During the etching process, the etching gas used in the etching process generates etching reaction deposits. The material of the etching reaction layer includes metal oxides, and the etching gas used in the etching process includes a fluorine-containing etching gas.
2. The forming method as described in claim 1, characterized in that, The thickness of the etched reaction layer is 10 nm to 100 nm.
3. The forming method as described in claim 1, characterized in that, The metal oxide used in the etching reaction layer includes Al2O3 or a high dielectric constant material; The etching gas includes C n F m Or C x H y F z Etching gas, where n, m, x, y, and z are all positive integers.
4. The forming method as described in claim 3, characterized in that, The etching process includes: performing a first etching on the layer to be etched until the etching reaction layer is exposed; The exposed etch reaction layer is subjected to one or more etching cycles, the etching cycle process including: a second etching of the exposed etch reaction layer, wherein the etching gas used in the second etching generates the etching reaction deposit during the etching process of the etch reaction layer; The bottom and sidewalls of the through hole are cleaned using a gas that reacts with the etching reaction deposits, thereby removing at least a portion of the etching reaction deposits.
5. The forming method as described in claim 4, characterized in that, The cleaning process is plasma-assisted cleaning, and a bias voltage is applied during the plasma-assisted cleaning.
6. The forming method as described in claim 4, characterized in that, The material of the layer to be etched includes silicon oxide or silicon nitride, and the etching gas used for the first and second etching is the same.
7. The forming method as described in claim 4, characterized in that, The material of the etching reaction deposit includes AlF3 or HfF4, and the gas used in the cleaning process includes a mixture of Cl2 and O2 or a mixture of Cl2, O2 and BCl3.
8. The forming method as described in claim 7, characterized in that, The angle between the sidewall of the lower opening and the horizontal direction outside the through hole is 30° to 90°; the angle between the sidewall of the upper opening and the horizontal direction outside the through hole is 50° to 90°.
9. The forming method as described in claim 4, characterized in that, In the etching cycle process, the time percentage of the cleaning process is increased, which increases the slope of the sidewall of the lower opening. or, In the etching cycle process, the time ratio of the cleaning process is reduced, thereby reducing the slope of the sidewall of the lower opening.
10. The forming method according to claim 1, characterized in that, The forming method further includes: filling the vias to form an interconnect via structure electrically connected to the interconnect layer.
11. A semiconductor structure, characterized in that, include: A substrate in which an interconnect layer is formed, and the substrate exposes the top surface of the interconnect layer; The first material layer located on the substrate; A second material layer located on top of the first material layer; A via is formed through a first material layer and a second material layer above the interconnect layer, the via exposing the interconnect layer, and the via is formed by an upper opening and a lower opening with continuous sidewalls. The sidewall slope of the lower opening is less than that of the upper opening, such that the bottom size of the upper opening is larger than that of the lower opening. The material of the first material layer can react with the etching gas that etches the first material layer when the via is formed, producing an etching reaction deposit.
12. The semiconductor structure as claimed in claim 11, characterized in that, The material of the first material layer includes metal oxides.
13. The semiconductor structure as described in claim 12, characterized in that, The etching gas includes fluorine-containing etching gas.
14. The semiconductor structure as claimed in claim 12, characterized in that, The metal oxide used in the first material layer includes Al2O3 or a material with a high dielectric constant.
15. The semiconductor structure as described in claim 14, characterized in that, The angle between the sidewall of the lower opening and the horizontal direction outside the through hole is 30° to 90°; the angle between the sidewall of the upper opening and the horizontal direction outside the through hole is 50° to 90°.
16. The semiconductor structure as claimed in claim 11, characterized in that, The thickness of the first material layer is 10 nm to 100 nm.
17. The semiconductor structure as claimed in claim 11, characterized in that, The semiconductor structure further includes: an interconnect via structure that fills the via and is electrically connected to the interconnect layer.
18. The semiconductor structure as claimed in claim 11, characterized in that, The junction between the upper opening and the lower opening is located in the second material layer.