A processor hardware acceleration control system based on event dataflow networks

By combining event data stream networks and pipelined DMA modules, automated data transfer and computation processing of microcontroller peripheral modules are achieved, solving the problems of CPU resource consumption and insufficient real-time performance in traditional microcontrollers, and improving the real-time performance and computational efficiency of the system.

CN122363829APending Publication Date: 2026-07-10NANNING TAICHUANG XINKE INTELLIGENT TECH CO LTD
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Patent Information

Authority / Receiving Office
CN ยท China
Patent Type
Applications(China)
Current Assignee / Owner
NANNING TAICHUANG XINKE INTELLIGENT TECH CO LTD
Filing Date
2026-03-18
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

In traditional microcontrollers, the collaborative work between peripherals heavily relies on the CPU, resulting in a large consumption of CPU resources, difficulty in meeting real-time requirements, and difficulty in achieving parallel computing.

Method used

A processor hardware acceleration control system based on event data flow network is adopted. The system realizes automated data transfer and processing between peripheral modules through event flow network and pipelined DMA module, and constructs a mapping relationship between peripheral module trigger event source and data transfer task to reduce CPU intervention.

Benefits of technology

It enables programmable intelligent collaborative operation of peripheral modules at the hardware level, improving the system's real-time performance and computing efficiency, reducing the CPU burden, and is suitable for digital power supply and motor control systems.

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Abstract

This invention discloses a processor hardware acceleration control system based on an event data stream network, relating to the field of embedded microcontrollers. The system includes: multiple peripheral modules; an event stream network comprising multiple hardware-level event transmission channels for event triggering and data stream routing among the peripheral modules; and a pipelined DMA module connected to the event data stream network, used to automatically execute data transfer operations from a first peripheral module to a second peripheral module based on pre-stored index information after receiving an event trigger signal, and to trigger the second peripheral module to perform functional operations based on the received data via the event stream network upon completion. The index information represents the mapping relationship between the trigger event source of each peripheral module and the corresponding data transfer task. This invention solves the technical problem in the prior art where the CPU's execution of trivial peripheral tasks leads to excessive CPU resource consumption and difficulty in meeting real-time performance requirements.
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