A parallel mpwm modulation method for 3x harmonic elimination

Abstract

The application discloses a parallel MPWM modulation method of 3X harmonic elimination, and relates to the technical field of wireless communication.The method comprises the following steps: based on the principle of harmonic elimination, input baseband signals are decomposed into four phase-controlled baseband modulation signals; the baseband modulation signals are subjected to digital up-conversion to obtain intermediate frequency signals; a parallel optimization module is set in a parallel MPWM algorithm, and the intermediate frequency signals are subjected to optimization processing based on the parallel optimization module to obtain four bit pulse sequence codes; the four bit pulse sequence codes are converted into four two-level radio frequency pulse signals; wherein, the sum of the four two-level radio frequency pulse signals is a required five-level radio frequency pulse width modulation signal, the center frequency of the five-level radio frequency pulse width modulation signal is a carrier frequency, and 3X harmonic is eliminated.The application can improve the signal-to-noise ratio, suppress harmonics, and widen the achievable carrier frequency of RF-PWM.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and in particular to a parallel MPWM modulation method for eliminating 3X harmonics. Background Technology

[0002] Transmitters are a crucial component of wireless communication systems, determining the quality of output signals and operational efficiency. Smaller size, lower power consumption, higher communication rates, digitization, and reconfigurability are the development trends for transmitters. In recent years, digital transmitter (DTx) technology based on Direct Digital Radio Frequency Modulation (DDRFM) has developed rapidly and has become a research hotspot in the field of wireless communication. As the core component of DTx, DDRFM's main function is to up-convert the digital baseband signal to the transmission frequency and modulate the digital radio frequency signal into a radio frequency pulse signal that can be directly output by a general-purpose digital signal processor through pulse coding. This pulse signal contains all the information of the baseband modulation signal and can be recovered into a traditional analog radio frequency signal through simple filtering, followed by amplification and transmission through an antenna. DDRFM architecture-based DTx can complete the entire signal processing from baseband to radio frequency in the digital domain. Its high linearity and flexible reconfigurability and programmability are among the most attractive features of Software Defined Radio (SDR).

[0003] Currently, the quality of the output RF pulse width modulation signal and the harmonic suppression effect of threshold comparison-based specific harmonic cancellation RF-PWM modulators are positively correlated with the amplitude and phase resolutions of the reference and threshold signals. Higher amplitude and phase resolutions, better consistency between the two reference signals, and higher threshold accuracy result in a higher signal-to-noise ratio (SNR) and better harmonic suppression. For RF-PWM to achieve good performance, its implementation requires high amplitude and phase resolution. When RF-PWM is implemented in the digital domain, the highest operating frequency of a general-purpose digital signal processor (DSP) is the minimum time resolution achievable. Therefore, limited by the current DSP's highest operating frequency, RF-PWM cannot be implemented at high frequencies, and its harmonic suppression effect is limited. When RF-PWM is implemented in the analog domain, the inherent instability and poor consistency of analog devices make it difficult to achieve high consistency in the amplitude and phase of the two reference signals, and the threshold amplitudes cannot be perfectly symmetrical. This also limits the implementation of RF-PWM at high frequencies and its harmonic suppression effect.

[0004] Although current multi-level RF-PWM modulation methods and modulators for specific harmonic elimination can theoretically achieve high-performance RF pulse width modulation and effectively suppress specific harmonic components, thus improving coding efficiency, the application of multi-level RF-PWM modulators in high-frequency bands is difficult to realize due to the current manufacturing process of devices, and the actual harmonic elimination effect is also limited. Summary of the Invention

[0005] The purpose of this application is to provide a parallel MPWM modulation method for eliminating 3X harmonics, which can improve the signal-to-noise ratio, suppress harmonics, and broaden the achievable carrier frequency of RF-PWM.

[0006] To achieve the above objectives, this application provides the following solution: This application provides a parallel MPWM modulation method for 3X harmonic cancellation, including: Based on the principle of harmonic cancellation, the input baseband signal is decomposed into four phase-controlled baseband phase-modulated signals; the baseband signals include: I signals and Q signals; The baseband phase-modulated signal is digitally up-converted to obtain an intermediate frequency signal; The parallel MPWM algorithm is configured to have A parallel optimization module, and based on Four parallel optimization modules optimize the intermediate frequency signal to obtain four Bit pulse sequence code; 4 The bit pulse sequence code is converted into four two-level radio frequency pulse signals; the sum of the four two-level radio frequency pulse signals is the required five-level radio frequency pulse width modulation signal, and the center frequency of the five-level radio frequency pulse width modulation signal is the carrier frequency. The 3Xth harmonic is eliminated.

[0007] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides a parallel MPWM modulation method for 3X harmonic cancellation. Based on the principle of harmonic cancellation, the input baseband signal is decomposed into four phase-controlled baseband phase-modulated signals; the baseband phase-modulated signals are digitally up-converted to obtain intermediate frequency signals; and the parallel MPWM algorithm is configured to have... A parallel optimization module, and based on Four parallel optimization modules optimize the intermediate frequency signal to obtain four Bit pulse sequence code; 4 bits The bit pulse sequence code is converted into four two-level radio frequency pulse signals; the sum of the four two-level radio frequency pulse signals is the required five-level radio frequency pulse width modulation signal, and the center frequency of the five-level radio frequency pulse width modulation signal is the carrier frequency. The 3Xth harmonic is eliminated, significantly reducing the suppression requirements of subsequent filters. By employing parallel MPWM modulation, the time resolution of the RF pulse width modulator implemented on a general-purpose digital signal processor platform is greatly improved, thereby achieving a higher signal-to-noise ratio and harmonic suppression effect, and broadening the achievable carrier frequency range of RF-PWM. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A flowchart of a parallel MPWM modulation method for 3X harmonic elimination; Figure 2 This is a schematic diagram of a known 5-level RF-PWM modulator with 3Xth harmonic cancellation capability based on threshold comparison. Figure 3 This is a first schematic diagram of a known 5-level radio frequency pulse width modulation signal with 3Xth harmonic cancellation capability based on threshold comparison. Figure 4 This is a second schematic diagram of a 5-level radio frequency pulse width modulation signal with 3Xth harmonic cancellation capability based on threshold comparison, which is currently known. Figure 5 A schematic diagram of a parallel MPWM modulator for 3X harmonic cancellation; Figure 6 This is a schematic diagram of the parallel MPWM unit. Figure 7 This is a schematic diagram of the single-bit optimization module. Figure 8 This is a schematic diagram of the output signal waveform and spectrum of a parallel MPWM modulator with 3Xth harmonic cancellation capability. Figure 9 A schematic diagram of the spectrum of a parallel MPWM modulator with 3Xth harmonic cancellation capability; Figure 10 Simulation graphs of the third harmonic rejection ratio of a 5-level RF pulse width modulation signal at different carrier frequencies; Figure 11 Simulation diagrams showing the coding efficiency of 5-level RF pulse width modulation signals at different carrier frequencies. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0011] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] In one exemplary embodiment, such as Figure 1 As shown, a parallel MPWM modulation method for 3X harmonic cancellation is provided, including: Step 100: Based on the harmonic cancellation principle, the input baseband signal is decomposed into four phase-controlled baseband phase-modulated signals. The baseband signals include: I signal and Q signal.

[0013] Based on the principle of harmonic cancellation, the input baseband signal is decomposed into four phase-controlled baseband phase-modulated signals, specifically including: Based on the principle of harmonic cancellation, the input baseband signal... Decomposed into 4 phase-controlled baseband phase-modulated signals: , , , ;and: .

[0014] .

[0015] .

[0016] .

[0017] .

[0018] in, It is a baseband signal; baseband signal Includes I signals; baseband signal Includes the Q signal; The imaginary unit; This is the first phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal contained therein; This is the second phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal contained therein; This is the third phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal contained therein; This is the fourth phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal contained therein; ; The amplitude of the baseband phase modulation signal; , , , All are intermediate variables.

[0019] Step 200: Digitally upconvert the baseband phase modulation signal to obtain the intermediate frequency signal.

[0020] The baseband phase-modulated signal is digitally up-converted to obtain an intermediate frequency signal, specifically including: The baseband phase-modulated signal is digitally up-converted using the mathematical formula corresponding to the up-conversion, resulting in an intermediate frequency signal. The mathematical formula corresponding to the up-conversion is: .

[0021] in, This is the first intermediate frequency (IF) signal in the IF signal series. This is the first phase-controlled baseband phase-modulated signal; For carrier frequency; This is the sampling frequency of the intermediate frequency signal; This is the second intermediate frequency (IF) signal in the IF signal series. This is the second phase-controlled baseband phase-modulated signal; This is the third intermediate frequency (IF) signal in the IF signal series. This is the third phase-controlled baseband phase-modulated signal; This is the fourth intermediate frequency (IF) signal in the IF signal series. This is the fourth phase-controlled baseband phase-modulated signal.

[0022] Step 300: Configure the parallel MPWM algorithm to have... A parallel optimization module, and based on Four parallel optimization modules optimize the intermediate frequency signal to obtain four Bit pulse sequence code.

[0023] Among them, the parallel MPWM algorithm is configured to have A parallel optimization module, and based on Four parallel optimization modules optimize the intermediate frequency signal to obtain four Bit pulse sequence code, specifically including: In the parallel MPWM algorithm Each parallel optimization module corresponds to a pulse sequence code. 100 bits, of which the parallel optimization module Responsible for the bits Optimized value calculation for each input The intermediate frequency signal, calculation The error between the input intermediate frequency signal and the value of -1. ,as well as When the value is 1, the error compared to the input intermediate frequency signal .

[0024] Compare and The size of the error determines the minimum error value. The value is the optimized value for the corresponding bit. and will As The optimized calculation results are output.

[0025] The computational results of each parallel optimization module together constitute Bit pulse sequence code ; This is the output of the parallel MPWM algorithm.

[0026] The optimization objective equation corresponding to the pulse sequence code is: .

[0027] in, The first one Bit pulse sequence code; It is a pulse sequence code; For all pulse sequence codes of length N The set that constitutes; For the second one Bit pulse sequence code; The 3rd Bit pulse sequence code; The 4th Bit pulse sequence code; For carrier vectors; For the first One bit; , , , These are four phase-controlled phase-modulated signals.

[0028] Step 400: Place 4 The bit pulse sequence code is converted into four two-level radio frequency (RF) pulse signals. The sum of these four two-level RF pulse signals constitutes the required five-level RF pulse width modulation (PWM) signal, and the center frequency of the five-level RF PWM signal is the carrier frequency. The 3Xth harmonic is eliminated.

[0029] The sampling frequency of the intermediate frequency signal is The sampling rate of the radio frequency pulse signal is Sampling rate of radio frequency pulse signal Sampling frequency of intermediate frequency signal Relationship satisfaction .

[0030] The center frequency of the intermediate frequency signal With carrier frequency Relationship satisfaction ,in, It is an integer. These are mathematical parameters and have no specific physical meaning. .

[0031] 4-channel two-level radio frequency pulse signals , , and satisfy: First channel two-level radio frequency pulse signal With the third two-level radio frequency pulse signal The phase difference between them is always Second channel two-level radio frequency pulse signal With the fourth two-level radio frequency pulse signal The phase difference between them is always ;in, The carrier period.

[0032] First channel two-level radio frequency pulse signal With the second two-level radio frequency pulse signal Phase difference between The third two-level radio frequency pulse signal With the fourth two-level radio frequency pulse signal Phase difference between ;in, These are parameters and have no specific physical meaning. ; This represents the baseband signal amplitude.

[0033] In practical applications, since high-speed radio frequency pulse signals consist of only two or a finite number of discrete quantization levels, they not only contain the required RF signal (Radio Frequency Signal) but also contain a large number of noise and harmonic components. In order to reduce the noise of the radio frequency pulse signal, suppress nonlinear components, and improve the signal-to-noise ratio and coding efficiency of the output signal, the following literature (Zhou Qiang, Chen Jianbin, Zhu Lei. Active Harmonic Elimination Method Based on RF-PWM [J]. Journal of Terahertz Science and Electronic Information, 2017, 15(5): 828-833) and (Yao FQ, Zhou Q, Wei Z H. A Novel Multilevel RF-PWM Method With Active-Harmonic Elimination for All-Digital Transmitters [J]. IEEE Transactions on Microwave Theory and Techniques, 2018, 66(7): (3360-3373) respectively proposed a multi-level RF-PWM method for specific harmonic elimination of constant envelope and non-constant envelope signals; and a multi-level RF pulse width modulation method and modulator for specific harmonic elimination, which can realize the active elimination of specific harmonics of multi-level RFPWM output pulses. In particular, by prioritizing the elimination of low-order harmonics, the nonlinear components of RF pulse signals can be effectively suppressed, significantly improving coding efficiency, reducing the design requirements of subsequent filters, and improving the wideband performance of DTx.

[0034] The main idea of ​​multi-level RF-PWM for specific harmonic cancellation is: based on the superposition principle, the M-level RF-PWM signal is equivalent to the weighted superposition of N 3-level RF-PWM signals whose pulse widths are controlled by corresponding comparison thresholds. By controlling the pulse widths of the N 3-level RF-PWM signals and their corresponding weighting coefficients, the K specific harmonic components of the weighted superposition of the N 3-level RF-PWM signals cancel each other out, while the sum of the weighted superposition of their fundamental components is proportional to the amplitude of the normalized envelope signal SA, thereby achieving the active cancellation of specific harmonics in the M-level RF-PWM signal. Figure 2 A schematic diagram of a 5-level RF-PWM modulator with 3Xth harmonic cancellation capability, based on currently known technology, is presented. Figure 2 As shown, the baseband I and Q signals are decomposed into normalized amplitude signals according to the following formulas (1) and (2). and phase signal And by radio frequency carrier frequency and phase signal Generate 2 reference signals and .

[0035] (1) (2) According to formula (3), the amplitude signal Generate threshold signal , will 2 reference signals and respectively with threshold signal By comparison, the corresponding 3-level radio frequency pulse width modulation signal is obtained according to formulas (4) and (5). and 2-channel 3-level RF pulse width modulation signal and The sum of these is the required 5-level RF pulse width modulation signal. Its fundamental component is proportional to the input signal, and the 3Xth harmonic component is eliminated.

[0036] (3) (4) (5) A schematic diagram of a known 5-level RF pulse width modulation signal with 3X harmonic cancellation capability based on threshold comparison is shown below. Figure 3 and Figure 4 As shown.

[0037] This application simplifies the method for generating RF pulse width modulation signals and improves the achievable carrier frequency of RF pulse width modulation while ensuring the output of a 5-level RF pulse width modulation signal with 3X harmonic elimination.

[0038] This application, based on the superposition principle, equates a 5-level RF pulse width modulation signal to the superposition of four 2-level RF pulse signals. By controlling the phase of the four 2-level RF pulse signals, the 3Xth harmonic of the superimposed 5-level RF pulse width modulation signal is canceled. To improve the time resolution of the RF pulse signal, a parallel MPWM algorithm is used to generate four 2-level RF pulse signals: four phase-controlled phase modulation signals are calculated based on the input baseband signal. N parallel computing modules are set up for each phase modulation signal to perform pulse coding optimization calculations. The 4N parallel computing modules generate four N-bit pulse sequence codes. The four pulse sequence codes are converted into four 2-level RF pulse signals by four pulse generators. The sum of the four 2-level RF pulse signals is the 5-level RF pulse width modulation signal with 3Xth harmonic cancellation.

[0039] Specifically, based on the harmonic cancellation principle, the input baseband I and Q signals are decomposed into four phase-controlled baseband phase-modulated signals. , , , The four phase-modulated signals were digitally up-converted to obtain a sampling frequency of . The center frequency is intermediate frequency signal , , , Intermediate frequency With carrier frequency Relationship satisfaction ,in, It is an integer. The number of parallel optimization modules in the parallel MPWM algorithm is set to N, and the intermediate frequency signal is... , , , The parallel MPWM algorithm was implemented separately, and four N-bit pulse sequence codes were obtained through optimization. , , and The pulse sequence code is generated by four pulse generators. , , and The conversion rate to 4-channel high-speed serial is: Two-level radio frequency pulse signal , , and RF sampling rate Sampling frequency of intermediate frequency signal Relationship satisfaction The sum of the four two-level RF pulse signals is the required five-level RF pulse width modulation signal. Its center frequency is the carrier frequency. The 3Xth harmonic is eliminated; among which: N parallel optimization modules in the parallel MPWM algorithm Corresponding to pulse sequence codes N bits Parallel optimization module Responsible for bits The optimized value calculation is performed by parallel optimization modules for each input. The intermediate frequency signal is calculated respectively. The error between the input intermediate frequency signal and the input intermediate frequency signal at different values ​​(-1 or +1) and ),Compare and The size of the value determines the minimum error value. The value is the optimized value of this bit. and will As a parallel optimization module The optimized calculation results are output; the calculation results of N parallel optimization modules together constitute an N-bit pulse sequence code. , This is the output of the parallel MPWM algorithm.

[0040] Step 1: Based on the harmonic cancellation principle, the baseband I and Q signals are... , Decomposed into 4 phase-controlled baseband phase-modulated signals , , , ,and , , , and , The relationships satisfy formulas (6) to (9) respectively.

[0041] (6) (7) (8) (9) in, , This represents the amplitude of the baseband phase modulation signal.

[0042] (10) Step 2: Modulate the phase of the 4 baseband signals according to formula (11). , , , Digital up-conversion is performed separately to obtain intermediate frequency modulated signals. , , , .

[0043] (11) Step 3: Set the objective equation for optimizing the 4-channel pulse sequence code as shown in formula (12): (12) .

[0044] and They are respectively The real and imaginary parts, denoted , It is a set of carrier vectors; Code for all two-level pulse sequences of length N The set that is formed , ; 、 、 and The results are the optimization results for the four pulse sequence codes. , , , .

[0045] Step 4: Decompose formula (12) into 4N parallel optimization problems as shown in formula (13). Each bit Optimize the value of: , , (13) (13) Pulse sequence code To find the optimal value, N single-bit optimization modules are set up. Module Responsible for bits Optimized calculations for pulse sequence codes To find the optimal value, N single-bit optimization modules are set up. Module L i,2 Responsible for bits Optimized calculations for pulse sequence codes To find the optimal value, N single-bit optimization modules are set up. Module L i,3 Responsible for bits Optimized calculations for pulse sequence codes To find the optimal value, N single-bit optimization modules are set up. Module L i,4 Responsible for bits The optimization calculation involves 4N optimization modules running in parallel to complete the parallel MPWM calculation of 4 phase modulation signals.

[0046] Step 5: Optimize each group of modules L i,1 L i,2 L i,3 and L i,4 Calculate according to formulas (14) to (17) respectively. Error values ​​for two different values: -1 and +1 、 ), ( 、 ), ( 、 ), ( 、 ).

[0047] (14) (15) (16) (17) Step 6: Compare according to formula (18) , , , The size is determined based on the comparison results and formula (19). and The value of , , and That is, the optimization module L i,1 L i,2 L i,3 and L i,4 The optimized calculation results.

[0048] (18) (19) Step 7: Combine the results from the 4N parallel optimization calculations to obtain 4 pulse codes. , , , , , , This is the output of parallel MPWM.

[0049] Step 8: Use four pulse generators to generate the pulse sequence code. , , and The conversion rate to 4-channel high-speed serial is: radio frequency pulse signal , , and The sum of the four RF pulse signals is the required 5-level RF pulse width modulation signal. Its 3Xth harmonic is eliminated, and the center frequency is .

[0050] In an exemplary embodiment, a parallel MPWM modulator with 3X harmonic cancellation is provided, which is implemented using the aforementioned parallel MPWM modulation method with 3X harmonic cancellation. The parallel MPWM modulator with 3X harmonic cancellation includes: a phase decomposition unit, an up-conversion unit, a parallel MPWM unit, and a pulse generation unit. A schematic diagram of the structure of the parallel MPWM modulator with 3X harmonic cancellation is shown below. Figure 5 As shown.

[0051] The up-conversion unit is connected to the phase decomposition unit; the parallel MPWM unit is connected to the up-conversion unit; and the pulse generation unit is connected to the parallel MPWM unit.

[0052] The phase decomposition unit is used to receive the baseband signal and decompose it into four phase-controlled baseband phase modulation signals.

[0053] The upconversion unit is used to receive the baseband phase modulation signal and upconvert the baseband phase modulation signal into an intermediate frequency signal.

[0054] The parallel MPWM unit is used to configure the parallel MPWM algorithm. A parallel optimization module, and based on Four parallel optimization modules optimize the intermediate frequency signal to obtain four Bit pulse sequence code.

[0055] The pulse generation unit is used to generate four pulses. The bit pulse sequence code is converted into four two-level radio frequency pulse signals; the sum of the four two-level radio frequency pulse signals is the required five-level radio frequency pulse width modulation signal, and the center frequency of the five-level radio frequency pulse width modulation signal is the carrier frequency. The 3Xth harmonic is eliminated.

[0056] The structural diagram of the parallel MPWM unit is shown below. Figure 6 As shown. The parallel MPWM unit includes: a first parallel optimization module, a second parallel optimization module, a third parallel optimization module, a fourth parallel optimization module, a first pulse sequence code synthesizer, a second pulse sequence code synthesizer, a first pulse sequence code synthesizer, a second pulse sequence code synthesizer, and a carrier vector generator.

[0057] The first parallel optimization module, the second parallel optimization module, the third parallel optimization module, and the fourth parallel optimization module are all connected to the carrier vector generator; the first pulse sequence code synthesizer is connected to the first parallel optimization module; the second pulse sequence code synthesizer is connected to the second parallel optimization module; the third pulse sequence code synthesizer is connected to the third parallel optimization module; and the fourth pulse sequence code synthesizer is connected to the fourth parallel optimization module.

[0058] Carrier vector generator is used to receive radio frequency carrier frequencies. And generate a carrier vector; the first parallel optimization module is used to receive the carrier vector and the first intermediate frequency signal in the intermediate frequency signal, and perform the first... Optimized value calculation for each bit to determine the first Optimized value for each bit.

[0059] The second parallel optimization module is used to receive the carrier vector and the second intermediate frequency signal from the intermediate frequency signal, and to perform the second... Optimized value calculation for each bit to determine the second Optimized value for each bit.

[0060] The third parallel optimization module is used to receive the carrier vector and the third intermediate frequency signal from the intermediate frequency signal, and to perform the third... Optimized value calculation of each bit to determine the third Optimized value for each bit.

[0061] The fourth parallel optimization module is used to receive the carrier vector and the fourth intermediate frequency signal from the intermediate frequency signal, and to perform the fourth parallel optimization. Optimization calculation of each bit to determine the fourth Optimized value for each bit.

[0062] The first pulse sequence code synthesizer is used to convert the first... The optimized values ​​of each bit are synthesized into an N-bit parallel pulse code to obtain the first... The second pulse sequence code synthesizer is used to convert the second pulse sequence code into a second pulse sequence code. The optimized values ​​of each bit are synthesized into an N-bit parallel pulse code to obtain the second... Bit pulse sequence code.

[0063] The third pulse sequence code synthesizer is used to convert the third pulse sequence code into a third pulse sequence code synthesizer. The optimized values ​​of each bit are synthesized into an N-bit parallel pulse code to obtain the third... The fourth pulse sequence code synthesizer is used to convert the fourth pulse sequence code into a bit pulse sequence code; The optimized values ​​of each bit are synthesized into an N-bit parallel pulse code to obtain the fourth one. Bit pulse sequence code.

[0064] The first, second, third, and fourth parallel optimization modules each consist of N identical single-bit optimization modules. A schematic diagram of the single-bit optimization module is shown below. Figure 7 As shown.

[0065] The single-bit optimization module includes a multiplier, an adder, and a single-bit inverter; the multiplier is connected to the carrier vector generator; the adder is connected to the multiplier; and the single-bit inverter is connected to the adder.

[0066] The multiplier is used to receive the carrier vector; the adder is used to perform optimized bit value calculations based on the carrier vector and output the most significant bit. Coupled to a single-bit inverter.

[0067] A single-bit inverter is used to calculate the error value when the bit takes two different values: -1 and 1; when When it is 1, it represents At this point, the optimized value of the bit is... A single-bit inverter outputs a low level when... When it is 0, it represents At this point, the optimized value of the bit is... A single-bit inverter outputs a high level; where, For the first The corresponding parallel optimization module is the first bits The error between the input intermediate frequency signal and the value of -1; For the first The corresponding parallel optimization module is the first bits The error between the input intermediate frequency signal and the value 1; the output of the single-bit inverter is the output of the single-bit optimization module.

[0068] A 5-level RF pulse width modulator with 3X harmonic cancellation capability, featuring 4 signal inputs and 2 signal outputs, including: The signal decomposition unit has two input terminals and four output terminals. The two input terminals are the first and second input terminals of a parallel MPWM modulator with 3X harmonic cancellation, used to receive baseband I and Q signals. , It is converted into 4-channel normalized baseband phase-modulated signals. , , , Then, the outputs are generated through the first output terminal to the fourth output terminal respectively.

[0069] The upconversion unit has 5 input terminals and 8 output terminals. The first to fourth input terminals are respectively coupled to the 4 output terminals of the phase decomposition unit to receive the baseband phase modulation signal. , , , The fifth input terminal is the third input terminal of the parallel MPWM modulator with 3X harmonic cancellation, used to receive intermediate frequency information. The baseband phase-modulated signal is up-converted to an intermediate frequency modulated signal. , , , Then, the 8 output terminals output the I and Q signals of the 4 intermediate frequency signals respectively. , , , , , , , .

[0070] The parallel MPWM unit has 9 input terminals and 4 output terminals. The first to eighth input terminals are coupled to the first to eighth output terminals of the upconverter unit to receive 4 intermediate frequency modulation signals. , , , The I and Q signals, and the ninth input terminal is the fourth input terminal of the parallel MPWM modulator with 3X harmonic cancellation, used to receive the radio frequency carrier frequency. Generate carrier vectors and calculate pulse sequence codes. , , and Then it is output through 4 output terminals.

[0071] The pulse generation unit includes four pulse generators, each with the same structure and one input and one output. The inputs of the four pulse generators are coupled to the four outputs of the parallel MPWM unit to receive parallel pulse sequence codes. , , and The outputs of the four pulse generators are the first to fourth outputs of a parallel MPWM modulator with 3X harmonic cancellation, generating and outputting four high-speed serial two-level RF pulse signals. , , and .

[0072] The upconversion unit uses the received intermediate frequency information It generates two orthogonal local oscillator signals in real time.

[0073] In one embodiment of this application, the parallel MPWM unit includes a first parallel optimization module, a second parallel optimization module, a third parallel optimization module, a fourth parallel optimization module, a first pulse sequence code synthesizer, a second pulse sequence code synthesizer, a first pulse sequence code synthesizer, a second pulse sequence code synthesizer, and a carrier vector generator.

[0074] The first parallel optimization module has four input terminals and N output terminals. The first input terminal-second input terminal is the first input terminal-second input terminal of the parallel optimization unit, used to receive the first intermediate frequency modulation signal. I, Q signal and The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, for receiving the carrier vector set. real part and the virtual part The first parallel optimization module calculates the optimal value of N bits of the pulse sequence code according to formulas (12) and (13). Then, the output is generated from the first output terminal to the Nth output terminal.

[0075] The second parallel optimization module has the same structure as the first parallel optimization module, with 4 input terminals and N output terminals. The first and second input terminals are the third and fourth input terminals of the parallel optimization unit, used to receive the second intermediate frequency modulation signal. I, Q signal , The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, for receiving the carrier vector set. real part and the virtual part The second parallel optimization module calculates the optimal value of N bits of the pulse sequence code according to formulas (12) and (13). Then, the output is generated from the first output terminal to the Nth output terminal.

[0076] The third parallel optimization module has the same structure as the first parallel optimization module, with 4 input terminals and N output terminals. The first and second input terminals are the fifth and sixth input terminals of the parallel optimization unit, used to receive the third intermediate frequency modulation signal. I, Q signal and The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, for receiving the carrier vector set. real part and the virtual part The third parallel optimization module calculates the optimal value of the N bits of the pulse sequence code according to formulas (12) and (13). Then, the output is generated from the first output terminal to the Nth output terminal.

[0077] The fourth parallel optimization module has the same structure as the first parallel optimization module. It has four input terminals and N output terminals. The first and second input terminals of the fourth parallel optimization module are the seventh and eighth input terminals of the parallel optimization unit, used to receive the fourth intermediate frequency modulation signal. I, Q signal , The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, for receiving the carrier vector set. real part and the virtual part The fourth parallel optimization module calculates the optimal value of N bits of the pulse sequence code according to formulas (12) and (13). Then, the output is generated from the first output terminal to the Nth output terminal.

[0078] The carrier vector generator has one input and two outputs. The input is the fourth input of a 3X harmonic-canceling parallel MPWM modulator, used to receive the radio frequency carrier frequency. Calculate and generate carrier vector set The two outputs of the carrier vector generator are coupled to the third and fourth outputs of each parallel optimization module, respectively, and output carrier vector sets. real part and the virtual part It is used for the calculations of each parallel optimization module.

[0079] The first pulse sequence code synthesizer has N input terminals and 1 output terminal. Its first to Nth input terminals are coupled to the first to Nth output terminals of the first parallel optimization module, respectively, for receiving the optimized N-bit signal. And synthesize them into an N-bit parallel pulse code. It is output from the output terminal.

[0080] The second pulse sequence code synthesizer has the same structure as the first pulse sequence code synthesizer and has N input terminals and 1 output terminal. Its first to Nth input terminals are respectively coupled to the first to Nth output terminals of the second parallel optimization module to receive the optimized N-bit signal. This is combined into an N-bit parallel pulse code. It is output from its output terminal.

[0081] The third pulse sequence code synthesizer has the same structure as the first pulse sequence code synthesizer and has N input terminals and 1 output terminal. Its first to Nth input terminals are coupled to the first to Nth output terminals of the third parallel optimization module, respectively, to receive the optimized N-bit signal. This is combined into an N-bit parallel pulse code. It is output from its output terminal.

[0082] The fourth pulse sequence code synthesizer has the same structure as the first pulse sequence code synthesizer and has N input terminals and 1 output terminal. Its first to Nth input terminals are coupled to the first to Nth output terminals of the fourth parallel optimization module, respectively, to receive the optimized N-bit signal. This is combined into an N-bit parallel pulse code. It is output from the output terminal.

[0083] The first parallel optimization module includes N single-bit optimization modules with identical structures, whose bit numbers are denoted as follows: Each single-bit optimization module has 4 inputs and 1 output; single-bit optimization module The first input terminal-second input terminal is the first input terminal-second input terminal of the first parallel optimization module, used to receive the first intermediate frequency signal. I, Q signal and The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, to receive the corresponding carrier vectors. real part and the virtual part Single-bit optimization module The output terminal is coupled to the i-th output terminal of the first parallel optimization module; single-bit optimization module The optimal value of the i-th bit of the pulse sequence code is calculated using formulas (12) and (13). Then it is output by the i-th output terminal of the first parallel optimization module.

[0084] The second parallel optimization module has the same structure as the first parallel optimization module, and includes N single-bit optimization modules with identical structures, whose bit numbers are denoted as follows: Each single-bit optimization module has 4 inputs and 1 output; single-bit optimization module The first input terminal-second input terminal is the first input terminal-second input terminal of the second parallel optimization module, used to receive the second intermediate frequency signal. I, Q signal , The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, to receive the corresponding carrier vectors. real part and the virtual part Single-bit optimization module The output terminal is coupled to the i-th output terminal of the second parallel optimization module; single-bit optimization module The optimal value of the i-th bit of the pulse sequence code is calculated using formulas (12) and (13). Then it is output by the i-th output terminal of the second parallel optimization module.

[0085] The third parallel optimization module has the same structure as the first parallel optimization module, and includes N single-bit optimization modules with identical structures, whose bit numbers are denoted as follows: Each single-bit optimization module has 4 inputs and 1 output; single-bit optimization module The first input terminal and the second input terminal are the first input terminal and the second input terminal of the third parallel optimization module, used to receive the third intermediate frequency signal. I, Q signal and The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, to receive the corresponding carrier vectors. real part and the virtual part Single-bit optimization module The output terminal is coupled to the i-th output terminal of the third parallel optimization module; single-bit optimization module The optimal value of the i-th bit of the pulse sequence code is calculated using formulas (12) and (13). Then it is output by the i-th output terminal of the third parallel optimization module.

[0086] The fourth parallel optimization module has the same structure as the first parallel optimization module, including N single-bit optimization modules with identical structures, whose bit numbers are denoted as follows: Each single-bit optimization module has 4 inputs and 1 output; single-bit optimization module The first input terminal-second input terminal is the first input terminal-second input terminal of the fourth parallel optimization module, used to receive the third intermediate frequency signal. I, Q signal and The third and fourth input terminals are coupled to the first and second output terminals of the carrier vector generator, respectively, to receive the corresponding carrier vectors. real part and the virtual part Single-bit optimization module The output terminal is coupled to the i-th output terminal of the fourth parallel optimization module; single-bit optimization module The optimal value of the i-th bit of the pulse sequence code is calculated using formulas (12) and (13). Then it is output by the i-th output terminal of the fourth parallel optimization module.

[0087] The single-bit optimization module contains two multipliers, one adder, and one single-bit inverter. The first input of the two multipliers serves as the first-second input of the parallel optimization module, used to receive the I and Q signals of the intermediate frequency modulation signal. The second input of the two multipliers serves as the third and fourth inputs of the parallel optimization module, used to receive the carrier vector. real part and the virtual part The outputs of the two multipliers are coupled to the inputs of the adder, and the two multipliers and one adder work together to complete the calculation of formula (13). The highest bit of the adder output is coupled to the input of a single-bit inverter, which completes the calculations of formulas (14) to (17). When it is 1, it represents According to formula (19). When the inverter outputs a low level, When it is 0, it represents According to formula (19). The inverter outputs a high level; the output of the single-bit inverter is the output of the single-bit optimization module, which is coupled to the corresponding output of the parallel optimization module.

[0088] like Figure 8 As shown, the pulse width of the four two-level RF pulse signals generated by the parallel MPWM modulation method for 3X harmonic elimination provided in this application is half a RF carrier cycle. The level transition time of the corresponding digital signal processor I / O port is half a radio frequency cycle, which can significantly reduce the average switching frequency of the I / O port and thus reduce the power consumption of the processor.

[0089] like Figure 9 As shown, the 5-level RF pulse width modulation signal generated by the parallel MPWM modulation method for 3X harmonic elimination provided in this application contains only harmonic components in its spectrum, wherein the 3X harmonic components are suppressed, which can significantly reduce the suppression requirements of subsequent filters.

[0090] like Figure 10 and Figure 11 As shown, under fully digital implementation conditions, with a 16QAM signal of the same modulation parameters as input, at different carrier frequencies, the third harmonic of the 5-level RF pulse width modulation signal y(t) generated in this application reaches more than -40dBc compared to the main tone, and the coding efficiency (CE) is higher than 80%. The RF carrier frequency... The rate of the radio frequency pulse width modulation signal is 100MHz-3GHz. 16GHz, N=64, intermediate frequency sampling rate The input 16QAM signal has a symbol rate Rs of 10MHz and a frequency of 250MHz. Compared with known technologies, this application can be implemented in the entire digital domain, achieving an equivalent time resolution of 62.5ps on a general-purpose digital signal processing platform.

[0091] This application discloses a parallel MPWM modulation method for 3X harmonic cancellation. The input baseband I and Q signals are decomposed into four phase-controlled baseband phase-modulated signals. These four baseband phase-modulated signals are then up-converted to an intermediate frequency (IF), where the IF frequency is the remainder after dividing the carrier frequency by the IF sampling frequency. Based on a parallel MPWM algorithm, N parallel optimization modules are set up for each IF phase-modulated signal. Each optimization module optimizes the value of one bit in the pulse sequence. The calculation results of the 4N parallel optimization modules for the four signals are combined into four N-bit parallel pulse sequence codes. These four pulse sequence codes are then converted into four high-speed serial two-level RF pulse signals for output. Based on the above method, this application also provides a parallel MPWM modulator for 3X harmonic cancellation. Compared to traditional specific harmonic cancellation RF-PWM modulation methods and modulators based on threshold comparison and orthogonal upconversion, this application significantly improves the time resolution of the RF pulse width modulator implemented on a general-purpose digital signal processor platform by adopting a parallel MPWM modulation method. This results in a higher signal-to-noise ratio and harmonic suppression effect, and broadens the achievable carrier frequency range of RF-PWM.

[0092] This application replaces the traditional RF-PWM implementation method based on threshold comparison and quadrature upconversion with a parallel MPWM modulation method, which can realize the digitization of the entire processing process. The equivalent time resolution on a general digital signal processor platform can reach 50ps, which greatly improves the achievable time resolution of high-speed radio frequency pulse width modulation signals, thereby improving the signal-to-noise ratio and harmonic suppression effect, and broadening the achievable carrier frequency of RF-PWM.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A parallel MPWM modulation method for eliminating 3X harmonics, characterized in that, include: Based on the principle of harmonic cancellation, the input baseband signal is decomposed into four phase-controlled baseband phase-modulated signals. The baseband signal includes: an I signal and a Q signal; The baseband phase-modulated signal is digitally up-converted to obtain an intermediate frequency signal; The parallel MPWM algorithm is configured to have A parallel optimization module, and based on Four parallel optimization modules optimize the intermediate frequency signal to obtain four Bit pulse sequence code; 4 The bit pulse sequence code is converted into four two-level radio frequency pulse signals; the sum of the four two-level radio frequency pulse signals is the required five-level radio frequency pulse width modulation signal, and the center frequency of the five-level radio frequency pulse width modulation signal is the carrier frequency. The 3Xth harmonic is eliminated.

2. The parallel MPWM modulation method for eliminating the 3Xth harmonic as described in claim 1, characterized in that, The parallel MPWM algorithm is configured to have A parallel optimization module, and based on Four parallel optimization modules optimize the intermediate frequency signal to obtain four The bit pulse sequence code specifically includes: In the parallel MPWM algorithm Each parallel optimization module corresponds to a pulse sequence code. 1 bit, of which, parallel optimization module Responsible for the bits Optimized value calculation for each input The intermediate frequency signal, calculation The error between the input intermediate frequency signal and the value of -1. ,as well as The error between the input intermediate frequency signal and the value of 1. ; Compare and The size of the error determines the minimum error value. The value is the optimized value for the corresponding bit. and will As Output the optimized calculation results; The computational results of each parallel optimization module together constitute Bit pulse sequence code ; This is the output of the parallel MPWM algorithm.

3. The parallel MPWM modulation method for eliminating the 3Xth harmonic as described in claim 2, characterized in that, The optimization objective equation corresponding to the pulse sequence code is: ； in, For the first one Bit pulse sequence code; It is a pulse sequence code; For all pulse sequence codes of length N The set that constitutes; For the second one Bit pulse sequence code; The 3rd Bit pulse sequence code; The 4th Bit pulse sequence code; For carrier vectors; For the first One bit; , , , These are four phase-controlled phase-modulated signals.

4. The parallel MPWM modulation method for eliminating the 3Xth harmonic as described in claim 1, characterized in that, The sampling frequency of the intermediate frequency signal is The sampling rate of the radio frequency pulse signal is Sampling rate of radio frequency pulse signal Sampling frequency of intermediate frequency signal Relationship satisfaction ; The center frequency of the intermediate frequency signal With carrier frequency Relationship satisfaction ,in, It is an integer. For mathematical parameters, .

5. The parallel MPWM modulation method for eliminating the 3Xth harmonic as described in claim 1, characterized in that, 4-channel two-level radio frequency pulse signals , , and satisfy: First channel two-level radio frequency pulse signal With the third two-level radio frequency pulse signal The phase difference between them is always ; Second channel two-level radio frequency pulse signal With the fourth two-level radio frequency pulse signal The phase difference between them is always ;in, The carrier period; First channel two-level radio frequency pulse signal With the second two-level radio frequency pulse signal Phase difference between The third two-level radio frequency pulse signal With the fourth two-level radio frequency pulse signal Phase difference between ;in, For parameters; ; This represents the baseband signal amplitude.

6. The parallel MPWM modulation method for eliminating the 3Xth harmonic as described in claim 1, characterized in that, Based on the principle of harmonic cancellation, the input baseband signal is decomposed into four phase-controlled baseband phase-modulated signals, specifically including: Based on the principle of harmonic cancellation, the input baseband signal... Decomposed into 4 phase-controlled baseband phase-modulated signals: , , , ;and: ； ； ； ； ； in, It is a baseband signal; baseband signal Includes I signals; Baseband signal Includes the Q signal; The imaginary unit; This is the first phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal included; This is the second phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal contained therein; This is the third phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal included; This is the fourth phase-controlled baseband phase-modulated signal; for The I signal contained therein; for The Q signal included; ; The amplitude of the baseband phase modulation signal; , , , All are intermediate variables.

7. The parallel MPWM modulation method for eliminating the 3Xth harmonic as described in claim 1, characterized in that, The baseband phase-modulated signal is digitally up-converted to obtain an intermediate frequency signal, specifically including: The baseband phase-modulated signal is digitally up-converted using the mathematical formula corresponding to the up-conversion, to obtain the intermediate frequency signal; the mathematical formula corresponding to the up-conversion is: ； in, This is the first intermediate frequency (IF) signal in the IF signal series. This is the first phase-controlled baseband phase-modulated signal; For carrier frequency; This is the sampling frequency of the intermediate frequency signal; This is the second intermediate frequency (IF) signal in the IF signal series. This is the second phase-controlled baseband phase-modulated signal; This is the third intermediate frequency (IF) signal in the IF signal series. This is the third phase-controlled baseband phase-modulated signal; This is the fourth intermediate frequency (IF) signal in the IF signal series. This is the fourth phase-controlled baseband phase-modulated signal.

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