A low noise voltage controlled oscillator circuit

Abstract

The application relates to the technical field of radio frequency integrated circuits, and discloses a low-noise voltage-controlled oscillator circuit which comprises a source follower low-noise bias circuit with digital calibration, a cross-coupled amplifier array composed of multiple units, a stable DC bias switch capacitor unit array, a wide linear variable capacitor array driven by a ladder bias voltage, and an amplitude self-calibration loop composed of digital logic and a peak detector.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and in particular to a low-noise voltage-controlled oscillator circuit. Background Technology

[0002] With the rapid development of Internet of Things (IoT) technology, applications such as smart homes, industrial sensing, and wearable devices are placing increasingly stringent demands on low-cost, low-power, and high-performance radio frequency (RF) communication chips. In RF communication systems, the voltage-controlled oscillator (VCO), as a core module, is responsible for generating a local carrier signal for frequency conversion processing. The quality of the VCO's output signal, particularly its phase noise, tuning range, linearity, and output amplitude stability, directly determines the sensitivity, signal-to-noise ratio, anti-interference capability, and transmit spectrum purity of the RF receiver, thus affecting the reliability and data rate of the entire communication link. Therefore, designing a VCO that meets the stringent requirements of IoT applications is a continuous pursuit for those skilled in the art.

[0003] In practical applications, VCOs are widely used in various wireless communication terminals. For example, in IoT sensor nodes based on Bluetooth Low Energy (BLE) or Zigbee protocols, the local oscillator signal generated by the VCO modulates the data collected by the sensor onto a 2.4GHz carrier wave and transmits it through the antenna. The receiving end also requires the VCO to generate a local oscillator signal at the same frequency to demodulate the received weak radio frequency signal into baseband data. The performance of the VCO directly determines the communication distance, battery life, and stability of the sensor node in complex electromagnetic environments. If the VCO phase noise is too high, it will pollute adjacent channels, reduce the selectivity of the receiver, and lead to a shortened communication distance or an increased data packet loss rate. If its tuning range is insufficient or its linearity is poor, it will not be able to cover the required communication frequency band, or it will cause the phase-locked loop (PLL) lock time to be too long and its stability to deteriorate. If the output amplitude fluctuates drastically with changes in process technology, voltage, and temperature (PVT), it will not only introduce additional phase noise, but may also cause abnormal operation of subsequent circuits, or even make it difficult for the oscillator to start oscillating.

[0004] However, existing voltage-controlled oscillators (VCOs) are difficult to design to fully meet the dual requirements of high performance and low power consumption in IoT applications, and they have the following technical problems:

[0005] The first technical problem is the noise issue of the bias circuit, such as... Figure 8In the traditional VCO structure shown, the bias circuit typically employs a simple current mirror or error amplifier structure. This structure has poor noise suppression capabilities. Thermal noise and flicker noise generated by components in the bias circuit (such as MOSFETs and resistors) can be directly coupled to the cross-coupled transistors of the oscillation core through the power supply or current mirror, thereby deteriorating the overall phase noise of the VCO. Especially in scenarios where IoT devices operate intermittently, the settling time and noise characteristics of the bias circuit have a significant impact on system startup speed and signal quality.

[0006] The second technical issue is the tuning performance of the variable capacitor. Traditional VCOs typically use a single AMOS-type variable capacitor. The capacitance-voltage (CV) characteristic curve of this type of variable capacitor exhibits strong nonlinearity, and its effective tuning range is usually limited to a portion of the supply voltage. This causes the voltage-controlled gain (KVCO) of the VCO to vary drastically throughout the tuning range, not only worsening phase noise (because the high-gain region converts more noise on the tuning line into phase noise) but also posing a significant challenge to the loop stability design of the phase-locked loop (PLL). The limited tuning range also makes it difficult for the chip to cover multiple frequency bands or cope with frequency drift caused by process variations.

[0007] The third technical issue is the stability of the oscillation amplitude. The oscillation amplitude of a traditional VCO is heavily dependent on the bias current, supply voltage, temperature, and process angle. To ensure that the oscillator can reliably start up and maintain a sufficient oscillation amplitude even in the worst-case scenario, designers typically use a large bias current, leaving a large design margin. This approach results in excessively high static power consumption of the chip under most operating conditions, which contradicts the ultra-low power requirements of IoT devices. At the same time, amplitude fluctuations introduce additional phase noise through the nonlinear capacitance effect of the transistor (AM-PM conversion), further degrading signal quality.

[0008] The fourth technical issue is the balance between the structure and noise of cross-coupled amplifiers. Traditional cross-coupled pairs have simple structures, making it difficult to achieve the optimal balance between noise performance and gain. For example, while cross-coupled pairs composed only of NMOS or PMOS have a simple structure, their noise performance and output swing are limited. In addition, the low-frequency flicker noise of the amplifier transistors themselves will directly become phase noise near the oscillator output during up-conversion, severely affecting near-carrier phase noise performance.

[0009] The fifth technical issue is the DC bias problem of switched capacitors, in traditional switched capacitor arrays (such as...). Figure 6As shown in the diagram, when the NMOS transistor acting as a switch is turned off, its drain node is connected to the capacitor plate and is in a high-resistance state, lacking a stable DC potential. The potential of this node can drift due to charge leakage or external interference, thereby changing the capacitance value, introducing low-frequency noise, and potentially causing frequency uncertainty, which seriously affects the long-term stability and phase noise of the VCO.

[0010] The aforementioned technical problems are intertwined and jointly restrict the application potential of VCOs in IoT RF chips. Therefore, those skilled in the art urgently need a novel low-noise voltage-controlled oscillator circuit to solve these technical problems. Summary of the Invention

[0011] The core technical problem solved by this invention is that existing VCO technology mainly suffers from high bias noise, narrow tuning range and poor linearity, unstable output amplitude, poor balance between amplifier noise and gain, and potential drift at the switching capacitor node.

[0012] To address the aforementioned core technical problems, this invention designs a low-noise voltage-controlled oscillator circuit. Its purpose is to systematically solve the multiple challenges of noise, tuning, amplitude stability, and power consumption in the prior art through a bias circuit integrating digital calibration technology, an innovative wide linear adjustable capacitor array, a cross-coupled amplifier array with amplitude self-calibration, and a switched capacitor unit with a stable DC potential.

[0013] Furthermore, this invention also includes a voltage-controlled oscillator (VCO) that achieves low phase noise, high linearity tuning, stable output amplitude, and low power consumption across a wide bandwidth, thus perfectly meeting the requirements of IoT RF communication chips for high-performance local oscillator signal sources. Its core lies in the deep integration of digital logic control and analog circuit design, enabling refined and automated calibration and management of bias voltage, oscillation amplitude, and frequency coverage, thereby achieving robustness of circuit performance under PVT variations.

[0014] To achieve the above objectives, the specific technical solution of the present invention is a low-noise voltage-controlled oscillator circuit, comprising:

[0015] The bias circuit provides a calibrated bias voltage (Vreg) at its output.

[0016] A cross-coupled amplifier circuit has a bias power supply terminal that receives the bias voltage (Vreg), a control terminal that receives the amplitude calibration signal (Calamp), and a differential output terminal (vcop, vcon) that is used to output an oscillation signal.

[0017] The resonant circuit is connected to the differential output terminal (vcop, vcon) of the cross-coupled amplifier circuit, and is used to jointly determine the oscillation frequency with the cross-coupled amplifier circuit.

[0018] A peak detection circuit, whose input is connected to the differential output of the cross-coupled amplifier circuit, is used to detect the amplitude of the oscillation signal and output a detection signal (pkdout); and

[0019] The digital logic control circuit receives the detection signal (pkdout) at its input terminal and outputs the amplitude calibration signal (Calamp) to the cross-coupled amplifier circuit at its output terminal, so as to adjust the operating state of the cross-coupled amplifier circuit according to the detected amplitude, thereby calibrating the oscillation amplitude to the target value.

[0020] The bias circuit includes:

[0021] The programmable current source (MIRIB) receives a bias calibration signal (Calib) at its control terminal.

[0022] A current mirror structure is used to mirror the current generated by the programmable current source;

[0023] The output stage includes a source follower (PM5) whose gate receives a bias voltage (VB) generated by the current mirror structure, and whose source serves as the output of the bias voltage (Vreg).

[0024] A voltage divider filter network is connected between the bias voltage (Vreg) output terminal and ground to generate a detection voltage (VTEST).

[0025] A comparator whose two inputs receive a reference voltage (VREF) and the detected voltage (VTEST), respectively; and

[0026] The bias voltage digital logic calibration circuit has its input connected to the output of the comparator and its output output the bias calibration signal (Calib) to the programmable current source (MIRIB), forming a closed-loop calibration circuit.

[0027] The cross-coupled amplifier circuit includes an array composed of multiple amplifier unit circuits;

[0028] The amplitude calibration signal (Calamp) output by the digital logic control circuit is encoded and used to select or turn off the amplification unit circuits one by one to finely adjust the total transconductance and realize digital calibration of the oscillation amplitude.

[0029] Each of the aforementioned amplification unit circuits includes:

[0030] The cross-coupled transistors include a first PMOS transistor (PM1) and a second PMOS transistor (PM2), whose gates are cross-connected to the differential output terminal;

[0031] The control switching transistors include a third PMOS transistor (PM3) and a fourth PMOS transistor (PM4), which are connected in series between the drains of the first and second PMOS transistors and their corresponding differential output terminals, respectively. Their gates share a common first control signal (camp).

[0032] The NMOS cross-coupled pair has its source grounded through a resistor, its drain connected to the differential output, its gates cross-connected, and a switching transistor controlled by a control signal (cam) connected in series in its source path.

[0033] In the amplification unit circuit, the source of the PMOS cross-coupled pair is connected to the bias voltage (Vreg) through a first resistor-capacitor filter network, and the source of the NMOS cross-coupled pair is grounded through a second resistor-capacitor filter network.

[0034] The resistor-capacitor filter network is used to suppress low-frequency noise from the amplifier tube while allowing high-frequency oscillation signals to pass through.

[0035] The resonant circuit includes a switched capacitor circuit array connected to the differential output terminal (vcop, vcon) and receiving a capacitor calibration signal (calcap) from the digital logic control circuit or an external controller for coarse adjustment of the oscillation frequency.

[0036] The switched capacitor circuit array is composed of multiple switched capacitor unit circuits; each switched capacitor unit circuit includes:

[0037] The first capacitor (CS1) and the second capacitor (CS2) have one end connected to the differential output terminals (vcon, vcop), respectively.

[0038] The sources of the first PMOS switch (PMS1) and the second PMOS switch (PMS2) are respectively connected to the other ends of the first and second capacitors, and their drains are respectively connected to the other ends of the first and second capacitors through resistors.

[0039] Multiple NMOS switching transistors (NMS2, NMS3, NMS1) have their drain and source connected between the other end of the first capacitor, the other end of the second capacitor and ground, or between the other end of the first capacitor and the other end of the second capacitor.

[0040] The gates of all PMOS and NMOS switches share the capacitor calibration signal (calcap), so that when the NMOS switch is turned off, the PMOS switch is turned on, providing a stable DC potential for the floating node.

[0041] The resonant circuit also includes a variable capacitor circuit, which is connected to the differential output (vcop, vcon) and receives a tuning voltage (VTUNE) for fine-tuning the oscillation frequency.

[0042] The variable capacitor circuit includes:

[0043] A resistor series voltage divider network, connected between the bias voltage (Vreg) and ground, generates multiple stepped bias voltages (VB<19:0>); and

[0044] An array consisting of multiple variable capacitor unit circuits, each of which receives a stepped bias voltage (VB) at its control terminal, receives a common tuning voltage (VTUNE) at its tuning terminal, and has its differential terminal connected to the differential output terminal (vcop, vcon). By shifting the CV characteristics of each unit under different bias voltages, the overall tuning characteristics with a wide linear range are superimposed.

[0045] Each of the variable capacitor unit circuits includes:

[0046] The first NMOS varactor (NMV2) and the second NMOS varactor (NMV3) have their sources and drains shorted together and connected to the tuning voltage (VTUNE).

[0047] The first DC blocking capacitor (CV1) and the second DC blocking capacitor (CV2) have one end connected to the differential output terminal (vcon, vcop) respectively, and the other end connected to the gate of the first and second NMOS varactors respectively.

[0048] A bias resistor (RV3) is connected between the gates of the first and second NMOS varactor transistors and the corresponding stepped bias voltage (VB); and

[0049] The filter capacitors (CV3, CV4) are connected between the gates of the first and second NMOS varactors and ground, respectively.

[0050] Compared with the prior art, the technical solution disclosed in this application has the following non-obvious technical features:

[0051] First, this application constructs a source follower low-noise bias circuit with digital calibration, which differs from traditional error amplifier-based bias circuits (such as...). Figure 8In contrast, this application uses a source follower (PM5) to track the voltage VB and combines it with current negative feedback. At the same time, it performs closed-loop calibration of the programmable current source (MIRIB) through comparators and digital logic to accurately generate a stable bias voltage Vreg. This design not only simplifies the circuit structure and significantly reduces the noise introduced by the bias circuit, but also adaptively compensates for PVT changes. It is especially suitable for the intermittent working mode of IoT devices. This structure and its calibration mechanism are not obvious to those skilled in the art.

[0052] Second, this application constructs a cross-coupled amplifier unit array with a source resistor-capacitor feedback network. This application introduces a feedback filter network composed of resistors (RA1-RA4) and capacitors (CA1-CA4) at the source of the cross-coupled pairs (including PMOS and NMOS). This network achieves negative feedback suppression of low-frequency noise (through resistors), while utilizing the "short-circuit" characteristic of capacitors to ensure that positive feedback amplification of high-frequency oscillation signals is unaffected. This noise suppression technique, which differentiates the processing of low-frequency and high-frequency signals on the same path, combined with a digitally controlled unit array (Calamp<3:0> controlling 16 units), achieves fine calibration of the oscillation amplitude. Its structure and control logic are non-obvious.

[0053] Third, this application constructs a switched capacitor unit circuit with stable DC bias, which differs from traditional switched capacitor units (such as...). Figure 6 Compared to the NMOS transistor with its drain floating when turned off, the switched capacitor unit of this application ( Figure 5 When the NMOS switches (NMS2, NMS3) are off, the drain nodes of the NMOS transistors are connected to the differential output terminals (vcon, vcop) through the complementary control signals of the PMOS transistors (PMS1, PMS2), thereby providing a stable DC potential (common-mode voltage). Simultaneously, the additional NMOS transistor NMS1 short-circuits the nodes of the two capacitors when it is on. This circuit structure, which fundamentally solves the node potential drift problem, is not an obvious improvement to those skilled in the art.

[0054] Fourth, this application employs a variable capacitor linearization technique based on stepped bias voltage. This application divides a single variable capacitor into an array of 20 units. Figure 6 And through a series of resistors, a set of progressively increasing bias voltages (VB<19:0>) are generated and applied to each cell. Figure 7 The gate of the NMOS varactor. This move "shifts" the CV characteristic curve of each cell, so that their total capacitance change curve under the control of the tuning voltage VTUNE ( Figure 9The right side is broadened and linearized, thus greatly extending the linear tuning range of the VCO. This design approach, which simulates linearization through digital segmented bias, goes beyond a simple single variable capacitor design and demonstrates the inventiveness of the invention.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] 1. This invention has extremely low phase noise. By employing a source follower low-noise bias circuit with digital calibration and a resistor-capacitor feedback network with cross-coupling to the source, this invention effectively suppresses low-frequency noise from the bias branch and the amplifier tube itself, significantly optimizes the overall phase noise performance of the VCO, and can meet the stringent requirements of IoT RF communication for high receiving sensitivity and excellent signal-to-noise ratio.

[0057] 2. This invention features a wide tuning range and high linearity. Its innovative variable capacitor array structure achieves a wide frequency coverage and highly linear voltage-controlled gain (KVCO) by "shifting" the CV curve using a stepped bias voltage. Figure 10 As shown. This not only improves the chip's ability to cope with process variations and cover multiple frequency bands, but also simplifies the loop design of the phase-locked loop (PLL) and improves system stability;

[0058] 3. This invention features stable output amplitude and low power consumption. By using a digital amplitude calibration circuit to detect oscillation peaks in real time and dynamically adjusting the number of operating units in the cross-coupled amplifier array, this invention ensures that the output signal amplitude remains constant despite variations in process technology, voltage, and temperature (PVT). This avoids using excessive quiescent current to guarantee oscillation under worst-case conditions, thereby significantly reducing VCO power consumption while ensuring reliability.

[0059] 4. This invention has high reliability and consistency. The improved switched capacitor unit circuit provides a stable DC potential for the NMOS switch in the off state, fundamentally eliminating the frequency uncertainty and low-frequency noise caused by node potential drift, and improving the long-term stability of VCO operation and product consistency.

[0060] 5. This invention features a compact structure and easy integration. It mainly adopts digital and analog modules under standard CMOS technology, with a clear circuit structure and well-defined functions of each part. It is very suitable for the high integration, miniaturization and low cost design requirements of IoT RF communication chips. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of the low-noise voltage-controlled oscillator circuit described in Embodiment 1 of the present invention;

[0062] Figure 2This is a circuit diagram of the bias circuit described in Embodiment 1 of the present invention;

[0063] Figure 3 This is a circuit diagram of the cross-coupled amplification unit array described in Embodiment 1 of the present invention;

[0064] Figure 4 This is a circuit diagram of the amplification unit circuit described in Embodiment 1 of the present invention;

[0065] Figure 5 This is a circuit diagram of the switched capacitor unit circuit described in Embodiment 1 of the present invention;

[0066] Figure 6 This is a circuit diagram of the variable capacitor array circuit described in Embodiment 1 of the present invention;

[0067] Figure 7 This is a circuit diagram of the variable capacitor unit circuit described in Embodiment 1 of the present invention;

[0068] Figure 8 This is a circuit diagram of the conventional voltage-controlled oscillator circuit described in Embodiment 1 of the present invention;

[0069] Figure 9 The left figure shows the CV curve of the variable capacitor unit described in Embodiment 1 of the present invention. The left figure shows the CV curve of the variable capacitor unit through different bias shifts, and the right figure shows the CV curve of the linear variable capacitor unit generated by superposition.

[0070] Figure 10 This is the PVT curve of the gain of the simulated voltage-controlled oscillator described in Embodiment 1 of the present invention. Detailed Implementation

[0071] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings;

[0072] Example 1:

[0073] A low-noise voltage-controlled oscillator circuit, the structure and principle of which are as follows: Figure 1 As shown, to address the drawback of excessively high bias noise in existing technologies, this low-noise voltage-controlled oscillator circuit employs source follower technology for tracking. Figure 2 The VB and current negative feedback achieve output voltage regulation. Voltage calibration ensures the output voltage Vreg reaches the target voltage, making it suitable for intermittent operation. Combined with a single-ended PMOS source follower, the noise of the bias circuit is reduced by half.

[0074] To address the instability issues caused by variations in oscillator amplitude due to process variations, operating frequency, and PVT operating conditions, and the need to ensure a certain oscillation margin by using a larger current to guarantee normal operation of the oscillator at all times, this application's voltage-controlled oscillator circuit design incorporates an oscillator amplifier unit array, peak detection, and calibration methods. This ensures the consistency and reliability of the oscillator under PVT conditions, reduces current, improves phase noise performance, reduces low-frequency noise of the amplifier MOS through source resistor feedback, and maintains unaffected high-frequency signal amplification of the oscillator through source capacitor filtering.

[0075] The switched capacitor array widens the frequency coverage range, and this switched capacitor method avoids the drift of the source and drain of the NMOS after the traditional switched NMOS transistor is turned off, which is not a fixed potential and affects the performance.

[0076] To address the shortcomings of current variable capacitor circuits, such as small tuning range and poor linearity, this invention designs a wide-linearity adjustable capacitor array in its low-noise voltage-controlled oscillator circuit. By splitting the traditional single MOS variable capacitor and applying different bias voltages, the tuning capacitance curve of each variable capacitor unit is shifted, thereby widening the voltage adjustment range and improving the linearity of the variable capacitor. Figure 9 The diagram shows the linearity of the variable capacitor using a new variable capacitor structure, which greatly extends the linear range of the voltage. Figure 10 The figure shows the gain curve of the voltage-controlled oscillator under PVT conditions. As can be seen from the figure, its gain is very linear.

[0077] In this embodiment, the overall connection relationship of the low-noise voltage-controlled oscillator circuit is as follows:

[0078] The output of the bias circuit is connected to the bias power supply of the cross-coupled amplifier circuit.

[0079] The input control terminal calamp<3:0> of the cross-coupled amplifier circuit is connected to the output terminal of the digital logic control circuit. At the same time, its differential output terminal is connected to the resonant terminal of the variable capacitor circuit and the switched capacitor circuit array, which together form a resonant circuit, where the resonant inductance is L1.

[0080] The input voltage control terminal of the variable capacitor circuit receives the control voltage VTUNE, and its differential output terminals are vcop and vcon, which are connected to the resonant terminal of the cross-coupled amplifier circuit.

[0081] The switched capacitor circuit array SWCAP<7:0> is composed of... Figure 5The circuit consists of weighted parallel switching capacitor units; the control signal calcap<7:0> of the 8-switched capacitor array adjusts the capacitance of the LC oscillation slot of the oscillator to increase the frequency coverage of the voltage-controlled oscillator. Its resonant terminal is connected to the resonant terminal of the cross-coupled amplifier circuit.

[0082] The input of the peak detection circuit is connected to the output of the cross-coupled amplifier circuit to detect the peak value of the output signal. Its output, pkdout, is connected to the input of the digital logic control circuit.

[0083] The output terminal calamp<3:0> of the digital logic control circuit is connected to the control terminal of the cross-coupled amplifier circuit. It is used to adjust the number of switches on the cross-coupled amplifier circuit according to the peak detection result, thereby adjusting the oscillation amplitude of the oscillator to the target amplitude.

[0084] In this embodiment, the circuit structure of the bias circuit is as follows: Figure 2 As shown, the connection is implemented as follows:

[0085] a. Bias current generation and mirror branch:

[0086] The digital calibration signal Calib<3:0> is connected to the control terminal of the programmable current source MIRIB to adjust the magnitude of the bias current;

[0087] The output of the programmable current source MIRIB is connected to the drain of the NMOS transistor NM4. The gate and drain of NM4 are shorted to form a bias voltage VB. The source of NM4 is grounded through resistor R5, forming a discharge path for the bias current.

[0088] The gates of PMOS transistors PM1, PM2, and PM3 are all connected to the drain of PM1, forming a current mirror structure that mirrors the bias current to the subsequent branches.

[0089] b. Main bias voltage generation branch:

[0090] The drain of PMOS transistor PM1 is connected to the drain of NMOS transistor NM1. The gate of NM1 is shorted to the drain, and its source is grounded through resistor R1, forming the first stage of current-to-voltage conversion.

[0091] The drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM2, the gate of NM2 is connected to the drain of NM1, and its source is grounded through resistor R1 to achieve current replication and voltage follower feedback.

[0092] The drain of PMOS transistor PM3 is connected to the drain of NMOS transistor NM3, the gate of NM3 is connected to the gate of NM2, and its source is grounded through resistor R2, further replicating the current and generating the intermediate node voltage.

[0093] The gate of PMOS transistor PM4 is connected to the drain of PM3, and its drain serves as the bias voltage output terminal Vreg. It is also connected to the drain of PM5 via capacitor C2 for stability compensation. The gate of PM4 is connected to capacitor C1, and the other end of C1 is connected to the power supply VDD to improve the high-frequency power supply rejection ratio of the bias circuit.

[0094] c. Detection and filtering branch:

[0095] The gate of PMOS transistor PM5 receives the bias voltage VB, and its source is connected to the output node Vreg. The source is grounded through capacitor C3 to form a filter.

[0096] Resistors R3 and R4 are connected in series between Vreg and ground, and their common node is the detection node VTEST; capacitor C3 is connected between VTEST and ground to filter out noise in the detection signal.

[0097] d. Comparison and calibration branch:

[0098] The comparator's inverting input receives the reference voltage VREF, its non-inverting input receives the detected voltage VTEST, and its output Outv is connected to the input of the bias voltage digital logic calibration circuit. (Bias voltage digital logic calibration circuit)

[0099] The bias voltage digital logic calibration circuit outputs a digital calibration signal Calib<3:0> based on the level state of Outv, which is fed back to the control terminal of the programmable current source MIRIB, forming a closed-loop digital calibration circuit. Adjusting MIRIB ultimately brings Vreg to the target voltage.

[0100] In this embodiment, the structure of the cross-coupled amplification unit array is as follows: Figure 3 As shown, the connection is implemented as follows:

[0101] a. Bias and resonant load connection:

[0102] The amplifier unit array AMP<15:0> consists of 16 amplification unit circuits (such as... Figure 4It consists of (as shown). Its upper nodes rp1 and rp2 are connected to the bias voltage Vreg through resistors RA3 and RA4 respectively, and rp1 and rp2 are connected to ground through capacitors CA3 and CA4 respectively, forming an upper source feedback filter network, which is used to reduce the low-frequency noise of the PMOS transistor in the amplifier unit circuit without reducing the feedback amplification of the high-frequency oscillation signal by the oscillator;

[0103] The lower nodes rn1 and rn2 of the amplifier unit array are grounded through resistors RA1 and RA2, respectively. At the same time, rn1 and rn2 are connected to ground through capacitors CA1 and CA2, respectively, forming a lower source feedback filter network. This network is used to reduce the low-frequency noise of the PMOS transistor in the amplifier unit circuit without reducing the feedback amplification of the oscillator for the high-frequency oscillation signal.

[0104] The differential output terminals of the amplifier unit array are vcon and vcop;

[0105] b. Control signal and output connection:

[0106] The control terminal of the amplifier unit array is cam<15:0>, which controls 16 amplifier unit circuits respectively, and is used to select whether the amplifier unit is working or off.

[0107] Input the digital amplitude calibration control signal Calamp<3:0>; input it to the thermometer encoding module, and output the 16-bit control signal Cam<15:0> after encoding.

[0108] The output terminal Cam<15:0> of the thermometer encoding module is connected to the amplitude calibration control terminal of the amplifier unit array. By selecting the amplifier unit one by one, the digital calibration of the output amplitude is realized.

[0109] c. Amplifier unit circuit (its structure is as follows) Figure 4 (as shown)

[0110] PMOS cross-coupled pair: The source of PMOS transistor PM1 is connected to the upper node rp1, and its gate is connected to the differential output node vcop; the source of PMOS transistor PM3 is connected to the drain of PM1, and its drain is connected to the differential output node vcon, with its gate receiving the control signal campp. The source of PMOS transistor PM2 is connected to the upper node rp2, and its gate is connected to the differential output node vcon; the source of PMOS transistor PM4 is connected to the drain of PM2, and its drain is connected to the differential output node vcop, with its gate receiving the control signal campp. The gates of PM1 and PM2 are cross-connected: the gate of PM1 is connected to vcop, and the gate of PM2 is connected to vcon, forming a cross-coupled structure.

[0111] NMOS cross-coupled pairs: The source of NMOS transistor NM1 is connected to the lower node rn1, and its gate is connected to the differential output node vcop; the source of NMOS transistor NM3 is connected to the drain of NM1, and its drain is connected to the differential output node vcon, with its gate receiving the control signal cam. The source of NMOS transistor NM2 is connected to the lower node rn2, and its gate is connected to the differential output node vcon; the source of NMOS transistor NM4 is connected to the drain of NM2, and its drain is connected to the differential output node vcop, with its gate receiving the control signal cam. The gates of NM1 and NM2 are cross-connected: the gate of NM1 is connected to vcop, and the gate of NM2 is connected to vcon, forming a cross-coupled structure.

[0112] The control signal cam is inverted by inverter inv1 to generate a complementary control signal campp. cam is connected to the gates of NM3 and NM4, and campp is connected to the gates of PM3 and PM4, used to control the on and off of the corresponding MOS transistors, thereby enabling the selection and amplitude adjustment of the amplification unit.

[0113] The drain nodes vcon and vcop of the cross-coupled pair serve as differential output terminals, used to output the amplified oscillation signal.

[0114] In this embodiment, the structure of the switched capacitor unit circuit is as follows: Figure 5 As shown, the connection is implemented as follows:

[0115] a. PMOS branch connection:

[0116] The source of PMOS transistor PMS1 is connected to one end of capacitor CS1 and then to the differential node vcon. The drain is connected to the other end of capacitor CS1 via resistor RS1. The gate receives the digital calibration signal calcap.

[0117] The source of PMOS transistor PMS2 is connected to one end of capacitor CS1 and then to the differential node vcop. The drain is connected to the other end of capacitor CS2 via resistor RS2. The gate receives the digital calibration signal calcap.

[0118] b. NMOS connection:

[0119] The drain of NMOS transistor NMS2 is connected to the common node of CS1 and RS1, the source is grounded, and the gate receives the digital calibration signal calcap.

[0120] The drain of NMOS transistor NMS3 is connected to the common node of CS2 and RS2, the source is grounded, and the gate receives the digital calibration signal calcap.

[0121] The gate of NMOS transistor NMS1 receives the digital calibration signal calcap, the drain is connected to the common node of CS1 and RS1, and the source is connected to the common node of CS2 and RS2.

[0122] c. Differential nodes and control signals:

[0123] Differential nodes vcon and vcop serve as differential ports of the circuit and are connected to the resonant circuit or amplifier circuit.

[0124] The digital control signal calcap simultaneously controls the on / off states of PMS1, PMS2, NMS1, NMS2, and NMS3, achieving digital calibration of the resonant frequency by changing the size of the effective capacitor array. When calcap = "1", the NMOS transistor is on, the PMOS transistor is off, and the switching capacitor is at its maximum. At this time, the source and drain potentials of the NMOS transistor are grounded. When calcap = "0", the NMOS transistor is off, the PMOS transistor is on, and the switching capacitor is at its minimum. At this time, the source and drain potentials of the NMOS transistor are the oscillator's vco and vcop. The PMOS transistor's on state provides a DC potential after the NMOS transistor is off, and this DC potential is the common-mode potential of vcon and vcop.

[0125] Traditional voltage-controlled oscillator circuits, such as Figure 8 As shown, when the NMOS in the switched capacitor array is turned on, the drain and source of the NMOS are shorted to ground together. When the NMOS is turned off, the drain of the NMOS is connected to one plate of the capacitor. At this time, this plate and the NMOS drain node are in a high impedance state. There is no circuit to provide DC potential, so the node level is indeterminate and may be arbitrary. This will cause drift when the oscillator is working, affecting the phase noise performance.

[0126] In this embodiment, the variable capacitor circuit is as follows: Figure 6 The circuit shown consists of a 20-bit stepped-biased variable capacitor unit (e.g.) Figure 7 It consists of ) and its connection implementation is as follows:

[0127] a) Branch generated by resistor series bias:

[0128] The bias voltage Vreg is grounded after being divided by series resistors R19, R18, R17-R3, R2, R1, and R0, forming 20 voltage divider nodes;

[0129] Each voltage divider node outputs its corresponding bias voltage signal VB. <19> VB <18> VB<17:3>, VB <2> VB <1> VB <0> This forms a 20-bit stepped bias voltage VB<19:0>;

[0130] b. Connection of variable capacitor unit array:

[0131] The differential outputs of the variable capacitor unit array (Var<19:0>) are vcon and vcop, which are used to connect to the differential output nodes of the resonant circuit or amplifier circuit.

[0132] The control terminal of the variable capacitor unit array receives a 20-bit bias voltage VB<19:0>, and controls the equivalent capacitance value of each variable capacitor unit by different bias voltages.

[0133] The variable capacitor unit circuit also receives a tuning voltage VTUNE for continuous frequency tuning;

[0134] c. Overall Functionality:

[0135] The stepped bias voltage VB<19:0> generated by the resistor string provides discrete capacitor levels for the variable capacitor array, while the tuning voltage VTUNE enables continuous frequency fine-tuning within each level. Together, they constitute a frequency tuning mechanism that combines coarse and fine tuning.

[0136] d. Variable capacitor unit circuit (such as...) Figure 7 (as shown)

[0137] One end of capacitor CV1 is connected to the differential input node vcon, and the other end is connected to the gate of NMOS transistor NMV3. NMV3 is designed to operate as a variable capacitor.

[0138] One end of capacitor CV2 is connected to the differential input node vcop, and the other end is connected to the gate of NMOS transistor NMV2. NMV2 is designed to operate as a variable capacitor.

[0139] The source and drain of NMOS transistors NMV2 and NMV3 are shorted together and connected to the tuning voltage VTUNE.

[0140] One end of resistor RV3 is connected to the gate of NMOS transistor NMV3, and the other end is connected to the bias voltage VB;

[0141] One end of capacitor CV3 is connected to the gate of NMV3, and the other end is grounded;

[0142] One end of capacitor CV4 is connected to the gate of NMV2, and the other end is grounded;

[0143] Capacitors CV1, CV2, CV3, and CV4, along with NMOS transistors NMV2 and NMV3, form a series-parallel network for capacitor regulation, constituting a variable capacitor. A tuning voltage VTUNE is applied to the source and drain of NMV2 and NMV3 to adjust the equivalent capacitance of the NMOS transistors. A bias voltage VB is applied to the gates of NMV2 and NMV3 to set the operating point of the NMOS transistors. Different bias points shift the capacitance variation range of the variable capacitor unit. By configuring different bias voltages for each unit in the array, the adjustment range can be widened. Differential nodes vcon and vcop serve as the differential ports of the circuit, connected to a resonant circuit or amplifier circuit to achieve continuous tuning of the oscillation frequency.

[0144] As shown in Figure 9, the stepped bias voltage VB<19:0> generated by the resistor string "shifts" the CV curve of each NMOS variable capacitor unit (NMV2, NMV3), thereby achieving a wider and more linear overall tuning characteristic on a macroscopic scale.

[0145] Example 2:

[0146] A voltage-controlled oscillator (VCO) is provided, wherein the VCO adopts the low-noise VCO circuit described in Example 1. The VCO features low phase noise, high linearity tuning, stable output amplitude, and low power consumption operation over a wide frequency band, thereby effectively meeting the requirements of IoT RF communication chips for high-performance local oscillator signal sources.

[0147] Its core lies in the deep integration of digital logic control and analog circuit design to perform refined and automated calibration and management of bias voltage, oscillation amplitude and frequency coverage, thereby achieving robustness of circuit performance under PVT variations.

[0148] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, the phrase "comprising an element defined as..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0149] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A low-noise voltage-controlled oscillator circuit, characterized in that, include: The bias circuit provides a calibrated bias voltage Vreg at its output. A cross-coupled amplifier circuit has a bias power supply terminal that receives the bias voltage Vreg, a control terminal that receives the amplitude calibration signal Calamp, and a differential output terminal (vcop, vcon) that is used to output an oscillation signal. The resonant circuit is connected to the differential output terminal (vcop, vcon) of the cross-coupled amplifier circuit, and is used to jointly determine the oscillation frequency with the cross-coupled amplifier circuit. A peak detection circuit, whose input is connected to the differential output (vcop, vcon) of the cross-coupled amplifier circuit, is used to detect the amplitude of the oscillation signal and output a detection signal (pkdout); and A digital logic control circuit receives the detection signal (pkdout) at its input terminal and outputs the amplitude calibration signal Calamp to the cross-coupled amplifier circuit at its output terminal, so as to adjust the working state of the cross-coupled amplifier circuit according to the detected amplitude, thereby calibrating the oscillation amplitude to the target value. The bias circuit includes: The programmable current source MIRIB receives the bias calibration signal Calib at its control terminal. A current mirror structure is used to mirror the current generated by the programmable current source; The output stage includes a source follower PM5, whose gate receives the bias voltage VB generated by the current mirror structure, and whose source serves as the output terminal of the bias voltage Vreg. A voltage divider filter network is connected between the output terminal of the bias voltage Vreg and ground to generate the detection voltage VTEST. A comparator whose two inputs receive a reference voltage VREF and a detection voltage VTEST, respectively; and The bias voltage digital logic calibration circuit has its input connected to the output of the comparator and its output output the bias calibration signal Calib to the programmable current source MIRIB, forming a closed-loop calibration circuit. The cross-coupled amplifier circuit includes an array composed of multiple amplifier unit circuits; The amplitude calibration signal Calamp output by the digital logic control circuit is encoded and used to select or turn off the amplification unit circuits one by one to finely adjust the total transconductance and realize digital calibration of the oscillation amplitude.

2. The voltage-controlled oscillator circuit according to claim 1, characterized in that, Each of the aforementioned amplification unit circuits includes: The PMOS cross-coupled pair includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The gate of the first PMOS transistor PM1 is connected to the output terminal vcop, and the gate of the second PMOS transistor PM2 is connected to the output terminal vcon. The control switching transistors include a third PMOS transistor PM3 and a fourth PMOS transistor PM4. The source of the third PMOS transistor PM3 is connected to the drain of the first PMOS transistor PM1, and the drain of the third PMOS transistor PM3 is connected to the output terminal vcon. The source of the fourth PMOS transistor PM4 is connected to the drain of the second PMOS transistor PM2, and the drain of the fourth PMOS transistor PM4 is connected to the output terminal vcop. The gates of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 jointly receive a first control signal campp. The sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both connected to a first resistor-capacitor filter network (rp1, rp2). The NMOS cross-coupled pair includes a first NMOS transistor NM1 and a second NMOS transistor NM2. The drain of the first NMOS transistor NM1 is connected to the source of a third NMOS transistor NM3, and the drain of the third NMOS transistor NM3 is connected to the output terminal vcon. The drain of the second NMOS transistor NM2 is connected to the source of a fourth NMOS transistor NM4, and the drain of the fourth NMOS transistor NM4 is connected to the output terminal vcop. The gate of the first NMOS transistor NM1 is connected to the output terminal vcop, and the gate of the second NMOS transistor NM2 is connected to the output terminal vcon. The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 jointly receive the control signal cam. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are both connected to a second resistor-capacitor filter network (rn1, rn2).

3. The voltage-controlled oscillator circuit according to claim 2, characterized in that, In the amplification unit circuit, the source of the PMOS cross-coupled pair is connected to the bias voltage Vreg through the first resistor-capacitor filter network (rp1, rp2), and the source of the NMOS cross-coupled pair is grounded through the second resistor-capacitor filter network (rn1, rn2). The source of the PMOS cross-coupled pair includes the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2, and the source of the NMOS cross-coupled pair includes the source of the first NMOS transistor NM1 and the source of the second NMOS transistor NM2. The first resistor-capacitor filter network and the second resistor-capacitor filter network are used to suppress low-frequency noise of the amplifier tube while allowing high-frequency oscillation signals to pass through.

4. The voltage-controlled oscillator circuit according to claim 1, characterized in that, The resonant circuit includes a switched capacitor circuit array connected to the differential output terminal (vcop, vcon) and receiving a capacitor calibration signal calcap from the digital logic control circuit or an external controller for coarse adjustment of the oscillation frequency.

5. The voltage-controlled oscillator circuit according to claim 4, characterized in that, The switched capacitor circuit array is composed of multiple switched capacitor unit circuits; each switched capacitor unit circuit includes: A first capacitor CS1 and a second capacitor CS2 are connected, with one end of the first capacitor CS1 connected to the output terminal vcon and one end of the second capacitor CS2 connected to the output terminal vcop. A first PMOS switch PMS1 and a second PMOS switch PMS2 are connected. The source of the first PMOS switch PMS1 is connected to one end of the first capacitor CS1 and the output terminal vcon, and the drain of the first PMOS switch PMS1 is connected to the other end of the first capacitor CS1 through a resistor RS1. The source of the second PMOS switch PMS2 is connected to one end of the second capacitor CS2 and the output terminal vcop, and the drain of the second PMOS switch PMS2 is connected to the other end of the second capacitor CS2 through a resistor RS2. The three NMOS transistors are: a first NMOS switch NMS1, a second NMOS switch NMS2, and a third NMOS switch NMS3. The drain of the first NMOS switch NMS1 is connected to the other end of the first capacitor CS1, the source of the first NMOS switch NMS1 is connected to the other end of the second capacitor CS2, the drain of the second NMOS switch NMS2 is connected to the other end of the first capacitor CS1, and the source of the second NMOS switch NMS2 is grounded. The drain of the third NMOS switch NMS3 is connected to the other end of the second capacitor CS2, and the source of the third NMOS switch NMS3 is grounded. The gates of the first PMOS switch PMS1, the second PMOS switch PMS2, the first NMOS switch NMS1, the second NMOS switch NMS2, and the third NMOS switch NMS3 jointly receive the capacitance calibration signal calcap. When the capacitance calibration signal calcap = 1, the first PMOS switch PMS1 and the second PMOS switch PMS2 are turned off, and the first NMOS switch NMS1, the second NMOS switch NMS2, and the third NMOS switch NMS3 are turned on. When the capacitance calibration signal calcap = 0, the first PMOS switch PMS1 and the second PMOS switch PMS2 are turned on, and the first NMOS switch NMS1, the second NMOS switch NMS2, and the third NMOS switch NMS3 are turned off, providing a stable DC potential for the floating node.

6. The voltage-controlled oscillator circuit according to claim 1, characterized in that, The resonant circuit also includes a variable capacitor array circuit, which is connected to the differential output terminal (vcop, vcon) and receives the tuning voltage VTUNE for fine-tuning the oscillation frequency.

7. The voltage-controlled oscillator circuit according to claim 6, characterized in that, The variable capacitor array circuit includes: A resistor series voltage divider network, connected between the bias voltage Vreg and ground, generates multiple stepped bias voltages; and An array consisting of multiple variable capacitor unit circuits, each of which receives a stepped bias voltage at its control terminal and a common tuning voltage VTUNE at its tuning terminal, and its differential terminal is connected to the differential output terminal (vcop, vcon). By shifting the CV characteristics of each unit under different bias voltages, the overall tuning characteristics with a wide linear range are superimposed.

8. The voltage-controlled oscillator circuit according to claim 7, characterized in that, Each of the variable capacitor unit circuits includes: The first NMOS varactor NMV2 and the second NMOS varactor NMV3 are short-circuited with the source and drain of the first NMOS varactor NMV2 and the source and drain of the second NMOS varactor NMV3 and are connected together to the tuning voltage VTUNE. A first DC blocking capacitor CV1 and a second DC blocking capacitor CV2 are connected. One end of the first DC blocking capacitor CV1 is connected to the output terminal vcon, and the other end is connected to the gate of the second NMOS varactor NMV3. One end of the second DC blocking capacitor CV2 is connected to the output terminal vcop, and the other end is connected to the gate of the first NMOS varactor NMV2. Bias resistors RV2 and RV3 are provided, wherein bias resistor RV3 is connected between the gate of the second NMOS varactor NMV3 and the corresponding stepped bias voltage VB; and bias resistor RV2 is connected between the gate of the first NMOS varactor NMV2 and the corresponding stepped bias voltage VB. as well as Filter capacitors CV3 and CV4 are provided. Filter capacitor CV3 is connected between the gate of the second NMOS varactor NMV3 and ground, and filter capacitor CV4 is connected between the gate of the first NMOS varactor NMV2 and ground.

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