A high-speed data transmission communication method for a double data rate memory interface

Abstract

The application belongs to the technical field of memory interface and data transmission, and relates to a high-speed data transmission communication method of a double data rate memory interface. The application extracts traffic characteristics through a neural network to predict a direction switching time and calculate phase synchronization compensation, combines dynamic delay deviation and load ratio to calculate sampling compensation, accurately generates a transceiving cooperative scheduling strategy according to historical average propagation delay and hardware response time, cooperates with a check coding, hierarchical scheduling and avoidance retransmission mechanism, solves core problems such as bus timing step loss, link dynamic jitter offset, control signaling and service data conflict and state synchronization recovery lag in direction switching in high-speed bidirectional transmission, realizes accurate active capture of a transceiving switching boundary and dynamic accurate alignment of a data sampling edge, ensures conflict-free priority mapping transmission of key timing signaling, effectively shortens a fault recovery period, and comprehensively improves high-speed link transmission accuracy and overall cooperative efficiency.

Description

Technical Field

[0001] This invention belongs to the field of memory interface and data transmission technology, and relates to a high-speed data transmission communication method for a double data rate memory interface. Background Technology

[0002] Double Data Rate (DDR) memory interfaces are widely used in computing and embedded systems, achieving high-bandwidth interaction by transmitting data simultaneously on both the rising and falling edges of the clock. As interface speeds continue to increase and the effective data window narrows, timing deviations and dynamic disturbances in the transmission link have a more pronounced impact on communication quality.

[0003] In DDR memory interface read and write operations, the timing of direction switching is typically determined based on preset delay parameters or thresholds for specific signals. This type of fixed-rule approach may result in discrepancies between the determined switching boundaries and the actual transmission state when bus traffic changes dynamically. Even slight deviations in switching timing can lead to bus conflicts or data sampling window offsets, reducing the accuracy of effective data transmission.

[0004] For clock synchronization and sampling position adjustment, the delay-locked loop within the interface is often adjusted using a periodic calibration sequence or an initially configured phase compensation value. When the transmission delay of the physical link changes due to variations in environmental conditions such as temperature and voltage, or load fluctuations, the sampling point may deviate from its optimal position, increasing the probability of bit errors during data recovery.

[0005] In terms of transmission scheduling, when control information and service data share a queue, the indications for bearer timing adjustments and state switching may be delayed due to the continuous transmission of service data, thus failing to arrive before the optimal time for the peer to perform the corresponding operation. Furthermore, if the time window fixed by internal maintenance operations is not considered during scheduling, transmission slot conflicts may occur, leading to rescheduling delays and impacting overall transmission efficiency.

[0006] For error handling, typical retransmission mechanisms use a consistent processing method for all types of information. When a transmission error occurs, if the control indication used for state switching requires a long retransmission process of service data, it will introduce additional recovery delay, causing the state synchronization at both ends of the interface to lag behind the actual timing requirements. Summary of the Invention

[0007] In view of this, in order to solve the problems mentioned in the background technology, a high-speed data transmission communication method with a double data rate storage interface is proposed.

[0008] The objective of this invention can be achieved through the following technical solution: a high-speed data transmission communication method for a double data rate storage interface, comprising: collecting historical transmit and receive timing parameters and burst length parameters of the double data rate storage interface, and inputting them into a recurrent neural network to extract transmission traffic feature vectors.

[0009] If the rate of change of the Euclidean distance of the transmission traffic characteristic vector exceeds the limit, the moment of switching the transmission and reception directions is determined, and the number of compensation steps is calculated by combining the phase time difference and the minimum delay adjustment step size to obtain the synchronization compensation command.

[0010] A scheduling queue is constructed based on the time of switching between transmit and receive directions. Dynamic delay deviation and link dynamic jitter offset are calculated based on propagation delay and load ratio to obtain sampling compensation parameters. Terminal switching advance is obtained based on hardware response time, and transmit and receive coordinated scheduling strategy is generated.

[0011] The control message and corresponding data message containing synchronization compensation instructions, terminal handover advance and sequence number are constructed by the transmit and receive coordinated scheduling strategy. After performing cyclic redundancy check encoding on the control message, hierarchical scheduling is performed, and backoff and rescheduling are performed when scheduling conflicts are detected.

[0012] The received control messages are verified. If the verification is successful, the message is parsed and sampled for correction and terminal state switching is performed. If the verification of the control message or data message is abnormal, the corresponding retransmission is performed.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The present invention extracts the transmission traffic feature vector through a recurrent neural network and calculates the Euclidean distance change rate to determine the switching time of the transmission and reception direction. It combines the phase time difference and the minimum delay adjustment step size to calculate the number of compensation steps to obtain the synchronization compensation command. This method solves the problem of switching boundary deviation caused by fixed rules when the bus traffic changes dynamically, realizes accurate capture of switching time and phase advance compensation, eliminates bus conflicts and sampling window offset, and improves the accuracy of effective data transmission.

[0014] (2) This invention calculates the dynamic delay deviation by acquiring the current propagation delay in real time, obtains the load ratio by combining the bus load and the reference load ratio, and multiplies it by a preset normalization coefficient to obtain the link dynamic jitter offset to generate sampling compensation parameters. This method solves the problem of sampling point deviation caused by changes in transmission delay due to temperature and voltage changes or load fluctuations, realizes dynamic fine-tuning of the sampling clock edge and precise alignment with the center of the data eye diagram, reduces the probability of bit errors, and ensures the link sampling accuracy.

[0015] (3) This invention constructs control messages and data messages by parsing the transmit-receive coordinated scheduling strategy, performs hierarchical scheduling after executing cyclic redundancy check coding, and detects overlapping internal refresh instruction time slots to perform backoff and rescheduling. This method solves the problems of control instructions being delayed due to service data blocking in the shared queue and transmission conflicts caused by failure to avoid internal maintenance time slots, ensuring that key timing instructions are preferentially mapped and that refresh cycles are transmitted without conflict, eliminating rescheduling delays, and improving overall scheduling efficiency.

[0016] (4) This invention verifies control messages and sends a negative response to trigger priority retransmission when an anomaly occurs, thus solving the problem of additional delay introduced by the traditional mechanism when control instructions wait for business data retransmission. Based on hierarchical scheduling and isolation, data packets are suspended during retransmission. After the control plane is independently restored, the corresponding data packets are retransmitted as needed according to the sequence number, avoiding the lag in state synchronization at both ends of the interface and shortening the fault recovery cycle. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a high-speed data transmission communication method for a double data rate storage interface according to the present invention;

[0019] Figure 2 This is a flowchart of the method for obtaining synchronization compensation instructions in this invention;

[0020] Figure 3 This is a flowchart of the method for generating the transmit / receive coordinated scheduling strategy in this invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0023] The following description, in conjunction with the accompanying drawings, details a specific scheme for a high-speed data transmission communication method using a double data rate storage interface provided by the present invention.

[0024] Please see Figure 1 As shown, the implementation of this invention includes S1 to S5: Addressing the issues of timing misalignment and link jitter that easily occur when switching between high-speed transmit and receive directions in double data rate storage interfaces, this invention proposes a cooperative scheduling communication method based on traffic feature prediction and dynamic parameter compensation. This method first uses a recurrent neural network to extract transmission traffic feature vectors from historical transmit and receive timing and burst length parameters. It then predicts the transmit and receive direction switching time by calculating the rate of change of the Euclidean distance between feature vectors at adjacent times. Finally, it calculates the compensation steps by combining the phase time difference at that time with the minimum adjustment step size of the delay-locked loop, generating a synchronization compensation command to achieve active alignment of the front-end timing.

[0025] After the handover time is determined, a read / write scheduling queue is constructed. The real-time propagation delay deviation and the bus load ratio are fused to calculate the dynamic jitter offset of the link to obtain the sampling compensation parameters. At the same time, the sum of the historical average propagation delay and the terminal hardware response time is used as the transmission advance to determine the timing of control message transmission. The hardware response time is used as the terminal handover advance separately. Synchronization, sampling correction and direction reversal are uniformly arranged into a transmit / receive coordinated scheduling strategy that is executed precisely on time.

[0026] At the transmission execution layer, this strategy is parsed into control messages and data messages carrying synchronization compensation instructions and terminal handover advance. After being encoded by cyclic redundancy check, the control messages are sent preferentially through hierarchical scheduling, and a time slot delay backoff mechanism is constructed to address internal refresh instruction conflicts. The receiving end verifies the control messages, and after passing the verification, it parses and executes the sampling correction and pin level flipping of the delay-locked loop. Combined with the control message retransmission and data message hierarchical verification and retransmission strategy, a high-reliability, low-latency, high-speed data transmission closed loop is achieved in complex physical link environments.

[0027] S1. Collect historical transmit and receive timing parameters and burst length parameters of the double data rate storage interface, and input them into a recurrent neural network to extract the transmission traffic feature vector.

[0028] Under high-speed read / write operations, the timing parameters and burst length of the double data rate storage interface reflect the load status and transmission patterns of the link. Relying solely on static thresholds for judgment is susceptible to burst noise interference, and recurrent neural networks possess the ability to extract deep evolutionary features from timing data. Therefore, this step collects historical transmit / receive timing parameters and burst length parameters, inputs them into a recurrent neural network to extract transmission traffic feature vectors, and provides a quantitative basis for subsequent transmit / receive direction switching determination.

[0029] In one specific embodiment, a parameter monitoring register group is set up in the physical layer control module of the double data rate storage interface. This register group continuously collects historical transmit / receive timing parameters and burst length parameters at a fixed sampling period. The historical transmit / receive timing parameters include read / write request interval time, clock cycle offset, and data valid window duration. The burst length parameters include the burst length of consecutive read operations and the burst length of consecutive write operations. As an example, the sampling period can be configured according to the interface operating frequency, with a typical range of 5 microseconds to 20 microseconds.

[0030] Specifically, the above parameters are obtained in the sampling window in the following ways: The read / write request interval time is obtained by monitoring read commands and write commands on the bus. Whenever two adjacent valid read / write requests are detected, an internal counter is started to measure the number of clock cycles between them. At the end of the sampling window, all interval count values ​​are summed and divided by the number of occurrences to obtain the read / write request interval time.

[0031] The clock cycle offset is obtained by continuously comparing the alignment deviation between the rising edge of the data strobe signal and the system clock signal, and recording the absolute value of the maximum offset that occurs in each sampling window as the clock cycle offset.

[0032] The data valid window duration is obtained as follows: using independent hardware logic, the phase interval from 0 to 1 clock cycles is scanned asynchronously in 10 picosecond steps. The error rate of at least 1024 data bits in each phase is counted, and the width of the error-free continuous phase interval is taken as the scan result and cached in a register. At the beginning of each sampling window, such as 10 microseconds, the latest scan result cached in the register is read directly and taken as the data valid window duration for that sampling window.

[0033] The burst length is obtained as follows: for continuous read operations and continuous write operations respectively, the data length of each continuous burst transmission within each sampling window is counted and its average value is calculated, which is used as the burst length of continuous read operations and the burst length of continuous write operations respectively.

[0034] The multi-dimensional parameters collected within multiple consecutive sampling windows are used to form a sequence of input samples arranged in time steps, which are then sequentially fed into a pre-trained recurrent neural network. As an example, this recurrent neural network can adopt a Long Short-Term Memory (LSTM) network structure, including an input layer, a single-layer LSTM layer with 64 hidden units, and an output layer. The output vector at each time step serves as the transmission traffic feature vector for the corresponding sampling window.

[0035] The model parameters of the recurrent neural network are obtained through offline training: historical samples of the double data rate storage interface under continuous read / write and random read / write conditions are collected to construct a training set. Whether a switch in the transmit / receive direction actually occurs after the current time window is used as a binary label (1 indicates a switch has occurred, 0 indicates no switch has occurred). The loss function is to minimize the cross-entropy loss between the network output vector and the label. The network weights are iteratively updated using a time-based backpropagation algorithm. After training, the converged network weight parameters are fixed in the storage medium of the embedded controller.

[0036] During the online operation phase, at the end of each sampling window, the controller calls the fixed network parameters and inputs the latest input sample vector into the recurrent neural network to perform a forward propagation calculation. The 8-dimensional floating-point vector output by the network can then be used as the transmission traffic feature vector corresponding to the current window.

[0037] S2. If the rate of change of the Euclidean distance of the transmission flow characteristic vector exceeds the limit, the moment of switching the transmission and reception direction is determined. The number of compensation steps is calculated by combining the phase time difference and the minimum delay adjustment step size to obtain the synchronization compensation command.

[0038] In high-speed bidirectional transmission, the switching of the transmission and reception directions will cause instantaneous jumps in the clock phase and changes in the propagation path. If the switching boundary cannot be accurately captured and clock alignment cannot be performed in time, it will lead to the closure of the sampling eye diagram at the receiving end and data errors. Therefore, by continuously monitoring the spatial distance changes of the feature vector and combining the adjustment of the physical constraints of the hardware-level delay-locked loop to perform step size conversion, the connection from software feature mutation to hardware phase compensation can be realized.

[0039] In one specific embodiment, the method for obtaining the transmission and reception direction switching time is as follows: calculate the Euclidean distance of the transmission traffic feature vectors of adjacent time windows, and obtain the rate of change of the vectors with respect to the time window. When the rate of change exceeds the preset direction switching threshold, it is determined that the current transmission and reception direction switching boundary is reached, and the current value of the system clock counter is immediately latched and recorded as the transmission and reception direction switching time.

[0040] The method for determining the preset direction switching threshold is as follows: During the system initialization phase, at least 100 consecutive time windows of Euclidean distance change rate samples are collected from the double data rate storage interface under stable read and write operation states. The statistical maximum values ​​are calculated for each sample, and the larger of the two values ​​is multiplied by a safety factor to obtain the preset direction switching threshold. This safety factor can be adjusted according to the actual link noise level, with a typical value of 1.3.

[0041] After obtaining the transmission and reception direction switching time in the above manner, considering that at the instant the transmission and reception direction of the bus is reversed, the clock tree path and transmission link impedance characteristics of the data strobe signal will change, resulting in an instantaneous alignment deviation between the actual sampling clock phase of the receiver and the reference clock. Therefore, it is necessary to quantify this deviation and convert it into a hardware-executable adjustment quantity.

[0042] Please see Figure 2 As shown, the method for obtaining the synchronization compensation command includes the following steps: S201, obtaining the phase difference between the actual clock signal phase corresponding to the transmit / receive direction switching moment and the reference clock of the double data rate storage interface, and converting the phase difference into a phase time difference value in units of time. Specifically, at the transmit / receive direction switching moment, the phase detector simultaneously captures the rising edge of the data strobe signal and the rising edge of the reference clock, and quantizes the time difference between the two rising edges into a digital code value through the internal time-to-digital converter. The phase time difference value is obtained by multiplying the code value by the TDC resolution.

[0043] S202. By reading the control configuration register of the delay-locked loop, the inherent minimum delay adjustment step size determined by the chip process and internal delay unit circuit is obtained. The phase time difference is divided by the minimum delay adjustment step size. Since the hardware can only perform discrete adjustment in integer multiples of the step size, in order to ensure that the compensation amount can completely cover the phase deviation, the calculated quotient is rounded up to obtain the compensation step size. Then, the integer value of the compensation step size is written into the bit field specified in the header of the control message according to the message protocol format, and a synchronization compensation identifier code is attached to complete the packaging of the synchronization compensation instruction.

[0044] This synchronization compensation command indicates the time length corresponding to the product of the sampling clock phase adjustment compensation step number and the minimum delay adjustment step size required by the receiving end, so as to align the sampling point with the center of the data eye diagram and eliminate the sampling phase deviation when switching the transmission and reception directions.

[0045] S3. Construct a scheduling queue based on the time of switching between transmit and receive directions, calculate the dynamic delay deviation and link dynamic jitter offset based on the propagation delay and load ratio to obtain sampling compensation parameters, and obtain the terminal switching advance based on the hardware response time to generate a transmit-receive coordinated scheduling strategy.

[0046] Because physical links are subject to interference from voltage fluctuations, temperature drift, and sudden load surges during operation, the propagation delay will dynamically shift. If terminal switching is performed solely based on a fixed timing margin, sampling point shifts or even data loss may occur due to dynamic jitter. Therefore, this step executes a dynamic compensation mechanism based on real-time delay deviation and load ratio calculation in the scheduling queue and issues terminal switching instructions in advance, which can effectively eliminate the negative impact of link uncertainty on sampling accuracy.

[0047] In one specific embodiment, please refer to Figure 3 As shown, the method for generating the transmit / receive coordinated scheduling strategy includes the following steps: S301, taking the transmit / receive direction switching time as the dividing point, dividing the time axis before and after the dividing point into read scheduling time slots and write scheduling time slots, and inserting the synchronization compensation instruction into one clock cycle before the dividing point to form a scheduling queue.

[0048] The scheduling queue is a list of events arranged in chronological order. Each event contains an execution time represented by a clock cycle count and a corresponding operation instruction. This queue is stored in the controller's cache and is retrieved and executed sequentially by the scheduler.

[0049] S302. Real-time acquisition of the current propagation delay of the physical link. Specifically, the sending end records the local clock count value when issuing a read command to the double data rate storage interface, and records the clock count value when the data strobe signal returned by the receiving end arrives effectively. Based on the time difference between the two, after deducting the fixed number of clock cycles corresponding to the inherent read latency (CAS Latency and additional delay) in the protocol specification, half of the remaining time difference is taken to estimate the current propagation delay.

[0050] The dynamic delay bias is obtained by subtracting the pre-stored historical average propagation delay from the current propagation delay. As an example, the historical average propagation delay is a moving average of the most recent 100 measurements.

[0051] Real-time monitoring of the current bus load, i.e., the number of clock cycles in which the bus data strobe signal is in a valid toggling state per unit time, is used to calculate the proportion of this load to the total number of clock cycles within the window, which is then taken as the current bus load. A preset reference load, such as 50% of the interface's maximum theoretical bandwidth, is obtained, and the ratio of the current load to this reference load is calculated to obtain the load ratio.

[0052] The dynamic delay deviation, load ratio, and preset normalization coefficient are multiplied together to obtain the link dynamic jitter offset. The preset normalization coefficient is obtained by measuring the actual sampling point offset changes when only the dynamic delay deviation changes and when only the load ratio changes during the offline calibration phase of the system. The influence weights of the dynamic delay deviation and load ratio on the sampling point offset are fitted by the least squares method, and the weights are used as the normalization coefficient.

[0053] The sampling compensation parameter is generated by adding the dynamic jitter offset of the link to the time offset corresponding to the preset fixed phase deviation value. This sampling compensation parameter is in time units and is used to instruct the receiver to further advance or delay the sampling clock. The preset fixed phase deviation value is the fixed offset between the actual sampling point and the center of the data eye diagram under ideal no-load and no-temperature drift conditions of the link.

[0054] The historical average propagation delay is used as the baseline one-way flight time, and the hardware response time required for the terminal pin direction reversal of the double data rate storage interface is added to this value. The sum is used as the transmission advance. The hardware response time is used separately as the terminal switching advance. The hardware response time can be obtained from the interface chip's datasheet, and a typical value is 2 to 5 clock cycles.

[0055] S303. Insert the transmission advance as a scheduling event into the corresponding time slot node in the scheduling queue, and configure the synchronization compensation instruction and sampling compensation parameter already in the scheduling queue as the scheduling and receiving end sampling attributes in the time slot. Encapsulate the terminal switching advance into the control message to be generated, thereby generating a transmit-receive coordinated scheduling strategy.

[0056] It should be noted that the transmission advance is used by the sending end to schedule the transmission timing of the control message. The terminal switching advance is transmitted to the receiving end along with the control message. After receiving the control message, the receiving end only needs to wait for the hardware response time to trigger the pin flip, thereby ensuring that the direction switch is accurately completed at the expected switching time and avoiding additional offset caused by propagation delay.

[0057] The transmit / receive coordinated scheduling strategy includes the following information: the boundary division of read / write scheduling time slots, the start and end times of each time slot, the synchronization compensation instruction and its execution time, the sampling compensation parameters and their application time, the scheduling time slot node corresponding to the transmission advance, and the terminal handover advance that needs to be encapsulated in the control message.

[0058] S4. The control message and the corresponding data message containing the synchronization compensation instruction, terminal handover advance and sequence number are constructed by the transmit and receive coordinated scheduling strategy. After performing cyclic redundancy check encoding on the control message, hierarchical scheduling is performed, and backoff and rescheduling are performed when scheduling conflicts are detected.

[0059] Considering that in complex bus interaction environments, control messages carrying critical timing compensation parameters have the highest transmission priority and integrity, and that the double data rate storage interface has periodic refresh operations, if the control message and refresh instruction collide in the time slot, it will lead to the loss of control signaling or bus deadlock. Therefore, this step constructs independently encapsulated control messages and data messages, implements high and low priority preemption scheduling, and performs time slot collision detection and backoff before transmission to ensure the lossless transmission of critical control signaling and the safety of bus timing.

[0060] In one specific embodiment, the control message and the corresponding data message are first obtained, and the contents are as follows: the transmit and receive coordination scheduling strategy is parsed, the synchronization compensation instruction, the terminal handover advance and the data message sequence number associated with the current time slot are encapsulated into the message header to generate the control message; the service data to be transmitted is divided into fixed-length data blocks and a sequence number is added to generate the data message.

[0061] After generating control and data messages using the above method, to ensure the integrity and priority of the control messages during transmission and avoid conflicts with the internal refresh operations of the storage interface, it is necessary to further verify and encode the control messages, and perform hierarchical scheduling and conflict backoff processing. Therefore, after performing cyclic redundancy check encoding on the control messages, hierarchical scheduling is performed, and backoff and rescheduling are executed when scheduling conflicts are detected. The specific content is as follows: The CRC-16 standard generator polynomial is used to perform bit-by-bit XOR calculation on the data bits of the control messages. The calculation range covers all data bits of the control messages (excluding the reserved check code field). This calculation can be implemented using a serial shift register circuit or parallel computing logic. The 16-bit remainder obtained from the calculation is used as the check code and filled into the check field at the end of the message to complete the cyclic redundancy check encoding.

[0062] Control messages with completed cyclic redundancy check (CRC) coding are assigned to the high-priority transmission queue, while data messages are assigned to the low-priority transmission queue. When a control message exists in the high-priority transmission queue, it indicates that urgent control signaling needs to be sent with priority over ordinary service data transmission. At this time, the scheduler suspends the data message transmission of the low-priority transmission queue, maps the control message to the physical transmission link, and completes hierarchical scheduling. The suspension of the low-priority queue continues until the high-priority queue is empty, after which data message transmission resumes.

[0063] Before mapping the message to the physical transmission link, the absolute trigger time of the scheduling queue is compared in real time with the refresh window boundary recorded by the refresh counter through a hardware timestamp comparator to detect whether the current scheduling time slot overlaps with the internal refresh instruction time slot of the double data rate storage interface.

[0064] If an overlap occurs, it means that the message to be sent conflicts with the refresh operation required by the memory chip in terms of time. Forcing the transmission may result in data errors or refresh failure. In this case, the scheduler determines that a scheduling conflict has occurred, immediately terminates the current transmission action, and directly uses the end time of the internal refresh instruction time slot as the new start time slot. The unsent control messages and data messages are reinserted into the corresponding positions in the current scheduling queue immediately after the new start time slot. The queue manager will automatically re-trigger and perform backoff rescheduling in a conflict-free time window.

[0065] S5. Verify the received control message. If the verification is successful, parse and perform sampling correction and terminal state switching. If the control message or data message verification is abnormal, perform the corresponding retransmission process.

[0066] Considering that the receiving end needs to adjust the sampling phase and physically reverse the input / output direction of the pins within a limited clock cycle after receiving the control signaling, and that the physical link may introduce random bit errors, directly executing hardware actions based on erroneous signaling without a precise timing triggering mechanism and verification / retransmission logic will lead to complete loss of synchronization between the transmitting and receiving ends or bus deadlock.

[0067] Therefore, this step first verifies the control message at the receiving end, and divides it into a normal execution branch and an abnormal retransmission branch according to the verification result: after confirming that the signaling is accurate, it drives the underlying delay-locked loop register and internal timer to perform physical actions; when the signaling is abnormal, it implements layered retransmission based on sequence number comparison and negative acknowledgment mechanism to support the consistency of the terminal's physical state and reliable transmission of the data link layer.

[0068] In one specific embodiment, corresponding to the normal execution branch after the verification passes, the step of performing sampling correction and terminal state switching after the verification passes is as follows: receiving control messages from the physical transmission link, performing remainder calculation on the control messages using the same generator polynomial as the sending end to obtain a local checksum, and comparing the local checksum with the checksum carried at the end of the control messages bit by bit.

[0069] If the comparison results match, it means the control message verification passed and a correct control message was obtained. The receiving end extracts the synchronization compensation command and terminal handover advance from the correct control message.

[0070] The compensation step count in the synchronization compensation command is input to the delay-locked loop control register at the receiving end. Based on this compensation step count, the delay-locked loop advances or delays the phase of the data sampling edge by the product of the compensation step count and the minimum delay adjustment step size, thereby aligning the sampling point with the center of the data eye diagram and completing the sampling correction. The adjustment direction is determined by the synchronization compensation identifier code attached to the synchronization compensation command, which is set according to the sign of the phase time difference when the command is packaged.

[0071] An internal timer is started based on the number of clock cycles corresponding to the terminal switching advance. When the timer countdown reaches zero, the input / output pin levels of the double data rate storage interface are triggered to toggle, switching the bus direction from read to write or from write to read, thus completing the terminal state switch.

[0072] In another specific embodiment, corresponding to the retransmission processing branch for verification anomalies, the specific content of executing the corresponding retransmission processing when a control message or data message verification anomaly occurs is as follows: If the comparison result does not match, it indicates that a data error occurred in the control message during transmission. At this time, the receiving end determines that the control message verification is abnormal and sends a negative acknowledgment signal to the sending end through the feedback channel provided by the physical layer. This negative acknowledgment signal carries the sequence number of the control message that had the error. After receiving the negative acknowledgment signal, the sending end reads the corresponding control message from the transmission buffer according to the sequence number and performs retransmission. After sending the negative acknowledgment signal, the receiving end enters a waiting state, blocking subsequent physical actions until it receives the retransmitted correct control message.

[0073] After receiving and verifying the correctly retransmitted control message, the receiving end performs sampling correction and terminal state switching. At the same time, it parses the sequence number carried in the header of the correct control message, waits for the sending end to resume transmission, and starts receiving the corresponding data message based on the sequence number. After fully receiving the data message and performing its own integrity verification, if an error is detected in the data message verification, such as an error found through the CRC check of the data message itself, the receiving end sends a data retransmission request to the sending end. This request carries the sequence number of the data message to be retransmitted, triggering the sending end to retransmit the corresponding data message.

[0074] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0075] Those skilled in the art will recognize that the algorithmic steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0076] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0077] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0078] Finally, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-speed data transmission communication method for a double data rate storage interface, characterized in that, include: Collect historical transmit and receive timing parameters and burst length parameters of the double data rate storage interface, and input them into a recurrent neural network to extract transmission traffic feature vectors; If the rate of change of the Euclidean distance of the transmission traffic feature vector exceeds the limit, the moment of switching the transmission and reception direction is determined, and the number of compensation steps is calculated by combining the phase time difference and the minimum delay adjustment step size to obtain the synchronization compensation command. A scheduling queue is constructed based on the time of switching between transmit and receive directions. Dynamic delay deviation and link dynamic jitter offset are calculated based on propagation delay and load ratio to obtain sampling compensation parameters. Terminal switching advance is obtained based on hardware response time, and transmit and receive coordinated scheduling strategy is generated. The control message and corresponding data message containing synchronization compensation instruction, terminal handover advance and sequence number are constructed by the transmit and receive coordinated scheduling strategy. After performing cyclic redundancy check encoding on the control message, hierarchical scheduling is performed, and backoff and rescheduling are performed when scheduling conflicts are detected. The received control messages are verified. If the verification is successful, the message is parsed and sampled for correction and terminal state switching is performed. If the verification of the control message or data message is abnormal, the corresponding retransmission is performed.

2. The high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, The historical transmit / receive timing parameters include read / write request interval, clock cycle offset, and data valid window duration. The burst length parameters include the burst length of continuous read operations and the burst length of continuous write operations.

3. The high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, The method for obtaining the time of switching the transmission and reception direction is as follows: The Euclidean distance change rate is calculated for the transmission traffic feature vectors of adjacent time windows. When the change rate exceeds the preset direction switching threshold, the transmit / receive direction switching boundary is determined, and the current clock cycle count value is recorded as the transmit / receive direction switching time.

4. The high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, The method for obtaining the synchronization compensation instruction is as follows: Obtain the phase time difference between the actual clock signal phase corresponding to the moment of transmit / receive direction switching and the reference clock of the double data rate storage interface; Obtain the minimum delay adjustment step size of the double data rate storage interface delay lock loop, divide the phase time difference by the minimum delay adjustment step size, round the calculated quotient up, and package the rounded value as the compensation step number into a synchronization compensation instruction.

5. A high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, The method for generating the transmit / receive coordinated scheduling strategy is as follows: Using the moment of switching between transmit and receive directions as the dividing point, the time axis before and after the dividing point is divided into read scheduling time slots and write scheduling time slots. The synchronization compensation instruction is inserted into one clock cycle before the dividing point to form a scheduling queue. The current propagation delay of the physical link is obtained in real time, and the dynamic delay deviation is obtained by calculating the difference between the current propagation delay and the historical average propagation delay. The ratio of the current bus load to the reference load is obtained as the load ratio. The dynamic delay deviation, the load ratio and the preset normalization coefficient are multiplied to obtain the link dynamic jitter offset. The link dynamic jitter offset is added to the time offset corresponding to the preset fixed phase deviation value to generate the sampling compensation parameter. The result of adding the historical average propagation delay to the hardware response time required to flip the terminal pin direction of the double data rate storage interface is used as the transmission advance, and the hardware response time is used separately as the terminal switching advance. The transmission advance is inserted as a scheduling event into the corresponding time slot node in the scheduling queue. The synchronization compensation instruction and sampling compensation parameter already in the scheduling queue are configured as the scheduling and receiving end sampling attributes in this time slot. The terminal switching advance is encapsulated into the control message to be generated to generate a transmit and receive coordinated scheduling strategy.

6. The high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, The method for generating the control message and the corresponding data message is as follows: The transmit and receive coordination scheduling strategy is parsed, and the synchronization compensation instruction, terminal handover advance, and data packet sequence number associated with the current time slot are encapsulated into the packet header to generate a control message. The business data to be transmitted is divided into fixed-length data blocks and sequence numbers are added to generate data packets.

7. A high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, After performing cyclic redundancy check encoding on the control message, hierarchical scheduling is performed, and backoff and rescheduling are executed when scheduling conflicts are detected. Specifically, this includes: A generator polynomial is used to perform a bit-by-bit XOR operation on the data bits of the control message, and the remainder is used as a check code and appended to the end of the control message to complete the cyclic redundancy check encoding. Control messages that have completed cyclic redundancy check coding are assigned to the high-priority transmission queue, and data messages are assigned to the low-priority transmission queue. When there are control messages in the high-priority transmission queue, the transmission of data messages in the low-priority transmission queue is suspended. The control messages are mapped to the physical transmission link to complete the hierarchical scheduling. Before mapping the message to the physical transmission link, it is checked whether the current scheduling time slot overlaps with the internal refresh instruction time slot of the double data rate storage interface. If an overlap occurs, a scheduling conflict is determined, the current transmission action is immediately terminated, the end time of the internal refresh instruction time slot is taken as the new starting time slot, and the unsent control messages and data messages are re-inserted into the time slot position corresponding to the new starting time slot in the current scheduling queue, and backoff rescheduling is performed.

8. A high-speed data transmission communication method for a double data rate storage interface as described in claim 7, characterized in that, The generator polynomial is the CRC-16 standard generator polynomial.

9. A high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, The process of verifying the received control message, and parsing and performing sampling correction and terminal state switching after successful verification, specifically includes: The system receives control messages from the physical transmission link, performs remainder calculations on the received control messages using the same generator polynomial as the sender, obtains the local checksum, and compares it with the checksum carried at the end of the control message. If the comparison results match, it means that the control message verification has passed, the correct control message has been obtained, and the synchronization compensation instruction and terminal handover advance have been extracted from it. The number of compensation steps in the synchronization compensation command is input to the delay-locked loop control register at the receiving end. The delay-locked loop advances or delays the phase of the data sampling edge by the product of the number of compensation steps and the minimum delay adjustment step size, thereby completing the sampling correction. An internal timer is started based on the terminal switching advance. When the timer countdown reaches zero, the input and output pin levels of the double data rate storage interface are flipped to complete the terminal state switching.

10. A high-speed data transmission communication method for a double data rate storage interface as described in claim 1, characterized in that, When the control message or data message verification fails, corresponding retransmission processing is performed, specifically including: If the comparison results do not match, the control message verification is determined to be abnormal, a negative acknowledgment signal is sent to the sender, the sender is triggered to retransmit the control message, and waits to receive the retransmitted correct control message. The sequence number carried in the correct control message header is parsed, and the sender is waited for to resume transmission. The corresponding data message is received based on the sequence number. After verifying the received data message, if an error is detected in the data message verification, a request is made to the sender to retransmit the data message.

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