Non-volatile memory device

Abstract

A non-volatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a plurality of memory cell arrays arranged in a first direction. Each of the plurality of memory cell arrays includes a plurality of sub-planes arranged in the first direction and extending in a second direction intersecting the first direction. The peripheral circuit region is arranged below the memory cell region in a vertical direction and includes a plurality of page buffer circuits in association with the plurality of memory cell arrays, respectively. Each of the plurality of memory cell arrays further includes a first common source plate extending in the first direction and commonly associated with the plurality of sub-planes, and a first bit line group and a second bit line group associated with first and second sub-planes of the plurality of sub-planes, respectively.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0011893, filed on January 24, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to memory devices, and more specifically, to three-dimensional (3D) non-volatile memory devices in which memory cell arrays are arranged in a vertical direction relative to peripheral circuitry. Background Technology

[0003] In response to the demand for higher capacity and / or miniaturization of non-volatile memory devices, three-dimensional (3D) non-volatile memory devices with vertically arranged memory cell arrays and / or peripheral circuitry have been developed. For example, advancements in semiconductor process technology have created a need for smaller chip sizes, which can be addressed by implementing 3D non-volatile memory devices. Furthermore, 3D non-volatile memory devices can also address the growing demand for increasing the number of memory dies formed per wafer and / or improving wafer utilization efficiency. Summary of the Invention

[0004] One or more exemplary embodiments of this disclosure provide non-volatile memory devices that, compared to existing memory devices, can reduce chip size and improve wafer utilization and memory device performance.

[0005] According to one aspect of this disclosure, a non-volatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a plurality of memory cell arrays arranged in a first direction. Each of the plurality of memory cell arrays includes a plurality of subplanes disposed in the first direction. Each of the plurality of subplanes extends in a second direction intersecting the first direction. The peripheral circuit region is disposed below the memory cell region in a vertical direction. The peripheral circuit region includes a plurality of page buffer circuits respectively coupled to the plurality of memory cell arrays. Each of the plurality of memory cell arrays further includes: a first common-source plate extending in the first direction and commonly coupled to the plurality of subplanes; a first bit line group coupled to the first subplane among the plurality of subplanes; and a second bit line group coupled to the second subplane among the plurality of subplanes. Each of the plurality of page buffer circuits includes: a first page buffer coupled to the first subplane via the first bit line group; and a second page buffer coupled to the second subplane via the second bit line group.

[0006] According to one aspect of this disclosure, a non-volatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a plurality of memory cell arrays and an upper bonding pad. The plurality of memory cell arrays include a first memory cell array, a second memory cell array, a third memory cell array, and a fourth memory cell array. The first and second memory cell arrays are arranged in a first direction. The third and fourth memory cell arrays are arranged in the first direction. The first and third memory cell arrays are separated from each other in a second direction intersecting the first direction. The second and fourth memory cell arrays are separated from each other in the second direction. The peripheral circuit region includes a plurality of page buffer circuits and a lower bonding pad. The plurality of page buffer circuits include a first page buffer circuit, a second page buffer circuit, a third page buffer circuit, and a fourth page buffer circuit. The plurality of page buffer circuits are respectively coupled to the plurality of memory cell arrays. The peripheral circuit region is coupled to the memory cell region in a vertical direction via the upper and lower bonding pads. Each of the plurality of memory cell arrays includes a plurality of sub-planes arranged in the first direction. Each of the plurality of sub-planes extends in the second direction. The plurality of sub-planes are respectively coupled to a plurality of different bit line groups. Each of the plurality of page buffer circuits includes a plurality of page buffers respectively associated with the plurality of subplanes.

[0007] According to one aspect of this disclosure, a non-volatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a plurality of memory cell arrays arranged in an array on a first wafer and upper bonding pads coupled to the plurality of memory cell arrays. The peripheral circuit region includes lower bonding pads disposed on a second wafer. The peripheral circuit region is coupled to the memory cell region in a vertical direction via the upper and lower bonding pads. Each of the plurality of memory cell arrays includes: a plurality of sub-planes arranged in a first direction; a plurality of bit line groups, respectively coupled to the plurality of sub-planes; a first common source plate extending in the first direction; and a second common source plate extending in the first direction. Each of the plurality of sub-planes extends in a second direction intersecting the first direction. The first and second common source plates are separated from each other in the second direction. Each of the plurality of sub-planes includes: a plurality of first memory blocks coupled to the first common source plate; and a plurality of second memory blocks coupled to the second common source plate.

[0008] Additional aspects may be set forth in part in the description below, and in part will be apparent from the description, and / or may be learned by practice of the embodiments presented. Attached Figure Description

[0009] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a memory device according to an embodiment.

[0011] Figure 2 This is a circuit diagram showing a memory block according to an embodiment.

[0012] Figure 3 The structure of a memory device according to an embodiment is illustrated schematically.

[0013] Figure 4 A memory device having a bonding (or bonding) vertical NAND (B-VNAND) structure according to an embodiment is schematically shown.

[0014] Figure 5 This is a plan view showing a memory device according to an embodiment.

[0015] Figure 6 It is according to the embodiment along Figure 5 A cross-sectional view taken along line Y1-Y2.

[0016] Figure 7 It is according to the embodiment along Figure 5 A sectional view taken from line X1-X2.

[0017] Figure 8 A memory device having a B-VNAND structure according to an embodiment is schematically shown.

[0018] Figure 9 A memory device having a B-VNAND structure according to an embodiment is schematically shown.

[0019] Figure 10 This is a block diagram illustrating a memory device according to an embodiment.

[0020] Figure 11 A memory device having a B-VNAND structure according to an embodiment is schematically shown.

[0021] Figures 12 to 18 Each of these is a plan view of a memory device according to some embodiments.

[0022] Figure 19 This is a cross-sectional view of a memory device having a B-VNAND structure according to an embodiment.

[0023] Figure 20 A solid-state drive (SSD) including a memory device is shown according to an embodiment. Detailed Implementation

[0024] The following description, with reference to the accompanying drawings, is provided to aid in a full understanding of the embodiments of this disclosure as defined by the claims and their equivalents. Various specific details are included to aid understanding, but these details are considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures have been omitted.

[0025] Regarding the description of the accompanying drawings, similar reference numerals may be used to denote similar or related elements. It will be understood that, unless the relevant context clearly indicates otherwise, the singular form of the noun corresponding to an item may include one or more things. As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B or C” may include any or all possible combinations of the items listed together in the corresponding phrase within the phrase. As used herein, terms such as “first” and “second” or “first” and “second” may be used only to distinguish corresponding components from other components and do not otherwise limit the components (e.g., in terms of importance or order). It will be understood that if an element (e.g., the first element) is referred to as "combined" with, "combined to" another element (e.g., the second element), "connected" to, or "attached to" another element (e.g., the second element) when the terms "operationally" or "communicationally" are used, or when the terms "operationally" or "communicationally" are not used, it means that the element can be directly (e.g., wiredly) combined with another element, wirelessly combined with another element, or combined with another element via a third element.

[0026] It will be understood that when a component or layer is referred to as being "above," "on top of," "above," "below," "under," "connected to," or "bonded to" another component or layer, it can be directly above, above, below, under, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or layers present. In contrast, when a component is referred to as being "directly above," "above," "above," "below," "under," "under," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers present.

[0027] Terms such as "first," "second," and "third" may be used instead of terms like "upper (top)," "middle," and "lower (bottom)," which describe the relative positions of elements. The terms "first," "second," and "third" can be used to describe various elements, but these elements are not limited by these terms, and a "first element" may be referred to as a "second element." Optionally or additionally, the terms "first," "second," and "third," etc., may be used to distinguish components from each other and do not limit this disclosure. For example, the terms "first," "second," and "third," etc., need not necessarily imply any form of order or numerical meaning.

[0028] As used herein, when an element or layer is referred to as “covering,” “around,” or “overlaying” another element or layer, the element or layer may cover at least a portion of the other element or layer, wherein the portion may include a part of the other element or may include the entire other element. Similarly, when an element or layer is referred to as “penetrating” another element or layer, the element or layer may penetrate at least a portion of the other element or layer, wherein the portion may include a part of the other element or may include the entire dimensions (e.g., length, width, depth) of the other element.

[0029] References to “an embodiment,” “an embodiment,” “an exemplary embodiment,” or similar language throughout this disclosure may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Therefore, throughout this disclosure, the phrases “in one embodiment,” “in an embodiment,” “in an exemplary embodiment,” “in some embodiments,” “in a particular embodiment,” and similar language may, but not necessarily, represent the same embodiment. The embodiments described herein are exemplary embodiments, and therefore, the disclosure is not limited thereto and may be implemented in various other forms.

[0030] As used herein, each of the terms “SiN”, “SiO”, “TaN”, “TiAlN”, “TiN”, “WN”, etc., may represent a material made from the element included in each term, and is not a chemical formula representing a stoichiometric relationship.

[0031] Various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0032] Figure 1 This is a block diagram illustrating a memory device according to an embodiment.

[0033] Reference Figure 1The memory device 10 may include a memory cell array 11 and a peripheral circuitry PECT. The peripheral circuitry PECT may include a page buffer circuit 12, control logic circuitry 13, a voltage generator 14, and a row decoder 15. In some embodiments, the peripheral circuitry PECT may also include a data input / output (I / O) circuitry system or an I / O interface. Additionally, in some embodiments, the peripheral circuitry PECT may include a temperature sensor, a command decoder, an address decoder, etc. As used herein, memory device 10 may refer to a non-volatile memory device.

[0034] The memory cell array 11 may include multiple subplanes comprising a first subplane 11a and a second subplane 11b. For example, the memory cell array 11 may include and / or resemble a memory array tile (MAT) in many respects. In embodiments, the memory cell array 11 may include and / or resemble, in many respects, as referenced... Figure 5 The described MAT. Optionally or additionally, the memory cell array 11 may have a capacity of 16 kilobytes (KB). However, embodiments of this disclosure are not limited thereto. As used herein, the memory cell array 11 may be referred to as a memory plane or a plane.

[0035] In the embodiment, the plurality of subplanes 11a and 11b may each be in a first direction (e.g., Figure 5 It can be arranged on the Y) and can be arranged in a second direction intersecting the first direction (e.g., Figure 5 Extending on (X) in the diagram. As used herein, the first direction may include and / or may resemble the extension direction of the bit line in many respects. For example, each of the plurality of subplanes 11a and 11b may have a capacity of 8KB. However, embodiments of this disclosure are not limited thereto. In embodiments, as referenced Figure 2 As described, each of the plurality of subplanes 11a and 11b may include a plurality of memory blocks, and each memory block may include a plurality of memory cells. In an embodiment, as referred to Figure 9 and Figure 10 As described, each of the multiple memory blocks may include multiple memory stacks.

[0036] In one embodiment, a first subplane 11a may be connected to a first bit line group BLG1, which includes first bit lines extending in the first direction Y, and a second subplane 11b may be connected to a second bit line group BLG2, which includes second bit lines extending in the first direction Y. In this manner, the first subplane 11a and the second subplane 11b may be connected to the first bit line group BLG1 and the second bit line group BLG2, respectively, and may be controlled independently.

[0037] In an embodiment, the memory device 10 may further include a first plate common-source line (CSL) extending in the first direction Y (e.g., Figure 5 The first common source plate 51a), and some memory blocks included in the first sub-plane 11a and some memory blocks included in the second sub-plane 11b can be commonly connected to the first common source plate 51a. In an embodiment, the memory device 10 may also include a second plate CSL (e.g., Figure 5 The second common source plate 51b may extend in the first direction Y and may be separately disposed from the first common source plate 51a in the second direction X. Other (remaining) memory blocks included in the first subplane 11a and other (remaining) memory blocks included in the second subplane 11b may be commonly connected to the second common source plate 51b. As used herein, a common source plate may refer to a common source line structure having a plate shape and being commonly connected to multiple memory blocks.

[0038] The memory cell array 11 can be connected to the row decoder 15 via word line WL, serial select line SSL, and ground select line GSL. For example, the memory cells included in the memory cell array 11 may be and / or may include flash memory cells. In the following, embodiments are described using the example of memory cells being NAND flash memory cells. However, embodiments of this disclosure are not limited thereto. For example, in some embodiments, the memory cells may be and / or may include resistive memory cells (such as, but not limited to, resistive random access memory (ReRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), etc.).

[0039] In one embodiment, the memory cell array 11 may include a three-dimensional (3D) memory cell array. See reference... Figure 2 The described 3D memory cell array may include multiple NAND strings, and each NAND string may include memory cells respectively connected to word lines stacked vertically on a substrate. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 9,536,970 disclose constructions of 3D memory arrays having multiple layers in which word lines and / or bit lines are shared between the multiple layers, and the entire disclosure of these U.S. patents is incorporated herein by reference.

[0040] Page buffer circuit 12 may include multiple page buffers, including a first page buffer 12a and a second page buffer 12b. The first page buffer 12a is connected to a memory cell in a first subplane 11a via a first bit line group BLG1, and the second page buffer 12b is connected to a memory cell in a second subplane 11b via a second bit line group BLG2. Page buffer circuit 12 can select at least one bit line from multiple bit lines included in the first bit line group BLG1 and the second bit line group BLG2 under the control of control logic circuit 13. For example, page buffer circuit 12 can select some bit lines in response to a column address Y_ADDR received from control logic circuit 13.

[0041] Each of the multiple page buffers 12a and 12b can operate as a write driver and / or a sense amplifier. For example, during a programming operation, each of the multiple page buffers 12a and 12b can store data DATA in a memory cell by applying a voltage corresponding to the data DATA to be programmed to a bit line. For example, during a programming verification operation or a read operation, each of the multiple page buffers 12a and 12b can detect the programmed data DATA by detecting current and / or voltage via the bit line.

[0042] The control logic circuit 13 can output various control signals (such as, but not limited to, voltage control signal CTRL_vol, row address X_ADDR, and column address Y_ADDR) for programming data into the memory cell array 11, reading data from the memory cell array 11, and / or erasing data stored in the memory cell array 11 based on the command CMD, address ADDR, and control signal CTRL. In this manner, the control logic circuit 13 can control various overall operations within the memory device 10. For example, the control logic circuit 13 can receive the command CMD, address ADDR, and control signal CTRL from the memory controller.

[0043] Voltage generator 14 can generate various types (e.g., levels) of voltage for performing programming, reading, and / or erasing operations on memory cell array 11 based on the voltage control signal CTRL_vol. In embodiments, voltage generator 14 can generate word line voltages VWL (such as, but not limited to, programming voltage, read voltage, pass voltage, erase verification voltage, programming verification voltage, etc.). Additionally, voltage generator 14 can also generate string select line voltages and / or ground select line voltages based on the voltage control signal CTRL_vol.

[0044] The row decoder 15 can select one of a plurality of memory blocks included in a plurality of subplanes 11a and 11b in response to the row address X_ADDR received from the control logic circuit 13, select one of the word lines WL of the selected memory block, and select one of the string selection lines SSL. For example, during a programming operation, the row decoder 15 can apply a programming voltage and / or a programming verification voltage to the selected word line, and during a read operation, the row decoder 15 can apply a read voltage to the selected word line.

[0045] According to an embodiment, the memory cell array 11 may be arranged in a memory cell region, a first semiconductor layer, a first wafer, a first semiconductor chip, or a memory chip (e.g., Figure 3 Memory cell region 31, Figure 4 , Figure 6 , Figure 7 , Figure 11 Memory cell area CELL or Figure 19 The memory cell regions CELL1 and CELL2 are located within the memory cell regions, and the peripheral circuitry PECT can be arranged in the peripheral circuit region, the second semiconductor layer, the second wafer, the second semiconductor chip, or the peripheral circuitry chip (e.g., ...). Figure 3 Peripheral circuit area 32 or Figure 4 , Figure 6 , Figure 7 , Figure 11 , Figure 19 The peripheral circuit region (PERI) is located within the memory cell array 11. Therefore, at least a portion of the peripheral circuit PECT can be stacked vertically with the memory cell array 11.

[0046] Figure 2 This is a circuit diagram showing the memory block BLK according to an embodiment.

[0047] Reference Figure 2 The memory block BLK may include and / or may be similar in many respects to those included in the reference. Figure 1 This refers to one of a plurality of memory blocks in each of the plurality of subplanes 11a and 11b described, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 1 The description of the memory block BLK is repeated.

[0048] like Figure 2As shown, the memory block BLK may include multiple NAND strings (e.g., a first NAND string NS11, a second NAND string NS21, a third NAND string NS31, a fourth NAND string NS12, a fifth NAND string NS22, a sixth NAND string NS32, a seventh NAND string NS13, an eighth NAND string NS23, and a ninth NAND string NS33), and each NAND string (e.g., the first NAND string NS11) may include a string select transistor SST, multiple memory cells MC, and a ground select transistor GST connected in series. The transistors SST and GST included in each NAND string, as well as the memory cells MC, may be formed in a structure stacked vertically on a substrate.

[0049] Multiple bit lines (e.g., first bit line BL1, second bit line BL2, and third bit line BL3) can be in the first direction (e.g., Figure 3 Extending in the Y direction, and multiple character lines (e.g., first character line WL1, second character line WL2, third character line WL3, fourth character line WL4, fifth character line WL5, sixth character line WL6, seventh character line WL7 and eighth character line WL8) can extend in the second direction (e.g., Figure 3 Extending in the X direction (as described in the example). According to an embodiment, the first direction may be referred to as the first horizontal direction, and the second direction may be referred to as the second horizontal direction. The first NAND string NS11 to the third NAND string NS31 may be positioned between the first bit line BL1 and the common source line CSL; the fourth NAND string NS12 to the sixth NAND string NS32 may be positioned between the second bit line BL2 and the common source line CSL; and the seventh NAND string NS13 to the ninth NAND string NS33 may be positioned between the third bit line BL3 and the common source line CSL. For example, the first bit line BL1 to the third bit line BL3 may be included... Figure 1 In the first line group BLG1 or the second line group BLG2.

[0050] The string select transistor SST can be connected to the corresponding string select line (e.g., the first string select line SSL1, the second string select line SSL2, and the third string select line SSL3). The memory cell MC can be connected to the corresponding word line among the multiple word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select line among the ground select lines (e.g., the first ground select line GSL1, the second ground select line GSL2, and the third ground select line GSL3). The string select transistor SST can be connected to the corresponding bit line, and the ground select transistor GST can be connected to the common source line CSL. Although... Figure 2The illustration shows a specific number of first NAND strings NS11 to ninth NAND strings NS33, first word lines WL1 to eighth word lines WL8, first bit lines BL1 to third bit lines BL3, first ground select lines GSL1 to third ground select lines GSL3, and first string select lines SSL1 to third string select lines SSL3. However, embodiments of this disclosure are not limited thereto. For example, the number of NAND strings, word lines, bit lines, ground select lines, and string select lines may vary depending on the embodiment and / or design constraints.

[0051] Figure 3 The structure of a memory device according to an embodiment is illustrated schematically.

[0052] Reference Figure 3 The memory device 30 may include a memory cell region 31 and a peripheral circuit region 32. Figure 3 The memory device 30 may include and / or may be similar in many respects to the one described above. Figure 1 and Figure 2 The described memory device 10 may include additional features not mentioned above. Furthermore, Figure 3 The memory cell region 31 and the peripheral circuit region 32 may respectively include and / or be similar to the above reference in many respects. Figure 1 The memory cell array 11 and peripheral circuitry PECT are described, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figure 1 and Figure 2 The description of the memory device 30, memory cell region 31 and peripheral circuit region 32 is repeated.

[0053] The memory cell region 31 may be formed on a first wafer and may be referred to as a memory chip or a first semiconductor chip. The peripheral circuit region 32 may be formed on a second wafer and may be referred to as a peripheral circuit chip or a second semiconductor chip. In an embodiment, the memory cell region 31 and the peripheral circuit region 32 may be connected by bonding in the vertical direction Z, and therefore, the memory device 30 may be referred to as a memory device with a bonding vertical NAND (B-VNAND) type or chip-to-chip (C2C) bonding structure.

[0054] In an embodiment, the memory cell region 31 may include multiple memory cell arrays (e.g., a first memory cell array MCA1, a second memory cell array MCA2, a third memory cell array MCA3, and a fourth memory cell array MCA4). For example, at least one of the multiple memory cell arrays MCA1 to MCA4 may include and / or be similar in many respects to Figure 1The memory cell array 11. As used herein, each of the plurality of memory cell arrays MCA1 to MCA4 may be referred to as a memory plane or MAT, and thus, the memory cell region 31 may be referred to as having a 4-MAT structure. The peripheral circuit region 32 may include a plurality of peripheral circuits (e.g., a first peripheral circuit PECT1, a second peripheral circuit PECT2, a third peripheral circuit PECT3, and a fourth peripheral circuit PECT4) respectively corresponding to the plurality of memory cell arrays MCA1 to MCA4. In addition, the peripheral circuit region 32 may also include a pad region (or external pad bonding region) PA on which a plurality of pads PD may be disposed.

[0055] In one embodiment, each of the plurality of memory cell arrays MCA1 to MCA4 may include a plurality of sub-planes arranged in a first direction Y, and each sub-plane may extend in a second direction X. In another embodiment, each of the plurality of memory cell arrays MCA1 to MCA4 may further include a common source plate extending in the first direction Y and commonly connected to the plurality of sub-planes, and a plurality of bit line groups respectively connected to the plurality of sub-planes. The peripheral circuitry region 32 may include a plurality of page buffers respectively connected to the plurality of bit line groups.

[0056] In an embodiment, each of the plurality of subplanes may include a plurality of memory blocks and a plurality of word line groups. For example, the plurality of memory blocks may include first memory blocks through fourth memory blocks, and the plurality of word line groups may include a first word line group commonly connected to the first memory block and the second memory block, and a second word line group commonly connected to the third memory block and the fourth memory block. As another example, the plurality of memory blocks may include first memory blocks through fourth memory blocks, and the plurality of word line groups may include a first word line group connected to the first memory block, a second word line group connected to the second memory block, a third word line group connected to the third memory block, and a fourth word line group connected to the fourth memory block.

[0057] Figure 4 A memory device having a B-VNAND structure according to an embodiment is schematically shown.

[0058] Reference Figure 4 The memory device 40 may include a memory cell region (CELL) and a peripheral circuit region (PERI). Figure 4 The memory device 40 may include and / or may be similar in many respects to the one described above. Figures 1 to 3 The memory devices 10 and 30 are described, and may include additional features not mentioned above. Furthermore, Figure 4 The memory cell region (CELL) may include and / or may be similar in many ways to the reference above. Figures 1 to 3The memory cell array 11 and memory cell region 31 are described, and may include additional features not mentioned above. Additionally, the peripheral circuitry region PERI may include and / or be similar in many respects to the above-described references. Figures 1 to 3 The peripheral circuit PECT and peripheral circuit region 32 are described, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 3 The description of the memory device 40, the memory cell region CELL, and the peripheral circuit region PERI is repeated.

[0059] The memory cell region CELL may include a first sub-plane 41a, a second sub-plane 41b, a first upper bonding pad UBP1, and a second upper bonding pad UBP2. In the memory cell region CELL, the first upper bonding pad UBP1 is connected to a first bit line BL1 via a first via 44a, and the first bit line BL1 is connected to the first sub-plane 41a via a second via 44b. In the memory cell region CELL, the second upper bonding pad UBP2 is connected to a second bit line BL2 via a third via 44c, and the second bit line BL2 is connected to the second sub-plane 41b via a fourth via 44d. In an embodiment, Figure 4 The first subplane 41a and the second subplane 41b may respectively include and / or be similar in many respects to those described above. Figure 1 The first subplane 11a and the second subplane 11b are described. For example, the first line BL1 may be included. Figure 1 The first line group BLG1, and the second line BL2 can be included. Figure 1 In the second line group BLG2.

[0060] The Peripheral Circuit Area (PERI) may include a first page buffer PB1 42a, a second page buffer PB2 42b, a line decoder XDEC 43, and lower bonding pads (e.g., a first lower bonding pad LBP1 and a second lower bonding pad LBP2). In the PERI, the lower bonding pad LBP1 may be connected to the first page buffer 42a, and the lower bonding pad LBP2 may be connected to the second page buffer 42b. For example, the lower bonding pad LBP1 may be connected to the first page buffer 42a via a first via 45a and a second via 45b, and a lower metallization layer 46a. As another example, the lower bonding pad LBP2 may be connected to the second page buffer 42b via a third via 45c and a fourth via 45d, and a lower metallization layer 46b. The first page buffer 42a may include and / or may be similar in many respects to... Figure 1 The first page buffer 12a contains the page buffer, and the second page buffer 42b may include and / or may be similar in many respects to the page buffer in the first page buffer 12a. Figure 1 The page buffer in the second page buffer 12b.

[0061] Figure 5 This is a plan view showing a memory device according to an embodiment.

[0062] Reference Figure 5 The memory device 50 may include a plurality of MATs (e.g., a first MAT1 and a second MAT2 arranged in the first direction Y, and a third MAT3 and a fourth MAT4 arranged in the first direction Y). In an embodiment, the first MAT1 and the third MAT3 may be separated from each other in the second direction X, and the second MAT2 and the fourth MAT4 may be separated from each other in the second direction X. In this manner, the plurality of MATs1 to MAT4 may be arranged in a 2×2 array.

[0063] Figure 5 Each of the multiple MATs, MAT1 through MAT4, may include and / or may be similar to in many respects Figure 1 and Figure 2 Memory cell array 11 Figure 3 memory cell region 31 and Figure 4 The memory cell region (CELL) may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 4 The description is a repeated description of multiple MATs.

[0064] The first MAT MAT1 may include a plurality of subplanes (e.g., a first subplane SPL1a and a second subplane SPL1b) arranged in a first direction Y. For example, each of the plurality of subplanes SPL1a and SPL1b may extend in a second direction X. The plurality of subplanes SPL1a and SPL1b may respectively include and / or may be similar to in many respects. Figure 1 The device comprises multiple subplanes 11a and 11b, and may include additional features not mentioned above. In an embodiment, the aspect ratio of the region on which the first MATMAT1 is formed can be improved by arranging the first subplane SPL1a and the second subplane SPL1b in the first direction Y compared to existing non-volatile memory devices.

[0065] The dicing region (e.g., the tile dicing region) may not be located between the multiple sub-planes SPL1a and SPL1b. For example, the I / O contact plugs may not be arranged in the region between the first sub-plane SPL1a and the second sub-plane SPL1b. Therefore, the size of the first MAT MAT1 can be reduced, and the number of memory dies formed per wafer (e.g., the total die (GD) value) can be increased.

[0066] The first MAT MAT1 may further include a bit line BL connected to the first subplane SPL1a and a bit line BL connected to the second subplane SPL1b, and the bit lines BL may extend in the first direction Y and be separated from each other in the second direction X. For example, the bit line BL connected to the first subplane SPL1a may include and / or may be similar in many respects to Figure 1 The first bit group BLG1, and the bit line BL connected to the second subplane SPL1b, may include and / or may be similar in many respects to Figure 1 The second bit line group BLG2. In this manner, since the first subplane SPL1a and the second subplane SPL1b are respectively connected to the first bit line group BLG1 and the second bit line group BLG2, and the page buffer is arranged below the first subplane SPL1a and the second subplane SPL1b, the read time of the memory device 50 can be reduced compared with existing non-volatile memory devices, thereby potentially improving the performance of the memory device 50.

[0067] The first MAT MAT1 may further include multiple common source plates (e.g., a first common source plate 51a and a second common source plate 51b). The multiple common source plates 51a and 51b may each extend in a first direction Y and be separated from each other in a second direction X. The memory device 50 may further include a line decoder XDEC1 connected to the first MAT MAT1. For example, the line decoder XDEC1 may be disposed below the region between the first common source plate 51a and the second common source plate 51b. For example, the first subplane SPL1a and the second subplane SPL1b, the first common source plate 51a and the second common source plate 51b, and the bit line BL may be arranged in... Figure 4 The memory cell region CELL, and the line decoder XDEC1 can be arranged in Figure 4 In the peripheral circuit region PERI.

[0068] In one embodiment, the line decoder XDEC1 may include a first line decoder connected to a first subplane SPL1a and a second line decoder connected to a second subplane SPL1b. In this manner, the first subplane SPL1a and the second subplane SPL1b can be connected to different line decoders. Therefore, the word lines connected to the first subplane SPL1a and the second subplane SPL1b can be controlled independently. In another embodiment, a first pass transistor circuit may be connected between the line decoder XDEC1 and the first subplane SPL1a, and a second pass transistor circuit may be connected between the line decoder XDEC1 and the second subplane SPL1b. In this manner, the first subplane SPL1a and the second subplane SPL1b can be connected to different pass transistor circuits. Therefore, the word lines connected to the first subplane SPL1a and the second subplane SPL1b can be controlled independently.

[0069] The first subplane SPL1a may include a first memory block connected to the first common source plate 51a and a second memory block connected to the second common source plate 51b. The second subplane SPL1b may include a third memory block connected to the first common source plate 51a and a fourth memory block connected to the second common source plate 51b. In an embodiment, the line decoder XDEC1 may include a first line decoder disposed below a region between the first memory block and the second memory block, and a second line decoder disposed below a region between the third memory block and the fourth memory block. In an embodiment, a first transistor circuit may be disposed between the first memory block and the line decoder XDEC1, and a second transistor circuit may be disposed between the second memory block and the line decoder XDEC1.

[0070] The second MAT MAT2 may include a first subplane SPL2a and a second subplane SPL2b arranged in the first direction Y, a bit line BL connected to the first subplane SPL2a and the second subplane SPL2b respectively, and a first common source plate 52a and a second common source plate 52b. The memory device 50 may also include a line decoder XDEC2 connected to the second MAT MAT2. The third MAT MAT3 may include a first subplane SPL3a and a second subplane SPL3b arranged in the first direction Y, a bit line BL connected to the first subplane SPL3a and the second subplane SPL3b respectively, and a first common source plate 53a and a second common source plate 53b. The memory device 50 may also include a line decoder XDEC3 connected to the third MAT MAT3. The fourth MAT MAT4 may include a first subplane SPL4a and a second subplane SPL4b arranged in the first direction Y, bit lines BL connected to the first subplane SPL4a and the second subplane SPL4b respectively, and a first common source plate 54a and a second common source plate 54b. The memory device 50 may also include a line decoder XDEC4 connected to the fourth MAT MAT4. The description given above for the first MAT MAT1 can be applied to the second MAT MAT2 through the fourth MAT MAT4.

[0071] Figure 6 It is according to the embodiment along Figure 5 A sectional view taken along line Y1-Y2. Figure 7 It is according to the embodiment along Figure 5 A sectional view taken from line X1-X2.

[0072] Refer to together Figure 6 and Figure 7 The memory cell region (CELL) may include a first subplane SPL1a and a second subplane SPL1b, and a dummy block D_BLK may be disposed between the first subplane SPL1a and the second subplane SPL1b. For example, the dummy block D_BLK may not be connected to a bit line or metal layer. For example, the dummy block D_BLK may be floating. However, embodiments of this disclosure are not limited thereto. For example, according to an embodiment, a cut area (e.g., a tile cut area) may not be disposed between the first subplane SPL1a and the second subplane SPL1b. As another example, when compared to existing non-volatile memory devices, I / O contact plugs may not be disposed between the first subplane SPL1a and the second subplane SPL1b, thereby reducing the size of the memory cell region (CELL).

[0073] For example, the first subplane SPL1a, the second subplane SPL1b, and the dummy block D_BLK can be commonly connected to the first common source plate 51a. As another example, the first subplane SPL1a and the second subplane SPL1b can be connected to different bit lines BL1 and BL2, respectively. Optionally or additionally, the first subplane SPL1a, the second subplane SPL1b, and the dummy block D_BLK can be connected to different gate electrodes GE, respectively. However, embodiments of this disclosure are not limited thereto. For example, in one embodiment, the first subplane SPL1a, the second subplane SPL1b, and the dummy block D_BLK can be connected to the same gate electrode GE.

[0074] The memory cell region CELL may include an upper substrate U_SUB, a first common source plate 51a, a gate structure GS, a channel structure CH, an insulating layer IL, a first metal layer M1, a first metal contact MC1, an upper bonding via UBV, and an upper bonding pad UBP. The number of metal layers included in the memory cell region CELL may vary depending on the embodiment and / or design constraints. The upper substrate U_SUB may be implemented using polysilicon. For example, the first common source plate 51a may be formed in a plate shape by doping impurities into the upper substrate U_SUB. According to an embodiment, the upper substrate U_SUB may be defined to include a plate common source line and / or a common source plate. The gate structure GS may include a plurality of gate electrodes GE stacked in the vertical direction Z, and the insulating layer IL may be disposed between adjacent gate electrodes GE. The channel structure CH may extend from the upper substrate U_SUB or the first common source plate 51a in the vertical direction Z.

[0075] The first metal layer M1, the upper bonding via UBV, and the upper bonding pad UBP may comprise metallic materials (such as, but not limited to, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), and titanium aluminum nitride (TiAlN), or combinations thereof). The first metal contact MC1 may comprise a conductive material (such as, but not limited to, doped polycrystalline silicon, or aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), etc.).

[0076] According to an embodiment, the first metal layer M1 may include bit lines BL1 and BL2, each extending in a first direction Y and separated from each other in a second direction X. In this embodiment, bit lines BL1 and BL2 may be connected to the channel structure CH via corresponding metal contacts MC1 or drains. Additionally, bit lines BL1 and BL2 may be connected to the upper bonding pad UBP via corresponding upper bonding vias UBV.

[0077] The Peripheral Circuit Region (PERI) may include a lower substrate L_SUB, lower metal layers (e.g., a first lower metal layer LMa and a second lower metal layer LMb), lower metal contacts (e.g., a first lower metal contact LMCa and a second lower metal contact LMCb), a lower insulating layer L_IL, a lower bonding via LBV, and a lower bonding pad LBP. The number of lower metal layers included in the PERI may vary depending on the embodiment and / or design constraints. Multiple circuit devices (e.g., a first transistor 61, a second transistor 62, and a third transistor 71) may be arranged on the lower substrate L_SUB. For example, the first transistor 61 and the third transistor 71 may be included... Figure 4 The first page buffer 42a, and the second transistor 62 may be included. Figure 4 In the second page buffer 42b.

[0078] Figure 8 A memory device having a B-VNAND structure according to an embodiment is schematically shown.

[0079] Reference Figure 8 The memory device 80 may include a memory cell region (CELL) and a peripheral circuit region (PERI). Figure 8 The memory device 80 may include and / or may be similar in many respects to the one described above. Figures 1 to 7 The memory devices 10, 30, 40, and 50 are described, and may include additional features not mentioned above. Furthermore, Figure 8 The memory cell region (CELL) may include and / or may be similar in many ways to the reference above. Figures 1 to 7 The memory cell array 11, memory cell region 31, and memory cell region CELL are described, and may include additional features not mentioned above. Additionally, the peripheral circuitry region PERI may include and / or be similar in many respects to the above-described references. Figures 1 to 7 The description includes the peripheral circuit PECT, peripheral circuit region 32, and peripheral circuit region PERI, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 7 The description of the memory device 80, the memory cell region CELL, and the peripheral circuit region PERI is repeated.

[0080] The peripheral circuitry region PERI may include multiple transistors (e.g., a first transistor 81, a second transistor 82, and a third transistor 83). For example, the first transistor 81 may be connected to a bit line and thus included in a page buffer. As another example, the second transistor 82 and the third transistor 83 may be connected to a common-source line CSL and thus included in a common-source line driver.

[0081] The memory cell region (CELL) may include multiple channel structures and multiple gate electrodes (GE). Each channel structure may include a first memory stack (CH_L) and a second memory stack (CH_U) stacked in the vertical direction Z. The multiple channel structures may be commonly connected to a common source line (CSL). In an embodiment, the common source line (CSL) may be implemented as a common source plate and / or as a common source plate extending in the first direction Y.

[0082] Multiple vias V1 may be arranged on the common source line CSL, and an upper metal layer BAM may be arranged on the multiple vias V1. For example, the upper metal layer BAM may correspond to back-side aluminum metal arranged on the back side of the upper substrate. The memory cell region CELL may also include I / O metal contacts and / or I / O contact plugs IOMC. The upper bonding pad UBP may be connected to the common source line CSL through the upper bonding via UBV, the first metal layer M1, the I / O contact plugs IOMC, the multiple vias V1, and the upper metal layer BAM.

[0083] Figure 9 A memory device having a B-VNAND structure according to an embodiment is schematically shown.

[0084] Reference Figure 9 The memory device 90 may include a memory cell region (CELL) and a peripheral circuit region (PERI). Figure 9 The memory device 90 may include and / or may be similar in many respects to the one described above. Figures 1 to 8 The memory devices 10, 30, 40, 50, and 80 are described, and may include additional features not mentioned above. Furthermore, Figure 9 The memory cell region (CELL) may include and / or may be similar in many ways to the reference above. Figures 1 to 8 The memory cell array 11, memory cell region 31, and memory cell region CELL are described, and may include additional features not mentioned above. Additionally, the peripheral circuitry region PERI may include and / or be similar in many respects to the above-described references. Figures 1 to 8 The description includes the peripheral circuit PECT, peripheral circuit region 32, and peripheral circuit region PERI, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 8 The description of the memory device 90, memory cell region CELL, and peripheral circuit region PERI is repeated. In the following text, the memory device 90 and... Figure 8 The differences between the memory devices 80.

[0085] The memory cell region (CELL) may include multiple channel structures, and each channel structure may include multiple memory stacks (e.g., a first memory stack CH_L1, a second memory stack CH_L2, a third memory stack CH_U1, and a fourth memory stack CH_U2) stacked in the vertical direction Z. The multiple channel structures may be commonly connected to a common source line CSL. In an embodiment, the common source line CSL may be implemented as a common source plate extending in the first direction Y. Additionally, the multiple channel structures may be connected to multiple gate electrodes GE.

[0086] Figure 10 This is a block diagram illustrating a memory device according to an embodiment.

[0087] Reference Figure 10 The memory device 100 may include a memory cell array 11 and a peripheral circuit PECT, and the peripheral circuit PECT may include a page buffer circuit 12, a control logic circuit 13, a voltage generator 14, and a first row decoder 15a and a second row decoder 15b.

[0088] Figure 10 The memory device 100 may include and / or may be similar in many respects to the one described above. Figures 1 to 9 The memory devices 10, 30, 40, 50, 80, and 90 are described, and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above can be omitted. Figures 1 to 9 The memory device 100 described herein is repeated. In the following description, the memory device 100 is described in conjunction with... Figure 1 The differences between the memory devices 10.

[0089] The memory cell array 11 may include multiple subplanes comprising a first subplane 11a and a second subplane 11b. The first subplane 11a may be connected to a first row decoder 15a, and the second subplane 11b may be connected to a second row decoder 15b. In this manner, the first subplane 11a and the second subplane 11b may be connected to the first row decoder 15a and the second row decoder 15b respectively, and are therefore controlled independently. For example, the first subplane 11a may be connected to the first row decoder 15a via a word line WL, a serial select line SSL, and a ground select line GSL, and the second subplane 11b may be connected to the second row decoder 15b via a word line WL, a serial select line SSL, and a ground select line GSL.

[0090] Figure 11 A memory device having a B-VNAND structure according to an embodiment is schematically shown.

[0091] Reference Figure 11 The memory device 110 may include a memory cell region (CELL) and a peripheral circuit region (PERI). Figure 11 The memory device 110 may include and / or may be similar in many respects to the one described above. Figures 1 to 10 The memory devices 10, 30, 40, 50, 80, 90, and 100 are described and may include additional features not mentioned above. Therefore, for the sake of brevity, the references above may be omitted. Figures 1 to 10 The memory device 110 described herein is repeated.

[0092] The memory cell region (CELL) may include a first subplane 111a and a second subplane 111b, as well as upper bonding pads UBP1 and UBP2. In the memory cell region (CELL), upper bonding pad UBP1 is connected to a first bit line BL1 via via 114a, and the first bit line BL1 is connected to the first subplane 111a via via 114b. In the memory cell region (CELL), upper bonding pad UBP2 is connected to a second bit line BL2 via via 114c, and the second bit line BL2 is connected to the second subplane 111b via via 114d. For example, the first subplane 111a and the second subplane 111b may respectively include and / or may be similar to in many respects. Figure 10 The first subplane 11a and the second subplane 11b. For example, the first line BL1 may be included in... Figure 10 The first line group BLG1, and the second line BL2 can be included. Figure 10 In the second line group BLG2.

[0093] The Peripheral Circuit Region (PERI) may include a first page buffer PB1 112a, a second page buffer PB2 112b, multiple line decoders (e.g., a first line decoder 113a and a second line decoder 113b), and multiple lower bonding pads (e.g., a first lower bonding pad LBP1 and a second lower bonding pad LBP2). In the PERI, lower bonding pad LBP1 may be connected to the first page buffer 112a, and lower bonding pad LBP2 may be connected to the second page buffer 112b. For example, lower bonding pad LBP1 may be connected to the first page buffer 112a via a first via 115a and a second via 115b, and a lower metal layer 116a. For example, lower bonding pad LBP2 may be connected to the second page buffer 112b via a third via 115c and a fourth via 115d, and a lower metal layer 116b. For example, the first page buffer 112a may include and / or may be similar in many respects to... Figure 10 The page buffer in the first page buffer 12a, and the second page buffer 112b may include and / or may be similar in many respects to the page buffer in the first page buffer 12a. Figure 10 The page buffer in the second page buffer 12b.

[0094] Figure 12 This is a plan view showing a memory device according to an embodiment.

[0095] Reference Figure 12 The memory device 120 may include a plurality of MATs (e.g., a first MAT1 and a second MAT2 arranged in the first direction Y, and a third MAT3 and a fourth MAT4 arranged in the first direction Y). In an embodiment, the first MAT1 and the third MAT3 may be separated from each other in the second direction X, and the second MAT2 and the fourth MAT4 may be separated from each other in the second direction X. In this manner, the first MAT1 to the fourth MAT4 may be arranged in a 2×2 array. For example, each of the plurality of MAT1 to MAT4 may include and / or may be similar in many respects to Figure 1 or Figure 10 The memory cell array 11.

[0096] Memory device 120 may include and / or may be similar in many respects to Figure 5 A modified example of the memory device 50, and referring to the above. Figure 5 The given description can also be applied to this embodiment. In the embodiment, each of the plurality of MATs MAT1 to MAT4 may include three (3) subplanes. For example, the first MAT MAT1 may include a plurality of subplanes (e.g., a first subplane SPL1a, a second subplane SPL1b, and a third subplane SPL1c), bit lines BL respectively connected to the plurality of subplanes SPL1a to SPL1c, and a plurality of common source plates (e.g., a first common source plate 121a and a second common source plate 121b). The memory device 120 may also include a line decoder XDEC1 connected to the first MAT MAT1.

[0097] Figure 13 This is a plan view showing a memory device according to an embodiment.

[0098] Reference Figure 13 The memory device 130 may include a plurality of MATs (e.g., a first MAT MAT1 and a second MAT MAT2 arranged in the first direction Y, and a third MAT MAT3 and a fourth MAT MAT4 arranged in the first direction Y). In an embodiment, the first MAT MAT1 and the third MAT MAT3 may be adjacent in the second direction X, and the second MAT MAT2 and the fourth MAT MAT4 may be adjacent in the second direction X. In this manner, the first MAT MAT1 to the fourth MAT MAT4 may be arranged in a 2×2 array. For example, each of the plurality of MATs MAT1 to MAT4 may include and / or may be similar in many respects to Figure 1 or Figure 10 The memory cell array 11.

[0099] Memory device 130 may include and / or may be similar in many respects to Figure 12 A modified example of the memory device 120, and referring to the above. Figure 12 The given description can also be applied to memory device 130. In embodiments, each of the plurality of MATMAT1 to MAT4 may include four (4) subplanes. For example, the first MAT MAT1 may include a plurality of subplanes (e.g., first subplane SPL1a, second subplane SPL1b, third subplane SPL1c, and fourth subplane SPL1d), bit lines BL respectively connected to the plurality of subplanes SPL1a to SPL1d, and a plurality of common source plates (e.g., first common source plate 131a and second common source plate 131b). Memory device 130 may also include a line decoder XDEC1 connected to the first MAT MAT1.

[0100] Figure 14 This is a plan view showing a memory device according to an embodiment.

[0101] Reference Figure 14 The memory device 140 may include a plurality of MATs (e.g., a first MAT1 and a second MAT2) arranged in the first direction Y. In this manner, the plurality of MATs MAT1 and MAT2 may be arranged in a 2×1 array. For example, each of the plurality of MATs MAT1 and MAT2 may include and / or may be similar in many respects to Figure 1 or Figure 10 The memory cell array 11. The memory device 140 may include and / or may be similar in many respects to the memory cell array 11. Figure 13 A modified example of the memory device 130, and referring to the above. Figure 13 The given description can also be applied to memory device 140.

[0102] In an embodiment, each of the plurality of MATs MAT1 and MAT2 may include four (4) subplanes. For example, the first MAT1 may include a plurality of subplanes (e.g., first subplane SPL1a, second subplane SPL1b, third subplane SPL1c, and fourth subplane SPL1d), bit lines BL respectively connected to the plurality of subplanes SPL1a to SPL1d, and a plurality of common source plates (e.g., first common source plate 141a and second common source plate 141b). The memory device 140 may also include a line decoder XDEC1 connected to the first MAT MAT1. As another example, the second MAT MAT2 may include a plurality of subplanes (e.g., first subplane SPL2a, second subplane SPL2b, third subplane SPL2c, and fourth subplane SPL2d), bit lines BL respectively connected to the plurality of subplanes SPL2a to SPL2d, and a plurality of common source plates (e.g., first common source plate 142a and second common source plate 142b). Memory device 140 may also include a line decoder XDEC2 connected to a second MAT MAT2.

[0103] Figure 15 This is a plan view showing a memory device according to an embodiment.

[0104] Reference Figure 15 The memory device 150 may include a plurality of MATs. For example, the memory device 150 may include a first MAT MAT1 and a second MAT MAT2 arranged in a first direction Y, a third MAT MAT3 and a fourth MAT MAT4 arranged in the first direction Y, and a fifth MAT MAT5 and a sixth MAT MAT6 arranged in the first direction Y. In an embodiment, the first MAT1, the third MAT3 and the fifth MAT5 may be arranged in a second direction X, and the second MAT2, the fourth MAT4 and the sixth MAT6 may be arranged in the second direction X. In this manner, the plurality of MATs MAT1 to MAT6 may be arranged in a 2×3 array. For example, each of the plurality of MATs MAT1 to MAT6 may include and / or may be similar in many respects to Figure 1 or Figure 10 The memory cell array 11.

[0105] Memory device 150 may include and / or may be similar in many respects to Figure 5 A modified example of the memory device 50, and referring to the above. Figure 5The given description can also be applied to memory device 150. In embodiments, each of the plurality of MATs MAT1 to MAT6 may include two (2) subplanes. For example, the first MAT MAT1 may include a first subplane SPL1a and a second subplane SPL1b, bit lines BL connected to the first subplane SPL1a and the second subplane SPL1b respectively, and a first common source plate 151a and a second common source plate 151b. Memory device 150 may also include a line decoder XDEC1 connected to the first MAT MAT1.

[0106] Figure 16 This is a plan view showing a memory device according to an embodiment.

[0107] Reference Figure 16 The memory device 160 may include a plurality of MATs. For example, the memory device 160 may include a first MAT MAT1 and a second MAT MAT2 arranged in the first direction Y, a third MAT MAT3 and a fourth MAT MAT4 arranged in the first direction Y, a fifth MAT MAT5 and a sixth MAT MAT6 arranged in the first direction Y, and a seventh MAT MAT7 and an eighth MAT MAT8 arranged in the first direction Y. In an embodiment, the first MAT MAT1, the third MAT MAT3, the fifth MAT MAT5, and the seventh MAT MAT7 may be arranged in the second direction X, and the second MAT MAT2, the fourth MAT MAT4, the sixth MAT MAT6, and the eighth MAT MAT8 may be arranged in the second direction X. In this manner, the plurality of MATs MAT1 to MAT8 may be arranged in a 2×4 array. For example, each of the plurality of MATs MAT1 to MAT8 may include and / or may be similar in many respects to Figure 1 or Figure 10 The memory cell array 11. The memory device 160 may include and / or may be similar in many respects to the memory cell array 11. Figure 15 A modified example of the memory device 150, and referring to the above. Figure 15 The given description can also be applied to this embodiment. In the embodiment, each of the first MAT MAT1 to the eighth MAT MAT8 may include two (2) sub-planes and two (2) common source plates.

[0108] Figure 17 This is a plan view showing a memory device according to an embodiment.

[0109] Reference Figure 17The memory device 170 may include a plurality of MATs. For example, the memory device 170 may include a first MAT MAT1, a second MAT MAT2, and a third MAT MAT3 arranged in a first direction Y, and a fourth MAT MAT4, a fifth MAT MAT5, and a sixth MAT MAT6 arranged in the first direction Y. In an embodiment, the first MAT MAT1 and the fourth MAT MAT4 may be adjacent in the second direction X, the second MAT MAT2 and the fifth MAT MAT5 may be adjacent in the second direction X, and the third MAT MAT3 and the sixth MAT MAT6 may be adjacent in the second direction X. In this manner, the plurality of MATs MAT1 to MAT6 may be arranged in a 3×2 array. For example, each of the plurality of MATs MAT1 to MAT6 may include and / or may be similar in many respects to Figure 1 or Figure 10 The memory cell array 11. The memory device 170 may include and / or may be similar in many respects to the memory cell array 11. Figure 5 A modified example of the memory device 50, and referring to the above. Figure 5 The given description can also be applied to memory device 170. In an embodiment, each of the plurality of MATs MAT1 to MAT6 may include two (2) subplanes and two (2) common source plates.

[0110] Figure 18 This is a plan view showing a memory device according to an embodiment.

[0111] Reference Figure 18 The memory device 180 may include a plurality of MATs. For example, the memory device 180 may include a first MAT MAT1, a second MAT MAT2, and a third MAT MAT3 arranged in the first direction Y; a fourth MAT MAT4, a fifth MAT MAT5, and a sixth MAT MAT6 arranged in the first direction Y; and a seventh MAT MAT7, an eighth MAT MAT8, and a ninth MAT MAT9 arranged in the first direction Y. In an embodiment, the first MAT MAT1, the fourth MAT MAT4, and the seventh MAT MAT7 may be adjacent in the second direction X; the second MAT MAT2, the fifth MAT MAT5, and the eighth MAT MAT8 may be adjacent in the second direction X; and the third MAT MAT3, the sixth MAT MAT6, and the ninth MAT MAT9 may be adjacent in the second direction X. In this manner, the plurality of MATs MAT1 to MAT9 may be arranged in a 3×3 array. For example, each of the plurality of MATs MAT1 to MAT9 may include and / or may be similar in many respects to Figure 1 or Figure 10 The memory cell array 11. The memory device 180 may include and / or may be similar in many respects to the memory cell array 11. Figure 17 A modified example of the memory device 170, and referring to the above. Figure 17 The given description can also be applied to memory device 180. In an embodiment, each of the plurality of MATs MAT1 to MAT9 may include two (2) subplanes and two (2) common source plates.

[0112] Figure 19 This is a diagram illustrating a memory device according to an embodiment.

[0113] Reference Figure 19 The memory device 500 may have a C2C structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region (PERI) may be manufactured separately. The at least one upper chip and the lower chip may then be connected to each other by a bonding method to realize the C2C structure. For example, the bonding method may refer to a method of electrically connecting and / or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, if the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Optionally, the bonding metal pattern may include, but is not limited to, aluminum (Al), tungsten (W), etc.

[0114] The memory device 500 may include at least one on-chip containing cell regions. For example, such as Figure 19 As shown, the memory device 500 may include two (2) upper chips. However, embodiments of this disclosure are not limited thereto, and the memory device 500 may include more (e.g., three (3) or more) upper chips. In the case where the memory device 500 includes two (2) upper chips, a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PERI can be manufactured separately, and then the first upper chip, the second upper chip, and the lower chip can be connected to each other by a bonding method to manufacture the memory device 500. The first upper chip can be flipped and subsequently connected to the lower chip by a bonding method, and the second upper chip can also be flipped and subsequently connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first and second upper chips may be defined based on the orientation of the chip before each of the first and second upper chips is flipped. That is, in Figure 19 In this context, the upper portion of the lower chip may refer to an upper portion defined relative to the +Z-axis direction, and the upper portion of each of the first and second upper chips may refer to an upper portion defined relative to the -Z-axis direction. However, embodiments of this disclosure are not limited thereto. In some embodiments, at least one of the first and second upper chips may be flipped and subsequently connected to the corresponding chip by a bonding method.

[0115] Each of the peripheral circuit region PERI and the first cell region CELL1 and the second cell region CELL2 of the memory device 500 may include an external pad bonding region PA, a word line bonding region WLBA and a bit line bonding region BLBA.

[0116] The Peripheral Circuit Region (PERI) may include a first substrate 210 and a plurality of circuit devices (e.g., first circuit device 220a, second circuit device 220b, and third circuit device 220c) formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be disposed on the plurality of circuit devices 220a to 220c, and a plurality of metal wires electrically connected to the plurality of circuit devices 220a to 220c may be disposed in the interlayer insulating layer 215. For example, the plurality of metal wires may include first metal wires (e.g., first metal wire 230a, second metal wire 230b, and third metal wire 230c) connected to the plurality of circuit devices 220a to 220c and second metal wires (e.g., fourth metal wire 240a, fifth metal wire 240b, and sixth metal wire 240c) formed on the first metal wires 230a to 230c. The plurality of metal wires may include at least one of a variety of conductive materials. For example, the first metal lines 230a to 230c may include tungsten (W) with relatively high resistivity, and the second metal lines 240a to 240c may include copper (Cu) with relatively low resistivity.

[0117] The first metal lines 230a to 230c and the second metal lines 240a to 240c are shown and described based on this embodiment. However, the embodiments of this disclosure are not limited thereto. In some embodiments, at least one or more additional metal lines may be further formed on the second metal lines 240a to 240c. In this manner, the second metal lines 240a to 240c may comprise aluminum (Al), and at least some of the additional metal lines formed on the second metal lines 240a to 240c may comprise copper (Cu) having a resistivity lower than that of the aluminum (Al) of the second metal lines 240a to 240c.

[0118] Interlayer insulating layer 215 may be disposed on first substrate 210 and may include insulating materials such as, but not limited to, silicon oxide (SiO) and / or silicon nitride (SiN).

[0119] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (e.g., first word line 331, second word line 332, third word line 333, fourth word line 334, fifth word line 335, sixth word line 336, seventh word line 337, and eighth word line 338) may be stacked on the second substrate 310 in a direction perpendicular to the top surface of the second substrate 310 (e.g., the Z-axis direction). In some embodiments, the plurality of word lines 330 may be formed in at least one memory block. Serial select lines and ground select lines may be arranged above and below the word lines 330, and the plurality of word lines 330 may be arranged between the serial select lines and the ground select lines. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and multiple word lines 430 (e.g., first word line 431, second word line 432, third word line 433, fourth word line 434, fifth word line 435, sixth word line 436, seventh word line 437, and eighth word line 438) may be stacked on the third substrate 410 in a direction perpendicular to the top surface of the third substrate 410 (e.g., the Z-axis direction). In some embodiments, the multiple word lines 430 may be formed in at least one memory block. Each of the second substrate 310 and the third substrate 410 may include at least one of a variety of materials, such as, but not limited to, a silicon (Si) substrate, a silicon-germanium (Si-Ge) substrate, a germanium (Ge) substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Multiple channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2. In some embodiments, the multiple channel structures CH may be formed in at least one memory block.

[0120] In some embodiments, as shown in region A (e.g., region A1), a channel structure CH may be disposed in a bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate word line 330, serial select line, and ground select line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to a first metal line 350c and a second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH via the first metal line 350c. The bit line 360c may extend in a first direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 310.

[0121] In some embodiments, as shown in region A (e.g., region A2), the channel structure CH may include a lower channel LCH and an upper channel UCH that can be interconnected. For example, the channel structure CH may be formed by a process for forming the lower channel LCH and / or a process for forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filler insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filler insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. Compared to existing non-volatile memory devices, the memory device 500 according to the embodiment may include a channel with improved width consistency due to the lower channel LCH and upper channel UCH formed by a process performed sequentially.

[0122] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH, as shown in region A2, the word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, the second word line 332 and the third word line 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In such cases, data may not be stored in the memory cells connected to the dummy word lines. Optionally or additionally, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the general word lines. The voltage level applied to the dummy word lines may be different from the voltage level applied to the general word lines, and therefore, the impact of the inconsistent channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device can be reduced.

[0123] Furthermore, in region A2, the number of lower word lines (e.g., first word line 331 and second word line 332) penetrated by the lower channel LCH may be less than the number of upper word lines (e.g., third word line 333 to eighth word line 338) penetrated by the upper channel UCH. However, embodiments of this disclosure are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. Additionally, the structural features and connection relationships of the channel structures CH arranged in the second cell region CELL2 may be substantially the same as those of the channel structures CH arranged in the first cell region CELL1.

[0124] In the bit line bonding region BLBA, a first through electrode THV1 can be disposed in the first cell region CELL1, and a second through electrode THV2 can be disposed in the second cell region CELL2. For example... Figure 19 As shown, the first through-electrode THV1 can penetrate the common source line 320 and multiple word lines 330. In a particular embodiment, the first through-electrode THV1 can also penetrate the second substrate 310. The first through-electrode THV1 may include a conductive material. Optionally, the first through-electrode THV1 may include a conductive material surrounded by an insulating material. The second through-electrode THV2 may have the same shape and structure as the first through-electrode THV1.

[0125] In some embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected to each other via a first through metal pattern 372d and a second through metal pattern 472d. The first through metal pattern 372d can be formed at the bottom of a first upper chip including a first cell region CELL1, and the second through metal pattern 472d can be formed at the top of a second upper chip including a second cell region CELL2. The first through electrode THV1 can be electrically connected to a first metal line 350c and a second metal line 360c. A lower via 371d can be formed between the first through electrode THV1 and the first through metal pattern 372d, and an upper via 471d can be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d can be connected to each other by a bonding method.

[0126] Additionally, in the bit line bonding area BLBA, an upper metal pattern 252 may be formed in the uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed in the uppermost metal layer of the first cell region CELL1. The upper metal pattern 392 of the first cell region CELL1 and the upper metal pattern 252 of the peripheral circuit region PERI can be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, bit lines 360c can be electrically connected to page buffers included in the peripheral circuit region PERI. For example, some of the circuit devices 220c in the peripheral circuit region PERI can constitute page buffers, and bit lines 360c can be electrically connected to the circuit devices 220c constituting page buffers via the upper bonding metal pattern 370c of the first cell region CELL1 and the upper bonding metal pattern 270c of the peripheral circuit region PERI.

[0127] Continue to refer to Figure 19In the word line bonding area WLBA, the word line 330 of the first cell region CELL1 can extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 310, and can be connected to a plurality of cell contact plugs 340 (e.g., first cell contact plug 341, second cell contact plug 342, third cell contact plug 343, fourth cell contact plug 344, fifth cell contact plug 345, sixth cell contact plug 346, and seventh cell contact plug 347). A first metal line 350b and a second metal line 360b can be sequentially connected to the cell contact plugs 340 connected to the word line 330. In the word line bonding area WLBA, the cell contact plugs 340 can be connected to the peripheral circuit region PERI via the upper bonding metal pattern 370b of the first cell region CELL1 and the upper bonding metal pattern 270b of the peripheral circuit region PERI.

[0128] Cell contact plug 340 can be electrically connected to a line decoder included in the peripheral circuitry region PERI. For example, some of the circuit devices 220b in the peripheral circuitry region PERI can constitute a line decoder, and cell contact plug 340 can be electrically connected to the circuit devices 220b constituting the line decoder via the upper bonding metal pattern 370b of the first cell region CELL1 and the upper bonding metal pattern 270b of the peripheral circuitry region PERI. In some embodiments, the operating voltage of the circuit devices 220b constituting the line decoder can be different from the operating voltage of the circuit devices 220c constituting the page buffer. For example, the operating voltage of the circuit devices 220c constituting the page buffer can be greater than the operating voltage of the circuit devices 220b constituting the line decoder.

[0129] Similarly, in the word line bonding area WLBA, the word line 430 of the second cell region CELL2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 410, and may be connected to a plurality of cell contact plugs 440 (e.g., first cell contact plug 441, second cell contact plug 442, third cell contact plug 443, fourth cell contact plug 444, fifth cell contact plug 445, sixth cell contact plug 446, and seventh cell contact plug 447). The cell contact plugs 440 may be connected to the peripheral circuit region PERI via the upper metal pattern of the second cell region CELL2 and the lower metal pattern, upper metal pattern, and cell contact plug 348 of the first cell region CELL1.

[0130] In the word line bonding area WLBA, an upper bonding metal pattern 370b may be formed in the first cell area CELL1, and an upper bonding metal pattern 270b may be formed in the peripheral circuit area PERI. The upper bonding metal pattern 370b of the first cell area CELL1 and the upper bonding metal pattern 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 370b and the upper bonding metal pattern 270b may comprise aluminum, copper, or tungsten.

[0131] In the external pad bonding area PA, a lower metal pattern 371e may be formed in the lower part of the first cell region CELL1, and an upper metal pattern 472a may be formed in the upper part of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected to each other in the external pad bonding area PA by a bonding method. Similarly, the upper metal pattern 372a may be formed in the upper part of the first cell region CELL1, and the upper metal pattern 272a may be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected to each other by a bonding method.

[0132] Common source electrode contact plugs 380 and 480 may be disposed in the external pad bonding region PA. Common source electrode contact plugs 380 and 480 may comprise conductive materials (such as, but not limited to, metals, metal compounds, and / or doped polysilicon). Common source electrode contact plug 380 of the first cell region CELL1 may be electrically connected to common source electrode 320, and common source electrode contact plug 480 of the second cell region CELL2 may be electrically connected to common source electrode 420. First metal wire 350a and second metal wire 360a may be sequentially stacked on common source electrode contact plug 380 of the first cell region CELL1, and first metal wire 450a and second metal wire 460a may be sequentially stacked on common source electrode contact plug 480 of the second cell region CELL2.

[0133] Multiple I / O pads (e.g., first I / O pad 205, second I / O pad 405, and third I / O pad 406) may be arranged in the external pad mating area PA. See reference. Figure 19The lower insulating layer 201 may cover the bottom surface of the first substrate 210, and the first I / O pad 205 may be formed on the lower insulating layer 201. The first I / O pad 205 may be connected to at least one of a plurality of circuit devices 220a arranged in the peripheral circuit region PERI via the first I / O contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be disposed between the first I / O contact plug 203 and the first substrate 210 to electrically isolate the first I / O contact plug 203 from the first substrate 210.

[0134] An upper insulating layer 401 covering the top surface of the third substrate 410 may be formed on the third substrate 410. A second I / O pad 405 and / or a third I / O pad 406 may be disposed on the upper insulating layer 401. The second I / O pad 405 may be connected to at least one of a plurality of circuit devices 220a disposed in the peripheral circuit region PERI via second I / O contact plugs 403 and 303, and the third I / O pad 406 may be connected to at least one of a plurality of circuit devices 220a disposed in the peripheral circuit region PERI via third I / O contact plugs 404 and 304.

[0135] In some embodiments, the third substrate 410 may not be disposed in the region where the I / O contact plug is provided. For example, as shown in region B, the third I / O contact plug 404 may be spaced apart from the third substrate 410 in a direction parallel to the top surface of the third substrate 410 and may penetrate the interlayer insulation layer 415 of the second cell region CELL2 to connect to the third I / O pad 406. In such a case, the third I / O contact plug 404 may be formed by at least one of various processes.

[0136] In some embodiments, as shown in region B1, the third I / O contact plug 404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third I / O contact plug 404 may gradually increase (become larger) towards the upper insulating layer 401. That is, the diameter of the channel structure CH described in region A1 may gradually decrease (become smaller) towards the upper insulating layer 401, but the diameter of the third I / O contact plug 404 may gradually increase towards the upper insulating layer 401. For example, the third I / O contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are joined together by a joining method.

[0137] In a particular embodiment, as shown in region B2, the third I / O contact plug 404 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third I / O contact plug 404 may gradually decrease towards the upper insulating layer 401. That is, similar to the channel structure CH, the diameter of the third I / O contact plug 404 may gradually decrease towards the upper insulating layer 401. For example, the third I / O contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are engaged with each other.

[0138] In some embodiments, the I / O contact plug may be stacked with the third substrate 410. For example, as shown in region C, the second I / O contact plug 403 may penetrate the interlayer insulation layer 415 of the second cell region CELL2 in a third direction (e.g., the Z-axis direction) and be electrically connected to the second I / O pad 405 via the third substrate 410. In such a case, the connection structure of the second I / O contact plug 403 and the second I / O pad 405 may be implemented by various methods.

[0139] In some embodiments, as shown in region C1, the opening 408 may be formed to penetrate the third substrate 410, and the second I / O contact plug 403 may be directly connected to the second I / O pad 405 through the opening 408 formed in the third substrate 410. In such a case, as shown in region C1, the diameter of the second I / O contact plug 403 may gradually increase toward the second I / O pad 405. However, embodiments of the present disclosure are not limited thereto, and in some embodiments, the diameter of the second I / O contact plug 403 may gradually decrease toward the second I / O pad 405.

[0140] In some embodiments, as shown in region C2, an opening 408 penetrating the third substrate 410 may be formed, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second I / O pad 405, and the other end of the contact 407 may be connected to the second I / O contact plug 403. Thus, the second I / O contact plug 403 can be electrically connected to the second I / O pad 405 through the contact 407 in the opening 408. In such a case, as shown in region C2, the diameter of the contact 407 may gradually increase toward the second I / O pad 405, and the diameter of the second I / O contact plug 403 may gradually decrease toward the second I / O pad 405. For example, the second I / O contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are engaged with each other, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are engaged with each other.

[0141] In some embodiments, as shown in region C3, compared to the embodiment in region C2, a stop member 409 may be further formed on the bottom end of the opening 408 of the third substrate 410. The stop member 409 may be a metal wire formed in the same layer as the common source line 420. Optionally, the stop member 409 may be a metal wire formed in the same layer as at least one of the word lines 430. The second I / O contact plug 403 may be electrically connected to the second I / O pad 405 via the contact member 407 and the stop member 409.

[0142] Similar to the second I / O contact plug 403 and the third I / O contact plug 404 in the second cell region CELL2, the diameter of each of the second I / O contact plug 303 and the third I / O contact plug 304 in the first cell region CELL1 may gradually decrease and / or gradually increase towards the downward metal pattern 371e.

[0143] In some embodiments, slot 411 may be formed in the third substrate 410. For example, slot 411 may be formed at a specific location in the outer pad engagement region PA. For example, as shown in region D, slot 411 may be located between the second I / O pad 405 and the unit contact plug 440 when viewed in a plan view. Alternatively, the second I / O pad 405 may be located between slot 411 and the unit contact plug 440 when viewed in a plan view.

[0144] In some embodiments, as shown in region D1, the slit 411 may be formed to penetrate the third substrate 410. For example, the slit 411 may be used to prevent the third substrate 410 from slightly cracking when the opening 408 is formed. However, the embodiments are not limited thereto, and in some embodiments, the slit 411 may be formed to have a depth in the range of about 60% to about 70% of the thickness of the third substrate 410.

[0145] In some embodiments, as shown in region D2, conductive material 412 may be formed in slot 411. For example, conductive material 412 may be used to release leakage current that occurs during the driving of circuit devices in the external pad bonding region PA to the outside. In such a case, conductive material 412 may be connected to an external ground wire.

[0146] In some embodiments, as shown in region D3, insulating material 413 may be formed in the slot 411. For example, insulating material 413 may be used to electrically isolate the second I / O pad 405 and the second I / O contact plug 403 disposed in the outer pad bonding region PA from the word line bonding region WLBA. Because insulating material 413 is formed in the slot 411, the effect of the voltage supplied through the second I / O pad 405 on the metal layer disposed on the third substrate 410 in the word line bonding region WLBA can be prevented and / or reduced compared to conventional non-volatile memory devices.

[0147] In some embodiments, the first to third I / O pads 205, 405, and 406 may be selectively formed. For example, the memory device 500 may be implemented to include only the first I / O pad 205 disposed on the first substrate 210, only the second I / O pad 405 disposed on the third substrate 410, or only the third I / O pad 406 disposed on the upper insulating layer 401.

[0148] In some embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after the substrate removal. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then an insulating layer covering the top surface of the common source electrode 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and an upper insulating layer 401 covering the top surface of the common source electrode 420 and / or a conductive layer for connection may be formed.

[0149] According to an embodiment, the memory cell array included in each of the first cell region CELL1 and the second cell region CELL2 of the memory device 500 can be divided into multiple sub-planes, and the multiple sub-planes can be arranged in the extension direction of the bit lines (e.g., the first direction Y). The arrangement of the sub-planes can reduce the size of each of the first cell region CELL1 and the second cell region CELL2 including the memory cell array. Furthermore, compared to existing non-volatile memory devices, the arrangement of these sub-planes can improve the aspect ratio of the chip including the memory device 500, thereby improving wafer utilization efficiency.

[0150] Figure 20 A solid-state drive (SSD) system including a memory device is shown according to an embodiment.

[0151] Reference Figure 20The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may exchange signals (SIG) with the host 1100 via a signal connector and / or receive power (PWR) via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and multiple memory devices (MEMs) (e.g., a first memory device 1230, a second memory device 1240, and a third memory device 1250). The multiple memory devices 1230 to 1250 may be and / or may include vertically stacked NAND flash memory devices. In some embodiments, the multiple memory devices 1230 to 1250 may be connected to the SSD controller 1210 via multiple channels Ch1 to Chn, respectively. The SSD 1200 may use the above references... Figures 1 to 19 Implemented by one or more of the described embodiments.

[0152] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A non-volatile memory device, comprising: The memory cell region includes a plurality of memory cell arrays arranged in a first direction, each of the plurality of memory cell arrays including a plurality of subplanes arranged in the first direction, each of the plurality of subplanes extending in a second direction intersecting the first direction; as well as The peripheral circuit region is located vertically below the memory cell region, and includes multiple page buffer circuits respectively associated with the plurality of memory cell arrays. Each of the plurality of memory cell arrays further includes: A first common source plate extends in a first direction and is commonly coupled to the plurality of subplanes; The first line group is coupled to the first subplane among the plurality of subplanes; and The second line group is combined with the second sub-plane among the plurality of sub-planes. Each of the plurality of page buffer circuits includes: The first page buffer is coupled to the first subplane via the first bit line group; and The second page buffer is connected to the second subplane via the second bit line group.

2. The non-volatile memory device according to claim 1, wherein, Each of the plurality of sub-planes includes a plurality of memory blocks, and Each of the plurality of memory blocks includes: The channel structure extends vertically; and Multiple letter lines are integrated with the channel structure.

3. The non-volatile memory device according to claim 1, wherein, Each of the plurality of sub-planes includes a plurality of memory blocks, and Each of the plurality of memory blocks includes: Multiple memory stacks are stacked vertically, each of the multiple memory stacks extending vertically; and Multiple word lines, combined with the multiple memory stacks.

4. The non-volatile memory device according to claim 1, wherein, Each of the plurality of memory cell arrays further includes a second common-source plate, the second common-source plate extending in a first direction and separated from the first common-source plate in a second direction. The first subplane includes a first memory block coupled to a first common-source plate and a second memory block coupled to a second common-source plate. The second subplane includes a third memory block coupled to the first common source plate and a fourth memory block coupled to the second common source plate.

5. The non-volatile memory device according to claim 4, wherein, Each of the plurality of memory cell arrays further includes: The first word line group is commonly associated with the first memory block and the second memory block; and The second word line group is shared with the third and fourth memory blocks.

6. The non-volatile memory device according to claim 4, wherein, Each of the plurality of memory cell arrays further includes: The first word line group is associated with the first memory block; The second word line group is combined with the second memory block; The third word line group is combined with the third memory block; and The fourth word line group is combined with the fourth memory block.

7. The non-volatile memory device according to claim 4, wherein, The peripheral circuit area also includes: The first-line decoder is located below the first region between the first memory block and the second memory block; and The second-line decoder is located below the second region between the third and fourth memory blocks.

8. The non-volatile memory device according to claim 1, wherein, The peripheral circuit area also includes: The first row decoder, combined with the first subplane; and The second-line decoder is combined with the second subplane.

9. The non-volatile memory device according to claim 8, wherein, The peripheral circuit area also includes: The first step involves a transistor circuitry integrated between the first row decoder and the first subplane; and The second is achieved through transistor circuitry, which is integrated between the second row decoder and the second subplane.

10. The non-volatile memory device according to any one of claims 1 to 9, wherein, The memory cell region also includes an upper bonding pad. The peripheral circuit area also includes a lower bonding pad, and The memory cell region is vertically connected to the peripheral circuit region via upper and lower bonding pads.

11. A non-volatile memory device, comprising: The memory cell region includes multiple memory cell arrays and an upper bonding pad. The multiple memory cell arrays include a first memory cell array, a second memory cell array, a third memory cell array, and a fourth memory cell array. The first and second memory cell arrays are arranged in a first direction, the third and fourth memory cell arrays are arranged in the first direction, the first and third memory cell arrays are separated from each other in a second direction intersecting the first direction, and the second and fourth memory cell arrays are separated from each other in the second direction. as well as The peripheral circuit area includes multiple page buffer circuits and lower bonding pads. The multiple page buffer circuits include a first page buffer circuit, a second page buffer circuit, a third page buffer circuit, and a fourth page buffer circuit. The multiple page buffer circuits are respectively coupled to the multiple memory cell arrays. The peripheral circuit region is vertically coupled to the memory cell region via upper and lower bonding pads. Each of the plurality of memory cell arrays includes a plurality of sub-planes arranged in a first direction, each of the plurality of sub-planes extending in a second direction, and each of the plurality of sub-planes being associated with a plurality of different bit line groups. Each of the plurality of page buffer circuits includes a plurality of page buffers respectively associated with the plurality of subplanes.

12. The non-volatile memory device according to claim 11, wherein, Each of the plurality of sub-planes includes a plurality of memory blocks, and Each of the plurality of memory blocks includes: The channel structure extends vertically; and Multiple letter lines are integrated with the channel structure.

13. The non-volatile memory device according to claim 11, wherein, Each of the plurality of sub-planes includes a plurality of memory blocks, and Each of the plurality of memory blocks includes: Multiple memory stacks are stacked vertically, each of the multiple memory stacks extending vertically; and Multiple word lines, combined with the multiple memory stacks.

14. The non-volatile memory device according to claim 11, wherein, Each of the plurality of memory cell arrays further includes a first common source plate extending in a first direction and a second common source plate extending in the first direction, the first common source plate and the second common source plate being disposed separately from each other in a second direction. Each of the plurality of sub-planes includes a first memory block coupled to a first common-source plate and a second memory block coupled to a second common-source plate, and The peripheral circuit region includes a line decoder located below the region between the first common source plate and the second common source plate.

15. The non-volatile memory device according to claim 14, wherein, Each of the plurality of memory cell arrays also includes a first word line group that is commonly associated with the first memory block and the second memory block.

16. The non-volatile memory device according to claim 14, wherein, Each of the plurality of memory cell arrays further includes: The first word line group is associated with the first memory block; and The second word line group is combined with the second memory block.

17. The non-volatile memory device according to any one of claims 11 to 16, wherein, Each of the plurality of memory cell arrays also includes a common source plate that is commonly coupled to the plurality of subplanes.

18. A non-volatile memory device, comprising: The memory cell region includes a plurality of memory cell arrays arranged in an array on a first wafer and an upper bonding pad coupled to the plurality of memory cell arrays. as well as The peripheral circuit area includes the lower bonding pad disposed on the second wafer. The peripheral circuit region is vertically coupled to the memory cell region via upper and lower bonding pads. Each of the plurality of memory cell arrays includes: A plurality of subplanes are arranged in a first direction, each of the plurality of subplanes extending in a second direction intersecting the first direction; Multiple bit line groups are respectively coupled to the multiple sub-planes; The first common source plate extends in the first direction; and The second common source plate extends in the first direction, and the first and second common source plates are separated from each other in the second direction. Each of the plurality of sub-planes includes: Multiple first memory blocks, combined with a first common source plate; and Multiple second memory blocks are combined with a second common source plate.

19. The non-volatile memory device according to claim 18, wherein, The peripheral circuit area also includes multiple line decoders, which are disposed below the region between the first common source plate and the second common source plate and are respectively coupled to the multiple sub-planes.

20. The non-volatile memory device according to claim 18, wherein, The peripheral circuit area also includes multiple page buffer circuits, which are connected to the multiple subplanes via the multiple bit line groups.

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