Method of manufacturing poi structures with highly uniform piezoelectric layers

Abstract

The present invention relates to a method of manufacturing a piezoelectric on insulator (POI) structure, the method comprising: providing a donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises or consists of one of lithium tantalate and lithium niobate; transferring a piezoelectric layer from the piezoelectric substrate to a target substrate; and polishing the piezoelectric layer transferred to the target substrate using a chemical mechanical polishing (CMP) slurry, wherein the CMP slurry consists of an aqueous suspension of amorphous silicon, wherein the weight percentage of amorphous silicon is in the range of 4% to 18%.

Description

Technical Field

[0001] This invention relates to a method for manufacturing piezo-on-insulator (POI) structures, and particularly to a method for manufacturing POI structures that can be used to manufacture microelectronic devices, micromechanical devices, and photonic devices. Background Technology

[0002] In the fields of microelectronics, micromechanics, and photonics, POI structures are becoming increasingly important due to their superior sensitivity and information propagation performance, for example. Sensors such as surface acoustic wave (SAW) sensors or bulk acoustic wave (BAW) sensors, which utilize the piezoelectric effect to convert electrical signals into mechanical / acoustic waves, offer a particularly advantageous option because they can measure a variety of environmental parameters, including temperature, pressure, strain, and torque.

[0003] A typical POI structure comprises a layer of piezoelectric material, particularly a single-crystal material such as lithium niobate (LiNbO3) or lithium tantalate (LiTaO3), on a supporting substrate, for example, made of silicon. Various methods for forming thin layers of piezoelectric material on a supporting substrate are known in the art. (Smart Cut) TM The application of this technology has proven particularly advantageous. According to this technology (see, for example, WO2020 / 200986 A1), a piezoelectric substrate formed on a support substrate is weakened by implanting a light material, and then the piezoelectric substrate is bonded to a target substrate. A thin layer of piezoelectric material can be obtained on the support substrate by fracturing the weakened region. The transferred piezoelectric material layer is subjected to annealing followed by polishing, particularly chemical mechanical polishing (CMP), to improve crystal quality and obtain the desired uniformity of thickness for the single-domain piezoelectric material layer, where all dipole moments of the single-domain piezoelectric material layer are substantially parallel to each other along a given direction.

[0004] However, despite the progress made in engineering technology in recent years, there is still a risk that the thickness uniformity of the obtained transferred piezoelectric material layer is not high enough to meet the needs of practical applications. Summary of the Invention

[0005] Therefore, the object of this invention is to provide a method for manufacturing POI structures (based on Smart Cut). TM The technology (referring to the technology used in this study) allows the piezoelectric material layer of the POI structure to have high thickness uniformity.

[0006] This invention achieves this objective by providing a method for manufacturing a piezoelectric on-insulator (POI) structure, the method comprising: A donor substrate is provided, the donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises one of lithium tantalate (LiTaO3) and lithium niobate (LiNbO3) or is composed of one of lithium tantalate (LiTaO3) and lithium niobate (LiNbO3); Transferring the piezoelectric layer from the piezoelectric substrate to a target substrate (e.g., a silicon substrate); and The piezoelectric layer transferred to the target substrate was polished using a chemical mechanical polishing (CMP) slurry, wherein the CMP slurry consisted of an aqueous suspension of amorphous silicon, wherein the weight percentage of amorphous silicon ranged from 4% to 18%.

[0007] An annealing step can be performed before polishing to improve crystal quality and enhance the bonding between the piezoelectric layer and the target substrate. The amorphous silicon used in the CMP slurry can comprise or consist of precipitated amorphous silicon particles with a diameter ranging from 40 to 60 nanometers.

[0008] It is known in the art that polishing a transferred piezoelectric layer removes the top multidomain layer containing multiple regions exhibiting different polarities and improves surface quality (reducing roughness) and thickness uniformity. However, in the prior art, the CMP slurry used in the polishing process of the transferred piezoelectric layer consists of an aqueous suspension of amorphous silicon, wherein the weight percentage of amorphous silicon is much higher, i.e., in the range of 25 to 35%. The inventors of the present invention have discovered that, surprisingly, when polishing the transferred piezoelectric layer with a significantly lower concentration of amorphous silicon in the CMP slurry, better polishing results are obtained in terms of the thickness uniformity of the final obtained single-domain piezoelectric layer.

[0009] Other parameters throughout the manufacturing process can be selected according to conventional practices known to those skilled in the art (but see the description below). Depending on the actual selection of the piezoelectric material and other parameter values, a weight percentage of amorphous silicon ranging from 4% to 13%, particularly from 5% to 7%, may be beneficial for the resulting uniformity of the thickness of the transferred piezoelectric layer.

[0010] According to the implementation scheme, the step of providing a donor substrate (quasi-donor, PSD) includes: bonding a piezoelectric material block to a support (manipulation) substrate via a bonding layer; grinding and polishing the piezoelectric material block to obtain a piezoelectric substrate; and implanting a substance (e.g., hydrogen) into the piezoelectric substrate to obtain a weakening layer in the piezoelectric substrate. Thus, a suitable donor substrate can be reliably manufactured for providing a high-quality piezoelectric layer above the weakening layer. The bonding of the piezoelectric material block to the support substrate can be achieved using a dielectric bonding layer as an intermediate layer, such as a photopolymer layer, a layer made of silicon oxide and / or silicon nitride, or a layer containing silicon oxide and / or silicon nitride.

[0011] The steps of transferring a piezoelectric layer to a target substrate may include bonding a donor substrate to a target substrate (on the piezoelectric substrate side) and fracturing the piezoelectric substrate at a weakening layer during annealing. This allows for reliable transfer of the piezoelectric layer to the target substrate without significant defects. However, as mentioned above, further post-processing (annealing and polishing) is still required. It should be noted that naturally occurring silicon oxide may be present between the transferred piezoelectric layer and the target substrate. Furthermore, a dielectric assembly layer may be formed on or above the surface of the target substrate before transferring the piezoelectric layer. This dielectric assembly layer may be made of or contain silicon oxide and / or silicon nitride, or a stacked layer of these materials. Additionally, depending on the application, a charge trapping layer may be formed on or above the surface of the target substrate before transferring the piezoelectric layer. This charge trapping layer may be made of or contain polysilicon.

[0012] For the polishing process, the target substrate with the transferred piezoelectric layer is placed on a rotatable polishing head and brought into contact with a rotatable polishing pad. According to a specific embodiment, the polishing head rotates at 80 to 120 revolutions per minute (rpm), while the polishing pad rotates in the same direction as the polishing head, but at a different speed, ranging from 90 to 130 rpm. These parameter ranges have been shown to contribute to the uniformity of the thickness of the resulting polished piezoelectric layer.

[0013] According to another embodiment, the wafer pressure applied to the target substrate to press it onto the polishing pad is no greater than 20.68 kPa (3 psi) or less than 18.96 kPa (2.75 psi), for example, in the range of 17.24 kPa (2.5 psi) to 20.68 kPa (3 psi). For example, during polishing, the ratio of wafer pressure to the annular pressure used to hold the target substrate in the annular retainer is in the range of 1:2 to 5:3. These parameter ranges can be shown to be beneficial to the thickness uniformity of the resulting polished piezoelectric layer, especially when bonding within the aforementioned parameter ranges.

[0014] According to another embodiment, the flow rate of the CMP slurry is less than 250 ml / min, 200 ml / min, or 150 ml / min, or in the range of 150 ml / min to 250 ml / min. These parameter ranges can be shown to benefit the uniformity of the thickness of the resulting polished piezoelectric layer, especially when combined with the aforementioned parameter ranges.

[0015] Furthermore, a POI structure is provided, comprising a piezoelectric layer formed on or above a target substrate, the piezoelectric layer being obtained by one of the methods described above, wherein the piezoelectric layer exhibits a thickness uniformity of less than 50 nanometers, particularly less than 20 nanometers (thickness range along the diameter of the layer). Additionally, a microelectronic, micromechanical, or photonic device, or a microelectromechanical system (MEMS), incorporating this POI structure is also provided. Attached Figure Description

[0016] Other features and advantages of the invention will be described with reference to the accompanying drawings. In the description, reference will be made to the accompanying drawings, which are intended to illustrate preferred embodiments of the invention. It should be understood that these embodiments do not represent the full scope of the invention.

[0017] [ Figure 1 The steps of a method for manufacturing a POI structure according to an embodiment of the present invention are shown.

[0018] [ Figure 2 The diagram illustrates the technical effect of a method for manufacturing a POI structure according to an embodiment of the present invention, namely, obtaining a highly uniform piezoelectric layer. Detailed Implementation

[0019] This paper provides a method for fabricating a POI structure comprising a target substrate on which a piezoelectric layer with high thickness uniformity is formed. The high thickness uniformity is achieved through a polishing step using a relatively highly diluted aqueous suspension of amorphous silicon. The method employs Smart Cut... TM technology.

[0020] Figure 1 The steps of a method for manufacturing a POI structure according to an embodiment of the present invention are shown. This method is similar to that described in WO2020 / 200986 A1, but differs from the latter in that it employs an innovative method for polishing the transferred piezoelectric layer.

[0021] like Figure 1 As shown in step i), a donor substrate 1 is provided, which includes a piezoelectric substrate 1a formed on a support (manipulation) substrate 1b. The piezoelectric substrate 1a is made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3). The support substrate 1b can be made of one or more materials whose coefficient of thermal expansion is close to that of the target substrate 7, i.e., the difference between the coefficient of thermal expansion of the support substrate 1b and the target substrate 7 is less than the difference between the coefficients of thermal expansion of the piezoelectric substrate 1a and the target substrate 7. The support substrate 1b and the target substrate 7 can have the same coefficient of thermal expansion, and both substrates can, for example, be composed of or contain silicon. Furthermore, the two substrates can have similar thicknesses.

[0022] To obtain the donor substrate 1, a bulk piezoelectric material can be attached to the supporting substrate 1b, for example, using molecular adhesion bonding technology. This bonding can be achieved through a dielectric bonding (adhesion) layer ( Figure 1 (Not shown) is implemented as an intermediate layer, for example, a photopolymer layer or a layer made of silicon oxide and / or silicon nitride, or a layer containing silicon oxide and / or silicon nitride. The bonding process may include employing low-temperature thermal treatment (e.g., at a temperature between 50°C and 300°C, typically 100°C) to sufficiently enhance the bonding energy for subsequent thinning steps. Subsequently, the piezoelectric substrate 1a is formed by thinning (e.g., by grinding and / or chemical mechanical polishing).

[0023] The thinning step should be performed in a manner that gives the piezoelectric substrate 1a a sufficiently small thickness to alleviate the stress generated during the heat treatment applied in subsequent processing stages. On the other hand, in order to provide the piezoelectric layer 3 to be transferred to the target substrate 7, or to provide multiple such piezoelectric layers for sequential transfer to their respective target substrates in multiple transfer steps (after the donor substrate 1 has been regenerated accordingly), its thickness must be sufficiently large. The thickness of the piezoelectric substrate 1a can, for example, be between 5 micrometers and 400 micrometers, such as 20 micrometers or 100 micrometers.

[0024] Hydrogen (possibly supplemented with helium) is injected into the piezoelectric substrate 1a via the exposed surface 4 to generate a weakening layer 2, which marks the separation of the piezoelectric layer 3 from the remainder 5 of the donor substrate 1. The nature and dosage of the injected material, as well as the injection energy, can be selected based on the thickness of the piezoelectric layer 3 to be transferred to the target substrate 7 and the physicochemical properties of the piezoelectric substrate 1a. For example, for a lithium tantalate substrate, an injection dosage of 10... 16 and 5.10 17 at / cm 2 The hydrogen ions, with energies between 30 keV and 300 keV, define a piezoelectric layer 3 with a thickness of, for example, 200 nanometers to 2000 nanometers.

[0025] according to Figure 2 The method shown involves an attachment step (iii) following the implantation step (ii), whereby the donor substrate 1 is attached to the support substrate 7 via molecular adhesion and / or electrostatic bonding on the piezoelectric substrate 1a side. A dielectric component layer 7b may be disposed between the piezoelectric substrate 1a of the donor substrate 1 and the target substrate 7. The dielectric component layer 7b may comprise oxides and may comprise silicon oxide and / or silicon nitride or be made of silicon oxide and / or silicon nitride, or be a stacked layer composed of these materials. Furthermore, if required for practical application, a charge trapping layer (e.g., made of or containing polysilicon) may be formed on or above the target substrate 7 to improve its resistivity.

[0026] The piezoelectric layer 3 is then separated from the remainder 5 of the donor substrate 1, thereby obtaining iv) a POI structure 9 comprising the target substrate 7, the dielectric component layer 7b (if provided), and the piezoelectric layer 3. Separation at the weakening layer 2 can be facilitated by heat treatment in a temperature range of approximately 100°C to 600°C, thereby transferring the piezoelectric layer 3 to the target substrate 7. Alternatively or additionally, separation at the weakening layer 2 can be facilitated by applying a blade, a jet of gas or liquid, or any other mechanical force applied to the weakening layer 2.

[0027] The transferred piezoelectric layer 3 must undergo post-processing to achieve satisfactory single-domain crystal structure, surface quality (reduced roughness), and thickness uniformity to meet the requirements of practical applications. Post-processing includes, for example, heat treatment of the piezoelectric layer 3 in a neutral or oxygen-containing atmosphere at approximately 500°C. This heat treatment can repair crystal defects present in the piezoelectric layer and enhance the bonding between the piezoelectric layer 3 and the target substrate 7. However, the heat treatment causes the diffusion of hydrogen contained in the piezoelectric layer 3, particularly in its upper portion (e.g., a portion approximately 50 nm thick or less), resulting in multiple ferroelectric domains and giving the upper portion a multi-domain characteristic. In fact, the hydrogen injected into the piezoelectric substrate 1a during the step of defining the piezoelectric layer 3 above the weakening layer 2 exhibits a distribution curve with a concentration peak at the weakening plane 2. After fracture at the weakening layer 2, the piezoelectric layer 3 transferred to the target substrate 7 thus has a significant hydrogen concentration, and the heat treatment leads to the formation of multiple domains (i.e., multiple regions exhibiting different polarities). The performance of devices designed to be formed on / within the piezoelectric layer 3 will be severely affected by this multidomain effect.

[0028] To remove the upper multidomains and improve the surface quality and thickness uniformity of the transferred piezoelectric layer 3, post-processing includes polishing the exposed surface of the piezoelectric layer 3 (see [link to article]). Figure 1 (Step vi) In this context, for example, 100 to 300 nanometers of the upper part of the piezoelectric layer 3 can be removed by a polishing process to achieve a predetermined target thickness, such as about 600 nanometers.

[0029] According to the present invention, the piezoelectric layer 3 is polished by CMP using a relatively highly diluted CMP slurry. Typically, after thermal annealing of the transferred piezoelectric layer, a post-processing CMP step is performed using an aqueous suspension of amorphous silicon with a weight percentage of 25% to 35%. According to the present invention, the weight percentage of amorphous silicon in the aqueous suspension used as the CMP slurry is in the range of only 4% to 18%, particularly in the range of 4% to 13%, and even more particularly in the range of 5% to 7%. Other parameters of the entire manufacturing process can be selected according to conventional practices known to those skilled in the art. Thus, a single-domain piezoelectric layer can be formed over the target substrate 7, wherein almost all dipole moments are aligned parallel to each other along a given direction, thereby providing the desired thickness uniformity and surface and crystal quality.

[0030] For the polishing process, the target substrate 7 with the transferred piezoelectric layer 3 is placed on a rotatable polishing head and brought into contact with a rotatable polishing pad. A "single-zone" polishing head with a single retaining ring is preferably used, rather than a "multi-zone" polishing head with multiple retaining rings applying different pressures. For example, during polishing, the polishing head rotates at 80 to 120 revolutions per minute (rpm), and the polishing pad rotates in the same direction as the polishing head, but at a different speed, ranging from 90 to 130 rpm. For example, the polishing head can rotate at 75 rpm, and the polishing pad can rotate at 100 rpm. The speed of the repair brush can be selected to be similar to the speed of the polishing head or polishing pad.

[0031] The wafer pressure applied to the target substrate to press it onto the polishing pad can be selected to be no greater than 20.68 kPa (3 psi) or less than 18.96 kPa (2.75 psi), for example, in the range of 17.24 kPa (2.5 psi) to 20.68 kPa (3 psi). For example, during polishing, the ratio of wafer pressure to annular pressure used to hold the target substrate in the annular retainer is in the range of 1:2 to 5:3. The CMP slurry flow rate can be selected to be less than 250 ml / min, 200 ml / min, or 150 ml / min, or can be selected to be in the range of 150 ml / min to 250 ml / min.

[0032] The CMP slurry used according to the present invention can be prepared by diluting commercially available CMP slurries. For example, Klebosol 30HB50 can be diluted with water to obtain a CMP slurry with an amorphous silicon weight percentage ranging from 4% to 18%, particularly from 4% to 13%, and even more particularly from 5% to 7%. Klebosol 30HB50 has 25% to 35% amorphous silicon, and the average diameter of the precipitated amorphous silicon particles is 50 nanometers. Assuming the amorphous silicon content is 35% by weight, the CMP slurry obtained by diluting 1 part of Klebosol 30HB50 with 1 part of water (1:1 dilution) has 17.5% amorphous silicon by weight. Klebosol 30HB50 containing 25% amorphous silicon was diluted at a ratio of 1:4 to obtain a CMP slurry containing 5% amorphous silicon, while Klebosol 30HB50 containing 35% amorphous silicon was diluted at a ratio of 1:4 to obtain a CMP slurry containing 7% amorphous silicon.

[0033] Figure 2 Exemplary results of the thickness uniformity (thickness range) of the POI structure piezoelectric layer after CMP treatment with a CMP slurry obtained by diluting Klebosol 30HB50 at dilution ratios from 1:1 to 1:6 are shown. The horizontal axis represents the diameter of the piezoelectric layer in millimeters; the vertical axis represents the thickness of the piezoelectric (LTO) layer in nanometers. The figure shows thickness distribution curves for Klebosol 30HB50 diluted with water at dilution ratios of 1:1, 1:2, 1:3, 1:3.5, 1:4, 1:5, and 1:6. Other polishing parameters were selected within the above ranges.

[0034] As can be seen, for dilution ratios of 1:5 and 1:6, edge removal increases significantly, resulting in piezoelectric layer thicknesses of 147.844 nm and 180.313 nm, respectively. However, for other dilution ratios, at least fairly satisfactory results can be obtained. For a 1:1 dilution ratio, the thickness observed along the diameter of the layer is 61.879 nm. Excellent results are obtained for the other dilution ratios shown. For a 1:2 dilution ratio, the thickness observed along the diameter of the layer is 36.82 nm; for a 1:3 dilution ratio, the thickness observed along the diameter of the layer is 24.573 nm; for a 1:3.5 dilution ratio, the thickness observed along the diameter of the layer is 23.186 nm; and for a 1:4 dilution ratio, the thickness observed along the diameter of the layer is 21.849 nm.

Claims

1. A method for manufacturing a piezoelectric POI structure (9) on an insulator, the method comprising: A donor substrate (1) is provided, the donor substrate (1) comprising a piezoelectric substrate (1a), wherein the piezoelectric substrate (1a) comprises one of lithium tantalate and lithium niobate or is composed of one of lithium tantalate and lithium niobate; Transfer the piezoelectric layer (3) from the piezoelectric substrate to the target substrate (7); and The piezoelectric layer (3) transferred to the target substrate (7) is polished using a chemical mechanical polishing (CMP) slurry, wherein the CMP slurry is composed of an aqueous suspension of amorphous silicon, wherein the weight percentage of amorphous silicon is in the range of 4% to 18%.

2. The method according to claim 1, wherein, The CMP slurry consists of an aqueous suspension of amorphous silicon, wherein the weight percentage of the amorphous silicon is in the range of 4% to 13%, particularly in the range of 5% to 7%.

3. The method according to claim 1 or 2, wherein, The amorphous silicon comprises precipitated amorphous silicon particles with a diameter ranging from 40 to 60 nanometers, or is composed of precipitated amorphous silicon particles with a diameter ranging from 40 to 60 nanometers.

4. The method according to any one of the preceding claims, wherein, The steps of providing a donor substrate (1) include: bonding a piezoelectric material block to a support substrate (1b) via a bonding layer; grinding and polishing the piezoelectric material block to obtain a piezoelectric substrate (1a); and injecting a substance into the piezoelectric substrate (1a) to obtain a weakening layer (2) in the piezoelectric substrate (1a).

5. The method of claim 4, wherein, The step of transferring the piezoelectric layer (3) to the target substrate (7) includes: bonding the donor substrate (1) to the target substrate (7) and breaking the piezoelectric substrate (1a) at the weakening layer (2).

6. The method according to any one of the preceding claims further includes annealing the piezoelectric layer (3) transferred to the target substrate (7) before polishing the piezoelectric layer (3).

7. The method according to any one of the preceding claims, wherein, The polishing process includes rotating the target substrate at 80 to 120 revolutions per minute, rotating the polishing pad and polishing head in the same direction and contacting the piezoelectric layer (3), but at a different speed than the polishing head, at 90 to 130 revolutions per minute.

8. The method according to any one of the preceding claims, wherein, The polishing process includes applying wafer pressure to the target substrate (7) to press it onto a polishing pad, the wafer pressure being no greater than 20.68 kPa or less than 18.96 kPa, particularly in the range of 17.24 kPa to 20.68 kPa.

9. The method according to any one of the preceding claims, wherein, The polishing process involves applying CMP slurry to a polishing pad at a flow rate of less than 250 ml / min, or 200 ml / min, or 150 ml / min, or in the range of 150 ml / min to 250 ml / min.

10. A piezoelectric POI structure (9) on an insulator, comprising a piezoelectric layer (3) formed on or above a target substrate (7), said piezoelectric layer being obtained by the method of any one of the preceding claims, wherein, The piezoelectric layer (3) exhibits a thickness uniformity of less than 50 nanometers, especially less than 20 nanometers.

11. A microelectronic, micromechanical, or photonic device or microelectromechanical system comprising the POI structure (9) according to claim 10.

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