A high-gain operational amplifier circuit for a sigma-delta adc

Abstract

The application claims a high-gain operational amplifier circuit for Sigma-Delta ADC. The circuit comprises a main operational amplifier, a gain-improving auxiliary operational amplifier, a bias circuit and a switched-capacitor common-mode negative feedback circuit. The main operational amplifier serves as the main body of the circuit, has a high gain and a wide bandwidth; the auxiliary operational amplifier improves the output impedance and effectively improves the DC gain of the operational amplifier; the bias circuit is used to provide appropriate DC bias voltage for the main operational amplifier and the auxiliary operational amplifier; the switched-capacitor common-mode negative feedback is used to stabilize the output common-mode voltage. The application uses the auxiliary operational amplifier to improve the gain, ensures a high input-output swing of the operational amplifier, improves the DC gain of the operational amplifier, adopts a symmetrical switched-capacitor common-mode negative feedback, ensures the bandwidth range and reduces the nonlinearity of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, specifically relating to a high-gain operational amplifier circuit for Sigma-Delta ADC. Background Technology

[0002] Most signals in nature, such as light, sound, and pressure, are analog signals. Directly collecting and processing these signals is relatively complex. To utilize digital technology to process these analog signals with higher precision, higher reliability, and lower cost, they must first be converted into digital signals. Converting analog signals to digital signals requires an analog-to-digital converter (ADC), which can transform continuously changing analog signals into a series of discrete digital signals, enabling computers and other digital devices to process, store, and transmit various data captured in the physical world.

[0003] As an oversampling ADC, the Sigma-Delta ADC has a sampling frequency much higher than the Nyquist frequency, often resulting in very high accuracy. Therefore, it is widely used in high-precision applications with 18 bits or more. The Sigma-Delta ADC uses an integrator to shape quantization noise to a higher frequency and then filters out this noise in subsequent operations, thus achieving higher accuracy. As the core of the integrator, the operational amplifier's characteristics directly determine the overall circuit performance.

[0004] In traditional Sigma-Delta ADC designs, the operational amplifier circuit typically employs a cascode op-amp or a two-stage op-amp structure. The cascode op-amp offers high gain, but its output swing is limited due to the large number of MOSFETs stacked on a single path, and its input common-mode range is also relatively small. While the two-stage op-amp integrates the advantages of high gain and wide swing, its frequency response remains a major challenge.

[0005] To balance gain, swing, and system stability, folded cascode op-amps are currently widely used. These op-amps offer high gain and wide swing, representing a trade-off between speed, accuracy, and stability. However, they are difficult to balance all aspects in applications requiring high gain.

[0006] Therefore, in high-precision applications, improving the gain of operational amplifiers (op-amps) while ensuring their speed, power consumption, and stability becomes a key technical challenge. Consequently, designing the integrator for a Sigma-Delta ADC requires a new circuit architecture to enhance the op-amp's gain while maintaining its bandwidth and swing. Summary of the Invention

[0007] This invention aims to solve the above problems. It proposes a high-gain operational amplifier circuit for Sigma-Delta ADCs. This invention provides the following technical solution:

[0008] A high-gain operational amplifier circuit for a Sigma-Delta ADC includes: a main operational amplifier (1), a gain-enhancing auxiliary operational amplifier (2), a bias circuit (3), and a switched-capacitor common-mode negative feedback circuit (4). The main operational amplifier, as the core of the integrator in the Sigma-Delta ADC, is a fully differential operational amplifier used to integrate the input signal. The gain-enhancing auxiliary operational amplifier is used to increase the output impedance of the main operational amplifier, thereby increasing the DC gain of the operational amplifier. The bias circuit provides a DC bias voltage to the main operational amplifier and the gain-enhancing auxiliary operational amplifier. The switched-capacitor common-mode negative feedback circuit stabilizes the common-mode level of the output node of the fully differential operational amplifier.

[0009] The main operational amplifier is a folded cascode structure with high gain and input / output swing. An auxiliary operational amplifier is added to further improve the gain.

[0010] The gain-enhancing auxiliary operational amplifier includes an auxiliary operational amplifier AN with an input stage of NMOS differential pairs and an auxiliary operational amplifier AP with an input stage of PMOS differential pairs.

[0011] The bias circuit uses a wide-swing current mirror to provide appropriate bias voltages for the main operational amplifier and the auxiliary operational amplifier.

[0012] The switched capacitor common-mode negative feedback circuit adopts a symmetrical structure, which improves the nonlinearity of the circuit.

[0013] Furthermore, the main operational amplifier includes 7 PMOS transistors and 4 NMOS transistors, as well as 4 compensation capacitors. The 7 PMOS transistors are designated M0, M1, M2, M3, M4, M5, and M6; the 4 NMOS transistors are designated M7, M8, M9, and M10; and the 4 compensation capacitors are designated C1, C2, C3, and C4. The gate of transistor M0 is connected to the output terminal VBP1 of the bias circuit, the source of transistor M0 is connected to the power supply AVDD, the drain of transistor M0 is connected to the sources of transistors M1 and M2, and the gate of transistor M1 is connected to... The main operational amplifier's input terminal VIP is connected. The drain of transistor M1 is connected to the source of transistor M7, the drain of transistor M9, and the input terminal VIN_PBOOST of the auxiliary operational amplifier AP. The gate of transistor M2 is connected to the main operational amplifier's input terminal VIN. The drain of transistor M2 is connected to the source of transistor M8, the drain of transistor M10, and the input terminal VIP_PBOOST of the auxiliary operational amplifier AP. The gates of transistors M3 and M4 are connected to the output terminal VBP1 of the bias circuit. The sources of transistors M3 and M4 are connected to the power supply AVDD. The drain of transistor M3 is connected to the input terminal M5. The source of transistor M4 is connected to the input terminal VIP_NBOOST of auxiliary operational amplifier AN. The drain of transistor M4 is connected to the source of transistor M6 and the input terminal VIN_NBOOST of auxiliary operational amplifier AN. The gate of transistor M5 is connected to the output terminal VON_NBOOST of auxiliary operational amplifier AN and the negative plate of compensation capacitor C1. The drain of transistor M5 is connected to the positive plates of compensation capacitor C1 and C3, the drain of transistor M7, and the output terminal VOUTN of the main operational amplifier. The drain of transistor M6 is connected to the positive plate of compensation capacitor C2. The positive plate of the compensation capacitor C4, the drain of the M8 transistor, and the output terminal VOUTP of the main operational amplifier are connected. The gate of the M7 transistor is connected to the output terminal VOP_PBOOST of the auxiliary operational amplifier AP and the negative plate of the compensation capacitor C3. The gate of the M8 transistor is connected to the output terminal VON_PBOOST of the auxiliary operational amplifier AP and the negative plate of the compensation capacitor C4. The gates of the M9 and M10 transistors are connected to the output terminal CMFBOUT of the common-mode negative feedback circuit of the switched capacitor. The sources of the M9 and M10 transistors are connected to ground AGND.

[0014] The auxiliary operational amplifier AN, whose input stage is an NMOS differential pair, includes 7 NMOS transistors and 4 PMOS transistors. The 7 NMOS transistors are designated M11, M12, M13, M18, M19, M20, and M21, and the 4 PMOS transistors are designated M14, M15, M16, and M17. The gate of transistor M11 is connected to the output terminal VBN1 of the bias circuit, the source of transistor M11 is connected to ground AGND, the drain of transistor M11 is connected to the sources of transistors M12 and M13, and the gate of transistor M12... The input terminal VIP_NBOOST of the auxiliary operational amplifier AN is connected. The drain of transistor M12 is connected to the drain of transistor M14 and the source of transistor M16. The gate of transistor M13 is connected to the input terminal VIN_NBOOST of the auxiliary operational amplifier AN. The drain of transistor M13 is connected to the drain of transistor M15 and the source of transistor M17. The gates of transistors M14 and M15 are connected to the output terminal CMFBNBOOST of the switched capacitor common-mode negative feedback. The sources of transistors M14 and M15 are connected to the power supply AVDD. The gates of transistors M16 and M17 are connected to the output terminal VBP2 of the bias circuit. The drain of transistor M16 is connected to the drain of transistor M18 and the output terminal VON_NBOOST of the auxiliary operational amplifier AN. The drain of transistor M17 is connected to the drain of transistor M19 and the output terminal VOP_NBOOST of the auxiliary operational amplifier AN. The gates of transistors M18 and M19 are connected to the output terminal VBN2 of the bias circuit. The source of transistor M18 is connected to the drain of transistor M20. The source of transistor M19 is connected to the drain of transistor M21. The gates of transistors M20 and M21 are connected to the output terminal VBN1 of the bias circuit. The sources of transistors M20 and M21 are connected to ground AGND.

[0015] The auxiliary operational amplifier (AP) with a PMOS differential pair input stage includes 7 PMOS transistors and 4 NMOS transistors. The 7 PMOS transistors are designated M22, M23, M24, M25, M26, M27, and M28, and the 4 NMOS transistors are designated M29, M30, M31, and M32. The gate of transistor M22 is connected to the output terminal VBP1 of the bias circuit, the source of transistor M22 is connected to the power supply AVDD, and the drain of transistor M22 is connected to the sources of transistors M23 and M24. The gate of transistor M23 is connected to the input terminal VIN_PBOOST of the auxiliary operational amplifier (AP), and the drain of transistor M23 is connected to the source of transistor M29 and the drain of transistor M31. The gate of transistor M24 is connected to the input terminal VIP_PBOOST of the auxiliary operational amplifier (AP), and the drain of transistor M24 is connected to the source of transistor M30 and the drain of transistor M32. The gates of transistors M25 and M26 are connected to the output terminal VBP1 of the bias circuit. The sources of transistors M25 and M26 are connected to the power supply AVDD. The drain of transistor M25 is connected to the source of transistor M27. The drain of transistor M26 is connected to the source of transistor M28. The gates of transistors M27 and M28 are connected to the output terminal VBP2 of the bias circuit. The drain of transistor M27 is connected to the drain of transistor M29 and the output terminal VOP_PBOOST of the auxiliary operational amplifier AP. The drain of transistor M28 is connected to the drain of transistor M30 and the output terminal VON_PBOOST of the auxiliary operational amplifier AP. The gates of transistors M29 and M30 are connected to the output terminal VBN2 of the bias circuit. The gates of transistors M31 and M32 are connected to the output terminal CMFBPBOOST of the switched capacitor common-mode negative feedback circuit. The sources of transistors M31 and M32 are connected to ground AGND.

[0016] The bias circuit includes six NMOS transistors and six PMOS transistors. The six NMOS transistors are designated M33, M34, M35, M36, M37, and M38, and the six PMOS transistors are designated M39, M40, M41, and M42. The gate of transistor M33 is connected to the drain of transistor M33, the gate of transistor M34, the gate of transistor M35, and the input terminal IB of the bias circuit. The source of transistor M33 is connected to ground AGND. The drain of transistor M34 is connected to the drain of transistor M39, the gates of transistors M39 and M40, and the output terminal VBP2 of the bias circuit. The source of transistor M34 is connected to ground AGND. The drain of transistor M35 is connected to the drain of transistor M41, the gates of transistors M43 and M44, and the output terminal VBP1 of the bias circuit. The source of transistor M35 is connected to ground AGND. The gate of transistor M36 is connected to the drain of transistors M38 and M42, as well as the output terminal VBN1 of the bias circuit. The source of transistor M36 is connected to the ground AGND of the bias circuit. The drain of transistor M36 is connected to the source of transistor M38. The gate of transistor M37 is connected to the drain of transistors M37 and M40, as well as the output terminal VBN2 of the bias circuit. The source of transistor M37 is connected to ground AGND. The gate of transistor M38 is connected to the output terminal VBN2 of the bias circuit. The sources of transistors M39 and M40 are connected to the power supply AVDD. The gates of transistors M41 and M42 are connected to the output VBP2 of the bias circuit. The source of transistor M41 is connected to the drain of transistor M43. The source of transistor M42 is connected to the drain of transistor M44. The sources of transistors M43 and M44 are connected to the power supply AVDD.

[0017] The switched-capacitor common-mode negative feedback circuit includes 18 capacitors (C5-C22) and 36 switches (S1-S36). One end of S1 is connected to port VCM of the switched-capacitor common-mode negative feedback circuit; the other end of S1 is connected to the negative plates of S2 and C5; the other end of S2 is connected to the negative plates of S3 and C7 and port VOP of the switched-capacitor common-mode negative feedback circuit; the other end of S3 is connected to the negative plates of S4 and C9; the other end of S4 is connected to port VCM of the switched-capacitor common-mode negative feedback circuit; one end of S5 is connected to port VBN1 of the switched-capacitor common-mode negative feedback circuit; the other end of S5 is connected to the positive plates of C5 and C6 and one end of S6; the other end of S6 is connected to the positive plates of S7, C7, and C8. The circuit consists of two terminals: S11 and S2, S3 and S4. S7 is connected to the positive plates of C9 and C10, and S8. S8 is connected to the port VBN1 of the common-mode negative feedback circuit. S9 is connected to the port VCM of the common-mode negative feedback circuit, and the other end is connected to the negative plates of S10 and C6. S10 is connected to the negative plates of S11 and C8, and the port VON of the common-mode negative feedback circuit. S11 is connected to the negative plates of S12 and C10, and the other end is connected to the port VCM of the common-mode negative feedback circuit. S13 is connected to the port VBP2 of the common-mode negative feedback circuit, and the other end is connected to the negative plates of S14 and C11. The circuit boards are connected as follows: S14 is connected to the negative plates of S15 and C13 and the port VOP_NBOOST of the switched capacitor common-mode negative feedback circuit; S15 is connected to the negative plates of S16 and C15; S16 is connected to the port VBP2 of the switched capacitor common-mode negative feedback circuit; S17 is connected to the port VBP1 of the switched capacitor common-mode negative feedback circuit; S17 is connected to the positive plates of C11 and C12 and one end of S18; S18 is connected to the positive plates of S19, C13 and C14 and the port CMFBNBOOST of the switched capacitor common-mode negative feedback circuit; S19 is connected to the positive plates of C15 and C16 and S20; and S20 is connected to the switched capacitor common-mode negative feedback circuit. The circuit's port VBP1 is connected. One end of S21 is connected to port VBP2 of the switched capacitor common-mode negative feedback circuit. The other end of S21 is connected to the negative plates of S22 and C12. The other end of S22 is connected to the negative plates of S23 and C14 and the port VON_NBOOST of the switched capacitor common-mode negative feedback circuit. The other end of S23 is connected to the negative plates of S24 and C16. The other end of S24 is connected to port VBP2 of the switched capacitor common-mode negative feedback circuit. One end of S25 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit. The other end of S25 is connected to the negative plates of S26 and C17. The other end of S26 is connected to the negative plates of S27 and C19 and the port VOP_PBOOST of the switched capacitor common-mode negative feedback circuit.The other end of S27 is connected to the negative plates of S28 and C21. The other end of S28 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit. One end of S29 is connected to port VBN1 of the switched capacitor common-mode negative feedback circuit. The other end of S29 is connected to the positive plates of C17 and C18 and one end of S30. The other end of S30 is connected to the positive plates of S31, C19 and C20, and port CMFBPBOOST of the switched capacitor common-mode negative feedback circuit. The other end of S31 is connected to the positive plates of C21 and C22. S32 is connected, and the other end of S32 is connected to port VBN1 of the switched capacitor common-mode negative feedback circuit. One end of S33 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit, and the other end of S33 is connected to the negative plates of S34 and C18. The other end of S34 is connected to the negative plates of S35 and C20 and port VON_PBOOST of the switched capacitor common-mode negative feedback circuit. The other end of S35 is connected to the negative plates of S36 and C22, and the other end of S36 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit.

[0018] Beneficial effects:

[0019] 1. The main operational amplifier of this invention adopts a folded common-source common-gate structure, which has high gain and input-output swing, and good noise performance, and can meet the high precision requirements of the integrator in Sigma-Delta ADC; the gain-enhancing auxiliary operational amplifier is used to increase the output impedance of the main operational amplifier, thereby significantly improving the gain of the operational amplifier while ensuring the input-output swing and noise performance; the main operational amplifier and the gain-enhancing auxiliary operational amplifier share a bias circuit and adopt a wide-swing current source structure to ensure the output voltage swing of the circuit.

[0020] 2. Most Sigma-Delta ADCs employ switched-capacitor integrators, and the common-mode negative feedback is selected from the same type. Compared to continuous-time common-mode negative feedback, discrete-time switched-capacitor common-mode negative feedback saves static power and does not introduce new zeros and poles. However, traditional switched-capacitor common-mode negative feedback uses different feedback capacitors in the sampling and integration states to ensure the convergence speed of the feedback voltage. This results in a difference in the op-amp output load capacitance between the two states, affecting the op-amp's bandwidth and introducing nonlinearity. To improve this situation, this invention uses a symmetrical switched-capacitor common-mode negative feedback circuit, ensuring that the common-mode voltage and load capacitance are the same in both the sampling and integration states, avoiding the bandwidth reduction and nonlinearity problems caused by the difference in load capacitance between the sampling and integration states.

[0021] 3. Compared with traditional operational amplifiers, this invention uses a gain-enhancing auxiliary operational amplifier to improve the gain, ultimately achieving an open-loop gain of 154dB and a gain-bandwidth product of 23.38MHz. At the same time, it adopts a symmetrical switched-capacitor common-mode negative feedback circuit, which ensures that the circuit has the same load capacitance in the sampling state and the integration state, reducing the nonlinearity of the circuit and providing an excellent solution for applications such as high-precision ADCs and biomedical signal detection. Attached Figure Description

[0022] Figure 1 This is a block diagram of the overall structure of the high-gain operational amplifier circuit in this invention.

[0023] Figure 2 This is the schematic diagram of the main operational amplifier circuit in this invention.

[0024] Figure 3 This is the schematic diagram of the auxiliary operational amplifier (AP) and AN in this invention.

[0025] Figure 4 This is the schematic diagram of the bias circuit in this invention.

[0026] Figure 5 This is a schematic diagram of the switched capacitor common-mode negative feedback circuit in this invention.

[0027] Figure 6 These are the simulation results of the gain and phase margin of this invention.

[0028] Figure 7 These are the power supply rejection ratio simulation results of the present invention.

[0029] Figure 8 This is the noise simulation result of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0031] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0032] like Figure 1 As shown, the high-gain operational amplifier for Sigma-Delta ADC of the present invention consists of a main operational amplifier, a gain-enhancing auxiliary operational amplifier, a bias circuit, and a switched-capacitor common-mode negative feedback circuit.

[0033] The schematic diagram of the main operational amplifier is as follows: Figure 2As shown, M0 serves as the tail current source for the differential input. M1 and M2 form the differential input pair of the folded cascode circuit. To avoid the large parasitic capacitance affecting the speed of the op-amp, PMOS transistors are used for input transistors M1 and M2 to reduce op-amp noise and improve the frequency characteristics of the main op-amp. M3, M4, M5, and M6 form a cascode structure. AN and AP are gain-enhancing auxiliary op-amps used to increase the output impedance of the main op-amp, thereby increasing the DC gain of the op-amp. Due to the introduction of auxiliary op-amps, new pole-zero pairs are inevitably generated. To avoid the increase in settling time and the deterioration of the op-amp's settling characteristics caused by pole-zero pairs, compensation capacitors C1, C2, C3, and C4 are needed to compensate and eliminate the pole-zero pairs generated by the main op-amp near the unity-gain bandwidth.

[0034] The schematic diagram of the gain-enhancing auxiliary op-amp is as follows: Figure 3 As shown, since the gain-enhancing auxiliary operational amplifier AN operates at a higher common-mode voltage, NMOS transistors are used as the differential input pair for M12 and M13. Conversely, PMOS transistors are used as the differential input pair for the gain-enhancing auxiliary operational amplifier AP. The input terminal of the auxiliary operational amplifier AN is connected to the drain of transistors M3 and M4 in the main operational amplifier. Therefore, the auxiliary operational amplifier AN only needs to provide the common-mode level required for the saturation operation of M3 and M4, and thus does not require a large swing. The auxiliary operational amplifier AP is similar to AN. Furthermore, since the auxiliary operational amplifier is mainly used to improve the gain of the main operational amplifier, the requirements for speed and settling time are not high. Therefore, its tail current is generally small, which improves the power consumption and area of ​​the overall circuit.

[0035] The schematic diagram of the bias circuit is as follows: Figure 4 As shown, a wide-swing current source structure is adopted. The M33 transistor mirrors the current at the input terminal IB to the branch containing the M34 and M35 transistors. The drain of the M34 transistor is connected to the drain of the M39 transistor. The M39 transistor then mirrors the current to the branch containing the M40 transistor through a current mirror. The drain of the M35 transistor is connected to the drain of the M41 transistor. The M41 and M43 transistors then mirror the current to the branch containing the M42 and M44 transistors through a current mirror. The drain of the M42 transistor is connected to the drain of the M38 transistor. After a series of current mirrors, a stable bias voltage is finally output through the ports VBN1, VBN2, VBP1, and VBP2.

[0036] The schematic diagram of the switched capacitor common-mode negative feedback circuit is as follows: Figure 5 As shown, a symmetrical switched capacitor common-mode negative feedback structure is adopted, which makes the common-mode voltage and load capacitance the same in both the sampling state and the integral state, thus avoiding the problems of bandwidth reduction and nonlinearity caused by the difference in load capacitance between the sampling state and the integral state.

[0037] The innovation of this invention lies in the proposed high-gain operational amplifier circuit for Sigma-Delta ADCs. Specifically, the innovation and its beneficial effects are reflected in the following aspects:

[0038] Compared with traditional operational amplifiers, this invention uses a gain-enhancing auxiliary operational amplifier to improve the gain, ultimately achieving an open-loop gain of 154dB and a gain-bandwidth product of 23.28MHz. At the same time, it adopts a symmetrical switched-capacitor common-mode negative feedback circuit, which ensures that the circuit has the same load capacitance in the sampling and integration states, reducing the nonlinearity of the circuit and providing an excellent solution for applications such as high-precision ADCs and biomedical signal detection.

[0039] Simulation results

[0040] Simulation results of the gain and phase margin of the 5V high-gain op-amp are as follows: Figure 6 As shown, a gain-enhancing auxiliary operational amplifier is incorporated to achieve high gain. Simulation results show a gain of 154 dB, a phase margin of 52 degrees, and a bandwidth of 23.75 MHz. It can be seen that the simulation results are consistent with the above analysis.

[0041] The simulation results of power supply rejection ratio (PSRR) are as follows: Figure 7 As shown, the PSRR is 145.9dB at 1Hz, 86.53dB at 1kHz, and 46.53dB at 100kHz. The higher the PSRR, the less the output signal is affected by the power supply. The simulation results for noise are as follows... Figure 8 As shown, calculations show that the noise level is [value missing] in the 0.1Hz-10Hz range. In the 10Hz-20kHz range, the noise is The simulation results show that the present invention has good power supply rejection ratio and noise characteristics, and can be applied to high-precision, low-noise application scenarios.

[0042] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0043] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-gain operational amplifier circuit for a Sigma-Delta ADC, characterized in that, include: The system comprises a main operational amplifier (1), a gain-enhancing auxiliary operational amplifier (2), a bias circuit (3), and a switched-capacitor common-mode negative feedback circuit (4). The main operational amplifier, as the core of the integrator in the Sigma-Delta ADC, is a fully differential operational amplifier used to integrate the input signal. The gain-enhancing auxiliary operational amplifier includes an auxiliary operational amplifier AN with an input stage of NMOS differential pair and an auxiliary operational amplifier AP with an input stage of PMOS differential pair, used to increase the output impedance of the main operational amplifier, thereby increasing the DC gain of the operational amplifier. The bias circuit is used to provide DC bias voltage to the main operational amplifier and the gain-enhancing auxiliary operational amplifier. The switched capacitor common-mode negative feedback circuit is used to stabilize the common-mode level of the output node of the fully differential operational amplifier.

2. The high-gain operational amplifier circuit for a Sigma-Delta ADC according to claim 1, characterized in that, The main operational amplifier includes 7 PMOS transistors and 4 NMOS transistors, as well as 4 compensation capacitors. The 7 PMOS transistors are designated M0, M1, M2, M3, M4, M5, and M6; the 4 NMOS transistors are designated M7, M8, M9, and M10; and the 4 compensation capacitors are designated C1, C2, C3, and C4. The gate of transistor M0 is connected to the output terminal VBP1 of the bias circuit, the source of transistor M0 is connected to the power supply AVDD, the drain of transistor M0 is connected to the sources of transistors M1 and M2, and the gate of transistor M1 is connected to the main operational amplifier output terminal VBP1. The input terminals VIP are connected. The drain of transistor M1 is connected to the source of transistor M7, the drain of transistor M9, and the input terminal VIN_PBOOST of the auxiliary operational amplifier (AP). The gate of transistor M2 is connected to the input terminal VIN of the main operational amplifier (AP). The drain of transistor M2 is connected to the source of transistor M8, the drain of transistor M10, and the input terminal VIP_PBOOST of the auxiliary operational amplifier (AP). The gates of transistors M3 and M4 are connected to the output terminal VBP1 of the bias circuit. The sources of transistors M3 and M4 are connected to the power supply AVDD. The drain of transistor M3 is connected to the input terminal VIP_PBOOST of transistor M5. The source of transistor M4 is connected to the input terminal VIP_NBOOST of auxiliary operational amplifier AN. The drain of transistor M4 is connected to the source of transistor M6 and the input terminal VIN_NBOOST of auxiliary operational amplifier AN. The gate of transistor M5 is connected to the output terminal VON_NBOOST of auxiliary operational amplifier AN and the negative plate of compensation capacitor C1. The drain of transistor M5 is connected to the positive plates of compensation capacitors C1 and C3, the drain of transistor M7, and the output terminal VOUTN of the main operational amplifier. The drain of transistor M6 is connected to the positive plate of compensation capacitor C2. The positive plate of compensation capacitor C4, the drain of transistor M8, and the output terminal VOUTP of the main operational amplifier are connected. The gate of transistor M7 is connected to the output terminal VOP_PBOOST of auxiliary operational amplifier AP and the negative plate of compensation capacitor C3. The gate of transistor M8 is connected to the output terminal VON_PBOOST of auxiliary operational amplifier AP and the negative plate of compensation capacitor C4. The gates of transistors M9 and M10 are connected to the output terminal CMFBOUT of the common-mode negative feedback circuit of the switched capacitor. The sources of transistors M9 and M10 are connected to ground AGND.

3. The high-gain operational amplifier circuit for a Sigma-Delta ADC according to claim 1, characterized in that, The auxiliary operational amplifier AN, whose input stage is an NMOS differential pair, includes 7 NMOS transistors and 4 PMOS transistors. The 7 NMOS transistors are designated M11, M12, M13, M18, M19, M20, and M21, and the 4 PMOS transistors are designated M14, M15, M16, and M17. The gate of transistor M11 is connected to the output terminal VBN1 of the bias circuit, the source of transistor M11 is connected to ground AGND, the drain of transistor M11 is connected to the sources of transistors M12 and M13, and the gate of transistor M12... The input terminal VIP_NBOOST of the auxiliary operational amplifier AN is connected. The drain of transistor M12 is connected to the drain of transistor M14 and the source of transistor M16. The gate of transistor M13 is connected to the input terminal VIN_NBOOST of the auxiliary operational amplifier AN. The drain of transistor M13 is connected to the drain of transistor M15 and the source of transistor M17. The gates of transistors M14 and M15 are connected to the output terminal CMFBNBOOST of the switched capacitor common-mode negative feedback. The sources of transistors M14 and M15 are connected to the power supply AVDD. The gates of transistors M16 and M17 are connected to the output terminal VBP2 of the bias circuit. The drain of transistor M16 is connected to the drain of transistor M18 and the output terminal VON_NBOOST of the auxiliary operational amplifier AN. The drain of transistor M17 is connected to the drain of transistor M19 and the output terminal VOP_NBOOST of the auxiliary operational amplifier AN. The gates of transistors M18 and M19 are connected to the output terminal VBN2 of the bias circuit. The source of transistor M18 is connected to the drain of transistor M20. The source of transistor M19 is connected to the drain of transistor M21. The gates of transistors M20 and M21 are connected to the output terminal VBN1 of the bias circuit. The sources of transistors M20 and M21 are connected to ground AGND.

4. The high-gain operational amplifier circuit for a Sigma-Delta ADC according to claim 1, characterized in that, The auxiliary operational amplifier (AP) with a PMOS differential pair input stage includes 7 PMOS transistors and 4 NMOS transistors. The 7 PMOS transistors are designated M22, M23, M24, M25, M26, M27, and M28, and the 4 NMOS transistors are designated M29, M30, M31, and M32. The gate of transistor M22 is connected to the output terminal VBP1 of the bias circuit, the source of transistor M22 is connected to the power supply AVDD, and the drain of transistor M22 is connected to the sources of transistors M23 and M24. The gate of transistor M23 is connected to the input terminal VIN_PBOOST of the auxiliary operational amplifier (AP), and the drain of transistor M23 is connected to the source of transistor M29 and the drain of transistor M31. The gate of transistor M24 is connected to the input terminal VIP_PBOOST of the auxiliary operational amplifier (AP), and the drain of transistor M24 is connected to the source of transistor M30 and the drain of transistor M32. The gates of transistors M25 and M26 are connected to the output terminal VBP1 of the bias circuit. The sources of transistors M25 and M26 are connected to the power supply AVDD. The drain of transistor M25 is connected to the source of transistor M27. The drain of transistor M26 is connected to the source of transistor M28. The gates of transistors M27 and M28 are connected to the output terminal VBP2 of the bias circuit. The drain of transistor M27 is connected to the drain of transistor M29 and the output terminal VOP_PBOOST of the auxiliary operational amplifier AP. The drain of transistor M28 is connected to the drain of transistor M30 and the output terminal VON_PBOOST of the auxiliary operational amplifier AP. The gates of transistors M29 and M30 are connected to the output terminal VBN2 of the bias circuit. The gates of transistors M31 and M32 are connected to the output terminal CMFBPBOOST of the switched capacitor common-mode negative feedback circuit. The sources of transistors M31 and M32 are connected to ground AGND.

5. A high-gain operational amplifier circuit for a Sigma-Delta ADC according to claim 1, characterized in that, The bias circuit includes six NMOS transistors and six PMOS transistors. The six NMOS transistors are designated M33, M34, M35, M36, M37, and M38, and the six PMOS transistors are designated M39, M40, M41, and M42. The gate of transistor M33 is connected to the drain of transistor M33, the gate of transistor M34, the gate of transistor M35, and the input terminal IB of the bias circuit. The source of transistor M33 is connected to ground AGND. The drain of transistor M34 is connected to the drain of transistor M39, the gates of transistors M39 and M40, and the output terminal VBP2 of the bias circuit. The source of transistor M34 is connected to ground AGND. The drain of transistor M35 is connected to the drain of transistor M41, the gates of transistors M43 and M44, and the output terminal VBP1 of the bias circuit. The source of transistor M35 is connected to ground AGND. The gate of transistor M36 is connected to the drain of transistors M38 and M42, as well as the output terminal VBN1 of the bias circuit. The source of transistor M36 is connected to the ground AGND of the bias circuit. The drain of transistor M36 is connected to the source of transistor M38. The gate of transistor M37 is connected to the drain of transistors M37 and M40, as well as the output terminal VBN2 of the bias circuit. The source of transistor M37 is connected to ground AGND. The gate of transistor M38 is connected to the output terminal VBN2 of the bias circuit. The sources of transistors M39 and M40 are connected to the power supply AVDD. The gates of transistors M41 and M42 are connected to the output VBP2 of the bias circuit. The source of transistor M41 is connected to the drain of transistor M43. The source of transistor M42 is connected to the drain of transistor M44. The sources of transistors M43 and M44 are connected to the power supply AVDD.

6. A high-gain operational amplifier circuit for a Sigma-Delta ADC according to claim 1, characterized in that, The switched-capacitor common-mode negative feedback circuit includes 18 capacitors (C5-C22) and 36 switches (S1-S36). One end of S1 is connected to port VCM of the switched-capacitor common-mode negative feedback circuit; the other end of S1 is connected to the negative plates of S2 and C5; the other end of S2 is connected to the negative plates of S3 and C7 and port VOP of the switched-capacitor common-mode negative feedback circuit; the other end of S3 is connected to the negative plates of S4 and C9; the other end of S4 is connected to port VCM of the switched-capacitor common-mode negative feedback circuit; one end of S5 is connected to port VBN1 of the switched-capacitor common-mode negative feedback circuit; the other end of S5 is connected to the positive plates of C5 and C6 and one end of S6; the other end of S6 is connected to the positive plates of S7, C7, and C8. The circuit consists of two terminals: S11 and S2, S3 and S4. S7 is connected to the positive plates of C9 and C10, and S8. S8 is connected to the port VBN1 of the common-mode negative feedback circuit. S9 is connected to the port VCM of the common-mode negative feedback circuit, and the other end is connected to the negative plates of S10 and C6. S10 is connected to the negative plates of S11 and C8, and the port VON of the common-mode negative feedback circuit. S11 is connected to the negative plates of S12 and C10, and the other end is connected to the port VCM of the common-mode negative feedback circuit. S13 is connected to the port VBP2 of the common-mode negative feedback circuit, and the other end is connected to the negative plates of S14 and C11. The circuit boards are connected as follows: S14 is connected to the negative plates of S15 and C13 and the port VOP_NBOOST of the switched capacitor common-mode negative feedback circuit; S15 is connected to the negative plates of S16 and C15; S16 is connected to the port VBP2 of the switched capacitor common-mode negative feedback circuit; S17 is connected to the port VBP1 of the switched capacitor common-mode negative feedback circuit; S17 is connected to the positive plates of C11 and C12 and one end of S18; S18 is connected to the positive plates of S19, C13 and C14 and the port CMFBNBOOST of the switched capacitor common-mode negative feedback circuit; S19 is connected to the positive plates of C15 and C16 and S20; and S20 is connected to the switched capacitor common-mode negative feedback circuit. The circuit's port VBP1 is connected. One end of S21 is connected to port VBP2 of the switched capacitor common-mode negative feedback circuit. The other end of S21 is connected to the negative plates of S22 and C12. The other end of S22 is connected to the negative plates of S23 and C14 and the port VON_NBOOST of the switched capacitor common-mode negative feedback circuit. The other end of S23 is connected to the negative plates of S24 and C16. The other end of S24 is connected to port VBP2 of the switched capacitor common-mode negative feedback circuit. One end of S25 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit. The other end of S25 is connected to the negative plates of S26 and C17. The other end of S26 is connected to the negative plates of S27 and C19 and the port VOP_PBOOST of the switched capacitor common-mode negative feedback circuit.The other end of S27 is connected to the negative plates of S28 and C21. The other end of S28 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit. One end of S29 is connected to port VBN1 of the switched capacitor common-mode negative feedback circuit. The other end of S29 is connected to the positive plates of C17 and C18 and one end of S30. The other end of S30 is connected to the positive plates of S31, C19 and C20, and port CMFBPBOOST of the switched capacitor common-mode negative feedback circuit. The other end of S31 is connected to the positive plates of C21 and C22. S32 is connected, and the other end of S32 is connected to port VBN1 of the switched capacitor common-mode negative feedback circuit. One end of S33 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit, and the other end of S33 is connected to the negative plates of S34 and C18. The other end of S34 is connected to the negative plates of S35 and C20 and port VON_PBOOST of the switched capacitor common-mode negative feedback circuit. The other end of S35 is connected to the negative plates of S36 and C22, and the other end of S36 is connected to port VBN2 of the switched capacitor common-mode negative feedback circuit.

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