DNA self-assembly nanofloating gate type 3D NAND structure and preparation method thereof

Abstract

The application relates to a DNA self-assembly nano-floating gate type 3D NAND structure, which comprises a substrate, a periodic stack structure arranged on the substrate, the stack structure comprising a plurality of first insulating medium layers and nano-floating gate storage structures alternately stacked, a plurality of through holes penetrating through the stack structure, a center channel layer being arranged on the side wall of the through hole, and a center insulating medium layer being filled in the center channel layer; wherein the nano-floating gate storage structure comprises a tunneling medium layer contacting the center channel layer, a blocking medium layer wrapping the outside of the tunneling medium layer, and a gate word line metal located outside the blocking medium layer, and a carbon nanotube floating gate layer is arranged in the tunneling medium layer. The structure can significantly improve the storage density and size miniaturization ability, and greatly reduce the working voltage and driving power consumption.

Description

Technical Field

[0001] This invention relates to the field of storage devices, and more particularly to a DNA self-assembled nanofloating gate type 3D NAND structure and its preparation method. Background Technology

[0002] With the rapid development of mobile terminals, artificial intelligence, and big data technologies, memory chips need to achieve higher storage capacity within a limited chip area while meeting the stringent requirements of low-power operation. As the current mainstream non-volatile memory technology, 3D NAND's operating voltage and power consumption have become key factors restricting system performance and battery life.

[0003] Currently, the main approach in the industry to increase 3D NAND storage capacity is by increasing the number of word lines stacked. However, continuously increasing the number of stacked layers faces significant technical challenges: Increased programming / erase voltage: The increase in the number of layers leads to a more complex overall device structure, which usually requires higher programming / erase voltages to ensure storage reliability, resulting in additional energy consumption.

[0004] Word line pitch miniaturization bottleneck: As memory cell sizes continue to shrink, the ever-reducing word line pitch has become a significant constraint on increasing bit density. Excessively small word line pitch not only enhances charge coupling interference between word lines, leading to increased crosstalk, but also causes electric field concentration effects, resulting in threshold voltage fluctuations. This forces designers to increase operating voltages to maintain reliability, which contradicts the goal of low power consumption.

[0005] Complexity of fabrication process: The reduction of word line pitch places extremely high demands on the uniformity of deposition, etching and filling processes in the manufacturing process. Existing processes are difficult to balance morphological uniformity and the quality of the dielectric-floating gate interface at extremely small scales.

[0006] In summary, while pursuing high-density storage, existing 3D NAND technology struggles to effectively balance the contradictions between size reduction, power consumption, and reliability.

[0007] Therefore, there is an urgent need to propose a novel 3D NAND stacking structure and fabrication method, which aims to achieve physical miniaturization of word line spacing, while reducing operating voltage and power consumption in terms of electrical characteristics, so as to realize the next generation of high-density, low-power 3D NAND memory while ensuring yield and reliability. Summary of the Invention

[0008] The present invention aims to provide a DNA self-assembled nano-floating gate type 3D NAND structure and its preparation method to overcome the shortcomings of the prior art. The technical problem to be solved by the present invention is achieved through the following technical solution.

[0009] According to a first aspect of this application, a DNA self-assembled nano-floating gate type 3D NAND structure is provided, comprising: Substrate; A periodic stacked structure disposed on the substrate, the stacked structure comprising a plurality of alternating layers of first insulating dielectric layers and nanofloating gate storage structures; A plurality of through holes penetrate the stacked structure, and a central channel layer is provided on the sidewall of the through holes, and a central insulating dielectric layer is filled in the central channel layer; The nano-floating gate storage structure includes a tunneling dielectric layer that contacts the central channel layer, a barrier dielectric layer that surrounds the outside of the tunneling dielectric layer, and a gate line metal located outside the barrier dielectric layer. A carbon nanotube floating gate layer is disposed in the tunneling dielectric layer.

[0010] Preferably, the carbon nanotube floating grid layer is a single carbon nanotube formed by directional growth induced by a DNA molecular template, and the single carbon nanotube is in a straight state.

[0011] Preferably, the carbon nanotubes of the carbon nanotube floating grid layer are loaded with transition metal catalyst particles, which are located in the middle of the length of the carbon nanotubes.

[0012] Preferably, the equivalent oxide layer thickness (EOT) of the tunneling dielectric layer is less than 8 nm; the barrier dielectric layer is selected from one of alumina, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, titanium oxide and their silicates, nitrides or stacked structures.

[0013] Preferably, the material of the insulating dielectric layer is selected from silicon dioxide, silicon nitride, silicon oxynitride, low-k dielectric, or high-k dielectric.

[0014] According to a first aspect of this application, a method for preparing the above-mentioned DNA self-assembled nanofloating gate type 3D NAND structure is provided, comprising the following steps: Step 1: Vertically deposit several periodic stacked structures on the substrate, wherein the periodic stacked structures, from bottom to top, include a first insulating dielectric layer and a sacrificial layer. Step 2: Etch through holes, the through holes penetrating the plurality of periodic stacked structures; Step 3: Use selective etching to etch back the sacrificial layer to a depth of 5-30 nanometers to form the first groove; Step 4: Deposit a barrier dielectric layer on the sidewall of the through hole and the inner wall of the first groove using atomic layer deposition or chemical vapor deposition to form a nanogroove in the first groove; Step 5: Specific chemical modification or biofunctionalization of a single DNA template is performed within the nanogroove to achieve precise fixation of the single DNA template within the groove, introduce a single catalytic active site required for the growth of a single carbon nanotube, and ensure that the single DNA template is in a single, straight state within the groove. Step 6: Using the modified single DNA template within the nanogroove as the sole guide, directional growth of single carbon nanotubes is achieved through chemical vapor deposition, plasma-enhanced chemical vapor deposition, or hot-filament chemical vapor deposition. Step 7: Remove individual DNA templates in the grooves using enzymatic hydrolysis, high-temperature annealing, or chemical oxidation to form a carbon nanotube floating grid layer; Step 8: After preparing the tunneling dielectric layer in the nanogroove and the sidewall of the via using atomic layer deposition or chemical vapor deposition, remove the tunneling dielectric layer and the barrier dielectric layer from the sidewall and bottom of the via. Step 9: After growing the central trench layer on the sidewall of the through hole, fill the central insulating dielectric layer, and then use wet etching to etch the sacrificial layer to form the second groove; Step 10: After filling the second groove with grid line metal and performing CMP planarization, the fabrication of the nano-floating grid type 3DNAND structure is completed.

[0015] Preferably, the specific chemical modification of the nanogroove involves introducing amino, carboxyl, or thiol functional groups into the inner wall of the nanogroove, so that a single DNA template is fixed to the center of the inner wall of the nanogroove through covalent or non-covalent bonds, and adjusting the surfactant concentration in the reaction solution to 0.01-0.1 mmol / L so that the single DNA template is in a single, straight state along the direction of the nanogroove.

[0016] Preferably, the specific method for achieving the directional growth of a single carbon nanotube is as follows: the catalyst is activated in situ at 300-500℃ in an inert gas atmosphere to remove impurities from the template surface; a chemical vapor deposition process is used at 700-1000℃ and 1-10 kPa pressure, with hydrogen as a reducing gas to assist in controlling the carbon source growth rate, ensuring that the single carbon nanotube achieves directional growth in the range of 1-20 nanometers in diameter and 100-500 nanometers in length, and the growth height does not exceed 1.2 times the groove depth.

[0017] Preferably, in the enzymatic removal method, deoxyribonuclease is used to react at 37°C for 60-120 minutes; in the high-temperature annealing removal method, the temperature is raised to 400-600°C under an inert gas atmosphere; in the chemical oxidation removal method, an oxidizing agent with a concentration of 0.1-0.5 mol / L is used for room temperature soaking treatment.

[0018] Preferably, after removing a single DNA template, the process further includes the following quality testing steps: Raman spectroscopy is used to detect the crystallinity and purity of the carbon nanotubes, and a transmission electron microscope or atomic force microscope is used to scan the inside of the groove to verify that the residual rate of the DNA template in the groove is less than 5%, and to ensure that there are no impurities attached to the surface of the single carbon nanotube and no physical damage to the inner wall of the groove.

[0019] The embodiments of the present invention have the following advantages: Significantly enhanced storage density and miniaturization capabilities: By leveraging the precise template effect of DNA molecule self-assembly, the physical size limitations of traditional floating gate fabrication processes are overcome, enabling precise arrangement of nanoscale carbon nanotubes under ultra-small word line pitch conditions. This molecular-level control capability effectively compresses the physical spacing between adjacent word lines, thereby achieving higher vertical stacking layers and bit density within the same wafer area.

[0020] Significantly reduced operating voltage and drive power consumption: By leveraging the high specific surface area, high charge trapping capacity, and unique local electric field enhancement characteristics of carbon nanotubes, the gate control efficiency of floating gate charge is significantly enhanced. While maintaining electrical performance, this architecture can significantly reduce the programming and erasing operating voltage of the device, effectively solving the problem of soaring power consumption caused by increasing the number of layers in existing 3D NAND, and meeting the ultra-low power storage requirements of artificial intelligence and mobile terminals.

[0021] Enhancing charge storage uniformity and data reliability: A DNA template-mediated symmetrical carbon nanotube nanogate configuration achieves high-density vertical stacking while ensuring good electrical isolation between nanogates. By precisely controlling the growth arrangement and size uniformity of carbon nanotubes, this structure effectively suppresses charge coupling interference (crosstalk) between storage cells, improving the uniformity of charge storage and the long-term reliability of data retention.

[0022] The process is precise and controllable, and possesses high industrial compatibility: It combines DNA self-assembly template technology with mature thin-film deposition technologies such as ALD and PECVD, solving the process bottlenecks of uneven floating gate morphology and poor interface quality in ultra-small pitch layers. This fabrication method is highly compatible with existing 3D NAND manufacturing processes, requiring no large-scale modifications to mainstream production lines, greatly reducing industrialization costs and technological iteration difficulties, and possessing significant market competitiveness and large-scale mass production potential. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the DNA self-assembled nanofloating gate type 3D NAND structure in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure after the deposition of the layered structure in step 1 of embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure after etching the through-hole in step 2; Figure 4 This is a schematic diagram of the structure after selectively etching the sacrificial layer in step 3; Figure 5 This is a schematic diagram of the structure after the barrier medium layer is deposited in step 4; Figure 6 This is a schematic diagram of the structure after modifying the DNA template in the groove in step 5; Figure 7 This is a schematic diagram of the structure after DNA self-assembly to grow carbon nanotubes in step 6; Figure 8 This is a schematic diagram of the structure after removing the DNA template in step 7; Figure 9 This is a schematic diagram of the structure after the tunneling medium layer is deposited in step 8; Figure 10 This is a schematic diagram of the structure after etching away the tunneling dielectric layer and the barrier dielectric layer on the sidewall and bottom of the via in step 9; Figure 11 This is a schematic diagram of the structure after the growth center channel layer in step 10; Figure 12 This is a schematic diagram of the structure in step 11 where the central insulating dielectric layer is filled into the through hole; Figure 13 This is a schematic diagram of the structure after wet etching of the sacrificial layer in step 12; Figure 14 This is a schematic diagram of the structure after filling the grid lines with metal in step 13; Figure 15 a is a schematic diagram showing the effect of applying a 4V programming voltage to a 20nm floating gate device on the device's memory window; Figure 15 b is a schematic diagram illustrating the effect of applying a 4V programming voltage to a 1nm floating gate device on the device's memory window. Detailed Implementation

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0026] Example 1

[0027] like Figure 1 As shown, this embodiment provides a DNA self-assembled nano-floating gate type 3D NAND structure, including a substrate 100, on which a periodic stacked structure is disposed, the stacked structure including a plurality of first insulating dielectric layers 110 and nano-floating gate storage structures alternately stacked in the vertical direction;

[0028] A plurality of through holes 200 are provided through the stacked structure, and a central channel layer 250 is provided on the sidewall of the through holes 200. The central channel layer 250 is filled with a central insulating dielectric layer 260.

[0029] The nano-floating gate storage structure includes a tunneling dielectric layer 240 that contacts the central channel layer 250, a barrier dielectric layer 220 that wraps around the outside of the tunneling dielectric layer 240, and a gate line metal 270 located outside the barrier dielectric layer 220, and a carbon nanotube floating gate layer 230 is disposed in the tunneling dielectric layer 240.

[0030] In this embodiment, the substrate 100 can be a single-crystal silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium (SiGe) substrate, or a compound semiconductor substrate (such as GaAs or InP), used to provide mechanical support and serve as an electrical reference for the bottom layer of the device; its surface flatness, lattice integrity, and thermal stability must meet the requirements of subsequent high aspect ratio via etching and high-precision thin film deposition processes; in this application, the substrate 100 undertakes the functions of substrate support, heat sink heat dissipation, and bottom source / selection gate lead-out, and forms a physical and electrical isolation interface with the first insulating dielectric layer 110, effectively preventing leakage current from diffusing into the substrate.

[0031] In this embodiment, the first insulating dielectric layer 110 can be any one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), low dielectric constant medium (such as SiCOH, porous SiO2), or high dielectric constant medium (such as HfO2, Al2O3) or a composite stack thereof; its single layer thickness is preferably 10-50 nm; the first insulating dielectric layer 110 and the nano-floating gate storage structure are stacked alternately in the vertical direction to jointly constitute the physical carrier of the 3D NAND word line-memory cell, and its function is to provide electrical isolation, mechanical support and stress buffer between adjacent word lines; in this application, the material selection of the first insulating dielectric layer 110 needs to have a significant etching selectivity ratio with the sacrificial layer used in the preparation stage, so that the first insulating dielectric layer 110 can be retained as an inter-word line isolation layer when selectively etching back to form nanogrooves and when selectively etching away the sacrificial layer in the final stage.

[0032] The barrier dielectric layer 220 is selected from one or more of alumina (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), titanium oxide (TiO2) and their silicates, nitrides or stacked structures (such as Al2O3 / HfO2, HfO2 / Al2O3 / HfO2), and its thickness is preferably 3-10 nm. The barrier dielectric layer 220 is directly wrapped around the outside of the carbon nanotube floating gate layer 230. Its main function is to block the reverse injection and diffusion of charge from the gate word line metal 270 to the carbon nanotube floating gate layer 230. At the same time, it works with the tunneling dielectric layer 240 to form a symmetrical charge trapping and storage structure of "metal-barrier dielectric-floating gate-tunneling dielectric-channel", which ensures that the charge can be stably trapped in the carbon nanotube floating gate layer 230 in the programmed state and erased state and does not leak to the gate.

[0033] The tunneling dielectric layer 240 is selected from silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a SiO2 / SiN / SiO2 (ONO) stacked structure, with an equivalent oxide layer thickness (EOT) of less than 8 nm, preferably 3-6 nm. The tunneling dielectric layer 240 is distributed in a continuous columnar shape on the sidewall of the via 200 and extends into the nanogroove to encapsulate the carbon nanotube floating gate layer 230. In this application, the tunneling dielectric layer 240 allows channel carriers to tunnel into the carbon nanotube floating gate layer 230 via Fowler-Nordheim tunneling or direct tunneling under an applied bias voltage during programming. During the retention period, it provides a sufficiently high barrier to suppress reverse charge leakage, thereby ensuring data retention characteristics. The design with an EOT of less than 8 nm helps to obtain sufficient tunneling current at a lower operating voltage, which, in synergy with the high charge trapping capacity of the carbon nanotube floating gate, significantly reduces the device programming / erasing voltage.

[0034] The carbon nanotube floating grating layer 230 is composed of single carbon nanotubes formed by directional growth induced by a DNA molecular template, and the single carbon nanotubes are embedded in the center of the nanogrooves in a straight state along the horizontal direction. The diameter of the single carbon nanotube is preferably 1-20 nm, and the length is preferably 100-500 nm. Its tube wall structure can be single-walled carbon nanotubes (SWCNTs), double-walled carbon nanotubes (DWCNTs), or few-walled carbon nanotubes (FWCNTs). Transition metal catalyst particles are loaded on the single carbon nanotubes. The catalyst particles are located in the middle of the length of the carbon nanotubes and can be iron (Fe), cobalt (Co), nickel (Ni) nanoparticles or their alloy particles (such as Fe-Co, Co-Ni), with a particle size preferably 1-5 nm. nm; In this application, the carbon nanotube floating gate layer 230 serves as the charge storage core. Its cylindrical high specific surface area configuration can provide a much higher effective charge trapping area than traditional continuous floating gates under the same word line spacing. At the same time, the π electron cloud system of the carbon nanotube wall has excellent charge localization ability, and local electric field enhancement is easily formed at the tube end and catalyst particles, which enables efficient charge injection and trapping at a lower gate voltage, thereby significantly reducing the programming / erasing voltage and expanding the storage window.

[0035] The central channel layer 250 can be any one or a combination of polycrystalline silicon, monocrystalline silicon, indium gallium zinc oxide (IGZO), SiGe, molybdenum disulfide (MoS2), tungsten diselenide (WSe2), tungsten disulfide (WS2), and molybdenum diselenide (MoSe2); it can be formed by chemical vapor deposition (CVD), epitaxial growth, physical vapor deposition (PVD), or spin coating; the thickness is preferably 1-15 nm; the central channel layer 250 covers the inner side of the tunneling dielectric layer 240 of the sidewall of the via 200, forming the main carrier transport channel that runs through the entire stacked structure in the vertical direction; its conductivity type, doping concentration, and lattice quality directly determine the on-state current, subthreshold swing, and threshold voltage uniformity of the device.

[0036] The central insulating dielectric layer 260 can be any one of SiO2, SiON, SiCOH, HfO2, Al2O3, ZrO2, HfZrO, TiO2, low-k dielectric, or spin-coated glass; it is filled into the cavity inside the central channel layer 250 by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or spin coating, and its surface is planarized by chemical mechanical polishing (CMP); the central insulating dielectric layer 260 is used to isolate the inner surface of the aligned central channel layer 250 to prevent leakage current path or parasitic capacitance between the rear interconnect structure and the channel.

[0037] The gate word line metal 270 can be tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), polysilicon (poly-Si), or a composite stack of the above materials (such as TiN / W, TaN / W). The gate word line metal 270 is backfilled by the second groove formed after the sacrificial layer is removed by selective etching, and wraps around the barrier dielectric layer 220 in a horizontal direction as the input port of the word line potential. It is completely isolated from the carbon nanotube floating gate layer 230 by the barrier dielectric layer 220. The gate voltage forms a step-down voltage reduction path from top to bottom through the barrier dielectric layer 220, the carbon nanotube floating gate layer 230, and then to the tunneling dielectric layer 240, thereby precisely controlling the channel carrier state.

[0038] This embodiment constructs a nano-floating grid by embedding DNA self-assembly-induced single carbon nanotubes into nanogrooves. Arranged in a three-dimensional vertical stacking architecture with a coaxial symmetric structure of "grid word line metal—barrier medium—carbon nanotube floating grid—tunneling medium—channel," it achieves precise charge storage and readout within a molecular-level floating grid. Utilizing the high specific surface area, high charge trapping capacity, and enhanced local electric field characteristics of carbon nanotubes, programming and erasing voltages can be significantly reduced within the same storage window. By employing DNA templates for precise molecular-level control of the position, orientation, and length of individual CNTs, it overcomes the technological bottlenecks of traditional nano-floating grids, such as uneven morphology, large fluctuations in the number of charge trapping centers, and increased inter-cell crosstalk under small word line pitches. While compressing word line pitch and increasing the number of vertical stacking layers and bit density, it ensures charge storage uniformity and data retention reliability.

[0039] like Figure 15 a and Figure 15 As shown in b, when the floating gate size is reduced from the conventional 20 nanometers to a 1-nanometer scale metal nanofloating gate structure, a significant electric field concentration enhancement phenomenon can be generated under the same programming voltage. This effect has a similar physical mechanism to the formation of a strong electric field concentration at a needle tip. This study innovatively integrates the field enhancement mechanism from vacuum field emission theory into NAND memory cell design, realizing an interdisciplinary combination of nanoelectronic devices and vacuum physics effects. After optimizing the floating gate geometry, the tip concentration effect is effectively utilized while the size is reduced, causing the charge to accumulate highly locally in the floating gate, thereby improving the programming efficiency of the memory cell and reducing power consumption.

[0040] Example 2

[0041] like Figures 2 to 13 As shown, this embodiment provides a method for preparing the DNA self-assembled nano-floating gate type 3D NAND structure described in Example 1, including the following steps:

[0042] Step 1, Stacked Structure Deposition: Several periodic stacked structures are alternately deposited along the vertical direction on the substrate 100 using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) processes. The periodic stacked structures, from bottom to top, sequentially include a first insulating dielectric layer 110 and a sacrificial layer 160, such as... Figure 2 shown. Specifically:

[0043] The first insulating dielectric layer 110 can be made of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), low-k dielectrics (such as carbon oxide-doped SiCOH, porous SiO2) or high-k dielectrics (such as HfO2, Al2O3) and their composite stacks (such as SiO2 / SiN stacks), with a thickness ranging from 10 to 50 nm;

[0044] The sacrificial layer 160 can be made of any one of silicon nitride (SiN), amorphous silicon (a-Si), polycrystalline silicon (poly-Si), doped silicon (such as boron-doped or phosphorus-doped a-Si), or doped oxides (such as silicon phosphide glass (PSG) or borosilicate glass (BSG). The material of the sacrificial layer 160 must be independent of the first insulating dielectric layer 110 in terms of material, so that the two have a significant etching selectivity ratio (preferably ≥30:1) for the subsequent selective etchant, so as to achieve precise interlayer differentiation in the etch-back process in step 3 and the selective etching removal process in step 9. The thickness of the sacrificial layer 160 is preferably 10-50 nm, and its thickness directly determines the height of the subsequent nanogrooves, and thus the effective trapping cross section of the carbon nanotube floating gate layer 230.

[0045] The number of stacking cycles is designed according to the target bit density, typically 32, 64, 128, 192 or 256 layers. After the periodic stacking deposition is completed, annealing can be performed for 30-60 minutes in a nitrogen atmosphere at 800-1000 ℃ to release film stress, improve film density, and reduce the risk of film peeling and warping during subsequent high aspect ratio via etching.

[0046] Step 2, Etching the Via: A two-dimensional pattern of vias 200 is defined on the wafer after the stacked deposition using photolithography. Subsequently, reactive ion etching (RIE) based on Cl2 / HBr gas is employed to penetrate the periodic stacked structure vertically, forming vias 200 with a high aspect ratio ≥ 30:1. Figure 3 shown. Specifically:

[0047] An inductively coupled plasma (ICP) reactive ion etching system was employed, using Cl2 (flow rate 50-200 sccm) as the main etching gas. Rapid vertical chemical etching of the SiN / SiO2 / a-Si surface was achieved via Cl radicals. Simultaneously, HBr (flow rate 30-150 sccm) was introduced as a sidewall passivation gas, forming SiBr-rich deposits on the Si substrate sidewalls. x -O passivation protective layer effectively suppresses isotropic lateral etching; then, physical ion bombardment with Ar (flow rate 10-30 sccm) selectively removes passivation deposits at the bottom of the hole to maintain the vertical etching path; the chamber pressure is maintained at 5-30 mTorr, the source power at 1500-3000 W, and the bias power at 200-800 W; the etching endpoint is determined by real-time monitoring of the Si I 251 nm spectral line intensity using optical emission spectroscopy (OES), stopping the etching at the substrate 100 surface or a predetermined depth. This process can obtain vias 200 with steep sidewalls and an upper and lower diameter deviation of less than 5%, laying the foundation for subsequent nanogroove alignment fabrication.

[0048] Step 3, Selective Etching Back of Sacrificial Layer: A selective etching process is used to etch back the sacrificial layer 160 exposed on the sidewall of the via 200 in the horizontal direction. The etch back depth is 5-30 nm, forming a first groove 201 extending horizontally at each sacrificial layer 160 site. Specifically:

[0049] When the sacrificial layer 160 is silicon nitride, wet etching with 85% hot phosphoric acid (H3PO4) is used, with the solution temperature precisely controlled at 140-160 ℃ and the etching time at 60-300 seconds. The etching selectivity ratio of hot phosphoric acid for SiN to SiO2 can reach more than 30:1, which can achieve precise lateral etching back of the SiN sacrificial layer without damaging the first insulating dielectric layer 110 (SiO2).

[0050] When the sacrificial layer 160 is amorphous silicon or polycrystalline silicon, isotropic plasma etching based on NF3 / CF4 / O2 or wet etching based on TMAH / KOH is used. The etching depth is precisely controlled by controlling the etchant concentration, temperature and time.

[0051] During the etching process, the sacrificial layer 160 is etched back uniformly by 5-30 nm using a preset etching time and in-situ ellipsometry monitoring, with a preferred etching depth of 10-20 nm. The first groove 201 formed is distributed in a ring along the radial direction of the through hole 200, and its upper and lower interfaces are respectively composed of adjacent first insulating dielectric layers 110. The depth uniformity deviation is preferably less than ±1 nm to ensure that the geometric morphology of each nanogroove is consistent, thereby ensuring the uniformity of electrical characteristics of different word line layers.

[0052] Step 4, Deposition of Barrier Dielectric Layer 220: A barrier dielectric layer 220 is conformally deposited on the sidewalls of the via 200 and the inner walls (including the upper surface, lower surface, and bottom of the groove) of the first groove 201 using atomic layer deposition (ALD) or chemical vapor deposition (CVD), with a deposition thickness of 3-10 nm. After deposition, since the barrier dielectric layer 220 fills the groove but is not completely filled, a vertically symmetrical nanogroove 210 is formed inside each first groove 201, such as... Figure 4 As shown.

[0053] The specific steps for using ALD deposition of alumina (Al2O3) as the barrier dielectric layer 220 in this application are as follows: the wafer that has completed the etch-back process is placed in the ALD reaction chamber, and the chamber is evacuated to a base vacuum (<1×10⁻⁶). -6 After heating to 200-300 °C, high-purity nitrogen (N2) is introduced to stabilize the chamber pressure to 0.1-5 Torr. Trimethylaluminum (TMA) is selected as the aluminum precursor and introduced into the chamber with a short pulse of 0.1-0.5 seconds. TMA molecules undergo self-limiting chemisorption on all exposed surfaces of the sidewalls of the through-hole 200 and the inner wall of the first groove 201, forming a saturated Al-CH3 monolayer. Subsequently, a high-flow-rate N2 is introduced to purge for 15-30 seconds, removing unadsorbed excess TMA and gaseous byproducts. Water vapor (H2O) is then introduced with a pulse of 0.1-1 seconds, which reacts with the surface methyl groups to generate hydroxylated aluminum oxide and release methane (CH4). The chamber is then purged again with N2 for 15-30 seconds to remove residual H2O and byproducts, completing an ALD cycle that grows approximately 0.1 nm Al2O3. Repeating the pulse-purge-pulse-purge cycle 30-100 times will result in a uniform deposition of a thickness of 3-10 nm on the inner wall of the groove. nm high-conformity Al2O3 barrier dielectric layer 220.

[0054] This process, leveraging the self-limiting surface reaction characteristics of ALD, achieves a step coverage rate exceeding 95% in complex three-dimensional morphologies with intersecting horizontal grooves and vertical vias. The resulting Al2O3 film is dense and pinhole-free, forming a steep interface with the first insulating dielectric layer 110. The thickness of the barrier dielectric layer 220 directly determines the geometry of the remaining cavity (i.e., nanogrooves 210) within the first groove 201. By precisely controlling the number of ALD cycles, the height of the nanogrooves 210 can be precisely controlled within the range of 5-20 nm, providing physical confinement for the subsequent single fixation of DNA templates 211. After deposition, annealing in a N2 atmosphere at 400-500 ℃ for 30 minutes can be performed to improve the film's density and insulation properties.

[0055] Step 5: Modifying DNA template 211 within the nanogroove 210: Specific chemical modification or biofunctionalization of a single DNA template 211 is performed within the nanogroove 210. The core objective is to achieve precise immobilization of the single DNA template 211 within the nanogroove 210, introduce a single catalytic active site required for the growth of a single carbon nanotube, and ensure that the DNA template 211 remains in a single, straight state within the nanogroove 210, avoiding entanglement or overlap of multiple DNA templates 211. Figure 5 As shown. The specific modification method includes the following three parallel sub-steps:

[0056] (5-1) Chemical functionalization of the inner wall of the groove: The wafer with the barrier dielectric layer 220 deposited is immersed in an ethanol / toluene solution containing aminosilane coupling agents (such as 3-aminopropyltriethoxysilane, APTES), carboxylsilane coupling agents (such as (trimethoxysilyl)propylsuccinic anhydride), or mercaptosilane coupling agents (such as 3-mercaptopropyltrimethoxysilane, MPTMS). The solution concentration is 1-5 vol%, the reaction temperature is 25-60 ℃, and the reaction time is 30-120 minutes, so that the inner wall of the nanogroove 210 (mainly the Al2O3 surface) is grafted with uniform amino (-NH2), carboxyl (-COOH), or mercapto (-SH) functional groups. After the reaction, the wafer is thoroughly cleaned with anhydrous ethanol and dried under nitrogen at 80 ℃ to remove unreacted coupling agent molecules.

[0057] (5-2) Specific fixation of a single DNA template 211: Take a single-stranded or double-stranded DNA template 211 with modified ends (preferably 100-500 base pairs in length, corresponding to the target CNT length). The ends can be modified with amino, carboxyl, or thiol functional groups, allowing the DNA molecule ends to form covalent bonds (such as amide bonds, thiogold bonds) or non-covalent bonds (such as hydrogen bonds, van der Waals forces) with the functional groups on the inner wall of the groove. Dissolve the DNA template 211 in a Tris-EDTA buffer containing sodium dodecyl sulfate (SDS), adjusting the SDS concentration to 0.01-0.1 mmol / L, and the DNA concentration preferably 1-10 nmol / L. Immerse the wafer in this fixation reaction solution at a reaction temperature of 25-60°C. At ℃, with a reaction time of 30-120 minutes, the presence of SDS effectively shields the electrostatic repulsion between DNA molecules, causing them to extend along the groove direction. It also prevents multiple DNA molecules from entangled or overlapping within the same groove. Since the horizontal width of the nanogrooves 210 is only about 5-20 nm, matching the Kuhn length of a single DNA molecule, the physical confinement effect of the grooves and the chemical assistance effect of SDS work synergistically to stably fix only one DNA template 211 within a single groove. Furthermore, this DNA template 211 extends along the groove axis in a single, straight, unbent, and folded state.

[0058] (5-3) Catalyst site introduction: On the wafer with the immobilized single DNA template 211, a catalyst containing transition metal ions (such as Fe³⁺) is introduced. + Co² + Ni² + A low-concentration aqueous solution of the metal ion is used, with a preferred metal ion concentration of 0.5-5 mmol / L and a reaction time of 10-30 minutes. Transition metal ions selectively bind to the central position of the DNA template 211 molecule through specific coordination with specific DNA base sequences (such as G- or A-rich sites). After reduction with 0.05-0.2 mol / L sodium borohydride (NaBH4) solution (reaction time 5-10 minutes at room temperature), a single transition metal catalyst particle (such as Fe, Co, or Ni nanoparticles) with a particle size of 1-5 nm can be precisely generated in the central part of the DNA template 211. By precisely controlling the metal salt concentration, reaction time, and DNA base sequence length, only a single catalytic active site can be anchored on each DNA template 211.

[0059] After the modification reaction, atomic force microscopy (AFM) was used to scan and verify multiple randomly sampled grooves to ensure that the single DNA fixation rate was ≥95%, and that the DNA template 211 was straight along the groove axis and the catalyst particles were located in the middle of the groove. This step cleverly utilizes the physical confinement effect of the nanogroove 210 and the synergistic effect of DNA molecule terminal functional group modification, SDS surfactant regulation, and transition metal ion specific coordination to achieve molecular-level precise control of "one groove, one tube, one catalyst". This fundamentally solves the problems of uncontrollable size and position of the floating gate and large fluctuations in the number of charge trapping centers between different storage units during the growth of traditional nanofloating gate materials.

[0060] Step 6: DNA template 211-induced directional growth of single carbon nanotubes: Using a single modified DNA template 211 and its supported single transition metal catalyst particle within the nanogroove 210 as the sole guide, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or hot-wire chemical vapor deposition (HFCVD) processes are employed to grow only one carbon nanotube within each groove, such as... Figure 6 As shown. Taking CVD process as an example, the specific steps are as follows:

[0061] (6-1) In-situ activation of the catalyst: The wafer modified with DNA template 211 and catalyst was placed in the CVD reaction chamber, and an inert gas mixture of high-purity argon (Ar, flow rate 200-500 sccm) and nitrogen (N2, flow rate 100-300 sccm) was introduced. The chamber pressure was stabilized at 0.5-2 kPa, and the temperature was increased to 300-500 ℃ at a rate of 1-5 ℃ / min and held for 10-30 minutes. This process removes adsorbed water molecules and organic residues from the surface of DNA template 211, and causes surface reconstruction and active reduction of the transition metal catalyst particles, forming a highly active surface that is conducive to the adsorption and dissociation of carbon source.

[0062] (6-2) Directed growth of single CNTs: After activation, the chamber is further heated to 700-1000 ℃, preferably 800-900 ℃; carbon source gas (such as methane CH4, acetylene C2H2, ethylene C2H4, flow rate 50-200 sccm) is introduced, and hydrogen (H2, flow rate 100-300 sccm) is used as a reduction and rate control gas; the chamber pressure is maintained at 1-10 kPa, and the growth time is 10-60 minutes; at high temperature, the carbon source gas undergoes pyrolysis on the surface of the catalyst particles, and carbon atoms dissolve in the catalyst metal and precipitate on the catalyst surface through the Vapor-Liquid-Solid (VLS) mechanism or Vapor-Solid (VS) mechanism, forming single carbon nanotubes along the catalyst surface / DNA template 211 axis; since the catalytic active site is only single in the middle of the groove, and the DNA template 211 provides strict axial guidance, the grown carbon nanotubes always maintain the morphological characteristics of being straight and single;

[0063] (6-3) Growth termination control: By precisely controlling the carbon source supply, growth time and H2 / carbon source ratio, the diameter of a single carbon nanotube is stabilized within 1-20 nm and the length within 100-500 nm. The growth height is strictly limited to no more than 1.2 times the depth of the nanogroove 210 to prevent CNTs from being exposed to the main channel of the through hole 200 and forming a short circuit. After growth, the carbon source is turned off and the CNTs are removed under an H2 / Ar mixed atmosphere at a rate of 5-10 ℃ / min to a temperature below 300 ℃ to prevent air from entering at high temperatures and causing oxidation damage to the CNTs.

[0064] Using the DNA template 211-mediated VLS / VS directional growth mechanism described in this step, single carbon nanotubes with precise positioning, consistent orientation, and uniform size can be obtained in each groove. Raman spectroscopy analysis shows that the G / D peak intensity ratio of the obtained CNTs is typically ≥10, indicating high crystallinity, low defect density, and excellent charge transport and trapping properties. This step is the core innovation of this application in achieving "molecular-level precise floating gates," distinguishing them from traditional nanocrystalline floating gates and continuous floating gates.

[0065] Step 7, Removing the DNA Template 211: After completing the directional growth of a single CNT, the DNA molecule used as a template needs to be removed, leaving only a single carbon nanotube within the nanogroove 210, thus forming a pure carbon nanotube floating gate layer 230, such as... Figure 7 As shown. This step can employ any one of the following methods: enzymatic removal, high-temperature annealing, or chemical oxidation. The preferred removal path is one that does not damage the carbon nanotube's structure or the dielectric layer within the groove:

[0066] Enzymatic removal method: The wafer is immersed in a buffer solution containing deoxyribonuclease I (DNase I) at a concentration of 0.1-1 U / μL. The buffer solution contains 10 mmol / L Tris-HCl (pH 7.5-8.0), 2.5 mmol / L MgCl2, and 0.5 mmol / L CaCl2. The reaction temperature is strictly controlled at 37 °C, and the reaction time is 60-120 minutes. DNase I selectively cleaves the phosphodiester bonds of DNA, generating oligonucleotide fragments soluble in the buffer solution that are eluted from the grooves. After the reaction, the wafer is repeatedly rinsed with deionized water for 5-10 minutes and dried under nitrogen at 80 °C. This method is mild and causes no damage to the CNTs and the barrier medium layer 220, making it the preferred method in this application.

[0067] High-temperature annealing removal method: The wafer is placed in an annealing furnace and heated to 400-600℃ at a rate of 5-10℃ / min in a high-purity inert gas atmosphere (Ar or N2, flow rate 200-500 sccm), and held for 30-60 minutes. DNA molecules undergo pyrolysis in the high-temperature, oxygen-deficient atmosphere, generating small gaseous products such as CO2, H2O, and NH3, which are then extracted with the carrier gas. Since the oxidation threshold of CNTs in an oxygen-deficient atmosphere is higher than 600℃, their structural integrity can be maintained.

[0068] Chemical oxidation removal method: Immerse the wafer in a mild oxidant solution with a concentration of 0.1-0.5 mol / L, such as ammonium persulfate ((NH4)2S2O8), hydrogen peroxide (H2O2), or sodium hypochlorite (NaClO), at room temperature for 10-30 minutes; DNA molecules are selectively oxidized and degraded into soluble fragments, while carbon nanotubes remain stable under the conditions of this concentration of oxidant at room temperature; after the reaction, rinse repeatedly with deionized water and dry.

[0069] After removing the DNA template 211, the following quality testing steps are performed: Raman spectroscopy is used to detect the crystallinity and purity of the carbon nanotubes, confirming that the intensity ratio of the G peak / D peak (I_G / I_D) has not significantly deteriorated (change <10%); Transmission electron microscopy (TEM) or atomic force microscopy (AFM) is used to scan the inside of the groove to verify that the residual rate of the DNA template 211 is less than 5%, and that there are no impurities attached to the surface of the individual carbon nanotubes and no physical damage to the inner wall of the barrier medium layer 220; If the test finds that the residual rate exceeds the standard or the CNT structure is damaged, deionized water ultrasonic cleaning (5-10 minutes) can be added and the test can be repeated until the quality meets the preset threshold.

[0070] Step 8: Fabrication of the tunneling dielectric layer 240: The tunneling dielectric layer 240 is deposited conformally using ALD or CVD on all exposed surfaces within the nanogroove 210 and on the sidewalls of the via 200. Then, anisotropic etching is used to remove the tunneling dielectric layer 240 and the barrier dielectric layer 220 from the sidewalls and bottom of the via 200, leaving only the composite storage structure formed by the tunneling dielectric layer 240, the barrier dielectric layer 220, and the carbon nanotube floating gate layer 230 within the nanogroove 210. Figure 8 As shown. Taking ALD deposition of silicon dioxide (SiO2) as an example, the specific operation is as follows:

[0071] The wafer is placed in the ALD reaction chamber, the chamber is heated to 150-300 ℃, and high-purity N2 or Ar is introduced as a carrier gas to stabilize the pressure inside the chamber to 0.1-10 Torr;

[0072] Bis(tert-butylamino)silane (BTBAS) or hexachlorosilane (HCDS) are selected as silicon-containing precursors and introduced into the cavity in a short pulse manner of 0.1-1 seconds, so that the precursor forms a saturated silicon precursor monolayer on the CNT surface in the groove, the surface of the barrier dielectric layer 220, and the surface of the first insulating dielectric layer 110 on the sidewall of the through hole 200;

[0073] Then, purge with a high flow rate of N2 for 10-30 seconds; followed by the introduction of ozone (O3) or water vapor (H2O) as an oxygen source pulse, which reacts with the silicon precursor to generate a hydroxylated SiO2 monolayer and release byproducts;

[0074] After purging with N2 for 10-30 seconds, repeat this cycle 40-80 times to uniformly deposit a high-quality SiO2 tunneling dielectric layer 240 with a thickness of 4-8 nm and an EOT stability of less than 8 nm on the outer side of the CNTs in the groove and the sidewalls of the via 200. The thickness accuracy can be controlled within ±1 Å as verified by ellipsometry. After deposition, rapid thermal annealing in an N2 atmosphere at 400-600 ℃ for 1-5 minutes can be selected to improve the film density and repair interface defects.

[0075] Step 9: Anisotropic etching back to remove tunneling dielectric and barrier dielectric from the via surface: A reactive ion etching process based on CHF3 / Ar or C4F8 / Ar / O2 gas is used. By controlling the RF bias power (200-800 W) and the gas flow ratio, the tunneling dielectric layer 240 and barrier dielectric layer 220 on the surface of the first insulating dielectric layer 110 on the bottom and sidewalls of the via 200 are removed vertically.

[0076] Since the tunneling dielectric layer 240 and the barrier dielectric layer 220 inside the nanogroove 210 are located in a horizontally recessed region, the longitudinal ion bombardment of anisotropic etching has a very weak effect on them, thus the composite storage structure inside the groove is effectively protected. The etching endpoint is determined by real-time monitoring of Si-based characteristic spectral lines through optical emission spectroscopy (OES), so that the etching stops at the surface of the first insulating dielectric layer 110 or the surface of the substrate 100, avoiding over-etching and damage.

[0077] The tunneling dielectric layer 240 obtained by the above process has a complete arc-shaped wrapping shape in the nanogroove 210, which seals the single carbon nanotube floating gate layer 230 in the closed symmetrical dielectric cavity formed by the tunneling dielectric layer 240 and the barrier dielectric layer 220, forming a charge trapping and storage structure with five vertically stacked layers of "metal-Al2O3-CNT-SiO2-channel".

[0078] Step 10, Deposition of the central trench layer: In this embodiment, low-pressure CVD (LPCVD) is used to grow polycrystalline silicon as an example of the central trench layer 250, specifically as follows:

[0079] The wafer is fed into the LPCVD reaction chamber, which is heated to 580-650 ℃. Silane (SiH4, flow rate 50-200 sccm) and phosphine (PH3, dilution concentration 500-1000 ppm) are introduced as doping sources. The chamber pressure is maintained at 0.1-1 Torr, and the deposition time is 10-30 minutes.

[0080] A 5-15 nm thick polycrystalline silicon thin film is simultaneously formed on the surface of the tunneling dielectric layer 240 on the sidewall of the via 200 and on the surface of the exposed first insulating dielectric layer 110, as an n-type lightly doped (1×10¹) 7 -1×10¹ 9 cm -³) Central channel layer 250;

[0081] After deposition, an activation annealing process can be performed at 800-900 ℃ in an N2 atmosphere for 30-60 minutes to activate phosphorus doping, increase grain size, and reduce the scattering of charge carriers by grain boundaries.

[0082] Step 11, Central Insulating Dielectric Filling and Planarization: A sub-atmospheric pressure CVD process based on tetraethyl orthosilicate (TEOS) and ozone (O3) is used to continue filling the cavity inside the central channel layer 250 with silicon oxide; the deposition temperature is 350-500 ℃, the cavity pressure is 0.5-5 Torr, and the deposition rate is <10 nm / min to ensure that there are no voids in the filling; after the silicon oxide completely fills the central cavity, chemical mechanical polishing (CMP) is used with the central channel layer 250 as the stop layer to remove excess silicon oxide from the wafer surface to achieve surface planarization.

[0083] Step 12, Sacrificial Layer Removal: A central trench layer 250 is conformally grown on the exposed sidewall of the via 200. A central insulating dielectric layer 260 is filled inside the central trench layer 250 and planarized by CMP. Subsequently, the sacrificial layer 160 is removed by selective etching via word line slots (GLS) around the via 200 using wet etching, forming a second groove 202 that penetrates the stacked structure horizontally. Specifically:

[0084] Selective etching solution is introduced into the pre-drilled letter line slots (GLS) trenches around the stacked structure. The type of etching solution depends on the sacrificial layer material.

[0085] For the SiN sacrificial layer, using hot phosphoric acid at 150-160 ℃, the selective ratio of SiO2 (first insulating dielectric layer 110) to Al2O3 (barrier dielectric layer 220) can reach 30:1 and above, respectively, which can selectively remove all SiN sacrificial layer 160 without damaging other layers;

[0086] For a-Si or poly-Si sacrificial layers, a 5-25 wt% TMAH solution (60-80 ℃) is used, and its selectivity relative to SiO2 also meets the requirements; the etching time is precisely controlled according to the length and thickness of the sacrificial layer, typically 10-60 minutes;

[0087] After etching is completed, a second groove 202 is formed in the horizontal direction, penetrating the entire stacked structure. The upper and lower interfaces of the second groove 202 are adjacent to the first insulating dielectric layer 110, and the interior is the filling space for the subsequent grid line metal 270.

[0088] Step 13, Gate Line Metal Filling and CMP Planarization: Gate line metal 270 is filled into the second groove 202, and after CMP planarization, the fabrication of the nano-floating gate type 3D NAND structure is completed, such as... Figure 10 shown. Specifically:

[0089] Barrier / Adhesion Layer (Optional) Deposition: Optionally, a 5-10 nm TiN or TaN layer is first deposited using ALD as an adhesion and diffusion barrier layer for subsequent tungsten metal. The deposition temperature is 300-400 ℃. The precursor can be titanium tetrachloride (TiCl4) + ammonia (NH3) or pentaethylmethylamine tantalum (PEMAT) + NH3.

[0090] Gate Line Metal Deposition: This embodiment uses ALD deposition of tungsten (W) as an example. Specifically, the wafer is placed in the ALD reaction chamber, the chamber is heated to 300-400 ℃, and high-purity N2 is introduced as a carrier gas to stabilize the chamber pressure to 1-10 Torr. Tungsten hexafluoride (WF6, flow rate 10-50 sccm) is used as the tungsten precursor and is alternately pulsed with silane (SiH4) or diborane (B2H6) as a reducing agent, with each growth cycle being approximately 0.1 nm. After 50-200 cycles, a 5-30 nm thick layer of tungsten is uniformly deposited on the inner wall of the second groove 202. Due to the excellent conformability of ALD, seamless and void-free filling can be achieved in the horizontal groove, effectively avoiding the void defects in the high aspect ratio grooves of traditional PVD / CVD processes.

[0091] Word line separation and CMP planarization: After tungsten deposition, excess tungsten metal in the word line slots (GLS) is removed by plasma etching based on SF6 / Ar or NF3 / Ar gas, thereby separating the tungsten film that extends continuously along the groove in the horizontal direction into independent gate word lines; then, the wafer surface is finally planarized using CMP process, with the central channel layer 250 or the first insulating dielectric layer 110 as the stop layer, to complete the core fabrication process of the nano-floating gate 3D NAND structure; subsequently, conventional back-end processes of 3D NAND such as top select gate (SSL), source lead-out layer, word line contact (WL Contact), bit line (BL) and metal interconnect can be completed, which will not be elaborated here.

[0092] The preparation method described in this embodiment organically integrates the molecular-level precision manufacturing technology of DNA molecule self-assembly-induced directional growth of single carbon nanotubes with mature semiconductor processes such as ALD, PECVD, anisotropic RIE, and CMP. Without introducing special or expensive dedicated equipment, it can achieve large-scale production on mainstream 3D NAND mass production lines. Through the triple synergy of physical confinement of nanogrooves 210, chemical guidance of DNA template 211, and position locking of transition metal catalysts, only one carbon nanotube floating gate with highly consistent size, orientation, and catalytic sites is formed at each storage cell position. This fundamentally overcomes the core bottleneck of the random distribution of charge trapping centers between different storage cells in traditional nanofloating gates (nanocrystals, nanodots) under small word line spacing, thereby significantly reducing the threshold voltage fluctuation of storage cells and improving the uniformity of storage windows.

[0093] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0094] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0095] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0096] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0097] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0098] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A DNA self-assembled nanofloating gate type 3D NAND structure, characterized in that, include: Substrate; A periodic stacked structure disposed on the substrate, the stacked structure comprising a plurality of alternating layers of first insulating dielectric layers and nanofloating gate storage structures; A plurality of through holes penetrate the stacked structure, and a central channel layer is provided on the sidewall of the through holes, and a central insulating dielectric layer is filled in the central channel layer; The nano-floating gate storage structure includes a tunneling dielectric layer that contacts the central channel layer, a barrier dielectric layer that surrounds the outside of the tunneling dielectric layer, and a gate line metal located outside the barrier dielectric layer. A carbon nanotube floating gate layer is disposed in the tunneling dielectric layer.

2. The DNA self-assembled nanofloating gate type 3D NAND structure according to claim 1, characterized in that, The carbon nanotube floating grid layer is formed by the directional growth of a single carbon nanotube induced by a DNA molecular template, and the single carbon nanotube is in a straight state.

3. The DNA self-assembled nanofloating gate type 3D NAND structure according to claim 1, characterized in that, The carbon nanotubes in the floating grid layer are loaded with transition metal catalyst particles, which are located in the middle of the length of the carbon nanotubes.

4. The DNA self-assembled nanofloating gate type 3D NAND structure according to claim 1, characterized in that, The equivalent oxide thickness (EOT) of the tunneling dielectric layer is less than 8 nm; the barrier dielectric layer is selected from one of alumina, hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, titanium oxide and their silicates, nitrides or stacked structures.

5. The DNA self-assembled nanofloating gate type 3D NAND structure according to claim 1, characterized in that, The insulating dielectric layer is made of one of the following materials: silicon dioxide, silicon nitride, silicon oxynitride, low-k dielectric, or high-k dielectric.

6. A method for preparing a DNA self-assembled nanofloating gate type 3D NAND structure according to any one of claims 1 to 5, characterized in that, Includes the following steps: Step 1: Vertically deposit several periodic stacked structures on the substrate, wherein the periodic stacked structures, from bottom to top, include a first insulating dielectric layer and a sacrificial layer. Step 2: Etch through holes, the through holes penetrating the plurality of periodic stacked structures; Step 3: Use selective etching to etch back the sacrificial layer to a depth of 5-30 nanometers to form the first groove; Step 4: Deposit a barrier dielectric layer on the sidewall of the through hole and the inner wall of the first groove using atomic layer deposition or chemical vapor deposition to form a nanogroove in the first groove; Step 5: Specific chemical modification or biofunctionalization of a single DNA template is performed within the nanogroove to achieve precise fixation of the single DNA template within the groove, introduce a single catalytic active site required for the growth of a single carbon nanotube, and ensure that the single DNA template is in a single, straight state within the groove. Step 6: Using the modified single DNA template within the nanogroove as the sole guide, directional growth of single carbon nanotubes is achieved through chemical vapor deposition, plasma-enhanced chemical vapor deposition, or hot-filament chemical vapor deposition. Step 7: Remove individual DNA templates in the grooves using enzymatic hydrolysis, high-temperature annealing, or chemical oxidation to form a carbon nanotube floating grid layer; Step 8: After preparing the tunneling dielectric layer in the nanogroove and the sidewall of the via using atomic layer deposition or chemical vapor deposition, remove the tunneling dielectric layer and the barrier dielectric layer from the sidewall and bottom of the via. Step 9: After growing the central trench layer on the sidewall of the through hole, fill the central insulating dielectric layer, and then use wet etching to etch the sacrificial layer to form the second groove; Step 10: After filling the second groove with grid line metal and performing CMP planarization, the fabrication of the nano-floating grid type 3D NAND structure is completed.

7. The preparation method according to claim 6, characterized in that, The specific chemical modification of the nanogroove involves introducing amino, carboxyl, or thiol functional groups into the inner wall of the nanogroove, so that a single DNA template is fixed to the center of the inner wall of the nanogroove through covalent or non-covalent bonds, and adjusting the surfactant concentration in the reaction solution to 0.01-0.1 mmol / L so that the single DNA template is in a straight state along the direction of the nanogroove.

8. The preparation method according to claim 6, characterized in that, The specific method for achieving the directional growth of single carbon nanotubes is as follows: the catalyst is activated in situ at 300-500℃ in an inert gas atmosphere to remove impurities from the template surface; a chemical vapor deposition process is used at 700-1000℃ and 1-10 kPa pressure, with hydrogen as a reducing gas to assist in controlling the carbon source growth rate, ensuring that single carbon nanotubes achieve directional growth in the range of diameter 1-20 nanometers and length 100-500 nanometers, and the growth height does not exceed 1.2 times the groove depth.

9. The preparation method according to claim 6, characterized in that, In the enzymatic removal method, deoxyribonuclease is used to react at 37°C for 60-120 minutes; in the high-temperature annealing removal method, the temperature is raised to 400-600°C under an inert gas atmosphere; in the chemical oxidation removal method, an oxidizing agent with a concentration of 0.1-0.5 mol / L is used for room temperature soaking treatment.

10. The preparation method according to claim 6, characterized in that, After removing individual DNA templates, the following quality testing steps are further included: Raman spectroscopy is used to detect the crystallinity and purity of carbon nanotubes, and transmission electron microscopy or atomic force microscopy is used to scan the inside of the groove to verify that the residual rate of DNA template in the groove is less than 5%, and to ensure that there are no impurities attached to the surface of the individual carbon nanotubes and no physical damage to the inner wall of the groove.

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